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DSPElib applications used during ZPSTC laboratory

This project contains raw results of experiments in jsonl format and converted to tsv

Narzędzie służące do zbadania właściwości kodów fontannowych w różnych wariantach.

A verilog module implementing conversion from FP32 to FP8 numbers

Verilog modules needed to perform stochastic rounding of FP8 numbers

A verilog module implementing multiplication of FP8 numbers (including denormalized numbers and stochastic rounding)

A verilog module implementing addition of FP8 numbers (including denormalized numbers and stochastic rounding)

Koder i dekoder kodu polaryzującego zrealizowany na FPGA

Jakub Draszkiewicz 193732 Jędrzej Borkowski 188943