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rsa-intel-fpga
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Julia Chomicka
rsa-intel-fpga
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master
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Branches
8
aria10_project
jchomick
master
default
protected
pkorczak
rkalinow
rsa-implementation-c
tkrezymo
webapp
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Created with Raphaël 2.2.0
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fix e list generation, fix ui for message encryption
webapp
webapp
Merge branch 'webapp' of git.pg.edu.pl:p1351350/rsa-intel-fpga into webapp
add api for text encryption
Resolve issue with incorrect encryption and decryption.
Resolved issue with incorrect display of RSA keys values
Merge branch 'webapp' of git.pg.edu.pl:p1351350/rsa-intel-fpga into webapp
modify gitignore file, add registers.rdl
aria10_project
aria10_project
modify key generator, add modul_szyfrowania, modify modul_studenta and clock, add tests
add error display for image encryption
add integration with FPGA through api for key generator
Remove app.output.css file from incorrect directory
Create a modal dialog with additional RSA and asymmetric cryptography information.
add validators for credentials, add saving api settings to appsettings.json
add popups when fpga not connected to 'uzyj fpga' buttons, fix ui bugs
move fpga status widget on server side
add fpga configuration service, fix ui in load file
change login ui
change default api address
refresh nav ui
add alerts for key download
Merge branch 'webapp' of git.pg.edu.pl:p1351350/rsa-intel-fpga into webapp
add PC/FPGA badge to key entry, add modal for rsa tutorial text
Change to FPGA widget image and style
add key download feature
cosmetic changes
Delete soc_system.sv
Initial commit
add modul_szyfrowania
rkalinow
rkalinow
modify divider module
fixed popups
Add increment and key generator module
rename parameters in C implementation
rsa-implementat…
rsa-implementation-c
rename parameters in C implementation
Update UI and functionality of RSA components
add basic ui to image encryption page
Add mnozenie unit testing
fix home page dark mode
add encrypted image display, change supported image format from png to bmp
Implementation of timer, measuring encryption and decryption time in milliseconds
Updated machine state and mult module