fpga project - Arria10 SoC DevKit board version

Useful information:

Arria10 SoC DevKit board

PeakRDL - control & status register (CSR) generator toolchain

SVUnit verification framework

Intel® Arria® 10 Hard Processor System Technical Reference Manual

Intel® Arria® 10 HPS Register Address Map and Definitions

AMBA AXI and ACE Protocol Specification

Update Submodules:

After changing branches, run the following command to update all submodules to the commit specified by the branch:

git submodule update --init --recursive

Generate files from RDL (Register Description Language):

1. Go to rdl directory:

cd rdl

2. Generate SystemVerilog from RDL file:

peakrdl regblock registers.rdl -o outputs/ --cpuif axi4-lite-flat

3. Generate HTML from RDL file:

peakrdl html registers.rdl -o outputs/html

Simulate design

1. Go to test directory:

cd tests/modul_studenta_unit_test

2. Run test in gui mode:

./run_svunit_gui.sh

3. Run test in console mode:

./run_svunit.sh

FPGA bitstream files generation from command line:

1. Go to quartus directory:

cd quartus

2. Run quartus compilation:

quartus_sh --flow compile soc_system

FPGA bitstream files generation from Quartus GUI (alternative method):

1. Go to quartus directory:

cd quartus

2. Open quartus:

quartus soc_system.qpf &

2. Run "Compile Design"

FPGA bitstream files generated by Quartus:

quartus/output_files/soc_system.sof
quartus/output_files/soc_system.core.rbf
quartus/output_files/soc_system.periph.rbf

Updating image on SDMMC for Arria10 SoC DevKit Board:

1. Create fit_spl_fpga.its file with the following content:

// SPDX-Licence-Identifirt: GPL-2.0
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
*
*/

/dts-v1/;
/ {
    description = "FIT image with FPGA bistream";
    #address-cells = <1>;

    images {
        fpga-periph-1{
            description = "FPGA peripheral bitstream";
            data = /incbin/("soc_system.periph.rbf");
            type = "fpga";
            arch = "arm";
            compression = "none";
        };
    };

    configurations {
        default = "config-1";
        config-1 {
            description = "Boot with FPGA early IO release config";
            fpga = "fpga-periph-1";
        };
    };

};

2. Make image for U-boot: mkimage -E -f fit_spl_fpga.its fit_spl_fpga.itb

3. Copy yocto image (.wic) for Arria10 SoC DevKit board to SDMCC: use Win32DiskImage or any other available tool

4. Copy 3 files to SDMMC: fit_spl_fpga.itb, soc_system.core.rbf and soc_system.periph.rbf

5. Rename a10soc-devkit.dtb to socfpga_arria10_socdk_sdmmc.dtb