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Created with Raphaël 2.2.014Apr84227Mar251816320Nov1829Oct8Jul32fix: more fixes2-logic-to-cont…2-logic-to-control-eneta_resetn-and-enetb_resetnfix: restore modules deleted by mistakechore: remove not-existing modules resulted in warningsfeat: add second eth_tsefeat: some changesfeat: bring up eth_tse connection to the topremoved clk 50 mhz and exports that are not present in examplefeat: did nothing specialfeat: generate hdlfix: removed underfined symbolfeat: add 50mHz 125mHz clocks & atx_pllfix: remove second driving value of the signalfeat: modify connections and exports of tse interfacesfeat: add eth_tse to qsys modulefix: renamed referencefeat: connect eneta_resetn and enetb_resetn to global_reset_generatorfeat: added global_reset_generator module to designMerge branch '1-assing-pins-in-qsf' into 'main'mainmainfix: missing io standard for ports of eth1added io standarts to pinsfeat: assigned pinsUpdate readme (related to peakrdl use) and gitignoreChange sim run style to native for SVUnit as was done for de0-nano-socAdd generation of .rbf bitstream format during quartus compilaitonUpdate .gitignore (and remove ignored files from repo)Update readmeUpdate .gitignoreUpdate README.mdMerge branch 'arria10' of git.pg.edu.pl:p765918/fpga_groups_project into arria10move axi4_lite and svunit_baseUpdate README.mdupdate README.mdexample project for arria10 SoCInitial commit