Update readme (related to peakrdl use) and gitignore

.gitignore

@@ -21,4 +21,5 @@ vsim.wlf
 **/incremental_db/*
 **/hps_isw_handoff/*
 **/qdb/*
-**/tmp_svunit/
\ No newline at end of file
+**/tmp_svunit/
+**/.qsys_edit/
\ No newline at end of file

README.md

@@ -18,15 +18,19 @@
 
     git submodule update --init --recursive
 
-### <ins>Generate Verilog from rdl:</ins>
+### <ins>Generate files from RDL (Register Description Language):</ins>
 #### 1. Go to rdl directory:
 
     cd rdl
 
-#### 2. Generate Verilog from rdl file:
+#### 2. Generate SystemVerilog from RDL file:
 
     peakrdl regblock registers.rdl -o outputs/ --cpuif axi4-lite-flat
 
+#### 3. Generate HTML from RDL file:
+
+    peakrdl html registers.rdl -o outputs/html
+
 ### <ins>Simulate design</ins>
 #### 1. Go to test directory: