diff --git a/quartus/qsys/.qsys_edit/arria10_hps.xml b/quartus/qsys/.qsys_edit/arria10_hps.xml
index e587eb4c17f3c345c035b85f0c99c33b6786f333..05d4f0925356a469fdbceaf7a3a05ac35ea1fe10 100644
--- a/quartus/qsys/.qsys_edit/arria10_hps.xml
+++ b/quartus/qsys/.qsys_edit/arria10_hps.xml
@@ -764,6 +764,11 @@
<placeholder>dock.single.Interconnect\ Requirements</placeholder>
</key>
</entry>
+ <entry>
+ <key shared="false">
+ <placeholder>dock.single.Parameters</placeholder>
+ </key>
+ </entry>
</placeholders>
</content>
</delegate>
@@ -853,7 +858,7 @@
</entry>
</placeholder-map>
</leaf>
- <leaf id="2" nodeId="1375985011087">
+ <leaf id="0" nodeId="1375985011087">
<placeholders>
<placeholder>dock.single.Hierarchy</placeholder>
</placeholders>
@@ -877,10 +882,10 @@
</placeholder-map>
</leaf>
</node>
- <node nodeId="1372710005725" orientation="VERTICAL" divider="0.75">
+ <node nodeId="1372710005725" orientation="VERTICAL" divider="0.7607555089192025">
<node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.6183193900785428">
<node nodeId="1372710005733" orientation="VERTICAL" divider="0.75">
- <leaf id="1" nodeId="1372710005735">
+ <leaf id="2" nodeId="1372710005735">
<placeholders>
<placeholder>dock.single.Connections</placeholder>
<placeholder>dock.single.System\ Contents</placeholder>
@@ -971,7 +976,7 @@
</leaf>
</node>
</node>
- <leaf id="0" nodeId="1372710005745">
+ <leaf id="1" nodeId="1372710005745">
<placeholders>
<placeholder>dock.single.Messages</placeholder>
<placeholder>dock.single.Generation\ Messages</placeholder>
@@ -1002,6 +1007,65 @@
</layout>
</adjacent>
<children ignore="false">
+ <child>
+ <layout factory="delegate_StackDockStationFactory">
+ <selected>0</selected>
+ <placeholders>
+ <version>0</version>
+ <format>dock.PlaceholderList</format>
+ <entry>
+ <key shared="false">
+ <placeholder>dock.single.Hierarchy</placeholder>
+ </key>
+ <item key="convert" type="b">true</item>
+ <item key="convert-keys" type="a">
+ <item type="s">index</item>
+ <item type="s">id</item>
+ <item type="s">placeholder</item>
+ </item>
+ <item key="dock.index" type="i">0</item>
+ <item key="dock.id" type="i">0</item>
+ <item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
+ </entry>
+ <entry>
+ <key shared="false">
+ <placeholder>dock.single.Device\ Family</placeholder>
+ </key>
+ <item key="convert" type="b">true</item>
+ <item key="convert-keys" type="a">
+ <item type="s">index</item>
+ <item type="s">id</item>
+ <item type="s">placeholder</item>
+ </item>
+ <item key="dock.index" type="i">1</item>
+ <item key="dock.id" type="i">1</item>
+ <item key="dock.placeholder" type="s">dock.single.Device\ Family</item>
+ </entry>
+ </placeholders>
+ </layout>
+ <children ignore="false">
+ <child>
+ <layout factory="predefined" placeholder="dock.single.Hierarchy">
+ <replacement id="dockablesingle Hierarchy"/>
+ <delegate id="delegate_ccontrol backup factory id">
+ <id>Hierarchy</id>
+ <area/>
+ </delegate>
+ </layout>
+ <children ignore="false"/>
+ </child>
+ <child>
+ <layout factory="predefined" placeholder="dock.single.Device\ Family">
+ <replacement id="dockablesingle Device Family"/>
+ <delegate id="delegate_ccontrol backup factory id">
+ <id>Device Family</id>
+ <area/>
+ </delegate>
+ </layout>
+ <children ignore="false"/>
+ </child>
+ </children>
+ </child>
<child>
<layout factory="predefined" placeholder="dock.single.Messages">
<replacement id="dockablesingle Messages"/>
@@ -1120,65 +1184,6 @@
</child>
</children>
</child>
- <child>
- <layout factory="delegate_StackDockStationFactory">
- <selected>0</selected>
- <placeholders>
- <version>0</version>
- <format>dock.PlaceholderList</format>
- <entry>
- <key shared="false">
- <placeholder>dock.single.Hierarchy</placeholder>
- </key>
- <item key="convert" type="b">true</item>
- <item key="convert-keys" type="a">
- <item type="s">index</item>
- <item type="s">id</item>
- <item type="s">placeholder</item>
- </item>
- <item key="dock.index" type="i">0</item>
- <item key="dock.id" type="i">0</item>
- <item key="dock.placeholder" type="s">dock.single.Hierarchy</item>
- </entry>
- <entry>
- <key shared="false">
- <placeholder>dock.single.Device\ Family</placeholder>
- </key>
- <item key="convert" type="b">true</item>
- <item key="convert-keys" type="a">
- <item type="s">index</item>
- <item type="s">id</item>
- <item type="s">placeholder</item>
- </item>
- <item key="dock.index" type="i">1</item>
- <item key="dock.id" type="i">1</item>
- <item key="dock.placeholder" type="s">dock.single.Device\ Family</item>
- </entry>
- </placeholders>
- </layout>
- <children ignore="false">
- <child>
- <layout factory="predefined" placeholder="dock.single.Hierarchy">
- <replacement id="dockablesingle Hierarchy"/>
- <delegate id="delegate_ccontrol backup factory id">
- <id>Hierarchy</id>
- <area/>
- </delegate>
- </layout>
- <children ignore="false"/>
- </child>
- <child>
- <layout factory="predefined" placeholder="dock.single.Device\ Family">
- <replacement id="dockablesingle Device Family"/>
- <delegate id="delegate_ccontrol backup factory id">
- <id>Device Family</id>
- <area/>
- </delegate>
- </layout>
- <children ignore="false"/>
- </child>
- </children>
- </child>
<child>
<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
<replacement id="dockablesingle IP Catalog"/>
@@ -1205,19 +1210,6 @@
<key shared="false">
<placeholder>dock.single.Parameters</placeholder>
</key>
- <item key="convert" type="b">true</item>
- <item key="convert-keys" type="a">
- <item type="s">size</item>
- <item type="s">index</item>
- <item type="s">id</item>
- <item type="s">placeholder</item>
- <item type="s">hold</item>
- </item>
- <item key="dock.size" type="i">400</item>
- <item key="dock.index" type="i">0</item>
- <item key="dock.id" type="i">0</item>
- <item key="dock.placeholder" type="s">dock.single.Parameters</item>
- <item key="dock.hold" type="b">false</item>
</entry>
</placeholders>
</content>
@@ -1228,18 +1220,7 @@
<type>dock.CContentArea.minimize</type>
</layout>
</adjacent>
- <children ignore="false">
- <child>
- <layout factory="predefined" placeholder="dock.single.Parameters">
- <replacement id="dockablesingle Parameters"/>
- <delegate id="delegate_ccontrol backup factory id">
- <id>Parameters</id>
- <area/>
- </delegate>
- </layout>
- <children ignore="false"/>
- </child>
- </children>
+ <children ignore="false"/>
</root>
</roots>
<children>
@@ -1299,6 +1280,26 @@
<children ignore="false"/>
</layout>
</child>
+ <child key="single Parameters" root="ccontrol north" location="true">
+ <location>
+ <property factory="flap dock">
+ <index>0</index>
+ <holding>false</holding>
+ <size>400</size>
+ <placeholder>dock.single.Parameters</placeholder>
+ </property>
+ </location>
+ <layout>
+ <layout factory="predefined" placeholder="dock.single.Parameters">
+ <replacement id="dockablesingle Parameters"/>
+ <delegate id="delegate_ccontrol backup factory id">
+ <id>Parameters</id>
+ <area/>
+ </delegate>
+ </layout>
+ <children ignore="false"/>
+ </layout>
+ </child>
<child key="single Schematic" root="ccontrol center" location="true">
<location>
<property factory="SplitDockPlaceholderProperty">
@@ -1572,7 +1573,7 @@
</property>
</properties>
</entry>
- <entry id="single Parameters" current="dock.mode.minimized">
+ <entry id="single Parameters">
<history>
<mode>dock.mode.normal</mode>
<mode>dock.mode.minimized</mode>
@@ -1585,7 +1586,7 @@
<property factory="flap dock">
<index>0</index>
<holding>false</holding>
- <size>400</size>
+ <size>651</size>
<placeholder>dock.single.Parameters</placeholder>
</property>
</location>
diff --git a/quartus/qsys/.qsys_edit/arria10_hps_schematic.nlv b/quartus/qsys/.qsys_edit/arria10_hps_schematic.nlv
index 5443641448557c7273ff2eacb620f21e73478550..31e61528e61da610a84f54b2aa882f835bc8ada6 100644
--- a/quartus/qsys/.qsys_edit/arria10_hps_schematic.nlv
+++ b/quartus/qsys/.qsys_edit/arria10_hps_schematic.nlv
@@ -1,17 +1,23 @@
# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
#
-preplace inst arria10_hps.axi_bridge_0 -pg 1 -lvl 3 -y 90
+preplace inst arria10_hps.xcvr_atx_pll_a10_0 -pg 1 -lvl 3 -y 950
preplace inst arria10_hps.a10_hps.i_qspi_QSPIDATA -pg 1
preplace inst arria10_hps.a10_hps.fpga_interfaces -pg 1
+preplace inst arria10_hps.eth_tse_0 -pg 1 -lvl 4 -y 420
preplace inst arria10_hps.a10_hps.i_uart_1_uart -pg 1
preplace inst arria10_hps.a10_hps.i_usbotg_0_globgrp -pg 1
preplace inst arria10_hps.a10_hps.i_nand_NANDDATA -pg 1
preplace inst arria10_hps.a10_hps.i_i2c_1_i2c -pg 1
preplace inst arria10_hps.a10_hps.i_spis_0_spis -pg 1
preplace inst arria10_hps.a10_hps.i_watchdog_1_l4wd -pg 1
+preplace inst arria10_hps.eth_tse_0.phyip_rxclkout_splitter_instance_0 -pg 1
+preplace inst arria10_hps.eth_tse_0.i_tse_pcs_0 -pg 1
+preplace inst arria10_hps.eth_tse_0.ref_clk_module -pg 1
+preplace inst arria10_hps.eth_tse_0.reg_rst_module -pg 1
+preplace inst arria10_hps.eth_tse_0.reg_clk_module -pg 1
preplace inst arria10_hps.a10_hps.f2s_free_clk -pg 1
preplace inst arria10_hps.a10_hps.hps_io -pg 1
-preplace inst arria10_hps.a10_hps -pg 1 -lvl 2 -y 100
+preplace inst arria10_hps.a10_hps -pg 1 -lvl 2 -y 130
preplace inst arria10_hps.a10_hps.i_sdmmc_sdmmc -pg 1
preplace inst arria10_hps.a10_hps.i_fpga_mgr_fpgamgrregs -pg 1
preplace inst arria10_hps.a10_hps.bridges -pg 1
@@ -27,48 +33,62 @@ preplace inst arria10_hps.a10_hps.i_spis_1_spis -pg 1
preplace inst arria10_hps.a10_hps.i_gpio_2_gpio -pg 1
preplace inst arria10_hps.a10_hps.i_gpio_1_gpio -pg 1
preplace inst arria10_hps.a10_hps.i_timer_sys_1_timer -pg 1
+preplace inst arria10_hps.eth_tse_0.i_tse_mac -pg 1
preplace inst arria10_hps.a10_hps.i_i2c_emac_2_i2c -pg 1
preplace inst arria10_hps.a10_hps.i_dma_DMASECURE -pg 1
preplace inst arria10_hps.a10_hps.arm_a9_0 -pg 1
preplace inst arria10_hps.a10_hps.cb_intosc_ls_clk -pg 1
preplace inst arria10_hps.a10_hps.eosc1 -pg 1
+preplace inst arria10_hps.eth_tse_0.i_nf_native_phyip_0 -pg 1
preplace inst arria10_hps.a10_hps.scu -pg 1
preplace inst arria10_hps.a10_hps.i_spim_1_spim -pg 1
preplace inst arria10_hps.a10_hps.i_spim_0_spim -pg 1
preplace inst arria10_hps.a10_hps.i_gpio_0_gpio -pg 1
preplace inst arria10_hps.a10_hps.arm_a9_1 -pg 1
preplace inst arria10_hps -pg 1 -lvl 1 -y 40 -regy -20
-preplace inst arria10_hps.clk_0 -pg 1 -lvl 1 -y 30
+preplace inst arria10_hps.eth_tse_0.avalon_arbiter -pg 1
+preplace inst arria10_hps.clk_0 -pg 1 -lvl 1 -y 70
preplace inst arria10_hps.a10_hps.i_i2c_emac_1_i2c -pg 1
preplace inst arria10_hps.a10_hps.i_emac_emac0 -pg 1
preplace inst arria10_hps.a10_hps.i_timer_sys_0_timer -pg 1
preplace inst arria10_hps.a10_hps.i_timer_sp_0_timer -pg 1
preplace inst arria10_hps.a10_hps.cb_intosc_hs_div2_clk -pg 1
+preplace inst arria10_hps.eth_tse_0.i_nf_native_phyip_terminator_0 -pg 1
preplace inst arria10_hps.a10_hps.i_emac_emac1 -pg 1
preplace inst arria10_hps.a10_hps.i_uart_0_uart -pg 1
preplace inst arria10_hps.a10_hps.i_timer_sp_1_timer -pg 1
preplace inst arria10_hps.a10_hps.mpu_reg_l2_MPUL2 -pg 1
preplace inst arria10_hps.a10_hps.arm_gic_0 -pg 1
+preplace inst arria10_hps.clk_125m -pg 1 -lvl 1 -y 810
preplace inst arria10_hps.a10_hps.i_usbotg_1_globgrp -pg 1
preplace inst arria10_hps.a10_hps.i_emac_emac2 -pg 1
preplace inst arria10_hps.a10_hps.clk_0 -pg 1
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(MASTER)arria10_hps.a10_hps_f2h_irq0,(MASTER)a10_hps.f2h_irq0) 1 2 2 NJ 190 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.axi_reset,(SLAVE)clk_0.clk_in_reset) 1 0 1 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(MASTER)a10_hps.h2f_reset,(MASTER)arria10_hps.a10_hps_h2f_reset) 1 2 2 NJ 270 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(MASTER)arria10_hps.axi_bridge_h2f_lw_axi_master,(MASTER)axi_bridge_0.m0) 1 3 1 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)a10_hps.f2h_cold_reset_req,(SLAVE)arria10_hps.a10_hps_f2h_cold_reset_req) 1 0 2 NJ 220 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.a10_hps_f2h_axi_slave,(SLAVE)a10_hps.f2h_axi_slave) 1 0 2 NJ 200 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.a10_hps_emif,(SLAVE)a10_hps.emif) 1 0 2 NJ 60 NJ
+preplace netloc POINT_TO_POINT<net_container>arria10_hps</net_container>(MASTER)a10_hps.h2f_axi_master,(SLAVE)eth_tse_0.control_port) 1 2 2 1140 430 NJ
preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)clk_0.clk_in,(SLAVE)arria10_hps.axi_clk) 1 0 1 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)a10_hps.f2h_axi_clock,(SLAVE)arria10_hps.a10_hps_f2h_axi_slave_clock) 1 0 2 NJ 130 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)a10_hps.emif,(SLAVE)arria10_hps.a10_hps_emif) 1 0 2 NJ 110 NJ
-preplace netloc POINT_TO_POINT<net_container>arria10_hps</net_container>(MASTER)a10_hps.h2f_lw_axi_master,(SLAVE)axi_bridge_0.s0) 1 2 1 760
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.a10_hps_io,(SLAVE)a10_hps.hps_io) 1 0 2 NJ 270 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)a10_hps.f2h_cold_reset_req,(SLAVE)arria10_hps.a10_hps_f2h_cold_reset_req) 1 0 2 NJ 190 NJ
-preplace netloc FAN_OUT<net_container>arria10_hps</net_container>(SLAVE)a10_hps.h2f_axi_reset,(SLAVE)a10_hps.h2f_lw_axi_reset,(MASTER)clk_0.clk_reset,(SLAVE)axi_bridge_0.clk_reset) 1 1 2 390 60 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.a10_hps_f2h_warm_reset_req,(SLAVE)a10_hps.f2h_warm_reset_req) 1 0 2 NJ 250 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.a10_hps_f2h_axi_slave_reset,(SLAVE)a10_hps.f2h_axi_reset) 1 0 2 NJ 150 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(MASTER)a10_hps.f2h_irq1,(MASTER)arria10_hps.a10_hps_f2h_irq1) 1 2 2 NJ 210 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)a10_hps.f2h_debug_reset_req,(SLAVE)arria10_hps.a10_hps_f2h_debug_reset_req) 1 0 2 NJ 210 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)a10_hps.f2h_axi_slave,(SLAVE)arria10_hps.a10_hps_f2h_axi_slave) 1 0 2 NJ 170 NJ
-preplace netloc FAN_OUT<net_container>arria10_hps</net_container>(MASTER)clk_0.clk,(SLAVE)axi_bridge_0.clk,(SLAVE)a10_hps.h2f_lw_axi_clock,(SLAVE)a10_hps.h2f_axi_clock) 1 1 2 410 40 NJ
-preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.a10_hps_f2h_stm_hw_events,(SLAVE)a10_hps.f2h_stm_hw_events) 1 0 2 NJ 230 NJ
-levelinfo -pg 1 0 180 1150
-levelinfo -hier arria10_hps 190 220 550 840 950
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.clk_125m,(SLAVE)clk_125m.clk_in) 1 0 1 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.xcvr_atx_pll_a10_0_pll_locked,(SLAVE)xcvr_atx_pll_a10_0.pll_locked) 1 0 3 NJ 980 NJ 980 NJ
+preplace netloc FAN_OUT<net_container>arria10_hps</net_container>(SLAVE)eth_tse_0.receive_clock_connection,(SLAVE)a10_hps.h2f_axi_clock,(SLAVE)eth_tse_0.transmit_clock_connection,(MASTER)clk_0.clk,(SLAVE)eth_tse_0.control_port_clock_connection,(SLAVE)a10_hps.h2f_lw_axi_clock) 1 1 3 510 450 NJ 450 1580
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.a10_hps_io,(SLAVE)a10_hps.hps_io) 1 0 2 NJ 320 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)a10_hps.f2h_axi_reset,(SLAVE)arria10_hps.a10_hps_f2h_axi_slave_reset) 1 0 2 NJ 180 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)eth_tse_0.serial_connection,(SLAVE)arria10_hps.eth_tse_0_serial_connection) 1 0 4 NJ 750 NJ 750 NJ 750 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(MASTER)a10_hps.h2f_reset,(MASTER)arria10_hps.a10_hps_h2f_reset) 1 2 3 NJ 320 NJ 320 NJ
+preplace netloc FAN_OUT<net_container>arria10_hps</net_container>(SLAVE)eth_tse_0.pcs_ref_clk_clock_connection,(MASTER)clk_125m.clk,(SLAVE)eth_tse_0.rx_cdr_refclk,(SLAVE)xcvr_atx_pll_a10_0.pll_refclk0) 1 1 3 NJ 820 1120 530 1560
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(MASTER)arria10_hps.a10_hps_f2h_irq0,(MASTER)a10_hps.f2h_irq0) 1 2 3 NJ 220 NJ 220 NJ
+preplace netloc POINT_TO_POINT<net_container>arria10_hps</net_container>(SLAVE)eth_tse_0.tx_serial_clk,(MASTER)xcvr_atx_pll_a10_0.tx_serial_clk) 1 3 1 1560
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.a10_hps_f2h_axi_slave_clock,(SLAVE)a10_hps.f2h_axi_clock) 1 0 2 NJ 40 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.a10_hps_f2h_stm_hw_events,(SLAVE)a10_hps.f2h_stm_hw_events) 1 0 2 NJ 280 NJ
+preplace netloc INTERCONNECT<net_container>arria10_hps</net_container>(SLAVE)eth_tse_0.reset_connection,(MASTER)clk_125m.clk_reset,(SLAVE)a10_hps.h2f_lw_axi_reset,(MASTER)clk_0.clk_reset,(SLAVE)a10_hps.h2f_axi_reset) 1 1 3 410 550 NJ 550 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)clk_125m.clk_in_reset,(SLAVE)arria10_hps.reset_125m) 1 0 1 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)clk_0.clk_in_reset,(SLAVE)arria10_hps.axi_reset) 1 0 1 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(MASTER)a10_hps.h2f_lw_axi_master,(MASTER)arria10_hps.a10_hps_h2f_lw_axi_master) 1 2 3 NJ 280 NJ 280 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)eth_tse_0.status_led_connection,(SLAVE)arria10_hps.eth_tse_0_status_led_connection) 1 0 4 NJ 770 NJ 770 NJ 770 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)arria10_hps.a10_hps_f2h_debug_reset_req,(SLAVE)a10_hps.f2h_debug_reset_req) 1 0 2 NJ 260 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)eth_tse_0.mac_mdio_connection,(SLAVE)arria10_hps.eth_tse_0_mac_mdio_connection) 1 0 4 NJ 470 NJ 470 NJ 470 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(MASTER)arria10_hps.a10_hps_f2h_irq1,(MASTER)a10_hps.f2h_irq1) 1 2 3 NJ 240 NJ 240 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)xcvr_atx_pll_a10_0.pll_cal_busy,(SLAVE)arria10_hps.xcvr_atx_pll_a10_0_pll_cal_busy) 1 0 3 NJ 960 NJ 960 NJ
+preplace netloc EXPORT<net_container>arria10_hps</net_container>(SLAVE)a10_hps.f2h_warm_reset_req,(SLAVE)arria10_hps.a10_hps_f2h_warm_reset_req) 1 0 2 NJ 300 NJ
+levelinfo -pg 1 0 200 2420
+levelinfo -hier arria10_hps 210 240 930 1370 2100 2230
diff --git a/quartus/qsys/.qsys_edit/preferences.xml b/quartus/qsys/.qsys_edit/preferences.xml
index 20fec0c4be5fbe4c5b59570d7d2d161afed868bf..3ba19ef192c0982291a1c827f3f14d4606887f23 100644
--- a/quartus/qsys/.qsys_edit/preferences.xml
+++ b/quartus/qsys/.qsys_edit/preferences.xml
@@ -3,13 +3,13 @@
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
- <connections preferredWidth="143" />
+ <connections preferredWidth="175" />
<irq preferredWidth="47" />
<name preferredWidth="261" />
- <export preferredWidth="229" />
+ <export preferredWidth="269" />
</columns>
</systemtable>
- <library expandedCategories="Library,Project" />
- <window width="1908" height="1041" x="0" y="27" />
+ <library expandedCategories="Project,Library" />
+ <window width="1808" height="945" x="0" y="27" />
<generation path="" />
</preferences>
diff --git a/quartus/qsys/arria10_hps.qsys b/quartus/qsys/arria10_hps.qsys
index 66be48c6ba00baffe2c3df8e9be8b8a4e734b527..d751ea49272fef5d672c3a08a6339a977704f738 100644
--- a/quartus/qsys/arria10_hps.qsys
+++ b/quartus/qsys/arria10_hps.qsys
@@ -30,6 +30,56 @@
type = "boolean";
}
}
+ element clk_125m
+ {
+ datum _sortIndex
+ {
+ value = "4";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
+ element eth_tse_0
+ {
+ datum _sortIndex
+ {
+ value = "2";
+ type = "int";
+ }
+ }
+ element eth_tse_1
+ {
+ datum _sortIndex
+ {
+ value = "5";
+ type = "int";
+ }
+ }
+ element eth_tse_1.control_port
+ {
+ datum baseAddress
+ {
+ value = "1024";
+ type = "String";
+ }
+ }
+ element xcvr_atx_pll_a10_0
+ {
+ datum _sortIndex
+ {
+ value = "3";
+ type = "int";
+ }
+ datum sopceditor_expanded
+ {
+ value = "0";
+ type = "boolean";
+ }
+ }
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
@@ -141,6 +191,52 @@
<interface name="arria10_hps_0_f2sdram2_reset" internal="a10_hps.f2sdram2_reset" />
<interface name="axi_clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface name="axi_reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
+ <interface name="clk_125m" internal="clk_125m.clk_in" type="clock" dir="end" />
+ <interface
+ name="eth_tse_0_mac_mdio_connection"
+ internal="eth_tse_0.mac_mdio_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth_tse_0_serial_connection"
+ internal="eth_tse_0.serial_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth_tse_0_status_led_connection"
+ internal="eth_tse_0.status_led_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth_tse_1_mac_mdio_connection"
+ internal="eth_tse_1.mac_mdio_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth_tse_1_serial_connection"
+ internal="eth_tse_1.serial_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="eth_tse_1_status_led_connection"
+ internal="eth_tse_1.status_led_connection"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="reset_125m"
+ internal="clk_125m.clk_in_reset"
+ type="reset"
+ dir="end" />
+ <interface
+ name="xcvr_atx_pll_a10_0_pll_cal_busy"
+ internal="xcvr_atx_pll_a10_0.pll_cal_busy"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="xcvr_atx_pll_a10_0_pll_locked"
+ internal="xcvr_atx_pll_a10_0.pll_locked"
+ type="conduit"
+ dir="end" />
<module name="a10_hps" kind="altera_arria10_hps" version="22.1" enabled="1">
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
<parameter name="BOOT_FROM_FPGA_Enable" value="false" />
@@ -365,6 +461,209 @@
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
+ <module name="clk_125m" kind="clock_source" version="22.1" enabled="1">
+ <parameter name="clockFrequency" value="125000000" />
+ <parameter name="clockFrequencyKnown" value="true" />
+ <parameter name="inputClockFrequency" value="0" />
+ <parameter name="resetSynchronousEdges" value="NONE" />
+ </module>
+ <module name="eth_tse_0" kind="altera_eth_tse" version="22.1" enabled="1">
+ <parameter name="AUTO_DEVICE" value="10AS066N3F40I2LG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
+ <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
+ <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
+ <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
+ <parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
+ <parameter name="core_variation" value="MAC_PCS" />
+ <parameter name="deviceFamilyName" value="Arria 10" />
+ <parameter name="eg_addr" value="11" />
+ <parameter name="ena_hash" value="false" />
+ <parameter name="enable_alt_reconfig" value="false" />
+ <parameter name="enable_ecc" value="false" />
+ <parameter name="enable_ena" value="32" />
+ <parameter name="enable_gmii_loopback" value="false" />
+ <parameter name="enable_hd_logic" value="false" />
+ <parameter name="enable_mac_flow_ctrl" value="false" />
+ <parameter name="enable_mac_vlan" value="false" />
+ <parameter name="enable_magic_detect" value="true" />
+ <parameter name="enable_ptp_1step" value="false" />
+ <parameter name="enable_sgmii" value="true" />
+ <parameter name="enable_shift16" value="true" />
+ <parameter name="enable_sup_addr" value="false" />
+ <parameter name="enable_timestamping" value="false" />
+ <parameter name="enable_use_internal_fifo" value="true" />
+ <parameter name="export_pwrdn" value="false" />
+ <parameter name="ext_stat_cnt_ena" value="false" />
+ <parameter name="ifGMII" value="MII_GMII" />
+ <parameter name="ing_addr" value="11" />
+ <parameter name="max_channels" value="1" />
+ <parameter name="mdio_clk_div" value="40" />
+ <parameter name="nf_phyip_rcfg_enable" value="false" />
+ <parameter name="phy_identifier" value="0" />
+ <parameter name="phyip_en_synce_support" value="false" />
+ <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+ <parameter name="phyip_pll_type" value="CMU" />
+ <parameter name="phyip_pma_bonding_mode" value="x1" />
+ <parameter name="starting_channel_number" value="0" />
+ <parameter name="stat_cnt_ena" value="true" />
+ <parameter name="transceiver_type" value="GXB" />
+ <parameter name="tstamp_fp_width" value="4" />
+ <parameter name="useMDIO" value="true" />
+ <parameter name="use_mac_clken" value="false" />
+ <parameter name="use_misc_ports" value="true" />
+ </module>
+ <module name="eth_tse_1" kind="altera_eth_tse" version="22.1" enabled="1">
+ <parameter name="AUTO_DEVICE" value="10AS066N3F40I2LG" />
+ <parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
+ <parameter name="XCVR_RCFG_JTAG_ENABLE" value="0" />
+ <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE" value="0" />
+ <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE" value="0" />
+ <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE" value="0" />
+ <parameter name="XCVR_SET_USER_IDENTIFIER" value="0" />
+ <parameter name="core_variation" value="MAC_PCS" />
+ <parameter name="deviceFamilyName" value="Arria 10" />
+ <parameter name="eg_addr" value="11" />
+ <parameter name="ena_hash" value="false" />
+ <parameter name="enable_alt_reconfig" value="false" />
+ <parameter name="enable_ecc" value="false" />
+ <parameter name="enable_ena" value="32" />
+ <parameter name="enable_gmii_loopback" value="false" />
+ <parameter name="enable_hd_logic" value="false" />
+ <parameter name="enable_mac_flow_ctrl" value="false" />
+ <parameter name="enable_mac_vlan" value="false" />
+ <parameter name="enable_magic_detect" value="true" />
+ <parameter name="enable_ptp_1step" value="false" />
+ <parameter name="enable_sgmii" value="true" />
+ <parameter name="enable_shift16" value="true" />
+ <parameter name="enable_sup_addr" value="false" />
+ <parameter name="enable_timestamping" value="false" />
+ <parameter name="enable_use_internal_fifo" value="true" />
+ <parameter name="export_pwrdn" value="false" />
+ <parameter name="ext_stat_cnt_ena" value="false" />
+ <parameter name="ifGMII" value="MII_GMII" />
+ <parameter name="ing_addr" value="11" />
+ <parameter name="max_channels" value="1" />
+ <parameter name="mdio_clk_div" value="40" />
+ <parameter name="nf_phyip_rcfg_enable" value="false" />
+ <parameter name="phy_identifier" value="0" />
+ <parameter name="phyip_en_synce_support" value="false" />
+ <parameter name="phyip_pll_base_data_rate" value="1250 Mbps" />
+ <parameter name="phyip_pll_type" value="CMU" />
+ <parameter name="phyip_pma_bonding_mode" value="x1" />
+ <parameter name="starting_channel_number" value="0" />
+ <parameter name="stat_cnt_ena" value="true" />
+ <parameter name="transceiver_type" value="GXB" />
+ <parameter name="tstamp_fp_width" value="4" />
+ <parameter name="useMDIO" value="true" />
+ <parameter name="use_mac_clken" value="false" />
+ <parameter name="use_misc_ports" value="true" />
+ </module>
+ <module
+ name="xcvr_atx_pll_a10_0"
+ kind="altera_xcvr_atx_pll_a10"
+ version="22.1"
+ enabled="1">
+ <parameter name="base_device" value="NIGHTFURY4" />
+ <parameter name="bw_sel" value="medium" />
+ <parameter name="device" value="10AS066N3F40I2LG" />
+ <parameter name="device_family" value="Arria 10" />
+ <parameter name="enable_16G_path" value="0" />
+ <parameter name="enable_8G_path" value="1" />
+ <parameter name="enable_analog_resets" value="0" />
+ <parameter name="enable_bonding_clks" value="0" />
+ <parameter name="enable_cascade_out" value="0" />
+ <parameter name="enable_debug_ports_parameters" value="0" />
+ <parameter name="enable_ext_lockdetect_ports" value="0" />
+ <parameter name="enable_fb_comp_bonding" value="0" />
+ <parameter name="enable_hfreq_clk" value="0" />
+ <parameter name="enable_hip_cal_done_port" value="0" />
+ <parameter name="enable_manual_configuration" value="1" />
+ <parameter name="enable_mcgb" value="0" />
+ <parameter name="enable_mcgb_pcie_clksw" value="0" />
+ <parameter name="enable_pcie_clk" value="0" />
+ <parameter name="enable_pld_atx_cal_busy_port" value="1" />
+ <parameter name="enable_pld_mcgb_cal_busy_port" value="0" />
+ <parameter name="enable_pll_reconfig" value="0" />
+ <parameter name="generate_add_hdl_instance_example" value="0" />
+ <parameter name="generate_docs" value="1" />
+ <parameter name="mcgb_aux_clkin_cnt" value="0" />
+ <parameter name="mcgb_div" value="1" />
+ <parameter name="message_level" value="error" />
+ <parameter name="pma_width" value="64" />
+ <parameter name="primary_pll_buffer">GX clock output buffer</parameter>
+ <parameter name="prot_mode" value="Basic" />
+ <parameter name="rcfg_debug" value="0" />
+ <parameter name="rcfg_enable_avmm_busy_port" value="0" />
+ <parameter name="rcfg_file_prefix">altera_xcvr_atx_pll_a10</parameter>
+ <parameter name="rcfg_h_file_enable" value="0" />
+ <parameter name="rcfg_jtag_enable" value="0" />
+ <parameter name="rcfg_mif_file_enable" value="0" />
+ <parameter name="rcfg_multi_enable" value="0" />
+ <parameter name="rcfg_profile_cnt" value="2" />
+ <parameter name="rcfg_profile_data0" value="" />
+ <parameter name="rcfg_profile_data1" value="" />
+ <parameter name="rcfg_profile_data2" value="" />
+ <parameter name="rcfg_profile_data3" value="" />
+ <parameter name="rcfg_profile_data4" value="" />
+ <parameter name="rcfg_profile_data5" value="" />
+ <parameter name="rcfg_profile_data6" value="" />
+ <parameter name="rcfg_profile_data7" value="" />
+ <parameter name="rcfg_profile_select" value="1" />
+ <parameter name="rcfg_reduced_files_enable" value="0" />
+ <parameter name="rcfg_separate_avmm_busy" value="0" />
+ <parameter name="rcfg_sv_file_enable" value="0" />
+ <parameter name="rcfg_txt_file_enable" value="0" />
+ <parameter name="refclk_cnt" value="1" />
+ <parameter name="refclk_index" value="0" />
+ <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en" value="1" />
+ <parameter name="set_auto_reference_clock_frequency" value="125.0" />
+ <parameter name="set_capability_reg_enable" value="0" />
+ <parameter name="set_csr_soft_logic_enable" value="0" />
+ <parameter name="set_fref_clock_frequency" value="156.25" />
+ <parameter name="set_hip_cal_en" value="0" />
+ <parameter name="set_k_counter" value="2000000000" />
+ <parameter name="set_l_cascade_counter" value="15" />
+ <parameter name="set_l_cascade_predivider" value="1" />
+ <parameter name="set_l_counter" value="16" />
+ <parameter name="set_m_counter" value="24" />
+ <parameter name="set_manual_reference_clock_frequency" value="200.0" />
+ <parameter name="set_output_clock_frequency" value="1250.0" />
+ <parameter name="set_rcfg_emb_strm_enable" value="0" />
+ <parameter name="set_ref_clk_div" value="1" />
+ <parameter name="set_user_identifier" value="0" />
+ <parameter name="silicon_rev" value="false" />
+ <parameter name="support_mode" value="user_mode" />
+ <parameter name="test_mode" value="0" />
+ </module>
+ <connection
+ kind="avalon"
+ version="22.1"
+ start="a10_hps.h2f_axi_master"
+ end="eth_tse_0.control_port">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0000" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="avalon"
+ version="22.1"
+ start="a10_hps.h2f_axi_master"
+ end="eth_tse_1.control_port">
+ <parameter name="arbitrationPriority" value="1" />
+ <parameter name="baseAddress" value="0x0400" />
+ <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_0.clk"
+ end="eth_tse_0.control_port_clock_connection" />
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_0.clk"
+ end="eth_tse_1.control_port_clock_connection" />
<connection
kind="clock"
version="22.1"
@@ -375,6 +674,61 @@
version="22.1"
start="clk_0.clk"
end="a10_hps.h2f_lw_axi_clock" />
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_125m.clk"
+ end="eth_tse_0.pcs_ref_clk_clock_connection" />
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_125m.clk"
+ end="eth_tse_1.pcs_ref_clk_clock_connection" />
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_125m.clk"
+ end="xcvr_atx_pll_a10_0.pll_refclk0" />
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_0.clk"
+ end="eth_tse_0.receive_clock_connection" />
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_0.clk"
+ end="eth_tse_1.receive_clock_connection" />
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_125m.clk"
+ end="eth_tse_0.rx_cdr_refclk" />
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_125m.clk"
+ end="eth_tse_1.rx_cdr_refclk" />
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_0.clk"
+ end="eth_tse_0.transmit_clock_connection" />
+ <connection
+ kind="clock"
+ version="22.1"
+ start="clk_0.clk"
+ end="eth_tse_1.transmit_clock_connection" />
+ <connection
+ kind="hssi_serial_clock"
+ version="22.1"
+ start="xcvr_atx_pll_a10_0.tx_serial_clk"
+ end="eth_tse_0.tx_serial_clk" />
+ <connection
+ kind="hssi_serial_clock"
+ version="22.1"
+ start="xcvr_atx_pll_a10_0.tx_serial_clk"
+ end="eth_tse_1.tx_serial_clk" />
<connection
kind="reset"
version="22.1"
@@ -385,6 +739,26 @@
version="22.1"
start="clk_0.clk_reset"
end="a10_hps.h2f_lw_axi_reset" />
+ <connection
+ kind="reset"
+ version="22.1"
+ start="clk_125m.clk_reset"
+ end="eth_tse_0.reset_connection" />
+ <connection
+ kind="reset"
+ version="22.1"
+ start="clk_0.clk_reset"
+ end="eth_tse_0.reset_connection" />
+ <connection
+ kind="reset"
+ version="22.1"
+ start="clk_0.clk_reset"
+ end="eth_tse_1.reset_connection" />
+ <connection
+ kind="reset"
+ version="22.1"
+ start="clk_125m.clk_reset"
+ end="eth_tse_1.reset_connection" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
diff --git a/quartus/qsys/arria10_hps.sopcinfo b/quartus/qsys/arria10_hps.sopcinfo
index 774a1e711cc375c0d15f7bc1fc3e8920c3d1a962..b93062884b64920c6607b3d8c570ed7ba7a58a08 100644
--- a/quartus/qsys/arria10_hps.sopcinfo
+++ b/quartus/qsys/arria10_hps.sopcinfo
@@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="arria10_hps" kind="arria10_hps" version="1.0" fabric="QSYS">
<!-- Format version 22.1 922 (Future versions may contain additional information.) -->
- <!-- 2024.06.14.16:04:38 -->
+ <!-- 2025.04.08.15:25:35 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
- <value>1718373857</value>
+ <value>1744118718</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@@ -148,6 +148,36 @@
<sysinfo_type>RESET_DOMAIN</sysinfo_type>
<sysinfo_arg>axi_clk</sysinfo_arg>
</parameter>
+ <parameter name="AUTO_CLK_125M_CLOCK_RATE">
+ <type>java.lang.Long</type>
+ <value>-1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>CLOCK_RATE</sysinfo_type>
+ <sysinfo_arg>clk_125m</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLK_125M_CLOCK_DOMAIN">
+ <type>java.lang.Integer</type>
+ <value>-1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
+ <sysinfo_arg>clk_125m</sysinfo_arg>
+ </parameter>
+ <parameter name="AUTO_CLK_125M_RESET_DOMAIN">
+ <type>java.lang.Integer</type>
+ <value>-1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>RESET_DOMAIN</sysinfo_type>
+ <sysinfo_arg>clk_125m</sysinfo_arg>
+ </parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>Arria 10</value>
@@ -3404,6 +3434,22 @@ parameters are a RESULT of the module parameters. -->
<width>1</width>
<role>rready</role>
</port>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_0</moduleName>
+ <slaveName>control_port</slaveName>
+ <name>eth_tse_0.control_port</name>
+ <baseAddress>0</baseAddress>
+ <span>1024</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_1</moduleName>
+ <slaveName>control_port</slaveName>
+ <name>eth_tse_1.control_port</name>
+ <baseAddress>1024</baseAddress>
+ <span>1024</span>
+ </memoryBlock>
</interface>
<interface name="f2h_axi_clock" kind="clock_sink" version="22.1">
<!-- The connection points exposed by a module instance for the
@@ -7461,6 +7507,22 @@ parameters are a RESULT of the module parameters. -->
<width>1</width>
<role>rready</role>
</port>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_0</moduleName>
+ <slaveName>control_port</slaveName>
+ <name>eth_tse_0.control_port</name>
+ <baseAddress>0</baseAddress>
+ <span>1024</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_1</moduleName>
+ <slaveName>control_port</slaveName>
+ <name>eth_tse_1.control_port</name>
+ <baseAddress>1024</baseAddress>
+ <span>1024</span>
+ </memoryBlock>
</interface>
<interface name="h2f_lw_axi_clock" kind="clock_sink" version="22.1">
<!-- The connection points exposed by a module instance for the
@@ -9412,6 +9474,22 @@ parameters are a RESULT of the module parameters. -->
<baseAddress>3221225472</baseAddress>
<span>536870912</span>
</memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_0</moduleName>
+ <slaveName>control_port</slaveName>
+ <name>eth_tse_0.control_port</name>
+ <baseAddress>3221225472</baseAddress>
+ <span>1024</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_1</moduleName>
+ <slaveName>control_port</slaveName>
+ <name>eth_tse_1.control_port</name>
+ <baseAddress>3221226496</baseAddress>
+ <span>1024</span>
+ </memoryBlock>
<memoryBlock>
<isBridge>true</isBridge>
<moduleName>a10_hps_bridges</moduleName>
@@ -10219,6 +10297,22 @@ parameters are a RESULT of the module parameters. -->
<baseAddress>3221225472</baseAddress>
<span>536870912</span>
</memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_0</moduleName>
+ <slaveName>control_port</slaveName>
+ <name>eth_tse_0.control_port</name>
+ <baseAddress>3221225472</baseAddress>
+ <span>1024</span>
+ </memoryBlock>
+ <memoryBlock>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_1</moduleName>
+ <slaveName>control_port</slaveName>
+ <name>eth_tse_1.control_port</name>
+ <baseAddress>3221226496</baseAddress>
+ <span>1024</span>
+ </memoryBlock>
<memoryBlock>
<isBridge>true</isBridge>
<moduleName>a10_hps_bridges</moduleName>
@@ -36416,6 +36510,18 @@ parameters are a RESULT of the module parameters. -->
<width>1</width>
<role>clk</role>
</port>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_0</moduleName>
+ <slaveName>control_port_clock_connection</slaveName>
+ <name>eth_tse_0.control_port_clock_connection</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_1</moduleName>
+ <slaveName>control_port_clock_connection</slaveName>
+ <name>eth_tse_1.control_port_clock_connection</name>
+ </clockDomainMember>
<clockDomainMember>
<isBridge>false</isBridge>
<moduleName>a10_hps_bridges</moduleName>
@@ -36428,6 +36534,30 @@ parameters are a RESULT of the module parameters. -->
<slaveName>h2f_lw_axi_clock</slaveName>
<name>a10_hps_bridges.h2f_lw_axi_clock</name>
</clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_0</moduleName>
+ <slaveName>receive_clock_connection</slaveName>
+ <name>eth_tse_0.receive_clock_connection</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_1</moduleName>
+ <slaveName>receive_clock_connection</slaveName>
+ <name>eth_tse_1.receive_clock_connection</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_0</moduleName>
+ <slaveName>transmit_clock_connection</slaveName>
+ <name>eth_tse_0.transmit_clock_connection</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_1</moduleName>
+ <slaveName>transmit_clock_connection</slaveName>
+ <name>eth_tse_1.transmit_clock_connection</name>
+ </clockDomainMember>
</interface>
<interface name="clk_reset" kind="reset_source" version="22.1">
<!-- The connection points exposed by a module instance for the
@@ -36491,187 +36621,7993 @@ parameters are a RESULT of the module parameters. -->
</port>
</interface>
</module>
- <connection
- name="a10_hps_clk_0.clk/a10_hps_bridges.clock_sink"
- kind="clock"
- version="22.1"
- start="a10_hps_clk_0.clk"
- end="a10_hps_bridges.clock_sink">
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk</startConnectionPoint>
- <endModule>a10_hps_bridges</endModule>
- <endConnectionPoint>clock_sink</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_clk_0.clk_reset/a10_hps_bridges.reset_sink"
- kind="reset"
- version="22.1"
- start="a10_hps_clk_0.clk_reset"
- end="a10_hps_bridges.reset_sink">
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_bridges</endModule>
- <endConnectionPoint>reset_sink</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_bridges.axi_h2f"
- kind="avalon"
- version="22.1"
- start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_bridges.axi_h2f">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xc0000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="defaultConnection">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <startModule>a10_hps_arm_a9_0</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_bridges</endModule>
- <endConnectionPoint>axi_h2f</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_bridges.axi_h2f"
- kind="avalon"
- version="22.1"
- start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_bridges.axi_h2f">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xc0000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="defaultConnection">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
+ <module name="clk_125m" kind="clock_source" version="22.1" path="clk_125m">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <parameter name="clockFrequency">
+ <type>long</type>
+ <value>125000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="generateLegacySim">
+ <parameter name="clockFrequencyKnown">
<type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <startModule>a10_hps_arm_a9_1</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_bridges</endModule>
- <endConnectionPoint>axi_h2f</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_bridges.axi_h2f_lw"
- kind="avalon"
- version="22.1"
- start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_bridges.axi_h2f_lw">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
+ <value>true</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xff200000</value>
+ <parameter name="inputClockFrequency">
+ <type>long</type>
+ <value>0</value>
<derived>false</derived>
<enabled>true</enabled>
- <visible>true</visible>
+ <visible>false</visible>
<valid>true</valid>
+ <sysinfo_type>CLOCK_RATE</sysinfo_type>
+ <sysinfo_arg>clk_in</sysinfo_arg>
</parameter>
- <parameter name="defaultConnection">
- <type>boolean</type>
- <value>false</value>
+ <parameter name="resetSynchronousEdges">
+ <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+ <value>NONE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="clk_in" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>qsys.ui.export_name</name>
+ <value>clk</value>
+ </assignment>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>java.lang.Boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRate">
+ <type>java.lang.Long</type>
+ <value>125000000</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>in_clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="clk_in_reset" kind="reset_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>qsys.ui.export_name</name>
+ <value>reset</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="synchronousEdges">
+ <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+ <value>NONE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <port>
+ <name>reset_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>reset_n</role>
+ </port>
+ </interface>
+ <interface name="clk" kind="clock_source" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedDirectClock">
+ <type>java.lang.String</type>
+ <value>clk_in</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>125000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="clockRateKnown">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>true</isStart>
+ <port>
+ <name>clk_out</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_0</moduleName>
+ <slaveName>pcs_ref_clk_clock_connection</slaveName>
+ <name>eth_tse_0.pcs_ref_clk_clock_connection</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_1</moduleName>
+ <slaveName>pcs_ref_clk_clock_connection</slaveName>
+ <name>eth_tse_1.pcs_ref_clk_clock_connection</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>xcvr_atx_pll_a10_0</moduleName>
+ <slaveName>pll_refclk0</slaveName>
+ <name>xcvr_atx_pll_a10_0.pll_refclk0</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_0</moduleName>
+ <slaveName>rx_cdr_refclk</slaveName>
+ <name>eth_tse_0.rx_cdr_refclk</name>
+ </clockDomainMember>
+ <clockDomainMember>
+ <isBridge>false</isBridge>
+ <moduleName>eth_tse_1</moduleName>
+ <slaveName>rx_cdr_refclk</slaveName>
+ <name>eth_tse_1.rx_cdr_refclk</name>
+ </clockDomainMember>
+ </interface>
+ <interface name="clk_reset" kind="reset_source" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedDirectReset">
+ <type>java.lang.String</type>
+ <value>clk_in_reset</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedResetSinks">
+ <type>[Ljava.lang.String;</type>
+ <value>clk_in_reset</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="synchronousEdges">
+ <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+ <value>NONE</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>reset</type>
+ <isStart>true</isStart>
+ <port>
+ <name>reset_n_out</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>reset_n</role>
+ </port>
+ </interface>
+ </module>
+ <module
+ name="eth_tse_0"
+ kind="altera_eth_tse"
+ version="22.1"
+ path="eth_tse_0">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <assignment>
+ <name>embeddedsw.CMacro.ENABLE_MACLITE</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.FIFO_WIDTH</name>
+ <value>32</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.IS_MULTICHANNEL_MAC</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.MACLITE_GIGE</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.MDIO_SHARED</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.NUMBER_OF_CHANNEL</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.NUMBER_OF_MAC_MDIO_SHARED</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.PCS</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.PCS_ID</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.PCS_SGMII</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.RECEIVE_FIFO_DEPTH</name>
+ <value>2048</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.REGISTER_SHARED</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.RGMII</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.TRANSMIT_FIFO_DEPTH</name>
+ <value>2048</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.USE_MDIO</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.compatible</name>
+ <value>altr,tse-1.0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.group</name>
+ <value>ethernet</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.name</name>
+ <value>tse</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.params.ALTR,rx-fifo-depth</name>
+ <value>2048</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.params.ALTR,tx-fifo-depth</name>
+ <value>2048</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.vendor</name>
+ <value>altr</value>
+ </assignment>
+ <parameter name="deviceFamilyName">
+ <type>java.lang.String</type>
+ <value>ARRIA10</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="enable_padding">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_lgth_check">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="gbit_only">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mbit_only">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="reduced_control">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="core_version">
+ <type>int</type>
+ <value>5633</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dev_version">
+ <type>int</type>
+ <value>5633</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="eg_fifo">
+ <type>int</type>
+ <value>2048</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ing_fifo">
+ <type>int</type>
+ <value>2048</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="reduced_interface_ena">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="synchronizer_depth">
+ <type>int</type>
+ <value>3</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>ARRIA10</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isUseMAC">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isUsePCS">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_clk_sharing">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="core_variation">
+ <type>java.lang.String</type>
+ <value>MAC_PCS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ifGMII">
+ <type>java.lang.String</type>
+ <value>MII_GMII</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="use_mac_clken">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_use_internal_fifo">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_ecc">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="max_channels">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="use_misc_ports">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transceiver_type">
+ <type>java.lang.String</type>
+ <value>GXB</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_hd_logic">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_gmii_loopback">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_sup_addr">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="stat_cnt_ena">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ext_stat_cnt_ena">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ena_hash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_shift16">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_mac_flow_ctrl">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_mac_vlan">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_magic_detect">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useMDIO">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mdio_clk_div">
+ <type>int</type>
+ <value>40</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_ena">
+ <type>int</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="eg_addr">
+ <type>int</type>
+ <value>11</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ing_addr">
+ <type>int</type>
+ <value>11</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="phy_identifier">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_sgmii">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="export_pwrdn">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_alt_reconfig">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="starting_channel_number">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="phyip_pll_type">
+ <type>java.lang.String</type>
+ <value>CMU</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="phyip_pll_base_data_rate">
+ <type>java.lang.String</type>
+ <value>1250 Mbps</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="phyip_en_synce_support">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="phyip_pma_bonding_mode">
+ <type>java.lang.String</type>
+ <value>x1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="nf_phyip_rcfg_enable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="XCVR_RCFG_JTAG_ENABLE">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="XCVR_SET_USER_IDENTIFIER">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="nf_lvds_iopll_num_channels">
+ <type>int</type>
+ <value>4</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_timestamping">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_ptp_1step">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="tstamp_fp_width">
+ <type>int</type>
+ <value>4</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+ <type>java.lang.String</type>
+ <value>10AS066N3F40I2LG</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+ <type>java.lang.String</type>
+ <value>2</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="control_port_clock_connection" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="reset_connection" kind="reset_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>control_port_clock_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="synchronousEdges">
+ <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+ <value>DEASSERT</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <port>
+ <name>reset</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>reset</role>
+ </port>
+ </interface>
+ <interface name="control_port" kind="avalon_slave" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isFlash</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isMemoryDevice</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isNonVolatileStorage</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isPrintableDevice</name>
+ <value>0</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>DYNAMIC</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>java.math.BigInteger</type>
+ <value>1024</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>control_port_clock_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value>reset_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgedAddressOffset">
+ <type>java.math.BigInteger</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>java.math.BigInteger</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingWriteTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <port>
+ <name>reg_data_out</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>reg_rd</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>read</role>
+ </port>
+ <port>
+ <name>reg_data_in</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>writedata</role>
+ </port>
+ <port>
+ <name>reg_wr</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write</role>
+ </port>
+ <port>
+ <name>reg_busy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>waitrequest</role>
+ </port>
+ <port>
+ <name>reg_addr</name>
+ <direction>Input</direction>
+ <width>8</width>
+ <role>address</role>
+ </port>
+ </interface>
+ <interface name="receive_clock_connection" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>ff_rx_clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="transmit_clock_connection" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>ff_tx_clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="receive" kind="avalon_streaming_source" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>receive_clock_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value>reset_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="beatsPerCycle">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dataBitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="emptyWithinPacket">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="errorDescriptor">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="firstSymbolInHighOrderBits">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="highOrderSymbolAtMSB">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maxChannel">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="packetDescription">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readyLatency">
+ <type>int</type>
+ <value>2</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="symbolsPerBeat">
+ <type>int</type>
+ <value>4</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon_streaming</type>
+ <isStart>true</isStart>
+ <port>
+ <name>ff_rx_data</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>data</role>
+ </port>
+ <port>
+ <name>ff_rx_eop</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>endofpacket</role>
+ </port>
+ <port>
+ <name>rx_err</name>
+ <direction>Output</direction>
+ <width>6</width>
+ <role>error</role>
+ </port>
+ <port>
+ <name>ff_rx_mod</name>
+ <direction>Output</direction>
+ <width>2</width>
+ <role>empty</role>
+ </port>
+ <port>
+ <name>ff_rx_rdy</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>ready</role>
+ </port>
+ <port>
+ <name>ff_rx_sop</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>startofpacket</role>
+ </port>
+ <port>
+ <name>ff_rx_dval</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>valid</role>
+ </port>
+ </interface>
+ <interface name="transmit" kind="avalon_streaming_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>transmit_clock_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value>reset_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="beatsPerCycle">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dataBitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="emptyWithinPacket">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="errorDescriptor">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="firstSymbolInHighOrderBits">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="highOrderSymbolAtMSB">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maxChannel">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="packetDescription">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readyLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="symbolsPerBeat">
+ <type>int</type>
+ <value>4</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon_streaming</type>
+ <isStart>false</isStart>
+ <port>
+ <name>ff_tx_data</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>data</role>
+ </port>
+ <port>
+ <name>ff_tx_eop</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>endofpacket</role>
+ </port>
+ <port>
+ <name>ff_tx_err</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>error</role>
+ </port>
+ <port>
+ <name>ff_tx_mod</name>
+ <direction>Input</direction>
+ <width>2</width>
+ <role>empty</role>
+ </port>
+ <port>
+ <name>ff_tx_rdy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ready</role>
+ </port>
+ <port>
+ <name>ff_tx_sop</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>startofpacket</role>
+ </port>
+ <port>
+ <name>ff_tx_wren</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>valid</role>
+ </port>
+ </interface>
+ <interface name="mac_mdio_connection" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>mdc</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>mdc</role>
+ </port>
+ <port>
+ <name>mdio_in</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>mdio_in</role>
+ </port>
+ <port>
+ <name>mdio_out</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>mdio_out</role>
+ </port>
+ <port>
+ <name>mdio_oen</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>mdio_oen</role>
+ </port>
+ </interface>
+ <interface name="mac_misc_connection" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>magic_wakeup</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>magic_wakeup</role>
+ </port>
+ <port>
+ <name>magic_sleep_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>magic_sleep_n</role>
+ </port>
+ <port>
+ <name>ff_tx_crc_fwd</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>ff_tx_crc_fwd</role>
+ </port>
+ <port>
+ <name>ff_tx_septy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_tx_septy</role>
+ </port>
+ <port>
+ <name>tx_ff_uflow</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>tx_ff_uflow</role>
+ </port>
+ <port>
+ <name>ff_tx_a_full</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_tx_a_full</role>
+ </port>
+ <port>
+ <name>ff_tx_a_empty</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_tx_a_empty</role>
+ </port>
+ <port>
+ <name>rx_err_stat</name>
+ <direction>Output</direction>
+ <width>18</width>
+ <role>rx_err_stat</role>
+ </port>
+ <port>
+ <name>rx_frm_type</name>
+ <direction>Output</direction>
+ <width>4</width>
+ <role>rx_frm_type</role>
+ </port>
+ <port>
+ <name>ff_rx_dsav</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_rx_dsav</role>
+ </port>
+ <port>
+ <name>ff_rx_a_full</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_rx_a_full</role>
+ </port>
+ <port>
+ <name>ff_rx_a_empty</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_rx_a_empty</role>
+ </port>
+ </interface>
+ <interface name="pcs_ref_clk_clock_connection" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>ref_clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="status_led_connection" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>led_crs</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>crs</role>
+ </port>
+ <port>
+ <name>led_link</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>link</role>
+ </port>
+ <port>
+ <name>led_panel_link</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>panel_link</role>
+ </port>
+ <port>
+ <name>led_col</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>col</role>
+ </port>
+ <port>
+ <name>led_an</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>an</role>
+ </port>
+ <port>
+ <name>led_char_err</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>char_err</role>
+ </port>
+ <port>
+ <name>led_disp_err</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>disp_err</role>
+ </port>
+ </interface>
+ <interface name="serdes_control_connection" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_recovclkout</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ </interface>
+ <interface name="serial_connection" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rxp</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>rxp</role>
+ </port>
+ <port>
+ <name>txp</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>txp</role>
+ </port>
+ </interface>
+ <interface name="tx_serial_clk" kind="hssi_serial_clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>hssi_serial_clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>tx_serial_clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="rx_cdr_refclk" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_cdr_refclk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="tx_analogreset" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>tx_analogreset</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>tx_analogreset</role>
+ </port>
+ </interface>
+ <interface name="tx_digitalreset" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>tx_digitalreset</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>tx_digitalreset</role>
+ </port>
+ </interface>
+ <interface name="rx_analogreset" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_analogreset</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>rx_analogreset</role>
+ </port>
+ </interface>
+ <interface name="rx_digitalreset" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_digitalreset</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>rx_digitalreset</role>
+ </port>
+ </interface>
+ <interface name="tx_cal_busy" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>tx_cal_busy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>tx_cal_busy</role>
+ </port>
+ </interface>
+ <interface name="rx_cal_busy" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_cal_busy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>rx_cal_busy</role>
+ </port>
+ </interface>
+ <interface name="rx_set_locktodata" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_set_locktodata</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>rx_set_locktodata</role>
+ </port>
+ </interface>
+ <interface name="rx_set_locktoref" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_set_locktoref</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>rx_set_locktoref</role>
+ </port>
+ </interface>
+ <interface name="rx_is_lockedtoref" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_is_lockedtoref</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>rx_is_lockedtoref</role>
+ </port>
+ </interface>
+ <interface name="rx_is_lockedtodata" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_is_lockedtodata</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>rx_is_lockedtodata</role>
+ </port>
+ </interface>
+ </module>
+ <module
+ name="eth_tse_1"
+ kind="altera_eth_tse"
+ version="22.1"
+ path="eth_tse_1">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <assignment>
+ <name>embeddedsw.CMacro.ENABLE_MACLITE</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.FIFO_WIDTH</name>
+ <value>32</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.IS_MULTICHANNEL_MAC</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.MACLITE_GIGE</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.MDIO_SHARED</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.NUMBER_OF_CHANNEL</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.NUMBER_OF_MAC_MDIO_SHARED</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.PCS</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.PCS_ID</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.PCS_SGMII</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.RECEIVE_FIFO_DEPTH</name>
+ <value>2048</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.REGISTER_SHARED</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.RGMII</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.TRANSMIT_FIFO_DEPTH</name>
+ <value>2048</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.CMacro.USE_MDIO</name>
+ <value>1</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.compatible</name>
+ <value>altr,tse-1.0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.group</name>
+ <value>ethernet</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.name</name>
+ <value>tse</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.params.ALTR,rx-fifo-depth</name>
+ <value>2048</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.params.ALTR,tx-fifo-depth</name>
+ <value>2048</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.dts.vendor</name>
+ <value>altr</value>
+ </assignment>
+ <parameter name="deviceFamilyName">
+ <type>java.lang.String</type>
+ <value>ARRIA10</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="enable_padding">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_lgth_check">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="gbit_only">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mbit_only">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="reduced_control">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="core_version">
+ <type>int</type>
+ <value>5633</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dev_version">
+ <type>int</type>
+ <value>5633</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="eg_fifo">
+ <type>int</type>
+ <value>2048</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ing_fifo">
+ <type>int</type>
+ <value>2048</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="reduced_interface_ena">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="synchronizer_depth">
+ <type>int</type>
+ <value>3</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>ARRIA10</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isUseMAC">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isUsePCS">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_clk_sharing">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="core_variation">
+ <type>java.lang.String</type>
+ <value>MAC_PCS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ifGMII">
+ <type>java.lang.String</type>
+ <value>MII_GMII</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="use_mac_clken">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_use_internal_fifo">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_ecc">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="max_channels">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="use_misc_ports">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transceiver_type">
+ <type>java.lang.String</type>
+ <value>GXB</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_hd_logic">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_gmii_loopback">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_sup_addr">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="stat_cnt_ena">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ext_stat_cnt_ena">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ena_hash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_shift16">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_mac_flow_ctrl">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_mac_vlan">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_magic_detect">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="useMDIO">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mdio_clk_div">
+ <type>int</type>
+ <value>40</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_ena">
+ <type>int</type>
+ <value>32</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="eg_addr">
+ <type>int</type>
+ <value>11</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ing_addr">
+ <type>int</type>
+ <value>11</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="phy_identifier">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_sgmii">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="export_pwrdn">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_alt_reconfig">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="starting_channel_number">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="phyip_pll_type">
+ <type>java.lang.String</type>
+ <value>CMU</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="phyip_pll_base_data_rate">
+ <type>java.lang.String</type>
+ <value>1250 Mbps</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="phyip_en_synce_support">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="phyip_pma_bonding_mode">
+ <type>java.lang.String</type>
+ <value>x1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="nf_phyip_rcfg_enable">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="XCVR_RCFG_JTAG_ENABLE">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="XCVR_SET_CAPABILITY_REG_ENABLE">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="XCVR_SET_USER_IDENTIFIER">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="XCVR_SET_CSR_SOFT_LOGIC_ENABLE">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="XCVR_SET_PRBS_SOFT_LOGIC_ENABLE">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="nf_lvds_iopll_num_channels">
+ <type>int</type>
+ <value>4</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_timestamping">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_ptp_1step">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="tstamp_fp_width">
+ <type>int</type>
+ <value>4</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+ <type>java.lang.String</type>
+ <value>10AS066N3F40I2LG</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+ <type>java.lang.String</type>
+ <value>2</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="control_port_clock_connection" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="reset_connection" kind="reset_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>control_port_clock_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="synchronousEdges">
+ <type>com.altera.sopcmodel.reset.Reset$Edges</type>
+ <value>DEASSERT</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <port>
+ <name>reset</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>reset</role>
+ </port>
+ </interface>
+ <interface name="control_port" kind="avalon_slave" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>embeddedsw.configuration.isFlash</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isMemoryDevice</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isNonVolatileStorage</name>
+ <value>0</value>
+ </assignment>
+ <assignment>
+ <name>embeddedsw.configuration.isPrintableDevice</name>
+ <value>0</value>
+ </assignment>
+ <parameter name="addressAlignment">
+ <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
+ <value>DYNAMIC</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressGroup">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressSpan">
+ <type>java.math.BigInteger</type>
+ <value>1024</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="addressUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="alwaysBurstMaxBurst">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>control_port_clock_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value>reset_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgedAddressOffset">
+ <type>java.math.BigInteger</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bridgesToMaster">
+ <type>com.altera.entityinterfaces.IConnectionPoint</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstOnBurstBoundariesOnly">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="burstcountUnits">
+ <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
+ <value>WORDS</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="constantBurstBehavior">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="explicitAddressSpan">
+ <type>java.math.BigInteger</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="holdTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="interleaveBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isBigEndian">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isFlash">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isMemoryDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="isNonVolatileStorage">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="linewrapBursts">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingReadTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maximumPendingWriteTransactions">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="minimumUninterruptedRunLength">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="printableDevice">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerIncomingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="registerOutgoingSignals">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="setupTime">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="timingUnits">
+ <type>com.altera.sopcmodel.avalon.TimingUnits</type>
+ <value>Cycles</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="transparentBridge">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="wellBehavedWaitrequest">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitStates">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="writeWaitTime">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <port>
+ <name>reg_data_out</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>readdata</role>
+ </port>
+ <port>
+ <name>reg_rd</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>read</role>
+ </port>
+ <port>
+ <name>reg_data_in</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>writedata</role>
+ </port>
+ <port>
+ <name>reg_wr</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>write</role>
+ </port>
+ <port>
+ <name>reg_busy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>waitrequest</role>
+ </port>
+ <port>
+ <name>reg_addr</name>
+ <direction>Input</direction>
+ <width>8</width>
+ <role>address</role>
+ </port>
+ </interface>
+ <interface name="receive_clock_connection" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>ff_rx_clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="transmit_clock_connection" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>ff_tx_clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="receive" kind="avalon_streaming_source" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>receive_clock_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value>reset_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="beatsPerCycle">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dataBitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="emptyWithinPacket">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="errorDescriptor">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="firstSymbolInHighOrderBits">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="highOrderSymbolAtMSB">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maxChannel">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="packetDescription">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readyLatency">
+ <type>int</type>
+ <value>2</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="symbolsPerBeat">
+ <type>int</type>
+ <value>4</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon_streaming</type>
+ <isStart>true</isStart>
+ <port>
+ <name>ff_rx_data</name>
+ <direction>Output</direction>
+ <width>32</width>
+ <role>data</role>
+ </port>
+ <port>
+ <name>ff_rx_eop</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>endofpacket</role>
+ </port>
+ <port>
+ <name>rx_err</name>
+ <direction>Output</direction>
+ <width>6</width>
+ <role>error</role>
+ </port>
+ <port>
+ <name>ff_rx_mod</name>
+ <direction>Output</direction>
+ <width>2</width>
+ <role>empty</role>
+ </port>
+ <port>
+ <name>ff_rx_rdy</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>ready</role>
+ </port>
+ <port>
+ <name>ff_rx_sop</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>startofpacket</role>
+ </port>
+ <port>
+ <name>ff_rx_dval</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>valid</role>
+ </port>
+ </interface>
+ <interface name="transmit" kind="avalon_streaming_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value>transmit_clock_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value>reset_connection</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="beatsPerCycle">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dataBitsPerSymbol">
+ <type>int</type>
+ <value>8</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="emptyWithinPacket">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="errorDescriptor">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="firstSymbolInHighOrderBits">
+ <type>boolean</type>
+ <value>true</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="highOrderSymbolAtMSB">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="maxChannel">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="packetDescription">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="readyLatency">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="symbolsPerBeat">
+ <type>int</type>
+ <value>4</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>avalon_streaming</type>
+ <isStart>false</isStart>
+ <port>
+ <name>ff_tx_data</name>
+ <direction>Input</direction>
+ <width>32</width>
+ <role>data</role>
+ </port>
+ <port>
+ <name>ff_tx_eop</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>endofpacket</role>
+ </port>
+ <port>
+ <name>ff_tx_err</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>error</role>
+ </port>
+ <port>
+ <name>ff_tx_mod</name>
+ <direction>Input</direction>
+ <width>2</width>
+ <role>empty</role>
+ </port>
+ <port>
+ <name>ff_tx_rdy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ready</role>
+ </port>
+ <port>
+ <name>ff_tx_sop</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>startofpacket</role>
+ </port>
+ <port>
+ <name>ff_tx_wren</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>valid</role>
+ </port>
+ </interface>
+ <interface name="mac_mdio_connection" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>mdc</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>mdc</role>
+ </port>
+ <port>
+ <name>mdio_in</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>mdio_in</role>
+ </port>
+ <port>
+ <name>mdio_out</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>mdio_out</role>
+ </port>
+ <port>
+ <name>mdio_oen</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>mdio_oen</role>
+ </port>
+ </interface>
+ <interface name="mac_misc_connection" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>magic_wakeup</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>magic_wakeup</role>
+ </port>
+ <port>
+ <name>magic_sleep_n</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>magic_sleep_n</role>
+ </port>
+ <port>
+ <name>ff_tx_crc_fwd</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>ff_tx_crc_fwd</role>
+ </port>
+ <port>
+ <name>ff_tx_septy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_tx_septy</role>
+ </port>
+ <port>
+ <name>tx_ff_uflow</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>tx_ff_uflow</role>
+ </port>
+ <port>
+ <name>ff_tx_a_full</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_tx_a_full</role>
+ </port>
+ <port>
+ <name>ff_tx_a_empty</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_tx_a_empty</role>
+ </port>
+ <port>
+ <name>rx_err_stat</name>
+ <direction>Output</direction>
+ <width>18</width>
+ <role>rx_err_stat</role>
+ </port>
+ <port>
+ <name>rx_frm_type</name>
+ <direction>Output</direction>
+ <width>4</width>
+ <role>rx_frm_type</role>
+ </port>
+ <port>
+ <name>ff_rx_dsav</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_rx_dsav</role>
+ </port>
+ <port>
+ <name>ff_rx_a_full</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_rx_a_full</role>
+ </port>
+ <port>
+ <name>ff_rx_a_empty</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>ff_rx_a_empty</role>
+ </port>
+ </interface>
+ <interface name="pcs_ref_clk_clock_connection" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>ref_clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="status_led_connection" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>led_crs</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>crs</role>
+ </port>
+ <port>
+ <name>led_link</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>link</role>
+ </port>
+ <port>
+ <name>led_panel_link</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>panel_link</role>
+ </port>
+ <port>
+ <name>led_col</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>col</role>
+ </port>
+ <port>
+ <name>led_an</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>an</role>
+ </port>
+ <port>
+ <name>led_char_err</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>char_err</role>
+ </port>
+ <port>
+ <name>led_disp_err</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>disp_err</role>
+ </port>
+ </interface>
+ <interface name="serdes_control_connection" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_recovclkout</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>export</role>
+ </port>
+ </interface>
+ <interface name="serial_connection" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rxp</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>rxp</role>
+ </port>
+ <port>
+ <name>txp</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>txp</role>
+ </port>
+ </interface>
+ <interface name="tx_serial_clk" kind="hssi_serial_clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>hssi_serial_clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>tx_serial_clk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="rx_cdr_refclk" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_cdr_refclk</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="tx_analogreset" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>tx_analogreset</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>tx_analogreset</role>
+ </port>
+ </interface>
+ <interface name="tx_digitalreset" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>tx_digitalreset</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>tx_digitalreset</role>
+ </port>
+ </interface>
+ <interface name="rx_analogreset" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_analogreset</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>rx_analogreset</role>
+ </port>
+ </interface>
+ <interface name="rx_digitalreset" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_digitalreset</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>rx_digitalreset</role>
+ </port>
+ </interface>
+ <interface name="tx_cal_busy" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>tx_cal_busy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>tx_cal_busy</role>
+ </port>
+ </interface>
+ <interface name="rx_cal_busy" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_cal_busy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>rx_cal_busy</role>
+ </port>
+ </interface>
+ <interface name="rx_set_locktodata" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_set_locktodata</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>rx_set_locktodata</role>
+ </port>
+ </interface>
+ <interface name="rx_set_locktoref" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_set_locktoref</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>rx_set_locktoref</role>
+ </port>
+ </interface>
+ <interface name="rx_is_lockedtoref" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_is_lockedtoref</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>rx_is_lockedtoref</role>
+ </port>
+ </interface>
+ <interface name="rx_is_lockedtodata" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>rx_is_lockedtodata</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>rx_is_lockedtodata</role>
+ </port>
+ </interface>
+ </module>
+ <module
+ name="xcvr_atx_pll_a10_0"
+ kind="altera_xcvr_atx_pll_a10"
+ version="22.1"
+ path="xcvr_atx_pll_a10_0">
+ <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+ <parameter name="rcfg_debug">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_pll_reconfig">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_advanced_avmm_options">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_jtag_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_separate_avmm_busy">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_enable_avmm_busy_port">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_capability_reg_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_user_identifier">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_csr_soft_logic_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dbg_embedded_debug_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dbg_capability_reg_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dbg_user_identifier">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dbg_stat_soft_logic_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dbg_ctrl_soft_logic_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_file_prefix">
+ <type>java.lang.String</type>
+ <value>altera_xcvr_atx_pll_a10</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_sv_file_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_h_file_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_txt_file_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_mif_file_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_multi_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_rcfg_emb_strm_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_emb_strm_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_reduced_files_enable">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_profile_cnt">
+ <type>int</type>
+ <value>2</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_profile_select">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_profile_data0">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_profile_data1">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_profile_data2">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_profile_data3">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_profile_data4">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_profile_data5">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_profile_data6">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_profile_data7">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_params">
+ <type>[Ljava.lang.String;</type>
+ <value>rcfg_debug,enable_pll_reconfig,rcfg_jtag_enable,rcfg_separate_avmm_busy,rcfg_enable_avmm_busy_port,set_capability_reg_enable,set_user_identifier,set_csr_soft_logic_enable,enable_pld_atx_cal_busy_port,support_mode,prot_mode,bw_sel,refclk_cnt,refclk_index,primary_pll_buffer,enable_8G_path,enable_16G_path,enable_pcie_clk,enable_cascade_out,enable_hip_cal_done_port,set_hip_cal_en,set_output_clock_frequency,set_auto_reference_clock_frequency,set_manual_reference_clock_frequency,set_fref_clock_frequency,set_m_counter,set_ref_clk_div,set_l_counter,set_l_cascade_counter,set_l_cascade_predivider,set_k_counter,enable_mcgb,mcgb_div,enable_hfreq_clk,enable_mcgb_pcie_clksw,mcgb_aux_clkin_cnt,enable_bonding_clks,enable_fb_comp_bonding,pma_width,enable_pld_mcgb_cal_busy_port</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_param_labels">
+ <type>[Ljava.lang.String;</type>
+ <value>rcfg_debug,Enable dynamic reconfiguration,Enable Altera Debug Master Endpoint,Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE,Enable avmm_busy port,Enable capability registers,Set user-defined IP identifier,Enable control and status registers,enable_pld_atx_cal_busy_port,Support mode,Protocol mode,Bandwidth,Number of PLL reference clocks,Selected reference clock source,Primary PLL clock output buffer,Enable PLL GX clock output port,Enable PLL GT clock output port,Enable PCIe clock output port,Enable cascade clock output port,Enable calibration status ports for HIP,Enable PCIe hard IP calibration,PLL output frequency,PLL integer reference clock frequency,PLL fractional reference clock frequency,PLL fractional reference clock frequency,Multiply factor (M-Counter),Divide factor (N-Counter),Divide factor (L-Counter),Divide factor (L-Cascade Counter),predivide factor (L-Cascade Predivider),Fractional multiply factor (K),Include Master Clock Generation Block,Clock division factor,Enable x6/xN non-bonded high-speed clock output port,Enable PCIe clock switch interface,Number of auxiliary MCGB clock input ports.,Enable bonding clock output ports,Enable feedback compensation bonding,PMA interface width,enable_pld_mcgb_cal_busy_port</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_param_vals0">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_param_vals1">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_param_vals2">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_param_vals3">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_param_vals4">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_param_vals5">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_param_vals6">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="rcfg_param_vals7">
+ <type>[Ljava.lang.String;</type>
+ <value></value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_powerdown_mode">
+ <type>java.lang.String</type>
+ <value>powerup</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xmux_lc_scratch0_src">
+ <type>java.lang.String</type>
+ <value>scratch0_src_lvpecl</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xmux_lc_scratch1_src">
+ <type>java.lang.String</type>
+ <value>scratch1_src_lvpecl</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xmux_lc_scratch2_src">
+ <type>java.lang.String</type>
+ <value>scratch2_src_lvpecl</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xmux_lc_scratch3_src">
+ <type>java.lang.String</type>
+ <value>scratch3_src_lvpecl</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xmux_lc_scratch4_src">
+ <type>java.lang.String</type>
+ <value>scratch4_src_lvpecl</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xmux_refclk_src">
+ <type>java.lang.String</type>
+ <value>src_lvpecl</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_iqclk_sel">
+ <type>java.lang.String</type>
+ <value>power_down</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch0_src">
+ <type>java.lang.String</type>
+ <value>scratch0_power_down</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch1_src">
+ <type>java.lang.String</type>
+ <value>scratch1_power_down</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch2_src">
+ <type>java.lang.String</type>
+ <value>scratch2_power_down</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch3_src">
+ <type>java.lang.String</type>
+ <value>scratch3_power_down</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_xpm_iqref_mux_scratch4_src">
+ <type>java.lang.String</type>
+ <value>scratch4_power_down</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_refclk_select">
+ <type>java.lang.String</type>
+ <value>ref_iqclk0</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_lc_refclk_select_mux_silicon_rev">
+ <type>java.lang.String</type>
+ <value>20nm4</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter
+ name="hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping">
+ <type>java.lang.String</type>
+ <value>ref_iqclk0</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter
+ name="hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping">
+ <type>java.lang.String</type>
+ <value>power_down</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter
+ name="hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping">
+ <type>java.lang.String</type>
+ <value>power_down</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter
+ name="hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping">
+ <type>java.lang.String</type>
+ <value>power_down</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter
+ name="hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping">
+ <type>java.lang.String</type>
+ <value>power_down</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_silicon_rev">
+ <type>java.lang.String</type>
+ <value>20nm4</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_clk_divider">
+ <type>java.lang.String</type>
+ <value>div2_off</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_core_clk_lvpecl">
+ <type>java.lang.String</type>
+ <value>core_clk_lvpecl_off</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_enable_lvpecl">
+ <type>java.lang.String</type>
+ <value>lvpecl_enable</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_optimal">
+ <type>java.lang.String</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_powerdown_mode">
+ <type>java.lang.String</type>
+ <value>powerup</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_sel_pldclk">
+ <type>java.lang.String</type>
+ <value>iqclk_sel_lvpecl</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_sup_mode">
+ <type>java.lang.String</type>
+ <value>user_mode</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_term_tristate">
+ <type>java.lang.String</type>
+ <value>tristate_off</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_vcm_pup">
+ <type>java.lang.String</type>
+ <value>pup_off</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_clkbuf_sel">
+ <type>java.lang.String</type>
+ <value>high_vcm</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_refclk_divider_iostandard">
+ <type>java.lang.String</type>
+ <value>lvpecl</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_silicon_rev">
+ <type>java.lang.String</type>
+ <value>20nm4</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_is_cascaded_pll">
+ <type>java.lang.String</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_cgb_div">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_pma_width">
+ <type>int</type>
+ <value>64</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_lc_atb">
+ <type>java.lang.String</type>
+ <value>atb_selectdisable</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_cp_compensation_enable">
+ <type>java.lang.String</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_cp_current_setting">
+ <type>java.lang.String</type>
+ <value>cp_current_setting26</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_cp_testmode">
+ <type>java.lang.String</type>
+ <value>cp_normal</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_cp_lf_3rd_pole_freq">
+ <type>java.lang.String</type>
+ <value>lf_3rd_pole_setting1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_lf_cbig_size">
+ <type>java.lang.String</type>
+ <value>lf_cbig_setting4</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_cp_lf_order">
+ <type>java.lang.String</type>
+ <value>lf_3rd_order</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_lf_resistance">
+ <type>java.lang.String</type>
+ <value>lf_setting1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_lf_ripplecap">
+ <type>java.lang.String</type>
+ <value>lf_ripple_cap_0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_cal_status">
+ <type>java.lang.String</type>
+ <value>cal_in_progress</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_bonding">
+ <type>java.lang.String</type>
+ <value>pll_bonding</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_expected_lc_boost_voltage">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_power_rail_et">
+ <type>int</type>
+ <value>950</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_lc_vreg_boost_scratch">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_lc_vreg1_boost_scratch">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_clk_vreg_boost_scratch">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_mcgb_vreg_boost_scratch">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_vreg_boost_step_size">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_vreg1_boost_step_size">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_clk_vreg_boost_step_size">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_mcgb_vreg_boost_step_size">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_lc_vreg_boost_expected_voltage">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_lc_vreg1_boost_expected_voltage">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_clk_vreg_boost_expected_voltage">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dprio_mcgb_vreg_boost_expected_voltage">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_clk_high_perf_voltage">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_clk_mid_power_voltage">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_clk_low_power_voltage">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_tank_sel">
+ <type>java.lang.String</type>
+ <value>lctank1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_tank_band">
+ <type>java.lang.String</type>
+ <value>lc_band4</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_tank_voltage_coarse">
+ <type>java.lang.String</type>
+ <value>vreg_setting_coarse0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_tank_voltage_fine">
+ <type>java.lang.String</type>
+ <value>vreg_setting5</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_output_regulator_supply">
+ <type>java.lang.String</type>
+ <value>vreg1v_setting0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_overrange_voltage">
+ <type>java.lang.String</type>
+ <value>over_setting0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_underrange_voltage">
+ <type>java.lang.String</type>
+ <value>under_setting4</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_fb_select">
+ <type>java.lang.String</type>
+ <value>direct_fb</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_d2a_voltage">
+ <type>java.lang.String</type>
+ <value>d2a_setting_4</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dsm_mode">
+ <type>java.lang.String</type>
+ <value>dsm_mode_integer</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dsm_out_sel">
+ <type>java.lang.String</type>
+ <value>pll_dsm_disable</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dsm_ecn_bypass">
+ <type>java.lang.String</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dsm_ecn_test_en">
+ <type>java.lang.String</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dsm_fractional_division">
+ <type>java.lang.String</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_dsm_fractional_value_ready">
+ <type>java.lang.String</type>
+ <value>pll_k_ready</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_enable_lc_calibration">
+ <type>java.lang.String</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_enable_lc_vreg_calibration">
+ <type>java.lang.String</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_iqclk_mux_sel">
+ <type>java.lang.String</type>
+ <value>iqtxrxclk0</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_vco_bypass_enable">
+ <type>java.lang.String</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_l_counter">
+ <type>int</type>
+ <value>8</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_l_counter_enable">
+ <type>java.lang.String</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_cascadeclk_test">
+ <type>java.lang.String</type>
+ <value>cascadetest_off</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_hclk_divide">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_enable_hclk">
+ <type>java.lang.String</type>
+ <value>hclk_disabled</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_m_counter">
+ <type>int</type>
+ <value>40</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_ref_clk_div">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_bandwidth_range_high">
+ <type>java.lang.String</type>
+ <value>0 hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_bandwidth_range_low">
+ <type>java.lang.String</type>
+ <value>0 hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_bw_sel">
+ <type>java.lang.String</type>
+ <value>medium</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_calibration_mode">
+ <type>java.lang.String</type>
+ <value>cal_off</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_datarate">
+ <type>java.lang.String</type>
+ <value>2500000000 bps</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_device_variant">
+ <type>java.lang.String</type>
+ <value>device1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_max_pfd">
+ <type>java.lang.String</type>
+ <value>350000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_max_ref">
+ <type>java.lang.String</type>
+ <value>800000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_max_tank_0">
+ <type>java.lang.String</type>
+ <value>8800000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_max_tank_1">
+ <type>java.lang.String</type>
+ <value>11400000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_max_tank_2">
+ <type>java.lang.String</type>
+ <value>14400000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_max_vco">
+ <type>java.lang.String</type>
+ <value>14400000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_max_x1">
+ <type>java.lang.String</type>
+ <value>8700000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_min_pfd">
+ <type>java.lang.String</type>
+ <value>61440000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_min_ref">
+ <type>java.lang.String</type>
+ <value>61440000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_min_tank_0">
+ <type>java.lang.String</type>
+ <value>6500000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_min_tank_1">
+ <type>java.lang.String</type>
+ <value>8800000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_min_tank_2">
+ <type>java.lang.String</type>
+ <value>11400000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_min_vco">
+ <type>java.lang.String</type>
+ <value>7200000000 Hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_initial_settings">
+ <type>java.lang.String</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_l_counter_scratch">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_lc_mode">
+ <type>java.lang.String</type>
+ <value>lccmu_normal</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_n_counter_scratch">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_output_clock_frequency">
+ <type>java.lang.String</type>
+ <value>1250000000 Hz</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_power_mode">
+ <type>java.lang.String</type>
+ <value>low_power</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_powerdown_mode">
+ <type>java.lang.String</type>
+ <value>powerup</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_prot_mode">
+ <type>java.lang.String</type>
+ <value>basic_tx</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_reference_clock_frequency">
+ <type>java.lang.String</type>
+ <value>125000000 Hz</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_side">
+ <type>java.lang.String</type>
+ <value>side_unknown</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_pm_speed_grade">
+ <type>java.lang.String</type>
+ <value>i3</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_sup_mode">
+ <type>java.lang.String</type>
+ <value>user_mode</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_top_or_bottom">
+ <type>java.lang.String</type>
+ <value>tb_unknown</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_vccdreg_clk">
+ <type>java.lang.String</type>
+ <value>vreg_clk5</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_vccdreg_fb">
+ <type>java.lang.String</type>
+ <value>vreg_fb8</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_vccdreg_fw">
+ <type>java.lang.String</type>
+ <value>vreg_fw5</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_regulator_bypass">
+ <type>java.lang.String</type>
+ <value>reg_enable</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_vco_freq">
+ <type>java.lang.String</type>
+ <value>10000000000 Hz</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_max_vco_fractional">
+ <type>java.lang.String</type>
+ <value>0 hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_max_pfd_fractional">
+ <type>java.lang.String</type>
+ <value>0 hz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_min_fractional_percentage">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_max_fractional_percentage">
+ <type>int</type>
+ <value>100</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_analog_mode">
+ <type>java.lang.String</type>
+ <value>user_custom</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_is_otn">
+ <type>java.lang.String</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_is_sdi">
+ <type>java.lang.String</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_primary_use">
+ <type>java.lang.String</type>
+ <value>hssi_x1</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_fpll_refclk_selection">
+ <type>java.lang.String</type>
+ <value>select_vco_output</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_lc_to_fpll_l_counter_scratch">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_lc_to_fpll_l_counter">
+ <type>java.lang.String</type>
+ <value>lcounter_setting0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_pfd_delay_compensation">
+ <type>java.lang.String</type>
+ <value>normal_delay</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_xcpvco_xchgpmplf_cp_current_boost">
+ <type>java.lang.String</type>
+ <value>normal_setting</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_f_max_lcnt_fpll_cascading">
+ <type>java.lang.String</type>
+ <value>1200000000</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_pfd_pulse_width">
+ <type>java.lang.String</type>
+ <value>pulse_width_setting0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_enable_idle_atx_pll_support">
+ <type>java.lang.String</type>
+ <value>idle_none</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_advanced_options">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_hip_options">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_manual_configuration">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generate_docs">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generate_add_hdl_instance_example">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="device_family">
+ <type>java.lang.String</type>
+ <value>ARRIA10</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="device">
+ <type>java.lang.String</type>
+ <value>10AS066N3F40I2LG</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="base_device">
+ <type>java.lang.String</type>
+ <value>NIGHTFURY4</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ <sysinfo_type>PART_TRAIT</sysinfo_type>
+ <sysinfo_arg>BASE_DEVICE</sysinfo_arg>
+ </parameter>
+ <parameter name="test_mode">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_pld_atx_cal_busy_port">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_debug_ports_parameters">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="support_mode">
+ <type>java.lang.String</type>
+ <value>user_mode</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="message_level">
+ <type>java.lang.String</type>
+ <value>error</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="pma_speedgrade">
+ <type>java.lang.String</type>
+ <value>i3</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="device_revision">
+ <type>java.lang.String</type>
+ <value>20nm4</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="prot_mode">
+ <type>java.lang.String</type>
+ <value>Basic</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="prot_mode_fnl">
+ <type>java.lang.String</type>
+ <value>basic_tx</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="primary_use">
+ <type>java.lang.String</type>
+ <value>hssi_x1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="bw_sel">
+ <type>java.lang.String</type>
+ <value>medium</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="refclk_cnt">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="refclk_index">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="silicon_rev">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="fb_select_fnl">
+ <type>java.lang.String</type>
+ <value>direct_fb</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="primary_pll_buffer">
+ <type>java.lang.String</type>
+ <value>GX clock output buffer</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_8G_buffer_fnl">
+ <type>java.lang.String</type>
+ <value>true</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_16G_buffer_fnl">
+ <type>java.lang.String</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_8G_path">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_16G_path">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_pcie_clk">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_cascade_out">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_atx_to_fpll_cascade_out">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_hip_cal_done_port">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_hip_cal_en">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hip_cal_en">
+ <type>java.lang.String</type>
+ <value>disable</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="dsm_mode">
+ <type>java.lang.String</type>
+ <value>dsm_mode_integer</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_output_clock_frequency">
+ <type>double</type>
+ <value>1250.0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="output_clock_datarate">
+ <type>double</type>
+ <value>2500.0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="output_clock_frequency">
+ <type>java.lang.String</type>
+ <value>1250.0 MHz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="vco_freq">
+ <type>java.lang.String</type>
+ <value>10000.0 MHz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="datarate">
+ <type>java.lang.String</type>
+ <value>2500.0 Mbps</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_fractional">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_auto_reference_clock_frequency">
+ <type>double</type>
+ <value>125.0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_manual_reference_clock_frequency">
+ <type>double</type>
+ <value>200.0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="reference_clock_frequency_fnl">
+ <type>java.lang.String</type>
+ <value>125.000000 MHz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_fref_clock_frequency">
+ <type>double</type>
+ <value>156.25</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="feedback_clock_frequency_fnl">
+ <type>double</type>
+ <value>156.25</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="select_manual_config">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="m_counter">
+ <type>int</type>
+ <value>40</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="effective_m_counter">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_m_counter">
+ <type>int</type>
+ <value>24</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ref_clk_div">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_ref_clk_div">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="l_counter">
+ <type>int</type>
+ <value>8</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_l_counter">
+ <type>int</type>
+ <value>16</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="l_cascade_counter">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_l_cascade_counter">
+ <type>int</type>
+ <value>15</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="l_cascade_predivider">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_l_cascade_predivider">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="k_counter">
+ <type>long</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_k_counter">
+ <type>long</type>
+ <value>2000000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="auto_list">
+ <type>java.lang.String</type>
+ <value>61.728395 {m 81 effective_m 81 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 62.500000 {m 80 effective_m 80 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 63.291139 {m 79 effective_m 79 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 64.102564 {m 78 effective_m 78 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 64.935065 {m 77 effective_m 77 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 65.789474 {m 76 effective_m 76 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 66.666667 {m 75 effective_m 75 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 67.567568 {m 74 effective_m 74 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 68.493151 {m 73 effective_m 73 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 69.444444 {m 72 effective_m 72 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 70.422535 {m 71 effective_m 71 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 71.428571 {m 70 effective_m 70 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 72.463768 {m 69 effective_m 69 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 73.529412 {m 68 effective_m 68 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 74.626866 {m 67 effective_m 67 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 75.757576 {m 66 effective_m 66 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 76.923077 {m 65 effective_m 65 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 78.125000 {m 64 effective_m 64 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 79.365079 {m 63 effective_m 63 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 80.645161 {m 62 effective_m 62 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 81.967213 {m 61 effective_m 61 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 83.333333 {m 60 effective_m 60 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 84.745763 {m 59 effective_m 59 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 86.206897 {m 58 effective_m 58 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 87.719298 {m 57 effective_m 57 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 89.285714 {m 56 effective_m 56 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 90.909091 {m 55 effective_m 55 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 92.592593 {m 54 effective_m 54 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 94.339623 {m 53 effective_m 53 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 96.153846 {m 52 effective_m 52 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 98.039216 {m 51 effective_m 51 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 100.000000 {m 50 effective_m 50 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 102.040816 {m 49 effective_m 49 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 104.166667 {m 48 effective_m 48 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 106.382979 {m 47 effective_m 47 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 108.695652 {m 46 effective_m 46 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 111.111111 {m 45 effective_m 45 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 113.636364 {m 44 effective_m 44 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 116.279070 {m 43 effective_m 43 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 119.047619 {m 42 effective_m 42 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 121.951220 {m 41 effective_m 41 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 123.456790 {m 81 effective_m 81 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 125.000000 {m 40 effective_m 40 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 126.582278 {m 79 effective_m 79 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 128.205128 {m 39 effective_m 39 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 129.870130 {m 77 effective_m 77 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 131.578947 {m 38 effective_m 38 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 133.333333 {m 75 effective_m 75 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 135.135135 {m 37 effective_m 37 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 136.986301 {m 73 effective_m 73 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 138.888889 {m 36 effective_m 36 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 140.845070 {m 71 effective_m 71 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 142.857143 {m 35 effective_m 35 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 144.927536 {m 69 effective_m 69 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 147.058824 {m 34 effective_m 34 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 149.253731 {m 67 effective_m 67 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 151.515152 {m 33 effective_m 33 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 153.846154 {m 65 effective_m 65 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 156.250000 {m 32 effective_m 32 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 158.730159 {m 63 effective_m 63 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 161.290323 {m 31 effective_m 31 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 163.934426 {m 61 effective_m 61 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 166.666667 {m 30 effective_m 30 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 169.491525 {m 59 effective_m 59 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 172.413793 {m 29 effective_m 29 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 175.438596 {m 57 effective_m 57 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 178.571429 {m 28 effective_m 28 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 181.818182 {m 55 effective_m 55 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 185.185185 {m 27 effective_m 27 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 188.679245 {m 53 effective_m 53 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 192.307692 {m 26 effective_m 26 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 196.078431 {m 51 effective_m 51 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 200.000000 {m 25 effective_m 25 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 204.081633 {m 49 effective_m 49 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 208.333333 {m 24 effective_m 24 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 212.765957 {m 47 effective_m 47 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 217.391304 {m 23 effective_m 23 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 222.222222 {m 45 effective_m 45 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 227.272727 {m 22 effective_m 22 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 232.558140 {m 43 effective_m 43 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 238.095238 {m 21 effective_m 21 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 243.902439 {m 41 effective_m 41 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 246.913580 {m 81 effective_m 81 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 250.000000 {m 20 effective_m 20 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 253.164557 {m 79 effective_m 79 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 256.410256 {m 39 effective_m 39 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 259.740260 {m 77 effective_m 77 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 263.157895 {m 19 effective_m 19 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 266.666667 {m 75 effective_m 75 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 270.270270 {m 37 effective_m 37 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 273.972603 {m 73 effective_m 73 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 277.777778 {m 18 effective_m 18 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 281.690141 {m 71 effective_m 71 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 285.714286 {m 35 effective_m 35 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 289.855072 {m 69 effective_m 69 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 294.117647 {m 17 effective_m 17 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 298.507463 {m 67 effective_m 67 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 303.030303 {m 33 effective_m 33 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 307.692308 {m 65 effective_m 65 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 312.500000 {m 16 effective_m 16 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 317.460317 {m 63 effective_m 63 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 322.580645 {m 31 effective_m 31 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 327.868852 {m 61 effective_m 61 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 333.333333 {m 15 effective_m 15 n 1 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 338.983051 {m 59 effective_m 59 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 344.827586 {m 29 effective_m 29 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 350.877193 {m 57 effective_m 57 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 357.142857 {m 28 effective_m 28 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 363.636364 {m 55 effective_m 55 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 370.370370 {m 27 effective_m 27 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 377.358491 {m 53 effective_m 53 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 384.615385 {m 26 effective_m 26 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 392.156863 {m 51 effective_m 51 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 400.000000 {m 25 effective_m 25 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 408.163265 {m 49 effective_m 49 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 416.666667 {m 24 effective_m 24 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 425.531915 {m 47 effective_m 47 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 434.782609 {m 23 effective_m 23 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 444.444444 {m 45 effective_m 45 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 454.545455 {m 22 effective_m 22 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 465.116279 {m 43 effective_m 43 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 476.190476 {m 21 effective_m 21 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 487.804878 {m 41 effective_m 41 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 493.827160 {m 81 effective_m 81 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 500.000000 {m 20 effective_m 20 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 506.329114 {m 79 effective_m 79 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 512.820513 {m 39 effective_m 39 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 519.480519 {m 77 effective_m 77 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 526.315789 {m 19 effective_m 19 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 533.333333 {m 75 effective_m 75 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 540.540541 {m 37 effective_m 37 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 547.945205 {m 73 effective_m 73 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 555.555556 {m 18 effective_m 18 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 563.380282 {m 71 effective_m 71 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 571.428571 {m 35 effective_m 35 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 579.710145 {m 69 effective_m 69 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 588.235294 {m 17 effective_m 17 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 597.014925 {m 67 effective_m 67 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 606.060606 {m 33 effective_m 33 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 615.384615 {m 65 effective_m 65 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 625.000000 {m 16 effective_m 16 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 634.920635 {m 63 effective_m 63 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 645.161290 {m 31 effective_m 31 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 655.737705 {m 61 effective_m 61 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 666.666667 {m 15 effective_m 15 n 2 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 677.966102 {m 59 effective_m 59 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 689.655172 {m 29 effective_m 29 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 701.754386 {m 57 effective_m 57 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 714.285714 {m 28 effective_m 28 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 727.272727 {m 55 effective_m 55 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 740.740741 {m 27 effective_m 27 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 754.716981 {m 53 effective_m 53 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 769.230769 {m 26 effective_m 26 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 784.313725 {m 51 effective_m 51 n 8 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0} 800.000000 {m 25 effective_m 25 n 4 l 8 l_cascade 1 l_cascade_predivider 1 k 1 tank_sel lctank2 tank_band lc_band0}</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="manual_list">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="pll_setting">
+ <type>java.lang.String</type>
+ <value>refclk {125.000000 MHz} m_cnt 40 n_cnt 1 l_cnt 8 k_cnt 1 l_cascade 1 l_cascade_predivider 1 outclk {1250.0 MHz}</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_fb_comp_bonding_fnl">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="check_output_ports_pll">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="iqclk_mux_sel">
+ <type>java.lang.String</type>
+ <value>iqtxrxclk0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="set_altera_xcvr_atx_pll_a10_calibration_en">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="calibration_en">
+ <type>java.lang.String</type>
+ <value>enable</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_analog_resets">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_ext_lockdetect_ports">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="is_c10">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="atx_pll_bonding_mode">
+ <type>java.lang.String</type>
+ <value>cpri_bonding</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="lc_refclk_select">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_mcgb">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mcgb_div">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mcgb_div_fnl">
+ <type>int</type>
+ <value>1</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_hfreq_clk">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_mcgb_pcie_clksw">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mcgb_aux_clkin_cnt">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mcgb_in_clk_freq">
+ <type>double</type>
+ <value>1250.0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mcgb_out_datarate">
+ <type>double</type>
+ <value>2500.0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_bonding_clks">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_fb_comp_bonding">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mcgb_enable_iqtxrxclk">
+ <type>java.lang.String</type>
+ <value>disable_iqtxrxclk</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="pma_width">
+ <type>int</type>
+ <value>64</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_mcgb_debug_ports_parameters">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="enable_pld_mcgb_cal_busy_port">
+ <type>int</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="check_output_ports_mcgb">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="is_protocol_PCIe">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mapped_output_clock_frequency">
+ <type>java.lang.String</type>
+ <value>1250.0 MHz</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mapped_primary_pll_buffer">
+ <type>java.lang.String</type>
+ <value>GX clock output buffer</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="mapped_hip_cal_done_port">
+ <type>int</type>
+ <value>0</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_prot_mode">
+ <type>java.lang.String</type>
+ <value>basic_tx</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_silicon_rev">
+ <type>java.lang.String</type>
+ <value>20nm4</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_x1_div_m_sel">
+ <type>java.lang.String</type>
+ <value>divbypass</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_cgb_enable_iqtxrxclk">
+ <type>java.lang.String</type>
+ <value>disable_iqtxrxclk</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_ser_mode">
+ <type>java.lang.String</type>
+ <value>sixty_four_bit</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_datarate">
+ <type>java.lang.String</type>
+ <value>2500000000 bps</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_cgb_power_down">
+ <type>java.lang.String</type>
+ <value>normal_cgb</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_observe_cgb_clocks">
+ <type>java.lang.String</type>
+ <value>observe_nothing</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_op_mode">
+ <type>java.lang.String</type>
+ <value>enabled</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_tx_ucontrol_reset_pcie">
+ <type>java.lang.String</type>
+ <value>pcscorehip_controls_mcgb</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_vccdreg_output">
+ <type>java.lang.String</type>
+ <value>vccdreg_nominal</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_input_select">
+ <type>java.lang.String</type>
+ <value>lcpll_top</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="hssi_pma_cgb_master_input_select_gen3">
+ <type>java.lang.String</type>
+ <value>unused</value>
+ <derived>true</derived>
+ <enabled>false</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="gui_parameter_list">
+ <type>[Ljava.lang.String;</type>
+ <value>K counter (valid in fractional mode),L counter (valid in non-cascade mode),M counter,N counter,L cascade predivider/VCO divider(valid in cascade mode) ,L cascade counter (valid in cascade mode),PLL output frequency,vco_freq,datarate</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="gui_parameter_values">
+ <type>[Ljava.lang.String;</type>
+ <value>1,8,40,1,select_vco_output,1,1250.0 MHz,10000.0 MHz,2500.0 Mbps</value>
+ <derived>true</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <interface name="pll_powerdown" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>pll_powerdown</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>pll_powerdown</role>
+ </port>
+ </interface>
+ <interface name="pll_refclk0" kind="clock_sink" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>input</value>
+ </assignment>
+ <parameter name="externallyDriven">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="ptfSchematicName">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>false</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <port>
+ <name>pll_refclk0</name>
+ <direction>Input</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="tx_serial_clk" kind="hssi_serial_clock_source" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="clockRate">
+ <type>long</type>
+ <value>0</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>hssi_serial_clock</type>
+ <isStart>true</isStart>
+ <port>
+ <name>tx_serial_clk</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>clk</role>
+ </port>
+ </interface>
+ <interface name="pll_locked" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>pll_locked</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>pll_locked</role>
+ </port>
+ </interface>
+ <interface name="pll_cal_busy" kind="conduit_end" version="22.1">
+ <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+ <assignment>
+ <name>ui.blockdiagram.direction</name>
+ <value>output</value>
+ </assignment>
+ <parameter name="associatedClock">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="associatedReset">
+ <type>java.lang.String</type>
+ <value></value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <port>
+ <name>pll_cal_busy</name>
+ <direction>Output</direction>
+ <width>1</width>
+ <role>pll_cal_busy</role>
+ </port>
+ </interface>
+ </module>
+ <connection
+ name="a10_hps_clk_0.clk/a10_hps_bridges.clock_sink"
+ kind="clock"
+ version="22.1"
+ start="a10_hps_clk_0.clk"
+ end="a10_hps_bridges.clock_sink">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>a10_hps_bridges</endModule>
+ <endConnectionPoint>clock_sink</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_clk_0.clk_reset/a10_hps_bridges.reset_sink"
+ kind="reset"
+ version="22.1"
+ start="a10_hps_clk_0.clk_reset"
+ end="a10_hps_bridges.reset_sink">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_clk_0</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>a10_hps_bridges</endModule>
+ <endConnectionPoint>reset_sink</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_bridges.axi_h2f"
+ kind="avalon"
+ version="22.1"
+ start="a10_hps_arm_a9_0.altera_axi_master"
+ end="a10_hps_bridges.axi_h2f">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xc0000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_arm_a9_0</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
+ <endModule>a10_hps_bridges</endModule>
+ <endConnectionPoint>axi_h2f</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_bridges.axi_h2f"
+ kind="avalon"
+ version="22.1"
+ start="a10_hps_arm_a9_1.altera_axi_master"
+ end="a10_hps_bridges.axi_h2f">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xc0000000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_arm_a9_1</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
+ <endModule>a10_hps_bridges</endModule>
+ <endConnectionPoint>axi_h2f</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_bridges.axi_h2f_lw"
+ kind="avalon"
+ version="22.1"
+ start="a10_hps_arm_a9_0.altera_axi_master"
+ end="a10_hps_bridges.axi_h2f_lw">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xff200000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
+ <type>boolean</type>
+ <value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -37161,53 +45097,220 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_1</startModule>
+ <startModule>a10_hps_arm_a9_1</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
+ <endModule>a10_hps_arm_gic_0</endModule>
+ <endConnectionPoint>axi_slave1</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_clk_0.clk_reset/a10_hps_baum_clkmgr.reset_sink"
+ kind="reset"
+ version="22.1"
+ start="a10_hps_clk_0.clk_reset"
+ end="a10_hps_baum_clkmgr.reset_sink">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_clk_0</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>a10_hps_baum_clkmgr</endModule>
+ <endConnectionPoint>reset_sink</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_cb_intosc_hs_div2_clk.clk/a10_hps_baum_clkmgr.cb_intosc_hs_div2_clk"
+ kind="clock"
+ version="22.1"
+ start="a10_hps_cb_intosc_hs_div2_clk.clk"
+ end="a10_hps_baum_clkmgr.cb_intosc_hs_div2_clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_cb_intosc_hs_div2_clk</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>a10_hps_baum_clkmgr</endModule>
+ <endConnectionPoint>cb_intosc_hs_div2_clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_cb_intosc_ls_clk.clk/a10_hps_baum_clkmgr.cb_intosc_ls_clk"
+ kind="clock"
+ version="22.1"
+ start="a10_hps_cb_intosc_ls_clk.clk"
+ end="a10_hps_baum_clkmgr.cb_intosc_ls_clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_cb_intosc_ls_clk</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>a10_hps_baum_clkmgr</endModule>
+ <endConnectionPoint>cb_intosc_ls_clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_f2s_free_clk.clk/a10_hps_baum_clkmgr.f2s_free_clk"
+ kind="clock"
+ version="22.1"
+ start="a10_hps_f2s_free_clk.clk"
+ end="a10_hps_baum_clkmgr.f2s_free_clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_f2s_free_clk</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>a10_hps_baum_clkmgr</endModule>
+ <endConnectionPoint>f2s_free_clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_eosc1.clk/a10_hps_baum_clkmgr.eosc1"
+ kind="clock"
+ version="22.1"
+ start="a10_hps_eosc1.clk"
+ end="a10_hps_baum_clkmgr.eosc1">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_eosc1</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>a10_hps_baum_clkmgr</endModule>
+ <endConnectionPoint>eosc1</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_baum_clkmgr.axi_slave0"
+ kind="avalon"
+ version="22.1"
+ start="a10_hps_arm_a9_0.altera_axi_master"
+ end="a10_hps_baum_clkmgr.axi_slave0">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xffd04000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_arm_gic_0</endModule>
- <endConnectionPoint>axi_slave1</endConnectionPoint>
+ <endModule>a10_hps_baum_clkmgr</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_baum_clkmgr.reset_sink"
- kind="reset"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_baum_clkmgr.axi_slave0"
+ kind="avalon"
version="22.1"
- start="a10_hps_clk_0.clk_reset"
- end="a10_hps_baum_clkmgr.reset_sink">
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
+ start="a10_hps_arm_a9_1.altera_axi_master"
+ end="a10_hps_baum_clkmgr.axi_slave0">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_baum_clkmgr</endModule>
- <endConnectionPoint>reset_sink</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_cb_intosc_hs_div2_clk.clk/a10_hps_baum_clkmgr.cb_intosc_hs_div2_clk"
- kind="clock"
- version="22.1"
- start="a10_hps_cb_intosc_hs_div2_clk.clk"
- end="a10_hps_baum_clkmgr.cb_intosc_hs_div2_clk">
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xffd04000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="generateLegacySim">
+ <parameter name="defaultConnection">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -37215,17 +45318,6 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_cb_intosc_hs_div2_clk</startModule>
- <startConnectionPoint>clk</startConnectionPoint>
- <endModule>a10_hps_baum_clkmgr</endModule>
- <endConnectionPoint>cb_intosc_hs_div2_clk</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_cb_intosc_ls_clk.clk/a10_hps_baum_clkmgr.cb_intosc_ls_clk"
- kind="clock"
- version="22.1"
- start="a10_hps_cb_intosc_ls_clk.clk"
- end="a10_hps_baum_clkmgr.cb_intosc_ls_clk">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37242,17 +45334,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_cb_intosc_ls_clk</startModule>
- <startConnectionPoint>clk</startConnectionPoint>
+ <startModule>a10_hps_arm_a9_1</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
<endModule>a10_hps_baum_clkmgr</endModule>
- <endConnectionPoint>cb_intosc_ls_clk</endConnectionPoint>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_f2s_free_clk.clk/a10_hps_baum_clkmgr.f2s_free_clk"
+ name="a10_hps_clk_0.clk/a10_hps_mpu_reg_l2_MPUL2.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_f2s_free_clk.clk"
- end="a10_hps_baum_clkmgr.f2s_free_clk">
+ start="a10_hps_clk_0.clk"
+ end="a10_hps_mpu_reg_l2_MPUL2.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37269,17 +45361,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_f2s_free_clk</startModule>
+ <startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
- <endModule>a10_hps_baum_clkmgr</endModule>
- <endConnectionPoint>f2s_free_clk</endConnectionPoint>
+ <endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
+ <endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_eosc1.clk/a10_hps_baum_clkmgr.eosc1"
- kind="clock"
+ name="a10_hps_clk_0.clk_reset/a10_hps_mpu_reg_l2_MPUL2.reset_sink"
+ kind="reset"
version="22.1"
- start="a10_hps_eosc1.clk"
- end="a10_hps_baum_clkmgr.eosc1">
+ start="a10_hps_clk_0.clk_reset"
+ end="a10_hps_mpu_reg_l2_MPUL2.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37296,17 +45388,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_eosc1</startModule>
- <startConnectionPoint>clk</startConnectionPoint>
- <endModule>a10_hps_baum_clkmgr</endModule>
- <endConnectionPoint>eosc1</endConnectionPoint>
+ <startModule>a10_hps_clk_0</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
+ <endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_baum_clkmgr.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_mpu_reg_l2_MPUL2.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_baum_clkmgr.axi_slave0">
+ end="a10_hps_mpu_reg_l2_MPUL2.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -37317,7 +45409,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd04000</value>
+ <value>0xfffff000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -37349,15 +45441,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_baum_clkmgr</endModule>
+ <endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_baum_clkmgr.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_mpu_reg_l2_MPUL2.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_baum_clkmgr.axi_slave0">
+ end="a10_hps_mpu_reg_l2_MPUL2.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -37368,7 +45460,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd04000</value>
+ <value>0xfffff000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -37400,15 +45492,23 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_baum_clkmgr</endModule>
+ <endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk/a10_hps_mpu_reg_l2_MPUL2.clock_sink"
- kind="clock"
+ name="a10_hps_arm_gic_0.irq_rx_offset_0/a10_hps_mpu_reg_l2_MPUL2.interrupt_sender"
+ kind="interrupt"
version="22.1"
- start="a10_hps_clk_0.clk"
- end="a10_hps_mpu_reg_l2_MPUL2.clock_sink">
+ start="a10_hps_arm_gic_0.irq_rx_offset_0"
+ end="a10_hps_mpu_reg_l2_MPUL2.interrupt_sender">
+ <parameter name="irqNumber">
+ <type>int</type>
+ <value>18</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37425,17 +45525,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk</startConnectionPoint>
+ <startModule>a10_hps_arm_gic_0</startModule>
+ <startConnectionPoint>irq_rx_offset_0</startConnectionPoint>
<endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
- <endConnectionPoint>clock_sink</endConnectionPoint>
+ <endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_mpu_reg_l2_MPUL2.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_dma_DMASECURE.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_mpu_reg_l2_MPUL2.reset_sink">
+ end="a10_hps_i_dma_DMASECURE.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37454,15 +45554,42 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
+ <endModule>a10_hps_i_dma_DMASECURE</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_mpu_reg_l2_MPUL2.axi_slave0"
+ name="a10_hps_baum_clkmgr.l4_main_clk/a10_hps_i_dma_DMASECURE.apb_pclk"
+ kind="clock"
+ version="22.1"
+ start="a10_hps_baum_clkmgr.l4_main_clk"
+ end="a10_hps_i_dma_DMASECURE.apb_pclk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_baum_clkmgr</startModule>
+ <startConnectionPoint>l4_main_clk</startConnectionPoint>
+ <endModule>a10_hps_i_dma_DMASECURE</endModule>
+ <endConnectionPoint>apb_pclk</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_dma_DMASECURE.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_mpu_reg_l2_MPUL2.axi_slave0">
+ end="a10_hps_i_dma_DMASECURE.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -37473,7 +45600,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xfffff000</value>
+ <value>0xffda1000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -37505,15 +45632,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
+ <endModule>a10_hps_i_dma_DMASECURE</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_mpu_reg_l2_MPUL2.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_dma_DMASECURE.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_mpu_reg_l2_MPUL2.axi_slave0">
+ end="a10_hps_i_dma_DMASECURE.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -37524,7 +45651,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xfffff000</value>
+ <value>0xffda1000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -37556,18 +45683,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
+ <endModule>a10_hps_i_dma_DMASECURE</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_0/a10_hps_mpu_reg_l2_MPUL2.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_dma_DMASECURE.interrupt_sender"
kind="interrupt"
version="22.1"
- start="a10_hps_arm_gic_0.irq_rx_offset_0"
- end="a10_hps_mpu_reg_l2_MPUL2.interrupt_sender">
+ start="a10_hps_arm_gic_0.irq_rx_offset_83"
+ end="a10_hps_i_dma_DMASECURE.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>18</value>
+ <value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -37590,16 +45717,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
- <startConnectionPoint>irq_rx_offset_0</startConnectionPoint>
- <endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
+ <startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
+ <endModule>a10_hps_i_dma_DMASECURE</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_dma_DMASECURE.reset_sink"
- kind="reset"
+ name="a10_hps_clk_0.clk/a10_hps_i_sys_mgr_core.clock_sink"
+ kind="clock"
version="22.1"
- start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_dma_DMASECURE.reset_sink">
+ start="a10_hps_clk_0.clk"
+ end="a10_hps_i_sys_mgr_core.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37617,16 +45744,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_dma_DMASECURE</endModule>
- <endConnectionPoint>reset_sink</endConnectionPoint>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>a10_hps_i_sys_mgr_core</endModule>
+ <endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_main_clk/a10_hps_i_dma_DMASECURE.apb_pclk"
- kind="clock"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_sys_mgr_core.reset_sink"
+ kind="reset"
version="22.1"
- start="a10_hps_baum_clkmgr.l4_main_clk"
- end="a10_hps_i_dma_DMASECURE.apb_pclk">
+ start="a10_hps_clk_0.clk_reset"
+ end="a10_hps_i_sys_mgr_core.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37643,17 +45770,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>l4_main_clk</startConnectionPoint>
- <endModule>a10_hps_i_dma_DMASECURE</endModule>
- <endConnectionPoint>apb_pclk</endConnectionPoint>
+ <startModule>a10_hps_clk_0</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>a10_hps_i_sys_mgr_core</endModule>
+ <endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_dma_DMASECURE.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_sys_mgr_core.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_dma_DMASECURE.axi_slave0">
+ end="a10_hps_i_sys_mgr_core.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -37664,7 +45791,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda1000</value>
+ <value>0xffd06000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -37696,15 +45823,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_dma_DMASECURE</endModule>
+ <endModule>a10_hps_i_sys_mgr_core</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_dma_DMASECURE.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_sys_mgr_core.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_dma_DMASECURE.axi_slave0">
+ end="a10_hps_i_sys_mgr_core.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -37715,7 +45842,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda1000</value>
+ <value>0xffd06000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -37747,50 +45874,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_dma_DMASECURE</endModule>
+ <endModule>a10_hps_i_sys_mgr_core</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_dma_DMASECURE.interrupt_sender"
- kind="interrupt"
- version="22.1"
- start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_dma_DMASECURE.interrupt_sender">
- <parameter name="irqNumber">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <startModule>a10_hps_arm_gic_0</startModule>
- <startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_dma_DMASECURE</endModule>
- <endConnectionPoint>interrupt_sender</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_clk_0.clk/a10_hps_i_sys_mgr_core.clock_sink"
+ name="a10_hps_clk_0.clk/a10_hps_i_rst_mgr_rstmgr.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_clk_0.clk"
- end="a10_hps_i_sys_mgr_core.clock_sink">
+ end="a10_hps_i_rst_mgr_rstmgr.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37809,15 +45901,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
- <endModule>a10_hps_i_sys_mgr_core</endModule>
+ <endModule>a10_hps_i_rst_mgr_rstmgr</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_sys_mgr_core.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_rst_mgr_rstmgr.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_sys_mgr_core.reset_sink">
+ end="a10_hps_i_rst_mgr_rstmgr.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37836,15 +45928,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_sys_mgr_core</endModule>
+ <endModule>a10_hps_i_rst_mgr_rstmgr</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_sys_mgr_core.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_rst_mgr_rstmgr.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_sys_mgr_core.axi_slave0">
+ end="a10_hps_i_rst_mgr_rstmgr.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -37855,7 +45947,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd06000</value>
+ <value>0xffd05000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -37887,15 +45979,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_sys_mgr_core</endModule>
+ <endModule>a10_hps_i_rst_mgr_rstmgr</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_sys_mgr_core.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_rst_mgr_rstmgr.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_sys_mgr_core.axi_slave0">
+ end="a10_hps_i_rst_mgr_rstmgr.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -37906,7 +45998,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd06000</value>
+ <value>0xffd05000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -37938,15 +46030,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_sys_mgr_core</endModule>
+ <endModule>a10_hps_i_rst_mgr_rstmgr</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk/a10_hps_i_rst_mgr_rstmgr.clock_sink"
+ name="a10_hps_clk_0.clk/a10_hps_i_fpga_mgr_fpgamgrregs.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_clk_0.clk"
- end="a10_hps_i_rst_mgr_rstmgr.clock_sink">
+ end="a10_hps_i_fpga_mgr_fpgamgrregs.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37965,15 +46057,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk</startConnectionPoint>
- <endModule>a10_hps_i_rst_mgr_rstmgr</endModule>
+ <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_rst_mgr_rstmgr.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_fpga_mgr_fpgamgrregs.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_rst_mgr_rstmgr.reset_sink">
+ end="a10_hps_i_fpga_mgr_fpgamgrregs.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -37992,15 +46084,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_rst_mgr_rstmgr</endModule>
+ <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_rst_mgr_rstmgr.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_rst_mgr_rstmgr.axi_slave0">
+ end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38011,7 +46103,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd05000</value>
+ <value>0xffd03000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38043,15 +46135,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_rst_mgr_rstmgr</endModule>
+ <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_rst_mgr_rstmgr.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_rst_mgr_rstmgr.axi_slave0">
+ end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38062,7 +46154,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd05000</value>
+ <value>0xffd03000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38094,24 +46186,32 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_rst_mgr_rstmgr</endModule>
+ <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk/a10_hps_i_fpga_mgr_fpgamgrregs.clock_sink"
- kind="clock"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1"
+ kind="avalon"
version="22.1"
- start="a10_hps_clk_0.clk"
- end="a10_hps_i_fpga_mgr_fpgamgrregs.clock_sink">
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
+ start="a10_hps_arm_a9_0.altera_axi_master"
+ end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="generateLegacySim">
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xffcfe400</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -38119,17 +46219,6 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk</startConnectionPoint>
- <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
- <endConnectionPoint>clock_sink</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_fpga_mgr_fpgamgrregs.reset_sink"
- kind="reset"
- version="22.1"
- start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_fpga_mgr_fpgamgrregs.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -38146,17 +46235,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk_reset</startConnectionPoint>
+ <startModule>a10_hps_arm_a9_0</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
<endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
- <endConnectionPoint>reset_sink</endConnectionPoint>
+ <endConnectionPoint>axi_slave1</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1"
kind="avalon"
version="22.1"
- start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0">
+ start="a10_hps_arm_a9_1.altera_axi_master"
+ end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38167,7 +46256,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd03000</value>
+ <value>0xffcfe400</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38197,34 +46286,34 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_0</startModule>
+ <startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
<endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <endConnectionPoint>axi_slave1</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0"
- kind="avalon"
+ name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_fpga_mgr_fpgamgrregs.interrupt_sender"
+ kind="interrupt"
version="22.1"
- start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0">
- <parameter name="arbitrationPriority">
+ start="a10_hps_arm_gic_0.irq_rx_offset_115"
+ end="a10_hps_i_fpga_mgr_fpgamgrregs.interrupt_sender">
+ <parameter name="irqNumber">
<type>int</type>
- <value>1</value>
+ <value>8</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xffd03000</value>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -38232,6 +46321,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>a10_hps_arm_gic_0</startModule>
+ <startConnectionPoint>irq_rx_offset_115</startConnectionPoint>
+ <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
+ <endConnectionPoint>interrupt_sender</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_clk_0.clk_reset/a10_hps_timer.reset_sink"
+ kind="reset"
+ version="22.1"
+ start="a10_hps_clk_0.clk_reset"
+ end="a10_hps_timer.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -38248,17 +46348,44 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_1</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>a10_hps_clk_0</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>a10_hps_timer</endModule>
+ <endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1"
+ name="a10_hps_baum_clkmgr.mpu_periph_clk/a10_hps_timer.clock_sink"
+ kind="clock"
+ version="22.1"
+ start="a10_hps_baum_clkmgr.mpu_periph_clk"
+ end="a10_hps_timer.clock_sink">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_baum_clkmgr</startModule>
+ <startConnectionPoint>mpu_periph_clk</startConnectionPoint>
+ <endModule>a10_hps_timer</endModule>
+ <endConnectionPoint>clock_sink</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1">
+ end="a10_hps_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38269,7 +46396,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffcfe400</value>
+ <value>0xffffc600</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38301,15 +46428,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
- <endConnectionPoint>axi_slave1</endConnectionPoint>
+ <endModule>a10_hps_timer</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1">
+ end="a10_hps_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38320,7 +46447,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffcfe400</value>
+ <value>0xffffc600</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38352,18 +46479,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
- <endConnectionPoint>axi_slave1</endConnectionPoint>
+ <endModule>a10_hps_timer</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_fpga_mgr_fpgamgrregs.interrupt_sender"
+ name="a10_hps_arm_gic_0.arm_gic_ppi/a10_hps_timer.interrupt_sender"
kind="interrupt"
version="22.1"
- start="a10_hps_arm_gic_0.irq_rx_offset_115"
- end="a10_hps_i_fpga_mgr_fpgamgrregs.interrupt_sender">
+ start="a10_hps_arm_gic_0.arm_gic_ppi"
+ end="a10_hps_timer.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>8</value>
+ <value>13</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38386,16 +46513,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
- <startConnectionPoint>irq_rx_offset_115</startConnectionPoint>
- <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
+ <startConnectionPoint>arm_gic_ppi</startConnectionPoint>
+ <endModule>a10_hps_timer</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_timer.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_timer_sp_0_timer.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_timer.reset_sink">
+ end="a10_hps_i_timer_sp_0_timer.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -38414,15 +46541,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_timer</endModule>
+ <endModule>a10_hps_i_timer_sp_0_timer</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.mpu_periph_clk/a10_hps_timer.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_timer_sp_0_timer.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.mpu_periph_clk"
- end="a10_hps_timer.clock_sink">
+ start="a10_hps_baum_clkmgr.l4_sp_clk"
+ end="a10_hps_i_timer_sp_0_timer.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -38440,16 +46567,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>mpu_periph_clk</startConnectionPoint>
- <endModule>a10_hps_timer</endModule>
+ <startConnectionPoint>l4_sp_clk</startConnectionPoint>
+ <endModule>a10_hps_i_timer_sp_0_timer</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_timer.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_timer_sp_0_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_timer.axi_slave0">
+ end="a10_hps_i_timer_sp_0_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38460,7 +46587,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffffc600</value>
+ <value>0xffc02700</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38492,15 +46619,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_timer</endModule>
+ <endModule>a10_hps_i_timer_sp_0_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_timer.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_timer_sp_0_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_timer.axi_slave0">
+ end="a10_hps_i_timer_sp_0_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38511,7 +46638,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffffc600</value>
+ <value>0xffc02700</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38543,18 +46670,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_timer</endModule>
+ <endModule>a10_hps_i_timer_sp_0_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.arm_gic_ppi/a10_hps_timer.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_timer_sp_0_timer.interrupt_sender"
kind="interrupt"
version="22.1"
- start="a10_hps_arm_gic_0.arm_gic_ppi"
- end="a10_hps_timer.interrupt_sender">
+ start="a10_hps_arm_gic_0.irq_rx_offset_115"
+ end="a10_hps_i_timer_sp_0_timer.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>13</value>
+ <value>0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38577,16 +46704,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
- <startConnectionPoint>arm_gic_ppi</startConnectionPoint>
- <endModule>a10_hps_timer</endModule>
+ <startConnectionPoint>irq_rx_offset_115</startConnectionPoint>
+ <endModule>a10_hps_i_timer_sp_0_timer</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_timer_sp_0_timer.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_timer_sp_1_timer.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_timer_sp_0_timer.reset_sink">
+ end="a10_hps_i_timer_sp_1_timer.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -38605,15 +46732,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_0_timer</endModule>
+ <endModule>a10_hps_i_timer_sp_1_timer</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_timer_sp_0_timer.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_timer_sp_1_timer.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_sp_clk"
- end="a10_hps_i_timer_sp_0_timer.clock_sink">
+ end="a10_hps_i_timer_sp_1_timer.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -38632,15 +46759,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_sp_clk</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_0_timer</endModule>
+ <endModule>a10_hps_i_timer_sp_1_timer</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_timer_sp_0_timer.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_timer_sp_1_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_timer_sp_0_timer.axi_slave0">
+ end="a10_hps_i_timer_sp_1_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38651,7 +46778,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02700</value>
+ <value>0xffc02800</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38683,15 +46810,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_0_timer</endModule>
+ <endModule>a10_hps_i_timer_sp_1_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_timer_sp_0_timer.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_timer_sp_1_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_timer_sp_0_timer.axi_slave0">
+ end="a10_hps_i_timer_sp_1_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38702,7 +46829,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02700</value>
+ <value>0xffc02800</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38734,18 +46861,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_0_timer</endModule>
+ <endModule>a10_hps_i_timer_sp_1_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_timer_sp_0_timer.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_timer_sp_1_timer.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_115"
- end="a10_hps_i_timer_sp_0_timer.interrupt_sender">
+ end="a10_hps_i_timer_sp_1_timer.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>0</value>
+ <value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38769,15 +46896,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_115</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_0_timer</endModule>
+ <endModule>a10_hps_i_timer_sp_1_timer</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_timer_sp_1_timer.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_timer_sys_0_timer.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_timer_sp_1_timer.reset_sink">
+ end="a10_hps_i_timer_sys_0_timer.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -38796,15 +46923,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_1_timer</endModule>
+ <endModule>a10_hps_i_timer_sys_0_timer</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_timer_sp_1_timer.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sys_free_clk/a10_hps_i_timer_sys_0_timer.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.l4_sp_clk"
- end="a10_hps_i_timer_sp_1_timer.clock_sink">
+ start="a10_hps_baum_clkmgr.l4_sys_free_clk"
+ end="a10_hps_i_timer_sys_0_timer.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -38822,16 +46949,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>l4_sp_clk</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_1_timer</endModule>
+ <startConnectionPoint>l4_sys_free_clk</startConnectionPoint>
+ <endModule>a10_hps_i_timer_sys_0_timer</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_timer_sp_1_timer.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_timer_sys_0_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_timer_sp_1_timer.axi_slave0">
+ end="a10_hps_i_timer_sys_0_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38842,7 +46969,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02800</value>
+ <value>0xffd00000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38874,15 +47001,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_1_timer</endModule>
+ <endModule>a10_hps_i_timer_sys_0_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_timer_sp_1_timer.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_timer_sys_0_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_timer_sp_1_timer.axi_slave0">
+ end="a10_hps_i_timer_sys_0_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -38893,7 +47020,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02800</value>
+ <value>0xffd00000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38925,18 +47052,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_1_timer</endModule>
+ <endModule>a10_hps_i_timer_sys_0_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_timer_sp_1_timer.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_timer_sys_0_timer.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_115"
- end="a10_hps_i_timer_sp_1_timer.interrupt_sender">
+ end="a10_hps_i_timer_sys_0_timer.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>1</value>
+ <value>2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -38960,15 +47087,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_115</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_1_timer</endModule>
+ <endModule>a10_hps_i_timer_sys_0_timer</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_timer_sys_0_timer.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_timer_sys_1_timer.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_timer_sys_0_timer.reset_sink">
+ end="a10_hps_i_timer_sys_1_timer.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -38987,15 +47114,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_0_timer</endModule>
+ <endModule>a10_hps_i_timer_sys_1_timer</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sys_free_clk/a10_hps_i_timer_sys_0_timer.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sys_free_clk/a10_hps_i_timer_sys_1_timer.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_sys_free_clk"
- end="a10_hps_i_timer_sys_0_timer.clock_sink">
+ end="a10_hps_i_timer_sys_1_timer.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39014,15 +47141,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_sys_free_clk</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_0_timer</endModule>
+ <endModule>a10_hps_i_timer_sys_1_timer</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_timer_sys_0_timer.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_timer_sys_1_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_timer_sys_0_timer.axi_slave0">
+ end="a10_hps_i_timer_sys_1_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39033,7 +47160,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00000</value>
+ <value>0xffd00100</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39065,15 +47192,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_0_timer</endModule>
+ <endModule>a10_hps_i_timer_sys_1_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_timer_sys_0_timer.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_timer_sys_1_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_timer_sys_0_timer.axi_slave0">
+ end="a10_hps_i_timer_sys_1_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39084,7 +47211,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00000</value>
+ <value>0xffd00100</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39116,18 +47243,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_0_timer</endModule>
+ <endModule>a10_hps_i_timer_sys_1_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_timer_sys_0_timer.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_timer_sys_1_timer.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_115"
- end="a10_hps_i_timer_sys_0_timer.interrupt_sender">
+ end="a10_hps_i_timer_sys_1_timer.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>2</value>
+ <value>3</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39151,15 +47278,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_115</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_0_timer</endModule>
+ <endModule>a10_hps_i_timer_sys_1_timer</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_timer_sys_1_timer.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_watchdog_0_l4wd.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_timer_sys_1_timer.reset_sink">
+ end="a10_hps_i_watchdog_0_l4wd.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39178,15 +47305,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_1_timer</endModule>
+ <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sys_free_clk/a10_hps_i_timer_sys_1_timer.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sys_free_clk/a10_hps_i_watchdog_0_l4wd.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_sys_free_clk"
- end="a10_hps_i_timer_sys_1_timer.clock_sink">
+ end="a10_hps_i_watchdog_0_l4wd.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39205,15 +47332,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_sys_free_clk</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_1_timer</endModule>
+ <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_timer_sys_1_timer.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_watchdog_0_l4wd.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_timer_sys_1_timer.axi_slave0">
+ end="a10_hps_i_watchdog_0_l4wd.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39224,7 +47351,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00100</value>
+ <value>0xffd00200</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39256,15 +47383,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_1_timer</endModule>
+ <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_timer_sys_1_timer.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_watchdog_0_l4wd.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_timer_sys_1_timer.axi_slave0">
+ end="a10_hps_i_watchdog_0_l4wd.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39275,7 +47402,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00100</value>
+ <value>0xffd00200</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39307,18 +47434,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_1_timer</endModule>
+ <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_timer_sys_1_timer.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_watchdog_0_l4wd.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_115"
- end="a10_hps_i_timer_sys_1_timer.interrupt_sender">
+ end="a10_hps_i_watchdog_0_l4wd.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>3</value>
+ <value>4</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39342,15 +47469,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_115</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_1_timer</endModule>
+ <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_watchdog_0_l4wd.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_watchdog_1_l4wd.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_watchdog_0_l4wd.reset_sink">
+ end="a10_hps_i_watchdog_1_l4wd.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39369,15 +47496,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
+ <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sys_free_clk/a10_hps_i_watchdog_0_l4wd.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sys_free_clk/a10_hps_i_watchdog_1_l4wd.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_sys_free_clk"
- end="a10_hps_i_watchdog_0_l4wd.clock_sink">
+ end="a10_hps_i_watchdog_1_l4wd.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39396,15 +47523,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_sys_free_clk</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
+ <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_watchdog_0_l4wd.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_watchdog_1_l4wd.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_watchdog_0_l4wd.axi_slave0">
+ end="a10_hps_i_watchdog_1_l4wd.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39415,7 +47542,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00200</value>
+ <value>0xffd00300</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39447,15 +47574,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
+ <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_watchdog_0_l4wd.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_watchdog_1_l4wd.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_watchdog_0_l4wd.axi_slave0">
+ end="a10_hps_i_watchdog_1_l4wd.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39466,7 +47593,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00200</value>
+ <value>0xffd00300</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39498,18 +47625,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
+ <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_watchdog_0_l4wd.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_watchdog_1_l4wd.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_115"
- end="a10_hps_i_watchdog_0_l4wd.interrupt_sender">
+ end="a10_hps_i_watchdog_1_l4wd.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>4</value>
+ <value>5</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39533,15 +47660,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_115</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
+ <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_watchdog_1_l4wd.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_gpio_0_gpio.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_watchdog_1_l4wd.reset_sink">
+ end="a10_hps_i_gpio_0_gpio.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39560,15 +47687,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
+ <endModule>a10_hps_i_gpio_0_gpio</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sys_free_clk/a10_hps_i_watchdog_1_l4wd.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_gpio_0_gpio.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.l4_sys_free_clk"
- end="a10_hps_i_watchdog_1_l4wd.clock_sink">
+ start="a10_hps_baum_clkmgr.l4_mp_clk"
+ end="a10_hps_i_gpio_0_gpio.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39586,16 +47713,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>l4_sys_free_clk</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
+ <startConnectionPoint>l4_mp_clk</startConnectionPoint>
+ <endModule>a10_hps_i_gpio_0_gpio</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_watchdog_1_l4wd.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_gpio_0_gpio.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_watchdog_1_l4wd.axi_slave0">
+ end="a10_hps_i_gpio_0_gpio.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39606,7 +47733,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00300</value>
+ <value>0xffc02900</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39638,15 +47765,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
+ <endModule>a10_hps_i_gpio_0_gpio</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_watchdog_1_l4wd.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_gpio_0_gpio.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_watchdog_1_l4wd.axi_slave0">
+ end="a10_hps_i_gpio_0_gpio.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39657,7 +47784,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00300</value>
+ <value>0xffc02900</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39689,18 +47816,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
+ <endModule>a10_hps_i_gpio_0_gpio</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_115/a10_hps_i_watchdog_1_l4wd.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_gpio_0_gpio.interrupt_sender"
kind="interrupt"
version="22.1"
- start="a10_hps_arm_gic_0.irq_rx_offset_115"
- end="a10_hps_i_watchdog_1_l4wd.interrupt_sender">
+ start="a10_hps_arm_gic_0.irq_rx_offset_83"
+ end="a10_hps_i_gpio_0_gpio.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>5</value>
+ <value>29</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39723,16 +47850,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
- <startConnectionPoint>irq_rx_offset_115</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
+ <startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
+ <endModule>a10_hps_i_gpio_0_gpio</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_gpio_0_gpio.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_gpio_1_gpio.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_gpio_0_gpio.reset_sink">
+ end="a10_hps_i_gpio_1_gpio.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39751,15 +47878,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_gpio_0_gpio</endModule>
+ <endModule>a10_hps_i_gpio_1_gpio</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_gpio_0_gpio.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_gpio_1_gpio.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_mp_clk"
- end="a10_hps_i_gpio_0_gpio.clock_sink">
+ end="a10_hps_i_gpio_1_gpio.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39778,15 +47905,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_mp_clk</startConnectionPoint>
- <endModule>a10_hps_i_gpio_0_gpio</endModule>
+ <endModule>a10_hps_i_gpio_1_gpio</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_gpio_0_gpio.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_gpio_1_gpio.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_gpio_0_gpio.axi_slave0">
+ end="a10_hps_i_gpio_1_gpio.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39797,7 +47924,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02900</value>
+ <value>0xffc02a00</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39829,15 +47956,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_gpio_0_gpio</endModule>
+ <endModule>a10_hps_i_gpio_1_gpio</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_gpio_0_gpio.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_gpio_1_gpio.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_gpio_0_gpio.axi_slave0">
+ end="a10_hps_i_gpio_1_gpio.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39848,7 +47975,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02900</value>
+ <value>0xffc02a00</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39880,18 +48007,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_gpio_0_gpio</endModule>
+ <endModule>a10_hps_i_gpio_1_gpio</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_gpio_0_gpio.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_gpio_1_gpio.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_gpio_0_gpio.interrupt_sender">
+ end="a10_hps_i_gpio_1_gpio.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>29</value>
+ <value>30</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -39915,15 +48042,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_gpio_0_gpio</endModule>
+ <endModule>a10_hps_i_gpio_1_gpio</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_gpio_1_gpio.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_gpio_2_gpio.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_gpio_1_gpio.reset_sink">
+ end="a10_hps_i_gpio_2_gpio.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39942,15 +48069,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_gpio_1_gpio</endModule>
+ <endModule>a10_hps_i_gpio_2_gpio</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_gpio_1_gpio.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_gpio_2_gpio.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_mp_clk"
- end="a10_hps_i_gpio_1_gpio.clock_sink">
+ end="a10_hps_i_gpio_2_gpio.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -39969,15 +48096,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_mp_clk</startConnectionPoint>
- <endModule>a10_hps_i_gpio_1_gpio</endModule>
+ <endModule>a10_hps_i_gpio_2_gpio</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_gpio_1_gpio.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_gpio_2_gpio.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_gpio_1_gpio.axi_slave0">
+ end="a10_hps_i_gpio_2_gpio.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -39988,7 +48115,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02a00</value>
+ <value>0xffc02b00</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40020,15 +48147,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_gpio_1_gpio</endModule>
+ <endModule>a10_hps_i_gpio_2_gpio</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_gpio_1_gpio.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_gpio_2_gpio.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_gpio_1_gpio.axi_slave0">
+ end="a10_hps_i_gpio_2_gpio.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40039,7 +48166,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02a00</value>
+ <value>0xffc02b00</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40071,18 +48198,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_gpio_1_gpio</endModule>
+ <endModule>a10_hps_i_gpio_2_gpio</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_gpio_1_gpio.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_gpio_2_gpio.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_gpio_1_gpio.interrupt_sender">
+ end="a10_hps_i_gpio_2_gpio.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>30</value>
+ <value>31</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40106,15 +48233,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_gpio_1_gpio</endModule>
+ <endModule>a10_hps_i_gpio_2_gpio</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_gpio_2_gpio.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_uart_0_uart.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_gpio_2_gpio.reset_sink">
+ end="a10_hps_i_uart_0_uart.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -40133,15 +48260,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_gpio_2_gpio</endModule>
+ <endModule>a10_hps_i_uart_0_uart</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_gpio_2_gpio.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_uart_0_uart.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.l4_mp_clk"
- end="a10_hps_i_gpio_2_gpio.clock_sink">
+ start="a10_hps_baum_clkmgr.l4_sp_clk"
+ end="a10_hps_i_uart_0_uart.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -40159,16 +48286,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>l4_mp_clk</startConnectionPoint>
- <endModule>a10_hps_i_gpio_2_gpio</endModule>
+ <startConnectionPoint>l4_sp_clk</startConnectionPoint>
+ <endModule>a10_hps_i_uart_0_uart</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_gpio_2_gpio.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_uart_0_uart.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_gpio_2_gpio.axi_slave0">
+ end="a10_hps_i_uart_0_uart.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40179,7 +48306,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02b00</value>
+ <value>0xffc02000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40211,15 +48338,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_gpio_2_gpio</endModule>
+ <endModule>a10_hps_i_uart_0_uart</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_gpio_2_gpio.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_uart_0_uart.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_gpio_2_gpio.axi_slave0">
+ end="a10_hps_i_uart_0_uart.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40230,7 +48357,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02b00</value>
+ <value>0xffc02000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40262,18 +48389,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_gpio_2_gpio</endModule>
+ <endModule>a10_hps_i_uart_0_uart</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_gpio_2_gpio.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_uart_0_uart.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_gpio_2_gpio.interrupt_sender">
+ end="a10_hps_i_uart_0_uart.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>31</value>
+ <value>27</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40297,15 +48424,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_gpio_2_gpio</endModule>
+ <endModule>a10_hps_i_uart_0_uart</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_uart_0_uart.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_uart_1_uart.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_uart_0_uart.reset_sink">
+ end="a10_hps_i_uart_1_uart.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -40324,15 +48451,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_uart_0_uart</endModule>
+ <endModule>a10_hps_i_uart_1_uart</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_uart_0_uart.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_uart_1_uart.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_sp_clk"
- end="a10_hps_i_uart_0_uart.clock_sink">
+ end="a10_hps_i_uart_1_uart.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -40351,15 +48478,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_sp_clk</startConnectionPoint>
- <endModule>a10_hps_i_uart_0_uart</endModule>
+ <endModule>a10_hps_i_uart_1_uart</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_uart_0_uart.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_uart_1_uart.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_uart_0_uart.axi_slave0">
+ end="a10_hps_i_uart_1_uart.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40370,7 +48497,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02000</value>
+ <value>0xffc02100</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40402,15 +48529,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_uart_0_uart</endModule>
+ <endModule>a10_hps_i_uart_1_uart</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_uart_0_uart.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_uart_1_uart.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_uart_0_uart.axi_slave0">
+ end="a10_hps_i_uart_1_uart.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40421,7 +48548,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02000</value>
+ <value>0xffc02100</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40453,18 +48580,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_uart_0_uart</endModule>
+ <endModule>a10_hps_i_uart_1_uart</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_uart_0_uart.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_uart_1_uart.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_uart_0_uart.interrupt_sender">
+ end="a10_hps_i_uart_1_uart.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>27</value>
+ <value>28</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40488,15 +48615,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_uart_0_uart</endModule>
+ <endModule>a10_hps_i_uart_1_uart</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_uart_1_uart.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_emac_emac0.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_uart_1_uart.reset_sink">
+ end="a10_hps_i_emac_emac0.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -40515,15 +48642,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_uart_1_uart</endModule>
+ <endModule>a10_hps_i_emac_emac0</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_uart_1_uart.clock_sink"
+ name="a10_hps_baum_clkmgr.emac0_clk/a10_hps_i_emac_emac0.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.l4_sp_clk"
- end="a10_hps_i_uart_1_uart.clock_sink">
+ start="a10_hps_baum_clkmgr.emac0_clk"
+ end="a10_hps_i_emac_emac0.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -40541,16 +48668,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>l4_sp_clk</startConnectionPoint>
- <endModule>a10_hps_i_uart_1_uart</endModule>
+ <startConnectionPoint>emac0_clk</startConnectionPoint>
+ <endModule>a10_hps_i_emac_emac0</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_uart_1_uart.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_emac_emac0.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_uart_1_uart.axi_slave0">
+ end="a10_hps_i_emac_emac0.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40561,7 +48688,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02100</value>
+ <value>0xff800000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40593,15 +48720,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_uart_1_uart</endModule>
+ <endModule>a10_hps_i_emac_emac0</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_uart_1_uart.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_emac_emac0.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_uart_1_uart.axi_slave0">
+ end="a10_hps_i_emac_emac0.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40612,7 +48739,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02100</value>
+ <value>0xff800000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40644,18 +48771,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_uart_1_uart</endModule>
+ <endModule>a10_hps_i_emac_emac0</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_uart_1_uart.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_emac_emac0.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_uart_1_uart.interrupt_sender">
+ end="a10_hps_i_emac_emac0.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>28</value>
+ <value>9</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40679,15 +48806,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_uart_1_uart</endModule>
+ <endModule>a10_hps_i_emac_emac0</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_emac_emac0.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_emac_emac1.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_emac_emac0.reset_sink">
+ end="a10_hps_i_emac_emac1.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -40706,15 +48833,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac0</endModule>
+ <endModule>a10_hps_i_emac_emac1</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.emac0_clk/a10_hps_i_emac_emac0.clock_sink"
+ name="a10_hps_baum_clkmgr.emac1_clk/a10_hps_i_emac_emac1.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.emac0_clk"
- end="a10_hps_i_emac_emac0.clock_sink">
+ start="a10_hps_baum_clkmgr.emac1_clk"
+ end="a10_hps_i_emac_emac1.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -40732,16 +48859,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>emac0_clk</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac0</endModule>
+ <startConnectionPoint>emac1_clk</startConnectionPoint>
+ <endModule>a10_hps_i_emac_emac1</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_emac_emac0.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_emac_emac1.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_emac_emac0.axi_slave0">
+ end="a10_hps_i_emac_emac1.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40752,7 +48879,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xff800000</value>
+ <value>0xff802000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40784,15 +48911,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac0</endModule>
+ <endModule>a10_hps_i_emac_emac1</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_emac_emac0.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_emac_emac1.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_emac_emac0.axi_slave0">
+ end="a10_hps_i_emac_emac1.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40803,7 +48930,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xff800000</value>
+ <value>0xff802000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40835,18 +48962,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac0</endModule>
+ <endModule>a10_hps_i_emac_emac1</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_emac_emac0.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_emac_emac1.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_emac_emac0.interrupt_sender">
+ end="a10_hps_i_emac_emac1.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>9</value>
+ <value>10</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40870,15 +48997,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac0</endModule>
+ <endModule>a10_hps_i_emac_emac1</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_emac_emac1.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_emac_emac2.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_emac_emac1.reset_sink">
+ end="a10_hps_i_emac_emac2.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -40897,15 +49024,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac1</endModule>
+ <endModule>a10_hps_i_emac_emac2</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.emac1_clk/a10_hps_i_emac_emac1.clock_sink"
+ name="a10_hps_baum_clkmgr.emac2_clk/a10_hps_i_emac_emac2.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.emac1_clk"
- end="a10_hps_i_emac_emac1.clock_sink">
+ start="a10_hps_baum_clkmgr.emac2_clk"
+ end="a10_hps_i_emac_emac2.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -40923,16 +49050,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>emac1_clk</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac1</endModule>
+ <startConnectionPoint>emac2_clk</startConnectionPoint>
+ <endModule>a10_hps_i_emac_emac2</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_emac_emac1.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_emac_emac2.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_emac_emac1.axi_slave0">
+ end="a10_hps_i_emac_emac2.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40943,7 +49070,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xff802000</value>
+ <value>0xff804000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -40975,15 +49102,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac1</endModule>
+ <endModule>a10_hps_i_emac_emac2</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_emac_emac1.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_emac_emac2.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_emac_emac1.axi_slave0">
+ end="a10_hps_i_emac_emac2.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -40994,7 +49121,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xff802000</value>
+ <value>0xff804000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41026,18 +49153,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac1</endModule>
+ <endModule>a10_hps_i_emac_emac2</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_emac_emac1.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_emac_emac2.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_emac_emac1.interrupt_sender">
+ end="a10_hps_i_emac_emac2.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>10</value>
+ <value>11</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41061,15 +49188,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac1</endModule>
+ <endModule>a10_hps_i_emac_emac2</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_emac_emac2.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_spim_0_spim.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_emac_emac2.reset_sink">
+ end="a10_hps_i_spim_0_spim.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -41088,15 +49215,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac2</endModule>
+ <endModule>a10_hps_i_spim_0_spim</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.emac2_clk/a10_hps_i_emac_emac2.clock_sink"
+ name="a10_hps_baum_clkmgr.spi_m_clk/a10_hps_i_spim_0_spim.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.emac2_clk"
- end="a10_hps_i_emac_emac2.clock_sink">
+ start="a10_hps_baum_clkmgr.spi_m_clk"
+ end="a10_hps_i_spim_0_spim.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -41114,16 +49241,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>emac2_clk</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac2</endModule>
+ <startConnectionPoint>spi_m_clk</startConnectionPoint>
+ <endModule>a10_hps_i_spim_0_spim</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_emac_emac2.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_spim_0_spim.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_emac_emac2.axi_slave0">
+ end="a10_hps_i_spim_0_spim.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -41134,7 +49261,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xff804000</value>
+ <value>0xffda4000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41166,15 +49293,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac2</endModule>
+ <endModule>a10_hps_i_spim_0_spim</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_emac_emac2.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_spim_0_spim.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_emac_emac2.axi_slave0">
+ end="a10_hps_i_spim_0_spim.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -41185,7 +49312,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xff804000</value>
+ <value>0xffda4000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41217,18 +49344,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac2</endModule>
+ <endModule>a10_hps_i_spim_0_spim</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_emac_emac2.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_spim_0_spim.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_emac_emac2.interrupt_sender">
+ end="a10_hps_i_spim_0_spim.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>11</value>
+ <value>20</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41252,15 +49379,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac2</endModule>
+ <endModule>a10_hps_i_spim_0_spim</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_spim_0_spim.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_spim_1_spim.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_spim_0_spim.reset_sink">
+ end="a10_hps_i_spim_1_spim.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -41279,15 +49406,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_spim_0_spim</endModule>
+ <endModule>a10_hps_i_spim_1_spim</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.spi_m_clk/a10_hps_i_spim_0_spim.clock_sink"
+ name="a10_hps_baum_clkmgr.spi_m_clk/a10_hps_i_spim_1_spim.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.spi_m_clk"
- end="a10_hps_i_spim_0_spim.clock_sink">
+ end="a10_hps_i_spim_1_spim.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -41306,15 +49433,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>spi_m_clk</startConnectionPoint>
- <endModule>a10_hps_i_spim_0_spim</endModule>
+ <endModule>a10_hps_i_spim_1_spim</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_spim_0_spim.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_spim_1_spim.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_spim_0_spim.axi_slave0">
+ end="a10_hps_i_spim_1_spim.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -41325,7 +49452,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda4000</value>
+ <value>0xffda5000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41357,15 +49484,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_spim_0_spim</endModule>
+ <endModule>a10_hps_i_spim_1_spim</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_spim_0_spim.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_spim_1_spim.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_spim_0_spim.axi_slave0">
+ end="a10_hps_i_spim_1_spim.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -41376,7 +49503,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda4000</value>
+ <value>0xffda5000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41408,18 +49535,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_spim_0_spim</endModule>
+ <endModule>a10_hps_i_spim_1_spim</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_spim_0_spim.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_spim_1_spim.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_spim_0_spim.interrupt_sender">
+ end="a10_hps_i_spim_1_spim.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>20</value>
+ <value>21</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41443,15 +49570,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_spim_0_spim</endModule>
+ <endModule>a10_hps_i_spim_1_spim</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_spim_1_spim.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_spis_0_spis.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_spim_1_spim.reset_sink">
+ end="a10_hps_i_spis_0_spis.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -41470,15 +49597,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_spim_1_spim</endModule>
+ <endModule>a10_hps_i_spis_0_spis</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.spi_m_clk/a10_hps_i_spim_1_spim.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_spis_0_spis.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.spi_m_clk"
- end="a10_hps_i_spim_1_spim.clock_sink">
+ start="a10_hps_baum_clkmgr.l4_mp_clk"
+ end="a10_hps_i_spis_0_spis.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -41496,16 +49623,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>spi_m_clk</startConnectionPoint>
- <endModule>a10_hps_i_spim_1_spim</endModule>
+ <startConnectionPoint>l4_mp_clk</startConnectionPoint>
+ <endModule>a10_hps_i_spis_0_spis</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_spim_1_spim.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_spis_0_spis.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_spim_1_spim.axi_slave0">
+ end="a10_hps_i_spis_0_spis.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -41516,7 +49643,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda5000</value>
+ <value>0xffda2000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41548,15 +49675,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_spim_1_spim</endModule>
+ <endModule>a10_hps_i_spis_0_spis</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_spim_1_spim.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_spis_0_spis.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_spim_1_spim.axi_slave0">
+ end="a10_hps_i_spis_0_spis.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -41567,7 +49694,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda5000</value>
+ <value>0xffda2000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41599,18 +49726,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_spim_1_spim</endModule>
+ <endModule>a10_hps_i_spis_0_spis</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_spim_1_spim.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_spis_0_spis.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_spim_1_spim.interrupt_sender">
+ end="a10_hps_i_spis_0_spis.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>21</value>
+ <value>18</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41634,15 +49761,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_spim_1_spim</endModule>
+ <endModule>a10_hps_i_spis_0_spis</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_spis_0_spis.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_spis_1_spis.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_spis_0_spis.reset_sink">
+ end="a10_hps_i_spis_1_spis.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -41661,15 +49788,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_spis_0_spis</endModule>
+ <endModule>a10_hps_i_spis_1_spis</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_spis_0_spis.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_spis_1_spis.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_mp_clk"
- end="a10_hps_i_spis_0_spis.clock_sink">
+ end="a10_hps_i_spis_1_spis.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -41688,15 +49815,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_mp_clk</startConnectionPoint>
- <endModule>a10_hps_i_spis_0_spis</endModule>
+ <endModule>a10_hps_i_spis_1_spis</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_spis_0_spis.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_spis_1_spis.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_spis_0_spis.axi_slave0">
+ end="a10_hps_i_spis_1_spis.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -41707,7 +49834,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda2000</value>
+ <value>0xffda3000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41739,15 +49866,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_spis_0_spis</endModule>
+ <endModule>a10_hps_i_spis_1_spis</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_spis_0_spis.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_spis_1_spis.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_spis_0_spis.axi_slave0">
+ end="a10_hps_i_spis_1_spis.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -41758,7 +49885,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda2000</value>
+ <value>0xffda3000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41790,18 +49917,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_spis_0_spis</endModule>
+ <endModule>a10_hps_i_spis_1_spis</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_spis_0_spis.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_spis_1_spis.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_spis_0_spis.interrupt_sender">
+ end="a10_hps_i_spis_1_spis.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>18</value>
+ <value>19</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41825,15 +49952,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_spis_0_spis</endModule>
+ <endModule>a10_hps_i_spis_1_spis</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_spis_1_spis.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_i2c_0_i2c.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_spis_1_spis.reset_sink">
+ end="a10_hps_i_i2c_0_i2c.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -41852,15 +49979,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_spis_1_spis</endModule>
+ <endModule>a10_hps_i_i2c_0_i2c</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_spis_1_spis.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_i2c_0_i2c.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.l4_mp_clk"
- end="a10_hps_i_spis_1_spis.clock_sink">
+ start="a10_hps_baum_clkmgr.l4_sp_clk"
+ end="a10_hps_i_i2c_0_i2c.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -41878,16 +50005,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>l4_mp_clk</startConnectionPoint>
- <endModule>a10_hps_i_spis_1_spis</endModule>
+ <startConnectionPoint>l4_sp_clk</startConnectionPoint>
+ <endModule>a10_hps_i_i2c_0_i2c</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_spis_1_spis.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_i2c_0_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_spis_1_spis.axi_slave0">
+ end="a10_hps_i_i2c_0_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -41898,7 +50025,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda3000</value>
+ <value>0xffc02200</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41930,15 +50057,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_spis_1_spis</endModule>
+ <endModule>a10_hps_i_i2c_0_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_spis_1_spis.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_i2c_0_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_spis_1_spis.axi_slave0">
+ end="a10_hps_i_i2c_0_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -41949,7 +50076,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda3000</value>
+ <value>0xffc02200</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -41981,18 +50108,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_spis_1_spis</endModule>
+ <endModule>a10_hps_i_i2c_0_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_spis_1_spis.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_i2c_0_i2c.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_spis_1_spis.interrupt_sender">
+ end="a10_hps_i_i2c_0_i2c.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>19</value>
+ <value>22</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42016,15 +50143,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_spis_1_spis</endModule>
+ <endModule>a10_hps_i_i2c_0_i2c</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_i2c_0_i2c.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_i2c_1_i2c.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_i2c_0_i2c.reset_sink">
+ end="a10_hps_i_i2c_1_i2c.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42043,15 +50170,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_i2c_0_i2c</endModule>
+ <endModule>a10_hps_i_i2c_1_i2c</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_i2c_0_i2c.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_i2c_1_i2c.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_sp_clk"
- end="a10_hps_i_i2c_0_i2c.clock_sink">
+ end="a10_hps_i_i2c_1_i2c.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42070,15 +50197,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_sp_clk</startConnectionPoint>
- <endModule>a10_hps_i_i2c_0_i2c</endModule>
+ <endModule>a10_hps_i_i2c_1_i2c</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_i2c_0_i2c.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_i2c_1_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_i2c_0_i2c.axi_slave0">
+ end="a10_hps_i_i2c_1_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -42089,7 +50216,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02200</value>
+ <value>0xffc02300</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42121,15 +50248,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_i2c_0_i2c</endModule>
+ <endModule>a10_hps_i_i2c_1_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_i2c_0_i2c.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_i2c_1_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_i2c_0_i2c.axi_slave0">
+ end="a10_hps_i_i2c_1_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -42140,7 +50267,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02200</value>
+ <value>0xffc02300</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42172,18 +50299,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_i2c_0_i2c</endModule>
+ <endModule>a10_hps_i_i2c_1_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_i2c_0_i2c.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_i2c_1_i2c.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_i2c_0_i2c.interrupt_sender">
+ end="a10_hps_i_i2c_1_i2c.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>22</value>
+ <value>23</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42207,15 +50334,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_i2c_0_i2c</endModule>
+ <endModule>a10_hps_i_i2c_1_i2c</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_i2c_1_i2c.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_i2c_emac_0_i2c.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_i2c_1_i2c.reset_sink">
+ end="a10_hps_i_i2c_emac_0_i2c.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42234,15 +50361,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_i2c_1_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_i2c_1_i2c.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_i2c_emac_0_i2c.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_sp_clk"
- end="a10_hps_i_i2c_1_i2c.clock_sink">
+ end="a10_hps_i_i2c_emac_0_i2c.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42261,15 +50388,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_sp_clk</startConnectionPoint>
- <endModule>a10_hps_i_i2c_1_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_i2c_1_i2c.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_i2c_emac_0_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_i2c_1_i2c.axi_slave0">
+ end="a10_hps_i_i2c_emac_0_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -42280,7 +50407,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02300</value>
+ <value>0xffc02400</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42312,15 +50439,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_i2c_1_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_i2c_1_i2c.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_i2c_emac_0_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_i2c_1_i2c.axi_slave0">
+ end="a10_hps_i_i2c_emac_0_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -42331,7 +50458,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02300</value>
+ <value>0xffc02400</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42363,18 +50490,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_i2c_1_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_i2c_1_i2c.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_i2c_emac_0_i2c.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_i2c_1_i2c.interrupt_sender">
+ end="a10_hps_i_i2c_emac_0_i2c.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>23</value>
+ <value>24</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42398,15 +50525,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_i2c_1_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_i2c_emac_0_i2c.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_i2c_emac_1_i2c.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_i2c_emac_0_i2c.reset_sink">
+ end="a10_hps_i_i2c_emac_1_i2c.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42425,15 +50552,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_i2c_emac_0_i2c.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_i2c_emac_1_i2c.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_sp_clk"
- end="a10_hps_i_i2c_emac_0_i2c.clock_sink">
+ end="a10_hps_i_i2c_emac_1_i2c.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42452,15 +50579,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_sp_clk</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_i2c_emac_0_i2c.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_i2c_emac_1_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_i2c_emac_0_i2c.axi_slave0">
+ end="a10_hps_i_i2c_emac_1_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -42471,7 +50598,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02400</value>
+ <value>0xffc02500</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42503,15 +50630,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_i2c_emac_0_i2c.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_i2c_emac_1_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_i2c_emac_0_i2c.axi_slave0">
+ end="a10_hps_i_i2c_emac_1_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -42522,7 +50649,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02400</value>
+ <value>0xffc02500</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42554,18 +50681,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_i2c_emac_0_i2c.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_i2c_emac_1_i2c.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_i2c_emac_0_i2c.interrupt_sender">
+ end="a10_hps_i_i2c_emac_1_i2c.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>24</value>
+ <value>25</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42589,15 +50716,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_i2c_emac_1_i2c.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_i2c_emac_2_i2c.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_i2c_emac_1_i2c.reset_sink">
+ end="a10_hps_i_i2c_emac_2_i2c.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42616,15 +50743,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_i2c_emac_1_i2c.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_i2c_emac_2_i2c.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_sp_clk"
- end="a10_hps_i_i2c_emac_1_i2c.clock_sink">
+ end="a10_hps_i_i2c_emac_2_i2c.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42643,15 +50770,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_sp_clk</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_i2c_emac_1_i2c.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_i2c_emac_2_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_i2c_emac_1_i2c.axi_slave0">
+ end="a10_hps_i_i2c_emac_2_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -42662,7 +50789,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02500</value>
+ <value>0xffc02600</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42694,15 +50821,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_i2c_emac_1_i2c.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_i2c_emac_2_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_i2c_emac_1_i2c.axi_slave0">
+ end="a10_hps_i_i2c_emac_2_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -42713,7 +50840,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02500</value>
+ <value>0xffc02600</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42745,18 +50872,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_i2c_emac_1_i2c.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_i2c_emac_2_i2c.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_i2c_emac_1_i2c.interrupt_sender">
+ end="a10_hps_i_i2c_emac_2_i2c.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>25</value>
+ <value>26</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42780,15 +50907,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
+ <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_i2c_emac_2_i2c.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_qspi_QSPIDATA.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_i2c_emac_2_i2c.reset_sink">
+ end="a10_hps_i_qspi_QSPIDATA.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42807,15 +50934,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
+ <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_sp_clk/a10_hps_i_i2c_emac_2_i2c.clock_sink"
+ name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_qspi_QSPIDATA.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.l4_sp_clk"
- end="a10_hps_i_i2c_emac_2_i2c.clock_sink">
+ start="a10_hps_baum_clkmgr.l4_mp_clk"
+ end="a10_hps_i_qspi_QSPIDATA.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42833,16 +50960,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>l4_sp_clk</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
+ <startConnectionPoint>l4_mp_clk</startConnectionPoint>
+ <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_i2c_emac_2_i2c.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_qspi_QSPIDATA.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_i2c_emac_2_i2c.axi_slave0">
+ end="a10_hps_i_qspi_QSPIDATA.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -42853,7 +50980,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02600</value>
+ <value>0xff809000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42885,15 +51012,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
+ <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_i2c_emac_2_i2c.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_qspi_QSPIDATA.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_i2c_emac_2_i2c.axi_slave0">
+ end="a10_hps_i_qspi_QSPIDATA.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -42904,7 +51031,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02600</value>
+ <value>0xff809000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -42936,32 +51063,32 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
+ <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_i2c_emac_2_i2c.interrupt_sender"
- kind="interrupt"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_qspi_QSPIDATA.axi_slave1"
+ kind="avalon"
version="22.1"
- start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_i2c_emac_2_i2c.interrupt_sender">
- <parameter name="irqNumber">
+ start="a10_hps_arm_a9_0.altera_axi_master"
+ end="a10_hps_i_qspi_QSPIDATA.axi_slave1">
+ <parameter name="arbitrationPriority">
<type>int</type>
- <value>26</value>
+ <value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xffa00000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="generateLegacySim">
+ <parameter name="defaultConnection">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -42969,17 +51096,6 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_gic_0</startModule>
- <startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
- <endConnectionPoint>interrupt_sender</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_qspi_QSPIDATA.reset_sink"
- kind="reset"
- version="22.1"
- start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_qspi_QSPIDATA.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -42996,17 +51112,41 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk_reset</startConnectionPoint>
+ <startModule>a10_hps_arm_a9_0</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
<endModule>a10_hps_i_qspi_QSPIDATA</endModule>
- <endConnectionPoint>reset_sink</endConnectionPoint>
+ <endConnectionPoint>axi_slave1</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_qspi_QSPIDATA.clock_sink"
- kind="clock"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_qspi_QSPIDATA.axi_slave1"
+ kind="avalon"
version="22.1"
- start="a10_hps_baum_clkmgr.l4_mp_clk"
- end="a10_hps_i_qspi_QSPIDATA.clock_sink">
+ start="a10_hps_arm_a9_1.altera_axi_master"
+ end="a10_hps_i_qspi_QSPIDATA.axi_slave1">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xffa00000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43023,34 +51163,34 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>l4_mp_clk</startConnectionPoint>
+ <startModule>a10_hps_arm_a9_1</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
<endModule>a10_hps_i_qspi_QSPIDATA</endModule>
- <endConnectionPoint>clock_sink</endConnectionPoint>
+ <endConnectionPoint>axi_slave1</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_qspi_QSPIDATA.axi_slave0"
- kind="avalon"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_qspi_QSPIDATA.interrupt_sender"
+ kind="interrupt"
version="22.1"
- start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_qspi_QSPIDATA.axi_slave0">
- <parameter name="arbitrationPriority">
+ start="a10_hps_arm_gic_0.irq_rx_offset_83"
+ end="a10_hps_i_qspi_QSPIDATA.interrupt_sender">
+ <parameter name="irqNumber">
<type>int</type>
- <value>1</value>
+ <value>17</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xff809000</value>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -43058,6 +51198,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>a10_hps_arm_gic_0</startModule>
+ <startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
+ <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
+ <endConnectionPoint>interrupt_sender</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_sdmmc_sdmmc.reset_sink"
+ kind="reset"
+ version="22.1"
+ start="a10_hps_clk_0.clk_reset"
+ end="a10_hps_i_sdmmc_sdmmc.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43074,34 +51225,26 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_0</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>a10_hps_clk_0</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
+ <endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_qspi_QSPIDATA.axi_slave0"
- kind="avalon"
+ name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_sdmmc_sdmmc.biu"
+ kind="clock"
version="22.1"
- start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_qspi_QSPIDATA.axi_slave0">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xff809000</value>
+ start="a10_hps_baum_clkmgr.l4_mp_clk"
+ end="a10_hps_i_sdmmc_sdmmc.biu">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -43109,6 +51252,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>a10_hps_baum_clkmgr</startModule>
+ <startConnectionPoint>l4_mp_clk</startConnectionPoint>
+ <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
+ <endConnectionPoint>biu</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_baum_clkmgr.sdmmc_clk/a10_hps_i_sdmmc_sdmmc.ciu"
+ kind="clock"
+ version="22.1"
+ start="a10_hps_baum_clkmgr.sdmmc_clk"
+ end="a10_hps_i_sdmmc_sdmmc.ciu">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43125,17 +51279,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_1</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>a10_hps_baum_clkmgr</startModule>
+ <startConnectionPoint>sdmmc_clk</startConnectionPoint>
+ <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
+ <endConnectionPoint>ciu</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_qspi_QSPIDATA.axi_slave1"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_sdmmc_sdmmc.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_qspi_QSPIDATA.axi_slave1">
+ end="a10_hps_i_sdmmc_sdmmc.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -43146,7 +51300,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffa00000</value>
+ <value>0xff808000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -43178,15 +51332,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
- <endConnectionPoint>axi_slave1</endConnectionPoint>
+ <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_qspi_QSPIDATA.axi_slave1"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_sdmmc_sdmmc.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_qspi_QSPIDATA.axi_slave1">
+ end="a10_hps_i_sdmmc_sdmmc.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -43197,7 +51351,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffa00000</value>
+ <value>0xff808000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -43229,18 +51383,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
- <endConnectionPoint>axi_slave1</endConnectionPoint>
+ <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_qspi_QSPIDATA.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_sdmmc_sdmmc.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_qspi_QSPIDATA.interrupt_sender">
+ end="a10_hps_i_sdmmc_sdmmc.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>17</value>
+ <value>15</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -43264,15 +51418,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
+ <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_sdmmc_sdmmc.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_nand_NANDDATA.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_sdmmc_sdmmc.reset_sink">
+ end="a10_hps_i_nand_NANDDATA.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43291,15 +51445,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
+ <endModule>a10_hps_i_nand_NANDDATA</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_sdmmc_sdmmc.biu"
+ name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_nand_NANDDATA.clock_sink"
kind="clock"
version="22.1"
start="a10_hps_baum_clkmgr.l4_mp_clk"
- end="a10_hps_i_sdmmc_sdmmc.biu">
+ end="a10_hps_i_nand_NANDDATA.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43318,15 +51472,39 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
<startConnectionPoint>l4_mp_clk</startConnectionPoint>
- <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
- <endConnectionPoint>biu</endConnectionPoint>
+ <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.sdmmc_clk/a10_hps_i_sdmmc_sdmmc.ciu"
- kind="clock"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_nand_NANDDATA.axi_slave0"
+ kind="avalon"
version="22.1"
- start="a10_hps_baum_clkmgr.sdmmc_clk"
- end="a10_hps_i_sdmmc_sdmmc.ciu">
+ start="a10_hps_arm_a9_0.altera_axi_master"
+ end="a10_hps_i_nand_NANDDATA.axi_slave0">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xffb90000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43343,17 +51521,68 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>sdmmc_clk</startConnectionPoint>
- <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
- <endConnectionPoint>ciu</endConnectionPoint>
+ <startModule>a10_hps_arm_a9_0</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
+ <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_sdmmc_sdmmc.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_nand_NANDDATA.axi_slave0"
+ kind="avalon"
+ version="22.1"
+ start="a10_hps_arm_a9_1.altera_axi_master"
+ end="a10_hps_i_nand_NANDDATA.axi_slave0">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xffb90000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_arm_a9_1</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
+ <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_nand_NANDDATA.axi_slave1"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_sdmmc_sdmmc.axi_slave0">
+ end="a10_hps_i_nand_NANDDATA.axi_slave1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -43364,7 +51593,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xff808000</value>
+ <value>0xffb80000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -43396,15 +51625,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <endConnectionPoint>axi_slave1</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_sdmmc_sdmmc.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_nand_NANDDATA.axi_slave1"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_sdmmc_sdmmc.axi_slave0">
+ end="a10_hps_i_nand_NANDDATA.axi_slave1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -43415,7 +51644,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xff808000</value>
+ <value>0xffb80000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -43447,18 +51676,18 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <endConnectionPoint>axi_slave1</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_sdmmc_sdmmc.interrupt_sender"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_nand_NANDDATA.interrupt_sender"
kind="interrupt"
version="22.1"
start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_sdmmc_sdmmc.interrupt_sender">
+ end="a10_hps_i_nand_NANDDATA.interrupt_sender">
<parameter name="irqNumber">
<type>int</type>
- <value>15</value>
+ <value>16</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -43482,15 +51711,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_gic_0</startModule>
<startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
+ <endModule>a10_hps_i_nand_NANDDATA</endModule>
<endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_nand_NANDDATA.reset_sink"
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_usbotg_0_globgrp.reset_sink"
kind="reset"
version="22.1"
start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_nand_NANDDATA.reset_sink">
+ end="a10_hps_i_usbotg_0_globgrp.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43509,15 +51738,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
<endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.l4_mp_clk/a10_hps_i_nand_NANDDATA.clock_sink"
+ name="a10_hps_baum_clkmgr.usb_clk/a10_hps_i_usbotg_0_globgrp.clock_sink"
kind="clock"
version="22.1"
- start="a10_hps_baum_clkmgr.l4_mp_clk"
- end="a10_hps_i_nand_NANDDATA.clock_sink">
+ start="a10_hps_baum_clkmgr.usb_clk"
+ end="a10_hps_i_usbotg_0_globgrp.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43535,16 +51764,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>l4_mp_clk</startConnectionPoint>
- <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <startConnectionPoint>usb_clk</startConnectionPoint>
+ <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
<endConnectionPoint>clock_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_nand_NANDDATA.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_usbotg_0_globgrp.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_nand_NANDDATA.axi_slave0">
+ end="a10_hps_i_usbotg_0_globgrp.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -43555,7 +51784,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffb90000</value>
+ <value>0xffb00000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -43587,15 +51816,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_nand_NANDDATA.axi_slave0"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_usbotg_0_globgrp.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_nand_NANDDATA.axi_slave0">
+ end="a10_hps_i_usbotg_0_globgrp.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -43606,7 +51835,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffb90000</value>
+ <value>0xffb00000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -43638,32 +51867,32 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_arm_a9_1</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_nand_NANDDATA.axi_slave1"
- kind="avalon"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_usbotg_0_globgrp.interrupt_sender"
+ kind="interrupt"
version="22.1"
- start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_nand_NANDDATA.axi_slave1">
- <parameter name="arbitrationPriority">
+ start="a10_hps_arm_gic_0.irq_rx_offset_83"
+ end="a10_hps_i_usbotg_0_globgrp.interrupt_sender">
+ <parameter name="irqNumber">
<type>int</type>
- <value>1</value>
+ <value>12</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xffb80000</value>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -43671,6 +51900,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>a10_hps_arm_gic_0</startModule>
+ <startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
+ <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
+ <endConnectionPoint>interrupt_sender</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_clk_0.clk_reset/a10_hps_i_usbotg_1_globgrp.reset_sink"
+ kind="reset"
+ version="22.1"
+ start="a10_hps_clk_0.clk_reset"
+ end="a10_hps_i_usbotg_1_globgrp.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43687,17 +51927,44 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_0</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_nand_NANDDATA</endModule>
- <endConnectionPoint>axi_slave1</endConnectionPoint>
+ <startModule>a10_hps_clk_0</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
+ <endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_nand_NANDDATA.axi_slave1"
+ name="a10_hps_baum_clkmgr.usb_clk/a10_hps_i_usbotg_1_globgrp.clock_sink"
+ kind="clock"
+ version="22.1"
+ start="a10_hps_baum_clkmgr.usb_clk"
+ end="a10_hps_i_usbotg_1_globgrp.clock_sink">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_baum_clkmgr</startModule>
+ <startConnectionPoint>usb_clk</startConnectionPoint>
+ <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
+ <endConnectionPoint>clock_sink</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_usbotg_1_globgrp.axi_slave0"
kind="avalon"
version="22.1"
- start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_nand_NANDDATA.axi_slave1">
+ start="a10_hps_arm_a9_0.altera_axi_master"
+ end="a10_hps_i_usbotg_1_globgrp.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -43708,7 +51975,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffb80000</value>
+ <value>0xffb40000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -43738,34 +52005,34 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_1</startModule>
+ <startModule>a10_hps_arm_a9_0</startModule>
<startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_nand_NANDDATA</endModule>
- <endConnectionPoint>axi_slave1</endConnectionPoint>
+ <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_nand_NANDDATA.interrupt_sender"
- kind="interrupt"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_usbotg_1_globgrp.axi_slave0"
+ kind="avalon"
version="22.1"
- start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_nand_NANDDATA.interrupt_sender">
- <parameter name="irqNumber">
+ start="a10_hps_arm_a9_1.altera_axi_master"
+ end="a10_hps_i_usbotg_1_globgrp.axi_slave0">
+ <parameter name="arbitrationPriority">
<type>int</type>
- <value>16</value>
+ <value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xffb40000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="generateLegacySim">
+ <parameter name="defaultConnection">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -43773,17 +52040,6 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_gic_0</startModule>
- <startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_nand_NANDDATA</endModule>
- <endConnectionPoint>interrupt_sender</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_usbotg_0_globgrp.reset_sink"
- kind="reset"
- version="22.1"
- start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_usbotg_0_globgrp.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43800,17 +52056,25 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
- <endConnectionPoint>reset_sink</endConnectionPoint>
+ <startModule>a10_hps_arm_a9_1</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
+ <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_baum_clkmgr.usb_clk/a10_hps_i_usbotg_0_globgrp.clock_sink"
- kind="clock"
+ name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_usbotg_1_globgrp.interrupt_sender"
+ kind="interrupt"
version="22.1"
- start="a10_hps_baum_clkmgr.usb_clk"
- end="a10_hps_i_usbotg_0_globgrp.clock_sink">
+ start="a10_hps_arm_gic_0.irq_rx_offset_83"
+ end="a10_hps_i_usbotg_1_globgrp.interrupt_sender">
+ <parameter name="irqNumber">
+ <type>int</type>
+ <value>13</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43827,34 +52091,26 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>usb_clk</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
- <endConnectionPoint>clock_sink</endConnectionPoint>
+ <startModule>a10_hps_arm_gic_0</startModule>
+ <startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
+ <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
+ <endConnectionPoint>interrupt_sender</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_usbotg_0_globgrp.axi_slave0"
- kind="avalon"
+ name="a10_hps_clk_0.clk/a10_hps_scu.clock_sink"
+ kind="clock"
version="22.1"
- start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_usbotg_0_globgrp.axi_slave0">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xffb00000</value>
+ start="a10_hps_clk_0.clk"
+ end="a10_hps_scu.clock_sink">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -43862,6 +52118,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>a10_hps_clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>a10_hps_scu</endModule>
+ <endConnectionPoint>clock_sink</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_clk_0.clk_reset/a10_hps_scu.reset_sink"
+ kind="reset"
+ version="22.1"
+ start="a10_hps_clk_0.clk_reset"
+ end="a10_hps_scu.reset_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -43878,17 +52145,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_0</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>a10_hps_clk_0</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>a10_hps_scu</endModule>
+ <endConnectionPoint>reset_sink</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_usbotg_0_globgrp.axi_slave0"
+ name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_scu.axi_slave0"
kind="avalon"
version="22.1"
- start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_usbotg_0_globgrp.axi_slave0">
+ start="a10_hps_arm_a9_0.altera_axi_master"
+ end="a10_hps_scu.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -43899,7 +52166,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffb00000</value>
+ <value>0xffffc000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -43929,61 +52196,34 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_1</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_usbotg_0_globgrp.interrupt_sender"
- kind="interrupt"
- version="22.1"
- start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_usbotg_0_globgrp.interrupt_sender">
- <parameter name="irqNumber">
- <type>int</type>
- <value>12</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <startModule>a10_hps_arm_gic_0</startModule>
- <startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
- <endConnectionPoint>interrupt_sender</endConnectionPoint>
+ <startModule>a10_hps_arm_a9_0</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
+ <endModule>a10_hps_scu</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_i_usbotg_1_globgrp.reset_sink"
- kind="reset"
+ name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_scu.axi_slave0"
+ kind="avalon"
version="22.1"
- start="a10_hps_clk_0.clk_reset"
- end="a10_hps_i_usbotg_1_globgrp.reset_sink">
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
+ start="a10_hps_arm_a9_1.altera_axi_master"
+ end="a10_hps_scu.axi_slave0">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="generateLegacySim">
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xffffc000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -43991,17 +52231,6 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
- <endConnectionPoint>reset_sink</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_baum_clkmgr.usb_clk/a10_hps_i_usbotg_1_globgrp.clock_sink"
- kind="clock"
- version="22.1"
- start="a10_hps_baum_clkmgr.usb_clk"
- end="a10_hps_i_usbotg_1_globgrp.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -44018,17 +52247,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_baum_clkmgr</startModule>
- <startConnectionPoint>usb_clk</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
- <endConnectionPoint>clock_sink</endConnectionPoint>
+ <startModule>a10_hps_arm_a9_1</startModule>
+ <startConnectionPoint>altera_axi_master</startConnectionPoint>
+ <endModule>a10_hps_scu</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_i_usbotg_1_globgrp.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_arm_gic_0.axi_slave0"
kind="avalon"
version="22.1"
- start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_i_usbotg_1_globgrp.axi_slave0">
+ start="a10_hps_bridges.axi_f2h"
+ end="a10_hps_arm_gic_0.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44039,7 +52268,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffb40000</value>
+ <value>0xffffd000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44069,17 +52298,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_0</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
+ <startModule>a10_hps_bridges</startModule>
+ <startConnectionPoint>axi_f2h</startConnectionPoint>
+ <endModule>a10_hps_arm_gic_0</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_i_usbotg_1_globgrp.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_arm_gic_0.axi_slave1"
kind="avalon"
version="22.1"
- start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_i_usbotg_1_globgrp.axi_slave0">
+ start="a10_hps_bridges.axi_f2h"
+ end="a10_hps_arm_gic_0.axi_slave1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44090,7 +52319,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffb40000</value>
+ <value>0xffffc100</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44120,34 +52349,34 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_1</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>a10_hps_bridges</startModule>
+ <startConnectionPoint>axi_f2h</startConnectionPoint>
+ <endModule>a10_hps_arm_gic_0</endModule>
+ <endConnectionPoint>axi_slave1</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_gic_0.irq_rx_offset_83/a10_hps_i_usbotg_1_globgrp.interrupt_sender"
- kind="interrupt"
+ name="a10_hps_bridges.axi_f2h/a10_hps_mpu_reg_l2_MPUL2.axi_slave0"
+ kind="avalon"
version="22.1"
- start="a10_hps_arm_gic_0.irq_rx_offset_83"
- end="a10_hps_i_usbotg_1_globgrp.interrupt_sender">
- <parameter name="irqNumber">
+ start="a10_hps_bridges.axi_f2h"
+ end="a10_hps_mpu_reg_l2_MPUL2.axi_slave0">
+ <parameter name="arbitrationPriority">
<type>int</type>
- <value>13</value>
+ <value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xfffff000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="generateLegacySim">
+ <parameter name="defaultConnection">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -44155,17 +52384,6 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_gic_0</startModule>
- <startConnectionPoint>irq_rx_offset_83</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
- <endConnectionPoint>interrupt_sender</endConnectionPoint>
- </connection>
- <connection
- name="a10_hps_clk_0.clk/a10_hps_scu.clock_sink"
- kind="clock"
- version="22.1"
- start="a10_hps_clk_0.clk"
- end="a10_hps_scu.clock_sink">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -44182,17 +52400,41 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk</startConnectionPoint>
- <endModule>a10_hps_scu</endModule>
- <endConnectionPoint>clock_sink</endConnectionPoint>
+ <startModule>a10_hps_bridges</startModule>
+ <startConnectionPoint>axi_f2h</startConnectionPoint>
+ <endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_clk_0.clk_reset/a10_hps_scu.reset_sink"
- kind="reset"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_dma_DMASECURE.axi_slave0"
+ kind="avalon"
version="22.1"
- start="a10_hps_clk_0.clk_reset"
- end="a10_hps_scu.reset_sink">
+ start="a10_hps_bridges.axi_f2h"
+ end="a10_hps_i_dma_DMASECURE.axi_slave0">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0xffda1000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -44209,17 +52451,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_clk_0</startModule>
- <startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_scu</endModule>
- <endConnectionPoint>reset_sink</endConnectionPoint>
+ <startModule>a10_hps_bridges</startModule>
+ <startConnectionPoint>axi_f2h</startConnectionPoint>
+ <endModule>a10_hps_i_dma_DMASECURE</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_0.altera_axi_master/a10_hps_scu.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_sys_mgr_core.axi_slave0"
kind="avalon"
version="22.1"
- start="a10_hps_arm_a9_0.altera_axi_master"
- end="a10_hps_scu.axi_slave0">
+ start="a10_hps_bridges.axi_f2h"
+ end="a10_hps_i_sys_mgr_core.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44230,7 +52472,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffffc000</value>
+ <value>0xffd06000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44260,17 +52502,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_0</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_scu</endModule>
+ <startModule>a10_hps_bridges</startModule>
+ <startConnectionPoint>axi_f2h</startConnectionPoint>
+ <endModule>a10_hps_i_sys_mgr_core</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_arm_a9_1.altera_axi_master/a10_hps_scu.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_rst_mgr_rstmgr.axi_slave0"
kind="avalon"
version="22.1"
- start="a10_hps_arm_a9_1.altera_axi_master"
- end="a10_hps_scu.axi_slave0">
+ start="a10_hps_bridges.axi_f2h"
+ end="a10_hps_i_rst_mgr_rstmgr.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44281,7 +52523,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffffc000</value>
+ <value>0xffd05000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44311,17 +52553,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_arm_a9_1</startModule>
- <startConnectionPoint>altera_axi_master</startConnectionPoint>
- <endModule>a10_hps_scu</endModule>
+ <startModule>a10_hps_bridges</startModule>
+ <startConnectionPoint>axi_f2h</startConnectionPoint>
+ <endModule>a10_hps_i_rst_mgr_rstmgr</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_arm_gic_0.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_arm_gic_0.axi_slave0">
+ end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44332,7 +52574,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffffd000</value>
+ <value>0xffd03000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44364,15 +52606,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_arm_gic_0</endModule>
+ <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_arm_gic_0.axi_slave1"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_arm_gic_0.axi_slave1">
+ end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44383,7 +52625,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffffc100</value>
+ <value>0xffcfe400</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44415,15 +52657,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_arm_gic_0</endModule>
+ <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
<endConnectionPoint>axi_slave1</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_mpu_reg_l2_MPUL2.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_uart_0_uart.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_mpu_reg_l2_MPUL2.axi_slave0">
+ end="a10_hps_i_uart_0_uart.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44434,7 +52676,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xfffff000</value>
+ <value>0xffc02000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44466,15 +52708,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_mpu_reg_l2_MPUL2</endModule>
+ <endModule>a10_hps_i_uart_0_uart</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_dma_DMASECURE.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_uart_1_uart.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_dma_DMASECURE.axi_slave0">
+ end="a10_hps_i_uart_1_uart.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44485,7 +52727,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda1000</value>
+ <value>0xffc02100</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44517,15 +52759,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_dma_DMASECURE</endModule>
+ <endModule>a10_hps_i_uart_1_uart</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_sys_mgr_core.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_timer_sp_0_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_sys_mgr_core.axi_slave0">
+ end="a10_hps_i_timer_sp_0_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44536,7 +52778,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd06000</value>
+ <value>0xffc02700</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44568,15 +52810,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_sys_mgr_core</endModule>
+ <endModule>a10_hps_i_timer_sp_0_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_rst_mgr_rstmgr.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_timer_sp_1_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_rst_mgr_rstmgr.axi_slave0">
+ end="a10_hps_i_timer_sp_1_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44587,7 +52829,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd05000</value>
+ <value>0xffc02800</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44619,15 +52861,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_rst_mgr_rstmgr</endModule>
+ <endModule>a10_hps_i_timer_sp_1_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_timer_sys_0_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave0">
+ end="a10_hps_i_timer_sys_0_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44638,7 +52880,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd03000</value>
+ <value>0xffd00000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44670,15 +52912,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
+ <endModule>a10_hps_i_timer_sys_0_timer</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_timer_sys_1_timer.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_fpga_mgr_fpgamgrregs.axi_slave1">
+ end="a10_hps_i_timer_sys_1_timer.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44689,7 +52931,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffcfe400</value>
+ <value>0xffd00100</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44721,15 +52963,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_fpga_mgr_fpgamgrregs</endModule>
- <endConnectionPoint>axi_slave1</endConnectionPoint>
+ <endModule>a10_hps_i_timer_sys_1_timer</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_uart_0_uart.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_watchdog_0_l4wd.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_uart_0_uart.axi_slave0">
+ end="a10_hps_i_watchdog_0_l4wd.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44740,7 +52982,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02000</value>
+ <value>0xffd00200</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44772,15 +53014,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_uart_0_uart</endModule>
+ <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_uart_1_uart.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_watchdog_1_l4wd.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_uart_1_uart.axi_slave0">
+ end="a10_hps_i_watchdog_1_l4wd.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44791,7 +53033,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02100</value>
+ <value>0xffd00300</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44823,15 +53065,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_uart_1_uart</endModule>
+ <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_timer_sp_0_timer.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_gpio_0_gpio.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_timer_sp_0_timer.axi_slave0">
+ end="a10_hps_i_gpio_0_gpio.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44842,7 +53084,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02700</value>
+ <value>0xffc02900</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44874,15 +53116,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_0_timer</endModule>
+ <endModule>a10_hps_i_gpio_0_gpio</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_timer_sp_1_timer.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_gpio_1_gpio.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_timer_sp_1_timer.axi_slave0">
+ end="a10_hps_i_gpio_1_gpio.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44893,7 +53135,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02800</value>
+ <value>0xffc02a00</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44925,15 +53167,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_timer_sp_1_timer</endModule>
+ <endModule>a10_hps_i_gpio_1_gpio</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_timer_sys_0_timer.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_gpio_2_gpio.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_timer_sys_0_timer.axi_slave0">
+ end="a10_hps_i_gpio_2_gpio.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44944,7 +53186,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00000</value>
+ <value>0xffc02b00</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -44976,15 +53218,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_0_timer</endModule>
+ <endModule>a10_hps_i_gpio_2_gpio</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_timer_sys_1_timer.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_i2c_0_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_timer_sys_1_timer.axi_slave0">
+ end="a10_hps_i_i2c_0_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -44995,7 +53237,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00100</value>
+ <value>0xffc02200</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45027,15 +53269,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_timer_sys_1_timer</endModule>
+ <endModule>a10_hps_i_i2c_0_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_watchdog_0_l4wd.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_i2c_1_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_watchdog_0_l4wd.axi_slave0">
+ end="a10_hps_i_i2c_1_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45046,7 +53288,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00200</value>
+ <value>0xffc02300</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45078,15 +53320,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_0_l4wd</endModule>
+ <endModule>a10_hps_i_i2c_1_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_watchdog_1_l4wd.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_i2c_emac_0_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_watchdog_1_l4wd.axi_slave0">
+ end="a10_hps_i_i2c_emac_0_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45097,7 +53339,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffd00300</value>
+ <value>0xffc02400</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45129,15 +53371,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_watchdog_1_l4wd</endModule>
+ <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_gpio_0_gpio.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_i2c_emac_1_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_gpio_0_gpio.axi_slave0">
+ end="a10_hps_i_i2c_emac_1_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45148,7 +53390,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02900</value>
+ <value>0xffc02500</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45180,15 +53422,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_gpio_0_gpio</endModule>
+ <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_gpio_1_gpio.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_i2c_emac_2_i2c.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_gpio_1_gpio.axi_slave0">
+ end="a10_hps_i_i2c_emac_2_i2c.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45199,7 +53441,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02a00</value>
+ <value>0xffc02600</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45231,15 +53473,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_gpio_1_gpio</endModule>
+ <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_gpio_2_gpio.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_nand_NANDDATA.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_gpio_2_gpio.axi_slave0">
+ end="a10_hps_i_nand_NANDDATA.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45250,7 +53492,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02b00</value>
+ <value>0xffb90000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45282,15 +53524,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_gpio_2_gpio</endModule>
+ <endModule>a10_hps_i_nand_NANDDATA</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_i2c_0_i2c.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_nand_NANDDATA.axi_slave1"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_i2c_0_i2c.axi_slave0">
+ end="a10_hps_i_nand_NANDDATA.axi_slave1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45301,7 +53543,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02200</value>
+ <value>0xffb80000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45333,15 +53575,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_i2c_0_i2c</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <endConnectionPoint>axi_slave1</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_i2c_1_i2c.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_spim_0_spim.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_i2c_1_i2c.axi_slave0">
+ end="a10_hps_i_spim_0_spim.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45352,7 +53594,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02300</value>
+ <value>0xffda4000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45384,15 +53626,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_i2c_1_i2c</endModule>
+ <endModule>a10_hps_i_spim_0_spim</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_i2c_emac_0_i2c.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_spim_1_spim.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_i2c_emac_0_i2c.axi_slave0">
+ end="a10_hps_i_spim_1_spim.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45403,7 +53645,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02400</value>
+ <value>0xffda5000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45435,15 +53677,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_0_i2c</endModule>
+ <endModule>a10_hps_i_spim_1_spim</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_i2c_emac_1_i2c.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_qspi_QSPIDATA.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_i2c_emac_1_i2c.axi_slave0">
+ end="a10_hps_i_qspi_QSPIDATA.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45454,7 +53696,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02500</value>
+ <value>0xff809000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45486,15 +53728,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_1_i2c</endModule>
+ <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_i2c_emac_2_i2c.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_qspi_QSPIDATA.axi_slave1"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_i2c_emac_2_i2c.axi_slave0">
+ end="a10_hps_i_qspi_QSPIDATA.axi_slave1">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45505,7 +53747,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffc02600</value>
+ <value>0xffa00000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45537,15 +53779,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_i2c_emac_2_i2c</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
+ <endConnectionPoint>axi_slave1</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_nand_NANDDATA.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_sdmmc_sdmmc.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_nand_NANDDATA.axi_slave0">
+ end="a10_hps_i_sdmmc_sdmmc.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45556,7 +53798,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffb90000</value>
+ <value>0xff808000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45588,15 +53830,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_nand_NANDDATA</endModule>
+ <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_nand_NANDDATA.axi_slave1"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_usbotg_0_globgrp.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_nand_NANDDATA.axi_slave1">
+ end="a10_hps_i_usbotg_0_globgrp.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45607,7 +53849,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffb80000</value>
+ <value>0xffb00000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45639,15 +53881,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_nand_NANDDATA</endModule>
- <endConnectionPoint>axi_slave1</endConnectionPoint>
+ <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_spim_0_spim.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_usbotg_1_globgrp.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_spim_0_spim.axi_slave0">
+ end="a10_hps_i_usbotg_1_globgrp.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45658,7 +53900,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda4000</value>
+ <value>0xffb40000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45690,15 +53932,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_spim_0_spim</endModule>
+ <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_spim_1_spim.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_emac_emac0.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_spim_1_spim.axi_slave0">
+ end="a10_hps_i_emac_emac0.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45709,7 +53951,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffda5000</value>
+ <value>0xff800000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45741,15 +53983,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_spim_1_spim</endModule>
+ <endModule>a10_hps_i_emac_emac0</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_qspi_QSPIDATA.axi_slave0"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_emac_emac1.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_qspi_QSPIDATA.axi_slave0">
+ end="a10_hps_i_emac_emac1.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45760,7 +54002,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xff809000</value>
+ <value>0xff802000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45792,15 +54034,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>a10_hps_bridges</startModule>
<startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
+ <endModule>a10_hps_i_emac_emac1</endModule>
<endConnectionPoint>axi_slave0</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_qspi_QSPIDATA.axi_slave1"
+ name="a10_hps_bridges.axi_f2h/a10_hps_i_emac_emac2.axi_slave0"
kind="avalon"
version="22.1"
start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_qspi_QSPIDATA.axi_slave1">
+ end="a10_hps_i_emac_emac2.axi_slave0">
<parameter name="arbitrationPriority">
<type>int</type>
<value>1</value>
@@ -45811,7 +54053,109 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="baseAddress">
<type>java.math.BigInteger</type>
- <value>0xffa00000</value>
+ <value>0xff804000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_bridges</startModule>
+ <startConnectionPoint>axi_f2h</startConnectionPoint>
+ <endModule>a10_hps_i_emac_emac2</endModule>
+ <endConnectionPoint>axi_slave0</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_bridges.h2f/eth_tse_0.control_port"
+ kind="avalon"
+ version="22.1"
+ start="a10_hps_bridges.h2f"
+ end="eth_tse_0.control_port">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0x0000</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="defaultConnection">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <startModule>a10_hps_bridges</startModule>
+ <startConnectionPoint>h2f</startConnectionPoint>
+ <endModule>eth_tse_0</endModule>
+ <endConnectionPoint>control_port</endConnectionPoint>
+ </connection>
+ <connection
+ name="a10_hps_bridges.h2f/eth_tse_1.control_port"
+ kind="avalon"
+ version="22.1"
+ start="a10_hps_bridges.h2f"
+ end="eth_tse_1.control_port">
+ <parameter name="arbitrationPriority">
+ <type>int</type>
+ <value>1</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="baseAddress">
+ <type>java.math.BigInteger</type>
+ <value>0x0400</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@@ -45842,33 +54186,25 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>a10_hps_bridges</startModule>
- <startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_qspi_QSPIDATA</endModule>
- <endConnectionPoint>axi_slave1</endConnectionPoint>
+ <startConnectionPoint>h2f</startConnectionPoint>
+ <endModule>eth_tse_1</endModule>
+ <endConnectionPoint>control_port</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_sdmmc_sdmmc.axi_slave0"
- kind="avalon"
+ name="clk_0.clk/eth_tse_0.control_port_clock_connection"
+ kind="clock"
version="22.1"
- start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_sdmmc_sdmmc.axi_slave0">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xff808000</value>
+ start="clk_0.clk"
+ end="eth_tse_0.control_port_clock_connection">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -45876,6 +54212,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>eth_tse_0</endModule>
+ <endConnectionPoint>control_port_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/eth_tse_1.control_port_clock_connection"
+ kind="clock"
+ version="22.1"
+ start="clk_0.clk"
+ end="eth_tse_1.control_port_clock_connection">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -45892,34 +54239,53 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_bridges</startModule>
- <startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_sdmmc_sdmmc</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>eth_tse_1</endModule>
+ <endConnectionPoint>control_port_clock_connection</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_usbotg_0_globgrp.axi_slave0"
- kind="avalon"
+ name="clk_0.clk/a10_hps_bridges.h2f_axi_clock"
+ kind="clock"
version="22.1"
- start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_usbotg_0_globgrp.axi_slave0">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
+ start="clk_0.clk"
+ end="a10_hps_bridges.h2f_axi_clock">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xffb00000</value>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>a10_hps_bridges</endModule>
+ <endConnectionPoint>h2f_axi_clock</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/a10_hps_bridges.h2f_lw_axi_clock"
+ kind="clock"
+ version="22.1"
+ start="clk_0.clk"
+ end="a10_hps_bridges.h2f_lw_axi_clock">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -45927,6 +54293,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>a10_hps_bridges</endModule>
+ <endConnectionPoint>h2f_lw_axi_clock</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_125m.clk/eth_tse_0.pcs_ref_clk_clock_connection"
+ kind="clock"
+ version="22.1"
+ start="clk_125m.clk"
+ end="eth_tse_0.pcs_ref_clk_clock_connection">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -45943,34 +54320,53 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_bridges</startModule>
- <startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_0_globgrp</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>clk_125m</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>eth_tse_0</endModule>
+ <endConnectionPoint>pcs_ref_clk_clock_connection</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_usbotg_1_globgrp.axi_slave0"
- kind="avalon"
+ name="clk_125m.clk/eth_tse_1.pcs_ref_clk_clock_connection"
+ kind="clock"
version="22.1"
- start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_usbotg_1_globgrp.axi_slave0">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
+ start="clk_125m.clk"
+ end="eth_tse_1.pcs_ref_clk_clock_connection">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xffb40000</value>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <startModule>clk_125m</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>eth_tse_1</endModule>
+ <endConnectionPoint>pcs_ref_clk_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_125m.clk/xcvr_atx_pll_a10_0.pll_refclk0"
+ kind="clock"
+ version="22.1"
+ start="clk_125m.clk"
+ end="xcvr_atx_pll_a10_0.pll_refclk0">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -45978,6 +54374,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>clk_125m</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>xcvr_atx_pll_a10_0</endModule>
+ <endConnectionPoint>pll_refclk0</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/eth_tse_0.receive_clock_connection"
+ kind="clock"
+ version="22.1"
+ start="clk_0.clk"
+ end="eth_tse_0.receive_clock_connection">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -45994,34 +54401,53 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_bridges</startModule>
- <startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_usbotg_1_globgrp</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>eth_tse_0</endModule>
+ <endConnectionPoint>receive_clock_connection</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_emac_emac0.axi_slave0"
- kind="avalon"
+ name="clk_0.clk/eth_tse_1.receive_clock_connection"
+ kind="clock"
version="22.1"
- start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_emac_emac0.axi_slave0">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
+ start="clk_0.clk"
+ end="eth_tse_1.receive_clock_connection">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xff800000</value>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>eth_tse_1</endModule>
+ <endConnectionPoint>receive_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_125m.clk/eth_tse_0.rx_cdr_refclk"
+ kind="clock"
+ version="22.1"
+ start="clk_125m.clk"
+ end="eth_tse_0.rx_cdr_refclk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -46029,6 +54455,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>clk_125m</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>eth_tse_0</endModule>
+ <endConnectionPoint>rx_cdr_refclk</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_125m.clk/eth_tse_1.rx_cdr_refclk"
+ kind="clock"
+ version="22.1"
+ start="clk_125m.clk"
+ end="eth_tse_1.rx_cdr_refclk">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -46045,34 +54482,53 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_bridges</startModule>
- <startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac0</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>clk_125m</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>eth_tse_1</endModule>
+ <endConnectionPoint>rx_cdr_refclk</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_emac_emac1.axi_slave0"
- kind="avalon"
+ name="clk_0.clk/eth_tse_0.transmit_clock_connection"
+ kind="clock"
version="22.1"
- start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_emac_emac1.axi_slave0">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
+ start="clk_0.clk"
+ end="eth_tse_0.transmit_clock_connection">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xff802000</value>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>eth_tse_0</endModule>
+ <endConnectionPoint>transmit_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk/eth_tse_1.transmit_clock_connection"
+ kind="clock"
+ version="22.1"
+ start="clk_0.clk"
+ end="eth_tse_1.transmit_clock_connection">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -46080,6 +54536,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk</startConnectionPoint>
+ <endModule>eth_tse_1</endModule>
+ <endConnectionPoint>transmit_clock_connection</endConnectionPoint>
+ </connection>
+ <connection
+ name="xcvr_atx_pll_a10_0.tx_serial_clk/eth_tse_0.tx_serial_clk"
+ kind="hssi_serial_clock"
+ version="22.1"
+ start="xcvr_atx_pll_a10_0.tx_serial_clk"
+ end="eth_tse_0.tx_serial_clk">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -46096,34 +54563,53 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_bridges</startModule>
- <startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac1</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>xcvr_atx_pll_a10_0</startModule>
+ <startConnectionPoint>tx_serial_clk</startConnectionPoint>
+ <endModule>eth_tse_0</endModule>
+ <endConnectionPoint>tx_serial_clk</endConnectionPoint>
</connection>
<connection
- name="a10_hps_bridges.axi_f2h/a10_hps_i_emac_emac2.axi_slave0"
- kind="avalon"
+ name="xcvr_atx_pll_a10_0.tx_serial_clk/eth_tse_1.tx_serial_clk"
+ kind="hssi_serial_clock"
version="22.1"
- start="a10_hps_bridges.axi_f2h"
- end="a10_hps_i_emac_emac2.axi_slave0">
- <parameter name="arbitrationPriority">
- <type>int</type>
- <value>1</value>
+ start="xcvr_atx_pll_a10_0.tx_serial_clk"
+ end="eth_tse_1.tx_serial_clk">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="baseAddress">
- <type>java.math.BigInteger</type>
- <value>0xff804000</value>
+ <parameter name="generateLegacySim">
+ <type>boolean</type>
+ <value>false</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
<valid>true</valid>
</parameter>
- <parameter name="defaultConnection">
+ <startModule>xcvr_atx_pll_a10_0</startModule>
+ <startConnectionPoint>tx_serial_clk</startConnectionPoint>
+ <endModule>eth_tse_1</endModule>
+ <endConnectionPoint>tx_serial_clk</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk_reset/a10_hps_bridges.h2f_axi_reset"
+ kind="reset"
+ version="22.1"
+ start="clk_0.clk_reset"
+ end="a10_hps_bridges.h2f_axi_reset">
+ <parameter name="deviceFamily">
+ <type>java.lang.String</type>
+ <value>UNKNOWN</value>
+ <derived>false</derived>
+ <enabled>true</enabled>
+ <visible>true</visible>
+ <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
<type>boolean</type>
<value>false</value>
<derived>false</derived>
@@ -46131,6 +54617,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>a10_hps_bridges</endModule>
+ <endConnectionPoint>h2f_axi_reset</endConnectionPoint>
+ </connection>
+ <connection
+ name="clk_0.clk_reset/a10_hps_bridges.h2f_lw_axi_reset"
+ kind="reset"
+ version="22.1"
+ start="clk_0.clk_reset"
+ end="a10_hps_bridges.h2f_lw_axi_reset">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -46147,17 +54644,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>a10_hps_bridges</startModule>
- <startConnectionPoint>axi_f2h</startConnectionPoint>
- <endModule>a10_hps_i_emac_emac2</endModule>
- <endConnectionPoint>axi_slave0</endConnectionPoint>
+ <startModule>clk_0</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>a10_hps_bridges</endModule>
+ <endConnectionPoint>h2f_lw_axi_reset</endConnectionPoint>
</connection>
<connection
- name="clk_0.clk/a10_hps_bridges.h2f_axi_clock"
- kind="clock"
+ name="clk_125m.clk_reset/eth_tse_0.reset_connection"
+ kind="reset"
version="22.1"
- start="clk_0.clk"
- end="a10_hps_bridges.h2f_axi_clock">
+ start="clk_125m.clk_reset"
+ end="eth_tse_0.reset_connection">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -46174,17 +54671,17 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>clk_0</startModule>
- <startConnectionPoint>clk</startConnectionPoint>
- <endModule>a10_hps_bridges</endModule>
- <endConnectionPoint>h2f_axi_clock</endConnectionPoint>
+ <startModule>clk_125m</startModule>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>eth_tse_0</endModule>
+ <endConnectionPoint>reset_connection</endConnectionPoint>
</connection>
<connection
- name="clk_0.clk/a10_hps_bridges.h2f_lw_axi_clock"
- kind="clock"
+ name="clk_0.clk_reset/eth_tse_0.reset_connection"
+ kind="reset"
version="22.1"
- start="clk_0.clk"
- end="a10_hps_bridges.h2f_lw_axi_clock">
+ start="clk_0.clk_reset"
+ end="eth_tse_0.reset_connection">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -46202,16 +54699,16 @@ parameters are a RESULT of the module parameters. -->
<valid>true</valid>
</parameter>
<startModule>clk_0</startModule>
- <startConnectionPoint>clk</startConnectionPoint>
- <endModule>a10_hps_bridges</endModule>
- <endConnectionPoint>h2f_lw_axi_clock</endConnectionPoint>
+ <startConnectionPoint>clk_reset</startConnectionPoint>
+ <endModule>eth_tse_0</endModule>
+ <endConnectionPoint>reset_connection</endConnectionPoint>
</connection>
<connection
- name="clk_0.clk_reset/a10_hps_bridges.h2f_axi_reset"
+ name="clk_0.clk_reset/eth_tse_1.reset_connection"
kind="reset"
version="22.1"
start="clk_0.clk_reset"
- end="a10_hps_bridges.h2f_axi_reset">
+ end="eth_tse_1.reset_connection">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -46230,15 +54727,15 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<startModule>clk_0</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_bridges</endModule>
- <endConnectionPoint>h2f_axi_reset</endConnectionPoint>
+ <endModule>eth_tse_1</endModule>
+ <endConnectionPoint>reset_connection</endConnectionPoint>
</connection>
<connection
- name="clk_0.clk_reset/a10_hps_bridges.h2f_lw_axi_reset"
+ name="clk_125m.clk_reset/eth_tse_1.reset_connection"
kind="reset"
version="22.1"
- start="clk_0.clk_reset"
- end="a10_hps_bridges.h2f_lw_axi_reset">
+ start="clk_125m.clk_reset"
+ end="eth_tse_1.reset_connection">
<parameter name="deviceFamily">
<type>java.lang.String</type>
<value>UNKNOWN</value>
@@ -46255,10 +54752,10 @@ parameters are a RESULT of the module parameters. -->
<visible>true</visible>
<valid>true</valid>
</parameter>
- <startModule>clk_0</startModule>
+ <startModule>clk_125m</startModule>
<startConnectionPoint>clk_reset</startConnectionPoint>
- <endModule>a10_hps_bridges</endModule>
- <endConnectionPoint>h2f_lw_axi_reset</endConnectionPoint>
+ <endModule>eth_tse_1</endModule>
+ <endConnectionPoint>reset_connection</endConnectionPoint>
</connection>
<plugin>
<instanceCount>1</instanceCount>
@@ -46269,7 +54766,7 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>52</instanceCount>
+ <instanceCount>54</instanceCount>
<name>reset_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
@@ -46277,7 +54774,7 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>6</instanceCount>
+ <instanceCount>39</instanceCount>
<name>conduit_end</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
@@ -46293,7 +54790,7 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>50</instanceCount>
+ <instanceCount>61</instanceCount>
<name>clock_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
@@ -46557,7 +55054,7 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>1</instanceCount>
+ <instanceCount>2</instanceCount>
<name>clock_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
@@ -46565,7 +55062,7 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>1</instanceCount>
+ <instanceCount>2</instanceCount>
<name>clock_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
@@ -46573,7 +55070,7 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>1</instanceCount>
+ <instanceCount>2</instanceCount>
<name>reset_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
@@ -46581,7 +55078,7 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>1</instanceCount>
+ <instanceCount>2</instanceCount>
<name>clock_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
@@ -46589,7 +55086,7 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>1</instanceCount>
+ <instanceCount>2</instanceCount>
<name>reset_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
@@ -46597,7 +55094,63 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>46</instanceCount>
+ <instanceCount>2</instanceCount>
+ <name>altera_eth_tse</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>Triple-Speed Ethernet Intel FPGA IP</displayName>
+ <version>22.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>2</instanceCount>
+ <name>avalon_slave</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Avalon Memory Mapped Slave</displayName>
+ <version>22.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>2</instanceCount>
+ <name>avalon_streaming_source</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Avalon Streaming Source</displayName>
+ <version>22.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>2</instanceCount>
+ <name>avalon_streaming_sink</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>Avalon Streaming Sink</displayName>
+ <version>22.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>2</instanceCount>
+ <name>hssi_serial_clock_sink</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>HSSI Serial Clock Input</displayName>
+ <version>22.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>altera_xcvr_atx_pll_a10</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IModule</subtype>
+ <displayName>Transceiver ATX PLL Intel Arria 10 FPGA IP</displayName>
+ <version>22.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>1</instanceCount>
+ <name>hssi_serial_clock_source</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+ <displayName>HSSI Serial Clock Output</displayName>
+ <version>22.1</version>
+ </plugin>
+ <plugin>
+ <instanceCount>57</instanceCount>
<name>clock</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
@@ -46605,7 +55158,7 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>42</instanceCount>
+ <instanceCount>46</instanceCount>
<name>reset</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
@@ -46613,7 +55166,7 @@ parameters are a RESULT of the module parameters. -->
<version>22.1</version>
</plugin>
<plugin>
- <instanceCount>123</instanceCount>
+ <instanceCount>125</instanceCount>
<name>avalon</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
@@ -46628,6 +55181,14 @@ parameters are a RESULT of the module parameters. -->
<displayName>Interrupt Connection</displayName>
<version>22.1</version>
</plugin>
+ <plugin>
+ <instanceCount>2</instanceCount>
+ <name>hssi_serial_clock</name>
+ <type>com.altera.entityinterfaces.IElementClass</type>
+ <subtype>com.altera.entityinterfaces.IConnection</subtype>
+ <displayName>HSSI Serial Clock Connection</displayName>
+ <version>22.1</version>
+ </plugin>
<reportVersion>22.1 922</reportVersion>
<uniqueIdentifier></uniqueIdentifier>
</EnsembleReport>
diff --git a/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_clock_crosser.v b/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_clock_crosser.v
new file mode 100644
index 0000000000000000000000000000000000000000..93fa22721413a90753078d89c17640a150189fa9
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_clock_crosser.v
@@ -0,0 +1,141 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $File: //acds/rel/22.1std/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_clock_crosser(
+ in_clk,
+ in_reset,
+ in_ready,
+ in_valid,
+ in_data,
+ out_clk,
+ out_reset,
+ out_ready,
+ out_valid,
+ out_data
+ );
+
+ parameter SYMBOLS_PER_BEAT = 1;
+ parameter BITS_PER_SYMBOL = 8;
+ parameter FORWARD_SYNC_DEPTH = 2;
+ parameter BACKWARD_SYNC_DEPTH = 2;
+ parameter USE_OUTPUT_PIPELINE = 1;
+
+ localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
+
+ input in_clk;
+ input in_reset;
+ output in_ready;
+ input in_valid;
+ input [DATA_WIDTH-1:0] in_data;
+
+ input out_clk;
+ input out_reset;
+ input out_ready;
+ output out_valid;
+ output [DATA_WIDTH-1:0] out_data;
+
+ // Data is guaranteed valid by control signal clock crossing. Cut data
+ // buffer false path.
+ (* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
+ reg [DATA_WIDTH-1:0] out_data_buffer;
+
+ reg in_data_toggle;
+ wire in_data_toggle_returned;
+ wire out_data_toggle;
+ reg out_data_toggle_flopped;
+
+ wire take_in_data;
+ wire out_data_taken;
+
+ wire out_valid_internal;
+ wire out_ready_internal;
+
+ assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
+ assign take_in_data = in_valid & in_ready;
+ assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
+ assign out_data_taken = out_ready_internal & out_valid_internal;
+
+ always @(posedge in_clk or posedge in_reset) begin
+ if (in_reset) begin
+ in_data_buffer <= {DATA_WIDTH{1'b0}};
+ in_data_toggle <= 1'b0;
+ end else begin
+ if (take_in_data) begin
+ in_data_toggle <= ~in_data_toggle;
+ in_data_buffer <= in_data;
+ end
+ end //in_reset
+ end //in_clk always block
+
+ always @(posedge out_clk or posedge out_reset) begin
+ if (out_reset) begin
+ out_data_toggle_flopped <= 1'b0;
+ out_data_buffer <= {DATA_WIDTH{1'b0}};
+ end else begin
+ out_data_buffer <= in_data_buffer;
+ if (out_data_taken) begin
+ out_data_toggle_flopped <= out_data_toggle;
+ end
+ end //end if
+ end //out_clk always block
+
+ altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
+ .clk(out_clk),
+ .reset_n(~out_reset),
+ .din(in_data_toggle),
+ .dout(out_data_toggle)
+ );
+
+ altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
+ .clk(in_clk),
+ .reset_n(~in_reset),
+ .din(out_data_toggle_flopped),
+ .dout(in_data_toggle_returned)
+ );
+
+ generate if (USE_OUTPUT_PIPELINE == 1) begin
+
+ altera_avalon_st_pipeline_base
+ #(
+ .BITS_PER_SYMBOL(BITS_PER_SYMBOL),
+ .SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
+ ) output_stage (
+ .clk(out_clk),
+ .reset(out_reset),
+ .in_ready(out_ready_internal),
+ .in_valid(out_valid_internal),
+ .in_data(out_data_buffer),
+ .out_ready(out_ready),
+ .out_valid(out_valid),
+ .out_data(out_data)
+ );
+
+ end else begin
+
+ assign out_valid = out_valid_internal;
+ assign out_ready_internal = out_ready;
+ assign out_data = out_data_buffer;
+
+ end
+
+ endgenerate
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_handshake_clock_crosser.sdc b/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_handshake_clock_crosser.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..913793e4eca938f52ff176ea0327f6fa8af1c374
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_handshake_clock_crosser.sdc
@@ -0,0 +1,71 @@
+# (C) 2001-2023 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any output
+# files from any of the foregoing (including device programming or simulation
+# files), and any associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License Subscription
+# Agreement, Intel FPGA IP License Agreement, or other applicable
+# license agreement, including, without limitation, that your use is for the
+# sole purpose of programming logic devices manufactured by Intel and sold by
+# Intel or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+
+# $File: //acds/main/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.sdc $
+# $Revision: #1 $
+# $Date: 2014/04/09 $
+# $Author: kespence $
+#------------------------------------------------------------------------------
+
+# -----------------------------------------------------------------------------
+# Altera timing constraints for Avalon clock domain crossing (CDC) paths.
+# The purpose of these constraints is to remove the false paths and replace with timing bounded
+# requirements for compilation.
+#
+# ***Important note ***
+#
+# The clocks involved in this transfer must be kept synchronous and no false path
+# should be set on these paths for these constraints to apply correctly.
+# -----------------------------------------------------------------------------
+
+set crosser_entity "altera_avalon_st_clock_crosser:"
+set_max_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] 100
+set_min_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] -100
+
+set sync_entity "altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:"
+set_max_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] 100
+set_min_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] -100
+
+if { [ is_project_open ] && [ string equal -nocase on [ get_global_assignment -name TIMEQUEST2 ] ] } {
+ set_net_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
+ set_net_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
+} else {
+ set_net_delay -from [get_registers *${crosser_entity}*|in_data_buffer* ] -to [get_registers *${crosser_entity}*|out_data_buffer* ] -max 2
+ set_net_delay -from [get_registers * ] -to [get_registers *${sync_entity}*|din_s1 ] -max 2
+}
+
+# -----------------------------------------------------------------------------
+# This procedure constrains the skew between the token and data bits, and should
+# be called from the top level SDC, once per instance of the clock crosser.
+#
+# The hierarchy path to the handshake clock crosser instance is required as an
+# argument.
+#
+# In practice, the token and data bits tend to be placed close together, making
+# excessive skew less of an issue.
+# -----------------------------------------------------------------------------
+proc constrain_alt_handshake_clock_crosser_skew { path } {
+
+ set in_regs [ get_registers $path|*altera_avalon_st_clock_crosser*|in_data_buffer* ]
+ set out_regs [ get_registers $path|*altera_avalon_st_clock_crosser*|out_data_buffer* ]
+
+ set in_regs [ add_to_collection $in_regs [ get_registers $path|*altera_avalon_st_clock_crosser*|in_data_toggle ] ]
+ set out_regs [ add_to_collection $out_regs [ get_registers $path|*altera_avalon_st_clock_crosser:*|altera_std_synchronizer_nocut:in_to_out_synchronizer|din_s1 ] ]
+
+ if { [ is_project_open ] && [ string equal -nocase on [ get_global_assignment -name TIMEQUEST2 ] ] } {
+ set_max_skew -from $in_regs -to $out_regs -get_skew_value_from_clock_period dst_clock_period -skew_value_multiplier 0.8
+ } else {
+ set_max_skew -from $in_regs -to $out_regs 1.5
+ }
+}
+
diff --git a/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_handshake_clock_crosser.v b/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_handshake_clock_crosser.v
new file mode 100644
index 0000000000000000000000000000000000000000..4f4b7c41f96dedfc73cb7f5a479a928da1b0974b
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_handshake_clock_crosser.v
@@ -0,0 +1,218 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $File: //acds/rel/22.1std/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+//------------------------------------------------------------------------------
+// Clock crosser module with handshaking mechanism
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_handshake_clock_crosser
+#(
+ parameter DATA_WIDTH = 8,
+ BITS_PER_SYMBOL = 8,
+ USE_PACKETS = 0,
+
+ // ------------------------------
+ // Optional signal widths
+ // ------------------------------
+ USE_CHANNEL = 0,
+ CHANNEL_WIDTH = 1,
+ USE_ERROR = 0,
+ ERROR_WIDTH = 1,
+
+ VALID_SYNC_DEPTH = 2,
+ READY_SYNC_DEPTH = 2,
+
+ USE_OUTPUT_PIPELINE = 1,
+
+ // ------------------------------
+ // Derived parameters
+ // ------------------------------
+ SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
+ EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
+)
+(
+ input in_clk,
+ input in_reset,
+ input out_clk,
+ input out_reset,
+
+ output in_ready,
+ input in_valid,
+ input [DATA_WIDTH - 1 : 0] in_data,
+ input [CHANNEL_WIDTH - 1 : 0] in_channel,
+ input [ERROR_WIDTH - 1 : 0] in_error,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
+
+ input out_ready,
+ output out_valid,
+ output [DATA_WIDTH - 1 : 0] out_data,
+ output [CHANNEL_WIDTH - 1 : 0] out_channel,
+ output [ERROR_WIDTH - 1 : 0] out_error,
+ output out_startofpacket,
+ output out_endofpacket,
+ output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
+);
+
+ // ------------------------------
+ // Payload-specific widths
+ // ------------------------------
+ localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
+ localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
+ localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
+
+ localparam PAYLOAD_WIDTH = DATA_WIDTH +
+ PACKET_WIDTH +
+ PCHANNEL_W +
+ EMPTY_WIDTH +
+ PERROR_W;
+
+
+ wire [PAYLOAD_WIDTH - 1: 0] in_payload;
+ wire [PAYLOAD_WIDTH - 1: 0] out_payload;
+
+ // ------------------------------
+ // Assign in_data and other optional sink interface
+ // signals to in_payload.
+ // ------------------------------
+ assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
+ generate
+ // optional packet inputs
+ if (PACKET_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH - 1 :
+ DATA_WIDTH
+ ] = {in_startofpacket, in_endofpacket};
+ end
+ // optional channel input
+ if (USE_CHANNEL) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
+ DATA_WIDTH + PACKET_WIDTH
+ ] = in_channel;
+ end
+ // optional empty input
+ if (EMPTY_WIDTH) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
+ ] = in_empty;
+ end
+ // optional error input
+ if (USE_ERROR) begin
+ assign in_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
+ ] = in_error;
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Pipe the input payload to our inner module which handles the
+ // actual clock crossing
+ // --------------------------------------------------
+ altera_avalon_st_clock_crosser
+ #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (PAYLOAD_WIDTH),
+ .FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
+ .BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
+ .USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
+ ) clock_xer (
+ .in_clk (in_clk ),
+ .in_reset (in_reset ),
+ .in_ready (in_ready ),
+ .in_valid (in_valid ),
+ .in_data (in_payload ),
+ .out_clk (out_clk ),
+ .out_reset (out_reset ),
+ .out_ready (out_ready ),
+ .out_valid (out_valid ),
+ .out_data (out_payload )
+ );
+
+ // --------------------------------------------------
+ // Split out_payload into the output signals.
+ // --------------------------------------------------
+ assign out_data = out_payload[DATA_WIDTH - 1 : 0];
+
+ generate
+ // optional packet outputs
+ if (USE_PACKETS) begin
+ assign {out_startofpacket, out_endofpacket} =
+ out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
+ end else begin
+ // avoid a "has no driver" warning.
+ assign {out_startofpacket, out_endofpacket} = 2'b0;
+ end
+
+ // optional channel output
+ if (USE_CHANNEL) begin
+ assign out_channel = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
+ DATA_WIDTH + PACKET_WIDTH
+ ];
+ end else begin
+ // avoid a "has no driver" warning.
+ assign out_channel = 1'b0;
+ end
+
+ // optional empty output
+ if (EMPTY_WIDTH) begin
+ assign out_empty = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
+ ];
+ end else begin
+ // avoid a "has no driver" warning.
+ assign out_empty = 1'b0;
+ end
+
+ // optional error output
+ if (USE_ERROR) begin
+ assign out_error = out_payload[
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
+ DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
+ ];
+ end else begin
+ // avoid a "has no driver" warning.
+ assign out_error = 1'b0;
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Calculates the log2ceil of the input value.
+ // --------------------------------------------------
+ function integer log2ceil;
+ input integer val;
+ integer i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_pipeline_base.v b/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_pipeline_base.v
new file mode 100644
index 0000000000000000000000000000000000000000..8485f07832b6caefff070d4128bb467089080833
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_avalon_st_pipeline_base.v
@@ -0,0 +1,139 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $File: //acds/rel/22.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_pipeline_base (
+ clk,
+ reset,
+ in_ready,
+ in_valid,
+ in_data,
+ out_ready,
+ out_valid,
+ out_data
+ );
+
+ parameter SYMBOLS_PER_BEAT = 1;
+ parameter BITS_PER_SYMBOL = 8;
+ parameter PIPELINE_READY = 1;
+ localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
+
+ input clk;
+ input reset;
+
+ output in_ready;
+ input in_valid;
+ input [DATA_WIDTH-1:0] in_data;
+
+ input out_ready;
+ output out_valid;
+ output [DATA_WIDTH-1:0] out_data;
+
+ reg full0;
+ reg full1;
+ reg [DATA_WIDTH-1:0] data0;
+ reg [DATA_WIDTH-1:0] data1;
+
+ assign out_valid = full1;
+ assign out_data = data1;
+
+ generate if (PIPELINE_READY == 1)
+ begin : REGISTERED_READY_PLINE
+
+ assign in_ready = !full0;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ data0 <= {DATA_WIDTH{1'b0}};
+ data1 <= {DATA_WIDTH{1'b0}};
+ end else begin
+ // ----------------------------
+ // always load the second slot if we can
+ // ----------------------------
+ if (~full0)
+ data0 <= in_data;
+ // ----------------------------
+ // first slot is loaded either from the second,
+ // or with new data
+ // ----------------------------
+ if (~full1 || (out_ready && out_valid)) begin
+ if (full0)
+ data1 <= data0;
+ else
+ data1 <= in_data;
+ end
+ end
+ end
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ full0 <= 1'b0;
+ full1 <= 1'b0;
+ end else begin
+ // no data in pipeline
+ if (~full0 & ~full1) begin
+ if (in_valid) begin
+ full1 <= 1'b1;
+ end
+ end // ~f1 & ~f0
+
+ // one datum in pipeline
+ if (full1 & ~full0) begin
+ if (in_valid & ~out_ready) begin
+ full0 <= 1'b1;
+ end
+ // back to empty
+ if (~in_valid & out_ready) begin
+ full1 <= 1'b0;
+ end
+ end // f1 & ~f0
+
+ // two data in pipeline
+ if (full1 & full0) begin
+ // go back to one datum state
+ if (out_ready) begin
+ full0 <= 1'b0;
+ end
+ end // end go back to one datum stage
+ end
+ end
+
+ end
+ else
+ begin : UNREGISTERED_READY_PLINE
+
+ // in_ready will be a pass through of the out_ready signal as it is not registered
+ assign in_ready = (~full1) | out_ready;
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ data1 <= 'b0;
+ full1 <= 1'b0;
+ end
+ else begin
+ if (in_ready) begin
+ data1 <= in_data;
+ full1 <= in_valid;
+ end
+ end
+ end
+ end
+ endgenerate
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_std_synchronizer_nocut.v b/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_std_synchronizer_nocut.v
new file mode 100644
index 0000000000000000000000000000000000000000..547456984e65a6eea477d4c9749c288222f3c1e8
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_avalon_st_handshake_clock_crosser_221/synth/altera_std_synchronizer_nocut.v
@@ -0,0 +1,195 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
+// $Revision: #8 $
+// $Date: 2009/02/18 $
+// $Author: pscheidt $
+//-----------------------------------------------------------------------------
+//
+// File: altera_std_synchronizer_nocut.v
+//
+// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
+// as altera_std_synchronizer.v, except that the embedded false
+// path constraint is removed in this module. If you use this
+// module, you will have to apply the appropriate timing
+// constraints.
+//
+// We expect to make this a standard Quartus atom eventually.
+//
+// Composed of two or more flip flops connected in series.
+// Random metastable condition is simulated when the
+// __ALTERA_STD__METASTABLE_SIM macro is defined.
+// Use +define+__ALTERA_STD__METASTABLE_SIM argument
+// on the Verilog simulator compiler command line to
+// enable this mode. In addition, define the macro
+// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
+// with every metastable event generated in the synchronizer.
+//
+// Copyright (C) Altera Corporation 2009, All Rights Reserved
+//-----------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_std_synchronizer_nocut (
+ clk,
+ reset_n,
+ din,
+ dout
+ );
+
+ parameter depth = 3; // This value must be >= 2 !
+ parameter rst_value = 0;
+
+ input clk;
+ input reset_n;
+ input din;
+ output dout;
+
+ // QuartusII synthesis directives:
+ // 1. Preserve all registers ie. do not touch them.
+ // 2. Do not merge other flip-flops with synchronizer flip-flops.
+ // QuartusII TimeQuest directives:
+ // 1. Identify all flip-flops in this module as members of the synchronizer
+ // to enable automatic metastability MTBF analysis.
+
+ (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
+
+ (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
+
+ //synthesis translate_off
+ initial begin
+ if (depth <2) begin
+ $display("%m: Error: synchronizer length: %0d less than 2.", depth);
+ end
+ end
+
+ // the first synchronizer register is either a simple D flop for synthesis
+ // and non-metastable simulation or a D flop with a method to inject random
+ // metastable events resulting in random delay of [0,1] cycles
+
+`ifdef __ALTERA_STD__METASTABLE_SIM
+
+ reg[31:0] RANDOM_SEED = 123456;
+ wire next_din_s1;
+ wire dout;
+ reg din_last;
+ reg random;
+ event metastable_event; // hook for debug monitoring
+
+ initial begin
+ $display("%m: Info: Metastable event injection simulation mode enabled");
+ end
+
+ always @(posedge clk) begin
+ if (reset_n == 0)
+ random <= $random(RANDOM_SEED);
+ else
+ random <= $random;
+ end
+
+ assign next_din_s1 = (din_last ^ din) ? random : din;
+
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_last <= (rst_value == 0)? 1'b0 : 1'b1;
+ else
+ din_last <= din;
+ end
+
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
+ else
+ din_s1 <= next_din_s1;
+ end
+
+`else
+
+ //synthesis translate_on
+ generate if (rst_value == 0)
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_s1 <= 1'b0;
+ else
+ din_s1 <= din;
+ end
+ endgenerate
+
+ generate if (rst_value == 1)
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_s1 <= 1'b1;
+ else
+ din_s1 <= din;
+ end
+ endgenerate
+ //synthesis translate_off
+
+`endif
+
+`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
+ always @(*) begin
+ if (reset_n && (din_last != din) && (random != din)) begin
+ $display("%m: Verbose Info: metastable event @ time %t", $time);
+ ->metastable_event;
+ end
+ end
+`endif
+
+ //synthesis translate_on
+
+ // the remaining synchronizer registers form a simple shift register
+ // of length depth-1
+ generate if (rst_value == 0)
+ if (depth < 3) begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b0}};
+ else
+ dreg <= din_s1;
+ end
+ end else begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b0}};
+ else
+ dreg <= {dreg[depth-3:0], din_s1};
+ end
+ end
+ endgenerate
+
+ generate if (rst_value == 1)
+ if (depth < 3) begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b1}};
+ else
+ dreg <= din_s1;
+ end
+ end else begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b1}};
+ else
+ dreg <= {dreg[depth-3:0], din_s1};
+ end
+ end
+ endgenerate
+
+ assign dout = dreg[depth-2];
+
+endmodule
+
+
+
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_2txhhaq.v b/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_2txhhaq.v
new file mode 100644
index 0000000000000000000000000000000000000000..6a29e5db8efbfcbb52608b3fb4e56d0326e0a2ae
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_2txhhaq.v
@@ -0,0 +1,1712 @@
+// arria10_hps_altera_eth_tse_221_2txhhaq.v
+
+// This file was auto-generated from altera_eth_tse_hw.tcl. If you edit it your changes
+// will probably be lost.
+//
+// Generated using ACDS version 22.1 922
+
+`timescale 1 ps / 1 ps
+module arria10_hps_altera_eth_tse_221_2txhhaq (
+ input wire clk, // control_port_clock_connection.clk
+ input wire reset, // reset_connection.reset
+ output wire [31:0] reg_data_out, // control_port.readdata
+ input wire reg_rd, // .read
+ input wire [31:0] reg_data_in, // .writedata
+ input wire reg_wr, // .write
+ output wire reg_busy, // .waitrequest
+ input wire [7:0] reg_addr, // .address
+ input wire ff_rx_clk, // receive_clock_connection.clk
+ input wire ff_tx_clk, // transmit_clock_connection.clk
+ output wire [31:0] ff_rx_data, // receive.data
+ output wire ff_rx_eop, // .endofpacket
+ output wire [5:0] rx_err, // .error
+ output wire [1:0] ff_rx_mod, // .empty
+ input wire ff_rx_rdy, // .ready
+ output wire ff_rx_sop, // .startofpacket
+ output wire ff_rx_dval, // .valid
+ input wire [31:0] ff_tx_data, // transmit.data
+ input wire ff_tx_eop, // .endofpacket
+ input wire ff_tx_err, // .error
+ input wire [1:0] ff_tx_mod, // .empty
+ output wire ff_tx_rdy, // .ready
+ input wire ff_tx_sop, // .startofpacket
+ input wire ff_tx_wren, // .valid
+ output wire mdc, // mac_mdio_connection.mdc
+ input wire mdio_in, // .mdio_in
+ output wire mdio_out, // .mdio_out
+ output wire mdio_oen, // .mdio_oen
+ output wire magic_wakeup, // mac_misc_connection.magic_wakeup
+ input wire magic_sleep_n, // .magic_sleep_n
+ input wire ff_tx_crc_fwd, // .ff_tx_crc_fwd
+ output wire ff_tx_septy, // .ff_tx_septy
+ output wire tx_ff_uflow, // .tx_ff_uflow
+ output wire ff_tx_a_full, // .ff_tx_a_full
+ output wire ff_tx_a_empty, // .ff_tx_a_empty
+ output wire [17:0] rx_err_stat, // .rx_err_stat
+ output wire [3:0] rx_frm_type, // .rx_frm_type
+ output wire ff_rx_dsav, // .ff_rx_dsav
+ output wire ff_rx_a_full, // .ff_rx_a_full
+ output wire ff_rx_a_empty, // .ff_rx_a_empty
+ input wire ref_clk, // pcs_ref_clk_clock_connection.clk
+ output wire led_crs, // status_led_connection.crs
+ output wire led_link, // .link
+ output wire led_panel_link, // .panel_link
+ output wire led_col, // .col
+ output wire led_an, // .an
+ output wire led_char_err, // .char_err
+ output wire led_disp_err, // .disp_err
+ output wire rx_recovclkout, // serdes_control_connection.export
+ input wire rxp, // serial_connection.rxp
+ output wire txp, // .txp
+ input wire [0:0] tx_serial_clk, // tx_serial_clk.clk
+ input wire rx_cdr_refclk, // rx_cdr_refclk.clk
+ input wire [0:0] tx_analogreset, // tx_analogreset.tx_analogreset
+ input wire [0:0] tx_digitalreset, // tx_digitalreset.tx_digitalreset
+ input wire [0:0] rx_analogreset, // rx_analogreset.rx_analogreset
+ input wire [0:0] rx_digitalreset, // rx_digitalreset.rx_digitalreset
+ output wire [0:0] tx_cal_busy, // tx_cal_busy.tx_cal_busy
+ output wire [0:0] rx_cal_busy, // rx_cal_busy.rx_cal_busy
+ input wire [0:0] rx_set_locktodata, // rx_set_locktodata.rx_set_locktodata
+ input wire [0:0] rx_set_locktoref, // rx_set_locktoref.rx_set_locktoref
+ output wire [0:0] rx_is_lockedtoref, // rx_is_lockedtoref.rx_is_lockedtoref
+ output wire [0:0] rx_is_lockedtodata // rx_is_lockedtodata.rx_is_lockedtodata
+ );
+
+ wire [31:0] avalon_arbiter_av_mac_master_0_readdata; // i_tse_mac:reg_data_out -> avalon_arbiter:mac_readdata_0
+ wire avalon_arbiter_av_mac_master_0_waitrequest; // i_tse_mac:reg_busy -> avalon_arbiter:mac_waitrequest_0
+ wire [7:0] avalon_arbiter_av_mac_master_0_address; // avalon_arbiter:mac_address_0 -> i_tse_mac:reg_addr
+ wire avalon_arbiter_av_mac_master_0_read; // avalon_arbiter:mac_read_0 -> i_tse_mac:reg_rd
+ wire [31:0] avalon_arbiter_av_mac_master_0_writedata; // avalon_arbiter:mac_writedata_0 -> i_tse_mac:reg_data_in
+ wire avalon_arbiter_av_mac_master_0_write; // avalon_arbiter:mac_write_0 -> i_tse_mac:reg_wr
+ wire i_tse_pcs_0_sd_loopback_sd_loopback; // i_tse_pcs_0:sd_loopback -> i_nf_native_phyip_terminator_0:sd_loopback
+ wire i_nf_native_phyip_0_rx_patterndetect_rx_patterndetect; // i_nf_native_phyip_0:rx_patterndetect -> i_tse_pcs_0:rx_patterndetect
+ wire [7:0] i_nf_native_phyip_0_rx_parallel_data_rx_parallel_data; // i_nf_native_phyip_0:rx_parallel_data -> i_tse_pcs_0:rx_frame
+ wire i_tse_pcs_0_tx_kchar_tx_datak; // i_tse_pcs_0:tx_kchar -> i_nf_native_phyip_0:tx_datak
+ wire i_nf_native_phyip_0_rx_disperr_rx_disperr; // i_nf_native_phyip_0:rx_disperr -> i_tse_pcs_0:rx_disp_err
+ wire i_nf_native_phyip_0_rx_errdetect_rx_errdetect; // i_nf_native_phyip_0:rx_errdetect -> i_tse_pcs_0:rx_char_err_gx
+ wire i_nf_native_phyip_0_rx_syncstatus_rx_syncstatus; // i_nf_native_phyip_0:rx_syncstatus -> i_tse_pcs_0:rx_syncstatus
+ wire i_nf_native_phyip_0_rx_runningdisp_rx_runningdisp; // i_nf_native_phyip_0:rx_runningdisp -> i_tse_pcs_0:rx_runningdisp
+ wire i_nf_native_phyip_0_rx_datak_rx_datak; // i_nf_native_phyip_0:rx_datak -> i_tse_pcs_0:rx_kchar
+ wire [7:0] i_tse_pcs_0_tx_frame_tx_parallel_data; // i_tse_pcs_0:tx_frame -> i_nf_native_phyip_0:tx_parallel_data
+ wire [4:0] i_nf_native_phyip_0_rx_std_bitslipboundarysel_rx_std_bitslipboundarysel; // i_nf_native_phyip_0:rx_std_bitslipboundarysel -> i_tse_pcs_0:wa_boundary
+ wire i_nf_native_phyip_terminator_0_rx_runlengthviolation_rx_runlengthviolation; // i_nf_native_phyip_terminator_0:rx_runlengthviolation -> i_tse_pcs_0:rx_runlengthviolation
+ wire i_nf_native_phyip_terminator_0_tx_pcs_clk_tx_pcs_clk; // i_nf_native_phyip_terminator_0:tx_pcs_clk -> i_tse_pcs_0:tx_pcs_clk
+ wire i_nf_native_phyip_terminator_0_rx_pcs_clk_rx_pcs_clk; // i_nf_native_phyip_terminator_0:rx_pcs_clk -> i_tse_pcs_0:rx_pcs_clk
+ wire [118:0] i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data; // i_nf_native_phyip_terminator_0:unused_tx_parallel_data -> i_nf_native_phyip_0:unused_tx_parallel_data
+ wire [0:0] i_nf_native_phyip_0_tx_serial_data_tx_serial_data; // i_nf_native_phyip_0:tx_serial_data -> i_nf_native_phyip_terminator_0:tx_serial_data
+ wire [0:0] i_nf_native_phyip_0_tx_clkout_clk; // i_nf_native_phyip_0:tx_clkout -> i_nf_native_phyip_terminator_0:tx_clk
+ wire i_nf_native_phyip_terminator_0_rx_seriallpbken_rx_seriallpbken; // i_nf_native_phyip_terminator_0:rx_seriallpbken -> i_nf_native_phyip_0:rx_seriallpbken
+ wire [113:0] i_nf_native_phyip_0_unused_rx_parallel_data_unused_rx_parallel_data; // i_nf_native_phyip_0:unused_rx_parallel_data -> i_nf_native_phyip_terminator_0:unused_rx_parallel_data
+ wire i_nf_native_phyip_terminator_0_rx_serial_data_rx_serial_data; // i_nf_native_phyip_terminator_0:rx_serial_data -> i_nf_native_phyip_0:rx_serial_data
+ wire [0:0] i_nf_native_phyip_0_rx_clkout_clk; // i_nf_native_phyip_0:rx_clkout -> i_nf_native_phyip_terminator_0:rx_clk
+ wire [0:0] i_nf_native_phyip_0_rx_pma_div_clkout_clk; // i_nf_native_phyip_0:rx_pma_div_clkout -> i_nf_native_phyip_terminator_0:rx_recovered_clk
+ wire i_nf_native_phyip_terminator_0_tx_coreclk_clk; // i_nf_native_phyip_terminator_0:tx_coreclk -> i_nf_native_phyip_0:tx_coreclkin
+ wire i_nf_native_phyip_terminator_0_rx_coreclk_clk; // i_nf_native_phyip_terminator_0:rx_coreclk -> i_nf_native_phyip_0:rx_coreclkin
+ wire [15:0] avalon_arbiter_av_pcs_master_0_readdata; // i_tse_pcs_0:reg_data_out -> avalon_arbiter:pcs_readdata_0
+ wire avalon_arbiter_av_pcs_master_0_waitrequest; // i_tse_pcs_0:reg_busy -> avalon_arbiter:pcs_waitrequest_0
+ wire [4:0] avalon_arbiter_av_pcs_master_0_address; // avalon_arbiter:pcs_address_0 -> i_tse_pcs_0:reg_addr
+ wire avalon_arbiter_av_pcs_master_0_read; // avalon_arbiter:pcs_read_0 -> i_tse_pcs_0:reg_rd
+ wire [15:0] avalon_arbiter_av_pcs_master_0_writedata; // avalon_arbiter:pcs_writedata_0 -> i_tse_pcs_0:reg_data_in
+ wire avalon_arbiter_av_pcs_master_0_write; // avalon_arbiter:pcs_write_0 -> i_tse_pcs_0:reg_wr
+ wire i_tse_pcs_0_pcs_transmit_clock_connection_clk; // i_tse_pcs_0:tx_clk -> [i_tse_mac:tx_clk, rst_controller:clk]
+ wire i_tse_pcs_0_pcs_receive_clock_connection_clk; // i_tse_pcs_0:rx_clk -> [i_tse_mac:rx_clk, rst_controller_001:clk]
+ wire [7:0] i_tse_pcs_0_gmii_connection_gmii_rx_d; // i_tse_pcs_0:gmii_rx_d -> i_tse_mac:gm_rx_d
+ wire i_tse_pcs_0_gmii_connection_gmii_rx_err; // i_tse_pcs_0:gmii_rx_err -> i_tse_mac:gm_rx_err
+ wire i_tse_pcs_0_gmii_connection_gmii_rx_dv; // i_tse_pcs_0:gmii_rx_dv -> i_tse_mac:gm_rx_dv
+ wire [7:0] i_tse_mac_mac_gmii_connection_gmii_tx_d; // i_tse_mac:gm_tx_d -> i_tse_pcs_0:gmii_tx_d
+ wire i_tse_mac_mac_gmii_connection_gmii_tx_en; // i_tse_mac:gm_tx_en -> i_tse_pcs_0:gmii_tx_en
+ wire i_tse_mac_mac_gmii_connection_gmii_tx_err; // i_tse_mac:gm_tx_err -> i_tse_pcs_0:gmii_tx_err
+ wire i_tse_mac_mac_mii_connection_mii_tx_en; // i_tse_mac:m_tx_en -> i_tse_pcs_0:mii_tx_en
+ wire [3:0] i_tse_pcs_0_mii_connection_mii_rx_d; // i_tse_pcs_0:mii_rx_d -> i_tse_mac:m_rx_d
+ wire i_tse_pcs_0_mii_connection_mii_col; // i_tse_pcs_0:mii_col -> i_tse_mac:m_rx_col
+ wire [3:0] i_tse_mac_mac_mii_connection_mii_tx_d; // i_tse_mac:m_tx_d -> i_tse_pcs_0:mii_tx_d
+ wire i_tse_mac_mac_mii_connection_mii_tx_err; // i_tse_mac:m_tx_err -> i_tse_pcs_0:mii_tx_err
+ wire i_tse_pcs_0_mii_connection_mii_crs; // i_tse_pcs_0:mii_crs -> i_tse_mac:m_rx_crs
+ wire i_tse_pcs_0_mii_connection_mii_rx_err; // i_tse_pcs_0:mii_rx_err -> i_tse_mac:m_rx_err
+ wire i_tse_pcs_0_mii_connection_mii_rx_dv; // i_tse_pcs_0:mii_rx_dv -> i_tse_mac:m_rx_en
+ wire i_tse_pcs_0_sgmii_status_connection_set_1000; // i_tse_pcs_0:set_1000 -> i_tse_mac:set_1000
+ wire i_tse_pcs_0_sgmii_status_connection_set_10; // i_tse_pcs_0:set_10 -> i_tse_mac:set_10
+ wire i_tse_pcs_0_clock_enable_connection_tx_clkena; // i_tse_pcs_0:tx_clkena -> i_tse_mac:tx_clkena
+ wire i_tse_pcs_0_clock_enable_connection_rx_clkena; // i_tse_pcs_0:rx_clkena -> i_tse_mac:rx_clkena
+ wire rst_controller_reset_out_reset; // rst_controller:reset_out -> i_tse_pcs_0:reset_tx_clk
+ wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> i_tse_pcs_0:reset_rx_clk
+ wire [127:0] i_nf_native_phyip_0_rx_parallel_data; // port fragment
+
+ altera_eth_tse_mac #(
+ .ING_ADDR (11),
+ .ENABLE_MAC_RX_VLAN (0),
+ .ENABLE_SUP_ADDR (0),
+ .DEVICE_FAMILY ("ARRIA10"),
+ .INSERT_TA (0),
+ .ING_FIFO (2048),
+ .ENABLE_ECC (0),
+ .CRC32DWIDTH (8),
+ .ENABLE_ENA (32),
+ .SYNCHRONIZER_DEPTH (3),
+ .ENABLE_MAC_TX_VLAN (0),
+ .RESET_LEVEL (1),
+ .STAT_CNT_ENA (1),
+ .CUST_VERSION (0),
+ .CRC32S1L2_EXTERN (0),
+ .MBIT_ONLY (1),
+ .EG_ADDR (11),
+ .CORE_VERSION (5633),
+ .CRC32GENDELAY (6),
+ .EG_FIFO (2048),
+ .REDUCED_INTERFACE_ENA (0),
+ .ENABLE_MAGIC_DETECT (1),
+ .ENABLE_MDIO (1),
+ .ENABLE_MAC_TXADDR_SET (1),
+ .RAM_TYPE ("AUTO"),
+ .CRC32CHECK16BIT (0),
+ .ENABLE_LGTH_CHECK (1),
+ .ENABLE_MAC_FLOW_CTRL (0),
+ .ENABLE_SHIFT16 (1),
+ .USE_SYNC_RESET (1),
+ .REDUCED_CONTROL (0),
+ .MDIO_CLK_DIV (40),
+ .ENABLE_PADDING (1),
+ .ENABLE_GMII_LOOPBACK (0),
+ .GBIT_ONLY (1),
+ .ENA_HASH (0),
+ .ENABLE_EXTENDED_STAT_REG (0),
+ .ENABLE_HD_LOGIC (0)
+ ) i_tse_mac (
+ .clk (clk), // control_port_clock_connection.clk
+ .reset (reset), // reset_connection.reset
+ .reg_addr (avalon_arbiter_av_mac_master_0_address), // control_port.address
+ .reg_data_out (avalon_arbiter_av_mac_master_0_readdata), // .readdata
+ .reg_rd (avalon_arbiter_av_mac_master_0_read), // .read
+ .reg_data_in (avalon_arbiter_av_mac_master_0_writedata), // .writedata
+ .reg_wr (avalon_arbiter_av_mac_master_0_write), // .write
+ .reg_busy (avalon_arbiter_av_mac_master_0_waitrequest), // .waitrequest
+ .ff_tx_clk (ff_tx_clk), // transmit_clock_connection.clk
+ .ff_rx_clk (ff_rx_clk), // receive_clock_connection.clk
+ .ff_rx_data (ff_rx_data), // receive.data
+ .ff_rx_eop (ff_rx_eop), // .endofpacket
+ .rx_err (rx_err), // .error
+ .ff_rx_mod (ff_rx_mod), // .empty
+ .ff_rx_rdy (ff_rx_rdy), // .ready
+ .ff_rx_sop (ff_rx_sop), // .startofpacket
+ .ff_rx_dval (ff_rx_dval), // .valid
+ .ff_tx_data (ff_tx_data), // transmit.data
+ .ff_tx_eop (ff_tx_eop), // .endofpacket
+ .ff_tx_err (ff_tx_err), // .error
+ .ff_tx_mod (ff_tx_mod), // .empty
+ .ff_tx_rdy (ff_tx_rdy), // .ready
+ .ff_tx_sop (ff_tx_sop), // .startofpacket
+ .ff_tx_wren (ff_tx_wren), // .valid
+ .magic_wakeup (magic_wakeup), // mac_misc_connection.export
+ .magic_sleep_n (magic_sleep_n), // .export
+ .ff_tx_crc_fwd (ff_tx_crc_fwd), // .export
+ .ff_tx_septy (ff_tx_septy), // .export
+ .tx_ff_uflow (tx_ff_uflow), // .export
+ .ff_tx_a_full (ff_tx_a_full), // .export
+ .ff_tx_a_empty (ff_tx_a_empty), // .export
+ .rx_err_stat (rx_err_stat), // .export
+ .rx_frm_type (rx_frm_type), // .export
+ .ff_rx_dsav (ff_rx_dsav), // .export
+ .ff_rx_a_full (ff_rx_a_full), // .export
+ .ff_rx_a_empty (ff_rx_a_empty), // .export
+ .mdc (mdc), // mac_mdio_connection.mdc
+ .mdio_in (mdio_in), // .mdio_in
+ .mdio_out (mdio_out), // .mdio_out
+ .mdio_oen (mdio_oen), // .mdio_oen
+ .gm_rx_d (i_tse_pcs_0_gmii_connection_gmii_rx_d), // mac_gmii_connection.gmii_rx_d
+ .gm_rx_dv (i_tse_pcs_0_gmii_connection_gmii_rx_dv), // .gmii_rx_dv
+ .gm_rx_err (i_tse_pcs_0_gmii_connection_gmii_rx_err), // .gmii_rx_err
+ .gm_tx_d (i_tse_mac_mac_gmii_connection_gmii_tx_d), // .gmii_tx_d
+ .gm_tx_en (i_tse_mac_mac_gmii_connection_gmii_tx_en), // .gmii_tx_en
+ .gm_tx_err (i_tse_mac_mac_gmii_connection_gmii_tx_err), // .gmii_tx_err
+ .m_rx_d (i_tse_pcs_0_mii_connection_mii_rx_d), // mac_mii_connection.mii_rx_d
+ .m_rx_en (i_tse_pcs_0_mii_connection_mii_rx_dv), // .mii_rx_dv
+ .m_rx_err (i_tse_pcs_0_mii_connection_mii_rx_err), // .mii_rx_err
+ .m_tx_d (i_tse_mac_mac_mii_connection_mii_tx_d), // .mii_tx_d
+ .m_tx_en (i_tse_mac_mac_mii_connection_mii_tx_en), // .mii_tx_en
+ .m_tx_err (i_tse_mac_mac_mii_connection_mii_tx_err), // .mii_tx_err
+ .m_rx_crs (i_tse_pcs_0_mii_connection_mii_crs), // .mii_crs
+ .m_rx_col (i_tse_pcs_0_mii_connection_mii_col), // .mii_col
+ .set_10 (i_tse_pcs_0_sgmii_status_connection_set_10), // mac_status_connection.set_10
+ .set_1000 (i_tse_pcs_0_sgmii_status_connection_set_1000), // .set_1000
+ .rx_clkena (i_tse_pcs_0_clock_enable_connection_rx_clkena), // mac_clkena_connection.rx_clkena
+ .tx_clkena (i_tse_pcs_0_clock_enable_connection_tx_clkena), // .tx_clkena
+ .tx_clk (i_tse_pcs_0_pcs_transmit_clock_connection_clk), // pcs_mac_tx_clock_connection.clk
+ .rx_clk (i_tse_pcs_0_pcs_receive_clock_connection_clk), // pcs_mac_rx_clock_connection.clk
+ .xon_gen (1'b0), // (terminated)
+ .xoff_gen (1'b0), // (terminated)
+ .mac_eccstatus (), // (terminated)
+ .rgmii_out1_aclr (), // (terminated)
+ .rgmii_out1_din (), // (terminated)
+ .rgmii_in1_dout (2'b00), // (terminated)
+ .rgmii_in1_ck (), // (terminated)
+ .rgmii_out4_din (), // (terminated)
+ .rgmii_out4_ck (), // (terminated)
+ .rgmii_in1_pad (), // (terminated)
+ .rgmii_out4_aclr (), // (terminated)
+ .rgmii_out1_pad (1'b0), // (terminated)
+ .rgmii_out1_ck (), // (terminated)
+ .rgmii_in4_dout (8'b00000000), // (terminated)
+ .rgmii_in4_pad (), // (terminated)
+ .rgmii_out4_pad (4'b0000), // (terminated)
+ .rgmii_in4_ck (), // (terminated)
+ .rgmii_in (4'b0000), // (terminated)
+ .rgmii_out (), // (terminated)
+ .rx_control (1'b0), // (terminated)
+ .tx_control (), // (terminated)
+ .eth_mode (), // (terminated)
+ .ena_10 () // (terminated)
+ );
+
+ altera_eth_tse_avalon_arbiter #(
+ .MAX_CHANNELS (1),
+ .MAC_ONLY (0),
+ .SLAVE_ADDR_WIDTH (8)
+ ) avalon_arbiter (
+ .clk (clk), // clk.clk
+ .reset (reset), // reset.reset
+ .reg_data_out (reg_data_out), // av_slave.readdata
+ .reg_rd (reg_rd), // .read
+ .reg_data_in (reg_data_in), // .writedata
+ .reg_wr (reg_wr), // .write
+ .reg_busy (reg_busy), // .waitrequest
+ .reg_addr (reg_addr), // .address
+ .mac_address_0 (avalon_arbiter_av_mac_master_0_address), // av_mac_master_0.address
+ .mac_readdata_0 (avalon_arbiter_av_mac_master_0_readdata), // .readdata
+ .mac_read_0 (avalon_arbiter_av_mac_master_0_read), // .read
+ .mac_writedata_0 (avalon_arbiter_av_mac_master_0_writedata), // .writedata
+ .mac_write_0 (avalon_arbiter_av_mac_master_0_write), // .write
+ .mac_waitrequest_0 (avalon_arbiter_av_mac_master_0_waitrequest), // .waitrequest
+ .pcs_address_0 (avalon_arbiter_av_pcs_master_0_address), // av_pcs_master_0.address
+ .pcs_readdata_0 (avalon_arbiter_av_pcs_master_0_readdata), // .readdata
+ .pcs_read_0 (avalon_arbiter_av_pcs_master_0_read), // .read
+ .pcs_writedata_0 (avalon_arbiter_av_pcs_master_0_writedata), // .writedata
+ .pcs_write_0 (avalon_arbiter_av_pcs_master_0_write), // .write
+ .pcs_waitrequest_0 (avalon_arbiter_av_pcs_master_0_waitrequest), // .waitrequest
+ .mac_address_1 (), // (terminated)
+ .mac_readdata_1 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_1 (), // (terminated)
+ .mac_writedata_1 (), // (terminated)
+ .mac_write_1 (), // (terminated)
+ .mac_waitrequest_1 (1'b0), // (terminated)
+ .pcs_address_1 (), // (terminated)
+ .pcs_readdata_1 (16'b0000000000000000), // (terminated)
+ .pcs_read_1 (), // (terminated)
+ .pcs_writedata_1 (), // (terminated)
+ .pcs_write_1 (), // (terminated)
+ .pcs_waitrequest_1 (1'b0), // (terminated)
+ .mac_address_2 (), // (terminated)
+ .mac_readdata_2 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_2 (), // (terminated)
+ .mac_writedata_2 (), // (terminated)
+ .mac_write_2 (), // (terminated)
+ .mac_waitrequest_2 (1'b0), // (terminated)
+ .pcs_address_2 (), // (terminated)
+ .pcs_readdata_2 (16'b0000000000000000), // (terminated)
+ .pcs_read_2 (), // (terminated)
+ .pcs_writedata_2 (), // (terminated)
+ .pcs_write_2 (), // (terminated)
+ .pcs_waitrequest_2 (1'b0), // (terminated)
+ .mac_address_3 (), // (terminated)
+ .mac_readdata_3 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_3 (), // (terminated)
+ .mac_writedata_3 (), // (terminated)
+ .mac_write_3 (), // (terminated)
+ .mac_waitrequest_3 (1'b0), // (terminated)
+ .pcs_address_3 (), // (terminated)
+ .pcs_readdata_3 (16'b0000000000000000), // (terminated)
+ .pcs_read_3 (), // (terminated)
+ .pcs_writedata_3 (), // (terminated)
+ .pcs_write_3 (), // (terminated)
+ .pcs_waitrequest_3 (1'b0), // (terminated)
+ .mac_address_4 (), // (terminated)
+ .mac_readdata_4 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_4 (), // (terminated)
+ .mac_writedata_4 (), // (terminated)
+ .mac_write_4 (), // (terminated)
+ .mac_waitrequest_4 (1'b0), // (terminated)
+ .pcs_address_4 (), // (terminated)
+ .pcs_readdata_4 (16'b0000000000000000), // (terminated)
+ .pcs_read_4 (), // (terminated)
+ .pcs_writedata_4 (), // (terminated)
+ .pcs_write_4 (), // (terminated)
+ .pcs_waitrequest_4 (1'b0), // (terminated)
+ .mac_address_5 (), // (terminated)
+ .mac_readdata_5 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_5 (), // (terminated)
+ .mac_writedata_5 (), // (terminated)
+ .mac_write_5 (), // (terminated)
+ .mac_waitrequest_5 (1'b0), // (terminated)
+ .pcs_address_5 (), // (terminated)
+ .pcs_readdata_5 (16'b0000000000000000), // (terminated)
+ .pcs_read_5 (), // (terminated)
+ .pcs_writedata_5 (), // (terminated)
+ .pcs_write_5 (), // (terminated)
+ .pcs_waitrequest_5 (1'b0), // (terminated)
+ .mac_address_6 (), // (terminated)
+ .mac_readdata_6 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_6 (), // (terminated)
+ .mac_writedata_6 (), // (terminated)
+ .mac_write_6 (), // (terminated)
+ .mac_waitrequest_6 (1'b0), // (terminated)
+ .pcs_address_6 (), // (terminated)
+ .pcs_readdata_6 (16'b0000000000000000), // (terminated)
+ .pcs_read_6 (), // (terminated)
+ .pcs_writedata_6 (), // (terminated)
+ .pcs_write_6 (), // (terminated)
+ .pcs_waitrequest_6 (1'b0), // (terminated)
+ .mac_address_7 (), // (terminated)
+ .mac_readdata_7 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_7 (), // (terminated)
+ .mac_writedata_7 (), // (terminated)
+ .mac_write_7 (), // (terminated)
+ .mac_waitrequest_7 (1'b0), // (terminated)
+ .pcs_address_7 (), // (terminated)
+ .pcs_readdata_7 (16'b0000000000000000), // (terminated)
+ .pcs_read_7 (), // (terminated)
+ .pcs_writedata_7 (), // (terminated)
+ .pcs_write_7 (), // (terminated)
+ .pcs_waitrequest_7 (1'b0), // (terminated)
+ .mac_address_8 (), // (terminated)
+ .mac_readdata_8 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_8 (), // (terminated)
+ .mac_writedata_8 (), // (terminated)
+ .mac_write_8 (), // (terminated)
+ .mac_waitrequest_8 (1'b0), // (terminated)
+ .pcs_address_8 (), // (terminated)
+ .pcs_readdata_8 (16'b0000000000000000), // (terminated)
+ .pcs_read_8 (), // (terminated)
+ .pcs_writedata_8 (), // (terminated)
+ .pcs_write_8 (), // (terminated)
+ .pcs_waitrequest_8 (1'b0), // (terminated)
+ .mac_address_9 (), // (terminated)
+ .mac_readdata_9 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_9 (), // (terminated)
+ .mac_writedata_9 (), // (terminated)
+ .mac_write_9 (), // (terminated)
+ .mac_waitrequest_9 (1'b0), // (terminated)
+ .pcs_address_9 (), // (terminated)
+ .pcs_readdata_9 (16'b0000000000000000), // (terminated)
+ .pcs_read_9 (), // (terminated)
+ .pcs_writedata_9 (), // (terminated)
+ .pcs_write_9 (), // (terminated)
+ .pcs_waitrequest_9 (1'b0), // (terminated)
+ .mac_address_10 (), // (terminated)
+ .mac_readdata_10 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_10 (), // (terminated)
+ .mac_writedata_10 (), // (terminated)
+ .mac_write_10 (), // (terminated)
+ .mac_waitrequest_10 (1'b0), // (terminated)
+ .pcs_address_10 (), // (terminated)
+ .pcs_readdata_10 (16'b0000000000000000), // (terminated)
+ .pcs_read_10 (), // (terminated)
+ .pcs_writedata_10 (), // (terminated)
+ .pcs_write_10 (), // (terminated)
+ .pcs_waitrequest_10 (1'b0), // (terminated)
+ .mac_address_11 (), // (terminated)
+ .mac_readdata_11 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_11 (), // (terminated)
+ .mac_writedata_11 (), // (terminated)
+ .mac_write_11 (), // (terminated)
+ .mac_waitrequest_11 (1'b0), // (terminated)
+ .pcs_address_11 (), // (terminated)
+ .pcs_readdata_11 (16'b0000000000000000), // (terminated)
+ .pcs_read_11 (), // (terminated)
+ .pcs_writedata_11 (), // (terminated)
+ .pcs_write_11 (), // (terminated)
+ .pcs_waitrequest_11 (1'b0), // (terminated)
+ .mac_address_12 (), // (terminated)
+ .mac_readdata_12 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_12 (), // (terminated)
+ .mac_writedata_12 (), // (terminated)
+ .mac_write_12 (), // (terminated)
+ .mac_waitrequest_12 (1'b0), // (terminated)
+ .pcs_address_12 (), // (terminated)
+ .pcs_readdata_12 (16'b0000000000000000), // (terminated)
+ .pcs_read_12 (), // (terminated)
+ .pcs_writedata_12 (), // (terminated)
+ .pcs_write_12 (), // (terminated)
+ .pcs_waitrequest_12 (1'b0), // (terminated)
+ .mac_address_13 (), // (terminated)
+ .mac_readdata_13 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_13 (), // (terminated)
+ .mac_writedata_13 (), // (terminated)
+ .mac_write_13 (), // (terminated)
+ .mac_waitrequest_13 (1'b0), // (terminated)
+ .pcs_address_13 (), // (terminated)
+ .pcs_readdata_13 (16'b0000000000000000), // (terminated)
+ .pcs_read_13 (), // (terminated)
+ .pcs_writedata_13 (), // (terminated)
+ .pcs_write_13 (), // (terminated)
+ .pcs_waitrequest_13 (1'b0), // (terminated)
+ .mac_address_14 (), // (terminated)
+ .mac_readdata_14 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_14 (), // (terminated)
+ .mac_writedata_14 (), // (terminated)
+ .mac_write_14 (), // (terminated)
+ .mac_waitrequest_14 (1'b0), // (terminated)
+ .pcs_address_14 (), // (terminated)
+ .pcs_readdata_14 (16'b0000000000000000), // (terminated)
+ .pcs_read_14 (), // (terminated)
+ .pcs_writedata_14 (), // (terminated)
+ .pcs_write_14 (), // (terminated)
+ .pcs_waitrequest_14 (1'b0), // (terminated)
+ .mac_address_15 (), // (terminated)
+ .mac_readdata_15 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_15 (), // (terminated)
+ .mac_writedata_15 (), // (terminated)
+ .mac_write_15 (), // (terminated)
+ .mac_waitrequest_15 (1'b0), // (terminated)
+ .pcs_address_15 (), // (terminated)
+ .pcs_readdata_15 (16'b0000000000000000), // (terminated)
+ .pcs_read_15 (), // (terminated)
+ .pcs_writedata_15 (), // (terminated)
+ .pcs_write_15 (), // (terminated)
+ .pcs_waitrequest_15 (1'b0), // (terminated)
+ .mac_address_16 (), // (terminated)
+ .mac_readdata_16 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_16 (), // (terminated)
+ .mac_writedata_16 (), // (terminated)
+ .mac_write_16 (), // (terminated)
+ .mac_waitrequest_16 (1'b0), // (terminated)
+ .pcs_address_16 (), // (terminated)
+ .pcs_readdata_16 (16'b0000000000000000), // (terminated)
+ .pcs_read_16 (), // (terminated)
+ .pcs_writedata_16 (), // (terminated)
+ .pcs_write_16 (), // (terminated)
+ .pcs_waitrequest_16 (1'b0), // (terminated)
+ .mac_address_17 (), // (terminated)
+ .mac_readdata_17 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_17 (), // (terminated)
+ .mac_writedata_17 (), // (terminated)
+ .mac_write_17 (), // (terminated)
+ .mac_waitrequest_17 (1'b0), // (terminated)
+ .pcs_address_17 (), // (terminated)
+ .pcs_readdata_17 (16'b0000000000000000), // (terminated)
+ .pcs_read_17 (), // (terminated)
+ .pcs_writedata_17 (), // (terminated)
+ .pcs_write_17 (), // (terminated)
+ .pcs_waitrequest_17 (1'b0), // (terminated)
+ .mac_address_18 (), // (terminated)
+ .mac_readdata_18 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_18 (), // (terminated)
+ .mac_writedata_18 (), // (terminated)
+ .mac_write_18 (), // (terminated)
+ .mac_waitrequest_18 (1'b0), // (terminated)
+ .pcs_address_18 (), // (terminated)
+ .pcs_readdata_18 (16'b0000000000000000), // (terminated)
+ .pcs_read_18 (), // (terminated)
+ .pcs_writedata_18 (), // (terminated)
+ .pcs_write_18 (), // (terminated)
+ .pcs_waitrequest_18 (1'b0), // (terminated)
+ .mac_address_19 (), // (terminated)
+ .mac_readdata_19 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_19 (), // (terminated)
+ .mac_writedata_19 (), // (terminated)
+ .mac_write_19 (), // (terminated)
+ .mac_waitrequest_19 (1'b0), // (terminated)
+ .pcs_address_19 (), // (terminated)
+ .pcs_readdata_19 (16'b0000000000000000), // (terminated)
+ .pcs_read_19 (), // (terminated)
+ .pcs_writedata_19 (), // (terminated)
+ .pcs_write_19 (), // (terminated)
+ .pcs_waitrequest_19 (1'b0), // (terminated)
+ .mac_address_20 (), // (terminated)
+ .mac_readdata_20 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_20 (), // (terminated)
+ .mac_writedata_20 (), // (terminated)
+ .mac_write_20 (), // (terminated)
+ .mac_waitrequest_20 (1'b0), // (terminated)
+ .pcs_address_20 (), // (terminated)
+ .pcs_readdata_20 (16'b0000000000000000), // (terminated)
+ .pcs_read_20 (), // (terminated)
+ .pcs_writedata_20 (), // (terminated)
+ .pcs_write_20 (), // (terminated)
+ .pcs_waitrequest_20 (1'b0), // (terminated)
+ .mac_address_21 (), // (terminated)
+ .mac_readdata_21 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_21 (), // (terminated)
+ .mac_writedata_21 (), // (terminated)
+ .mac_write_21 (), // (terminated)
+ .mac_waitrequest_21 (1'b0), // (terminated)
+ .pcs_address_21 (), // (terminated)
+ .pcs_readdata_21 (16'b0000000000000000), // (terminated)
+ .pcs_read_21 (), // (terminated)
+ .pcs_writedata_21 (), // (terminated)
+ .pcs_write_21 (), // (terminated)
+ .pcs_waitrequest_21 (1'b0), // (terminated)
+ .mac_address_22 (), // (terminated)
+ .mac_readdata_22 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_22 (), // (terminated)
+ .mac_writedata_22 (), // (terminated)
+ .mac_write_22 (), // (terminated)
+ .mac_waitrequest_22 (1'b0), // (terminated)
+ .pcs_address_22 (), // (terminated)
+ .pcs_readdata_22 (16'b0000000000000000), // (terminated)
+ .pcs_read_22 (), // (terminated)
+ .pcs_writedata_22 (), // (terminated)
+ .pcs_write_22 (), // (terminated)
+ .pcs_waitrequest_22 (1'b0), // (terminated)
+ .mac_address_23 (), // (terminated)
+ .mac_readdata_23 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_23 (), // (terminated)
+ .mac_writedata_23 (), // (terminated)
+ .mac_write_23 (), // (terminated)
+ .mac_waitrequest_23 (1'b0), // (terminated)
+ .pcs_address_23 (), // (terminated)
+ .pcs_readdata_23 (16'b0000000000000000), // (terminated)
+ .pcs_read_23 (), // (terminated)
+ .pcs_writedata_23 (), // (terminated)
+ .pcs_write_23 (), // (terminated)
+ .pcs_waitrequest_23 (1'b0) // (terminated)
+ );
+
+ altera_eth_tse_pcs_pma_nf_phyip #(
+ .ENABLE_TIMESTAMPING (0),
+ .DEV_VERSION (5633),
+ .ENABLE_ECC (0),
+ .DEVICE_FAMILY ("ARRIA10"),
+ .SYNCHRONIZER_DEPTH (3),
+ .ENABLE_CLK_SHARING (0),
+ .ENABLE_SGMII (1),
+ .PHY_IDENTIFIER (0)
+ ) i_tse_pcs_0 (
+ .clk (clk), // control_port_clock_connection.clk
+ .reset (reset), // reset_connection.reset
+ .reg_addr (avalon_arbiter_av_pcs_master_0_address), // control_port.address
+ .reg_data_out (avalon_arbiter_av_pcs_master_0_readdata), // .readdata
+ .reg_rd (avalon_arbiter_av_pcs_master_0_read), // .read
+ .reg_data_in (avalon_arbiter_av_pcs_master_0_writedata), // .writedata
+ .reg_wr (avalon_arbiter_av_pcs_master_0_write), // .write
+ .reg_busy (avalon_arbiter_av_pcs_master_0_waitrequest), // .waitrequest
+ .ref_clk (ref_clk), // pcs_ref_clk_clock_connection.clk
+ .rx_pcs_clk (i_nf_native_phyip_terminator_0_rx_pcs_clk_rx_pcs_clk), // rx_pcs_clk.rx_pcs_clk
+ .sd_loopback (i_tse_pcs_0_sd_loopback_sd_loopback), // sd_loopback.sd_loopback
+ .rx_disp_err (i_nf_native_phyip_0_rx_disperr_rx_disperr), // rx_disp_err.rx_disperr
+ .tx_pcs_clk (i_nf_native_phyip_terminator_0_tx_pcs_clk_tx_pcs_clk), // tx_pcs_clk.tx_pcs_clk
+ .rx_runningdisp (i_nf_native_phyip_0_rx_runningdisp_rx_runningdisp), // rx_runningdisp.rx_runningdisp
+ .rx_frame (i_nf_native_phyip_0_rx_parallel_data_rx_parallel_data), // rx_frame.rx_parallel_data
+ .rx_runlengthviolation (i_nf_native_phyip_terminator_0_rx_runlengthviolation_rx_runlengthviolation), // rx_runlengthviolation.rx_runlengthviolation
+ .rx_char_err_gx (i_nf_native_phyip_0_rx_errdetect_rx_errdetect), // rx_char_err_gx.rx_errdetect
+ .tx_frame (i_tse_pcs_0_tx_frame_tx_parallel_data), // tx_frame.tx_parallel_data
+ .rx_patterndetect (i_nf_native_phyip_0_rx_patterndetect_rx_patterndetect), // rx_patterndetect.rx_patterndetect
+ .rx_kchar (i_nf_native_phyip_0_rx_datak_rx_datak), // rx_kchar.rx_datak
+ .rx_syncstatus (i_nf_native_phyip_0_rx_syncstatus_rx_syncstatus), // rx_syncstatus.rx_syncstatus
+ .tx_kchar (i_tse_pcs_0_tx_kchar_tx_datak), // tx_kchar.tx_datak
+ .tx_clkena (i_tse_pcs_0_clock_enable_connection_tx_clkena), // clock_enable_connection.tx_clkena
+ .rx_clkena (i_tse_pcs_0_clock_enable_connection_rx_clkena), // .rx_clkena
+ .gmii_rx_dv (i_tse_pcs_0_gmii_connection_gmii_rx_dv), // gmii_connection.gmii_rx_dv
+ .gmii_rx_d (i_tse_pcs_0_gmii_connection_gmii_rx_d), // .gmii_rx_d
+ .gmii_rx_err (i_tse_pcs_0_gmii_connection_gmii_rx_err), // .gmii_rx_err
+ .gmii_tx_en (i_tse_mac_mac_gmii_connection_gmii_tx_en), // .gmii_tx_en
+ .gmii_tx_d (i_tse_mac_mac_gmii_connection_gmii_tx_d), // .gmii_tx_d
+ .gmii_tx_err (i_tse_mac_mac_gmii_connection_gmii_tx_err), // .gmii_tx_err
+ .mii_rx_dv (i_tse_pcs_0_mii_connection_mii_rx_dv), // mii_connection.mii_rx_dv
+ .mii_rx_d (i_tse_pcs_0_mii_connection_mii_rx_d), // .mii_rx_d
+ .mii_rx_err (i_tse_pcs_0_mii_connection_mii_rx_err), // .mii_rx_err
+ .mii_tx_en (i_tse_mac_mac_mii_connection_mii_tx_en), // .mii_tx_en
+ .mii_tx_d (i_tse_mac_mac_mii_connection_mii_tx_d), // .mii_tx_d
+ .mii_tx_err (i_tse_mac_mac_mii_connection_mii_tx_err), // .mii_tx_err
+ .mii_col (i_tse_pcs_0_mii_connection_mii_col), // .mii_col
+ .mii_crs (i_tse_pcs_0_mii_connection_mii_crs), // .mii_crs
+ .set_10 (i_tse_pcs_0_sgmii_status_connection_set_10), // sgmii_status_connection.set_10
+ .set_1000 (i_tse_pcs_0_sgmii_status_connection_set_1000), // .set_1000
+ .tx_clk (i_tse_pcs_0_pcs_transmit_clock_connection_clk), // pcs_transmit_clock_connection.clk
+ .rx_clk (i_tse_pcs_0_pcs_receive_clock_connection_clk), // pcs_receive_clock_connection.clk
+ .reset_tx_clk (rst_controller_reset_out_reset), // pcs_transmit_reset_connection.reset
+ .reset_rx_clk (rst_controller_001_reset_out_reset), // pcs_receive_reset_connection.reset
+ .led_crs (led_crs), // status_led_connection.export
+ .led_link (led_link), // .export
+ .led_panel_link (led_panel_link), // .export
+ .led_col (led_col), // .export
+ .led_an (led_an), // .export
+ .led_char_err (led_char_err), // .export
+ .led_disp_err (led_disp_err), // .export
+ .wa_boundary (i_nf_native_phyip_0_rx_std_bitslipboundarysel_rx_std_bitslipboundarysel), // wa_boundary.rx_std_bitslipboundarysel
+ .rx_rmfifodatadeleted (1'b0), // (terminated)
+ .rx_rmfifodatainserted (1'b0), // (terminated)
+ .set_100 (), // (terminated)
+ .hd_ena (), // (terminated)
+ .pcs_phase_measure_clk (1'b0), // (terminated)
+ .rx_latency_adj (), // (terminated)
+ .tx_latency_adj (), // (terminated)
+ .tx_ptp_alignment (), // (terminated)
+ .pcs_eccstatus () // (terminated)
+ );
+
+ arria10_hps_altera_xcvr_native_a10_221_sfv7jkq #(
+ .device_revision ("20nm4"),
+ .duplex_mode ("duplex"),
+ .channels (1),
+ .enable_calibration (1),
+ .enable_analog_resets (1),
+ .enable_reset_sequence (1),
+ .bonded_mode ("not_bonded"),
+ .pcs_bonding_master (0),
+ .plls (1),
+ .number_physical_bonding_clocks (1),
+ .cdr_refclk_cnt (1),
+ .enable_hip (0),
+ .hip_cal_en ("disable"),
+ .rcfg_enable (0),
+ .rcfg_shared (0),
+ .rcfg_jtag_enable (0),
+ .rcfg_separate_avmm_busy (0),
+ .adme_prot_mode ("gige_1588"),
+ .adme_data_rate ("1250000000"),
+ .enable_pcie_dfe_ip (0),
+ .sim_reduced_counters (0),
+ .disable_continuous_dfe (0),
+ .dbg_embedded_debug_enable (0),
+ .dbg_capability_reg_enable (0),
+ .dbg_user_identifier (0),
+ .dbg_stat_soft_logic_enable (0),
+ .dbg_ctrl_soft_logic_enable (0),
+ .dbg_prbs_soft_logic_enable (0),
+ .dbg_odi_soft_logic_enable (0),
+ .rcfg_emb_strm_enable (0),
+ .rcfg_profile_cnt (2),
+ .hssi_gen3_rx_pcs_block_sync ("bypass_block_sync"),
+ .hssi_gen3_rx_pcs_block_sync_sm ("disable_blk_sync_sm"),
+ .hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn ("disable"),
+ .hssi_gen3_rx_pcs_lpbk_force ("lpbk_frce_dis"),
+ .hssi_gen3_rx_pcs_mode ("disable_pcs"),
+ .hssi_gen3_rx_pcs_rate_match_fifo ("bypass_rm_fifo"),
+ .hssi_gen3_rx_pcs_rate_match_fifo_latency ("low_latency"),
+ .hssi_gen3_rx_pcs_reverse_lpbk ("rev_lpbk_dis"),
+ .hssi_gen3_rx_pcs_rx_b4gb_par_lpbk ("b4gb_par_lpbk_dis"),
+ .hssi_gen3_rx_pcs_rx_force_balign ("dis_force_balign"),
+ .hssi_gen3_rx_pcs_rx_ins_del_one_skip ("ins_del_one_skip_dis"),
+ .hssi_gen3_rx_pcs_rx_num_fixed_pat (0),
+ .hssi_gen3_rx_pcs_rx_test_out_sel ("rx_test_out0"),
+ .hssi_gen3_rx_pcs_sup_mode ("user_mode"),
+ .hssi_gen3_tx_pcs_mode ("disable_pcs"),
+ .hssi_gen3_tx_pcs_reverse_lpbk ("rev_lpbk_dis"),
+ .hssi_gen3_tx_pcs_sup_mode ("user_mode"),
+ .hssi_gen3_tx_pcs_tx_bitslip (0),
+ .hssi_gen3_tx_pcs_tx_gbox_byp ("bypass_gbox"),
+ .hssi_krfec_rx_pcs_blksync_cor_en ("detect"),
+ .hssi_krfec_rx_pcs_bypass_gb ("bypass_dis"),
+ .hssi_krfec_rx_pcs_clr_ctrl ("both_enabled"),
+ .hssi_krfec_rx_pcs_ctrl_bit_reverse ("ctrl_bit_reverse_en"),
+ .hssi_krfec_rx_pcs_data_bit_reverse ("data_bit_reverse_dis"),
+ .hssi_krfec_rx_pcs_dv_start ("with_blklock"),
+ .hssi_krfec_rx_pcs_err_mark_type ("err_mark_10g"),
+ .hssi_krfec_rx_pcs_error_marking_en ("err_mark_dis"),
+ .hssi_krfec_rx_pcs_low_latency_en ("disable"),
+ .hssi_krfec_rx_pcs_lpbk_mode ("lpbk_dis"),
+ .hssi_krfec_rx_pcs_parity_invalid_enum (8),
+ .hssi_krfec_rx_pcs_parity_valid_num (4),
+ .hssi_krfec_rx_pcs_pipeln_blksync ("enable"),
+ .hssi_krfec_rx_pcs_pipeln_descrm ("disable"),
+ .hssi_krfec_rx_pcs_pipeln_errcorrect ("disable"),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_ind ("enable"),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_lfsr ("disable"),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_loc ("disable"),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_pat ("disable"),
+ .hssi_krfec_rx_pcs_pipeln_gearbox ("enable"),
+ .hssi_krfec_rx_pcs_pipeln_syndrm ("enable"),
+ .hssi_krfec_rx_pcs_pipeln_trans_dec ("disable"),
+ .hssi_krfec_rx_pcs_prot_mode ("disable_mode"),
+ .hssi_krfec_rx_pcs_receive_order ("receive_lsb"),
+ .hssi_krfec_rx_pcs_rx_testbus_sel ("overall"),
+ .hssi_krfec_rx_pcs_signal_ok_en ("sig_ok_en"),
+ .hssi_krfec_rx_pcs_sup_mode ("user_mode"),
+ .hssi_krfec_tx_pcs_burst_err ("burst_err_dis"),
+ .hssi_krfec_tx_pcs_burst_err_len ("burst_err_len1"),
+ .hssi_krfec_tx_pcs_ctrl_bit_reverse ("ctrl_bit_reverse_en"),
+ .hssi_krfec_tx_pcs_data_bit_reverse ("data_bit_reverse_dis"),
+ .hssi_krfec_tx_pcs_enc_frame_query ("enc_query_dis"),
+ .hssi_krfec_tx_pcs_low_latency_en ("disable"),
+ .hssi_krfec_tx_pcs_pipeln_encoder ("enable"),
+ .hssi_krfec_tx_pcs_pipeln_scrambler ("enable"),
+ .hssi_krfec_tx_pcs_prot_mode ("disable_mode"),
+ .hssi_krfec_tx_pcs_sup_mode ("user_mode"),
+ .hssi_krfec_tx_pcs_transcode_err ("trans_err_dis"),
+ .hssi_krfec_tx_pcs_transmit_order ("transmit_lsb"),
+ .hssi_krfec_tx_pcs_tx_testbus_sel ("overall"),
+ .hssi_10g_rx_pcs_align_del ("align_del_dis"),
+ .hssi_10g_rx_pcs_ber_bit_err_total_cnt ("bit_err_total_cnt_10g"),
+ .hssi_10g_rx_pcs_ber_clken ("ber_clk_dis"),
+ .hssi_10g_rx_pcs_ber_xus_timer_window (19530),
+ .hssi_10g_rx_pcs_bitslip_mode ("bitslip_dis"),
+ .hssi_10g_rx_pcs_blksync_bitslip_type ("bitslip_comb"),
+ .hssi_10g_rx_pcs_blksync_bitslip_wait_cnt (1),
+ .hssi_10g_rx_pcs_blksync_bitslip_wait_type ("bitslip_cnt"),
+ .hssi_10g_rx_pcs_blksync_bypass ("blksync_bypass_en"),
+ .hssi_10g_rx_pcs_blksync_clken ("blksync_clk_dis"),
+ .hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt ("enum_invalid_sh_cnt_10g"),
+ .hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock ("knum_sh_cnt_postlock_10g"),
+ .hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock ("knum_sh_cnt_prelock_10g"),
+ .hssi_10g_rx_pcs_blksync_pipeln ("blksync_pipeln_dis"),
+ .hssi_10g_rx_pcs_clr_errblk_cnt_en ("disable"),
+ .hssi_10g_rx_pcs_control_del ("control_del_none"),
+ .hssi_10g_rx_pcs_crcchk_bypass ("crcchk_bypass_en"),
+ .hssi_10g_rx_pcs_crcchk_clken ("crcchk_clk_dis"),
+ .hssi_10g_rx_pcs_crcchk_inv ("crcchk_inv_en"),
+ .hssi_10g_rx_pcs_crcchk_pipeln ("crcchk_pipeln_en"),
+ .hssi_10g_rx_pcs_crcflag_pipeln ("crcflag_pipeln_en"),
+ .hssi_10g_rx_pcs_ctrl_bit_reverse ("ctrl_bit_reverse_dis"),
+ .hssi_10g_rx_pcs_data_bit_reverse ("data_bit_reverse_dis"),
+ .hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass ("dec_64b66b_rxsm_bypass_en"),
+ .hssi_10g_rx_pcs_dec64b66b_clken ("dec64b66b_clk_dis"),
+ .hssi_10g_rx_pcs_descrm_bypass ("descrm_bypass_en"),
+ .hssi_10g_rx_pcs_descrm_clken ("descrm_clk_dis"),
+ .hssi_10g_rx_pcs_descrm_mode ("async"),
+ .hssi_10g_rx_pcs_descrm_pipeln ("enable"),
+ .hssi_10g_rx_pcs_dft_clk_out_sel ("rx_master_clk"),
+ .hssi_10g_rx_pcs_dis_signal_ok ("dis_signal_ok_en"),
+ .hssi_10g_rx_pcs_dispchk_bypass ("dispchk_bypass_en"),
+ .hssi_10g_rx_pcs_empty_flag_type ("empty_rd_side"),
+ .hssi_10g_rx_pcs_fast_path ("fast_path_en"),
+ .hssi_10g_rx_pcs_fec_clken ("fec_clk_dis"),
+ .hssi_10g_rx_pcs_fec_enable ("fec_dis"),
+ .hssi_10g_rx_pcs_fifo_double_read ("fifo_double_read_dis"),
+ .hssi_10g_rx_pcs_fifo_stop_rd ("n_rd_empty"),
+ .hssi_10g_rx_pcs_fifo_stop_wr ("n_wr_full"),
+ .hssi_10g_rx_pcs_force_align ("force_align_dis"),
+ .hssi_10g_rx_pcs_frmsync_bypass ("frmsync_bypass_en"),
+ .hssi_10g_rx_pcs_frmsync_clken ("frmsync_clk_dis"),
+ .hssi_10g_rx_pcs_frmsync_enum_scrm ("enum_scrm_default"),
+ .hssi_10g_rx_pcs_frmsync_enum_sync ("enum_sync_default"),
+ .hssi_10g_rx_pcs_frmsync_flag_type ("location_only"),
+ .hssi_10g_rx_pcs_frmsync_knum_sync ("knum_sync_default"),
+ .hssi_10g_rx_pcs_frmsync_mfrm_length (2048),
+ .hssi_10g_rx_pcs_frmsync_pipeln ("frmsync_pipeln_en"),
+ .hssi_10g_rx_pcs_full_flag_type ("full_wr_side"),
+ .hssi_10g_rx_pcs_gb_rx_idwidth ("width_64"),
+ .hssi_10g_rx_pcs_gb_rx_odwidth ("width_64"),
+ .hssi_10g_rx_pcs_gbexp_clken ("gbexp_clk_dis"),
+ .hssi_10g_rx_pcs_low_latency_en ("disable"),
+ .hssi_10g_rx_pcs_lpbk_mode ("lpbk_dis"),
+ .hssi_10g_rx_pcs_master_clk_sel ("master_rx_pma_clk"),
+ .hssi_10g_rx_pcs_pempty_flag_type ("pempty_rd_side"),
+ .hssi_10g_rx_pcs_pfull_flag_type ("pfull_wr_side"),
+ .hssi_10g_rx_pcs_phcomp_rd_del ("phcomp_rd_del2"),
+ .hssi_10g_rx_pcs_pld_if_type ("fifo"),
+ .hssi_10g_rx_pcs_prot_mode ("disable_mode"),
+ .hssi_10g_rx_pcs_rand_clken ("rand_clk_dis"),
+ .hssi_10g_rx_pcs_rd_clk_sel ("rd_rx_pld_clk"),
+ .hssi_10g_rx_pcs_rdfifo_clken ("rdfifo_clk_dis"),
+ .hssi_10g_rx_pcs_rx_fifo_write_ctrl ("blklock_stops"),
+ .hssi_10g_rx_pcs_rx_scrm_width ("bit64"),
+ .hssi_10g_rx_pcs_rx_sh_location ("msb"),
+ .hssi_10g_rx_pcs_rx_signal_ok_sel ("synchronized_ver"),
+ .hssi_10g_rx_pcs_rx_sm_bypass ("rx_sm_bypass_en"),
+ .hssi_10g_rx_pcs_rx_sm_hiber ("rx_sm_hiber_en"),
+ .hssi_10g_rx_pcs_rx_sm_pipeln ("rx_sm_pipeln_en"),
+ .hssi_10g_rx_pcs_rx_testbus_sel ("rx_fifo_testbus1"),
+ .hssi_10g_rx_pcs_rx_true_b2b ("b2b"),
+ .hssi_10g_rx_pcs_rxfifo_empty ("empty_default"),
+ .hssi_10g_rx_pcs_rxfifo_full ("full_default"),
+ .hssi_10g_rx_pcs_rxfifo_mode ("phase_comp"),
+ .hssi_10g_rx_pcs_rxfifo_pempty (2),
+ .hssi_10g_rx_pcs_rxfifo_pfull (23),
+ .hssi_10g_rx_pcs_stretch_num_stages ("zero_stage"),
+ .hssi_10g_rx_pcs_sup_mode ("user_mode"),
+ .hssi_10g_rx_pcs_test_mode ("test_off"),
+ .hssi_10g_rx_pcs_wrfifo_clken ("wrfifo_clk_dis"),
+ .hssi_10g_rx_pcs_advanced_user_mode ("disable"),
+ .hssi_10g_tx_pcs_bitslip_en ("bitslip_dis"),
+ .hssi_10g_tx_pcs_bonding_dft_en ("dft_dis"),
+ .hssi_10g_tx_pcs_bonding_dft_val ("dft_0"),
+ .hssi_10g_tx_pcs_crcgen_bypass ("crcgen_bypass_en"),
+ .hssi_10g_tx_pcs_crcgen_clken ("crcgen_clk_dis"),
+ .hssi_10g_tx_pcs_crcgen_err ("crcgen_err_dis"),
+ .hssi_10g_tx_pcs_crcgen_inv ("crcgen_inv_en"),
+ .hssi_10g_tx_pcs_ctrl_bit_reverse ("ctrl_bit_reverse_dis"),
+ .hssi_10g_tx_pcs_data_bit_reverse ("data_bit_reverse_dis"),
+ .hssi_10g_tx_pcs_dft_clk_out_sel ("tx_master_clk"),
+ .hssi_10g_tx_pcs_dispgen_bypass ("dispgen_bypass_en"),
+ .hssi_10g_tx_pcs_dispgen_clken ("dispgen_clk_dis"),
+ .hssi_10g_tx_pcs_dispgen_err ("dispgen_err_dis"),
+ .hssi_10g_tx_pcs_dispgen_pipeln ("dispgen_pipeln_dis"),
+ .hssi_10g_tx_pcs_empty_flag_type ("empty_rd_side"),
+ .hssi_10g_tx_pcs_enc_64b66b_txsm_bypass ("enc_64b66b_txsm_bypass_en"),
+ .hssi_10g_tx_pcs_enc64b66b_txsm_clken ("enc64b66b_txsm_clk_dis"),
+ .hssi_10g_tx_pcs_fastpath ("fastpath_en"),
+ .hssi_10g_tx_pcs_fec_clken ("fec_clk_dis"),
+ .hssi_10g_tx_pcs_fec_enable ("fec_dis"),
+ .hssi_10g_tx_pcs_fifo_double_write ("fifo_double_write_dis"),
+ .hssi_10g_tx_pcs_fifo_reg_fast ("fifo_reg_fast_dis"),
+ .hssi_10g_tx_pcs_fifo_stop_rd ("rd_empty"),
+ .hssi_10g_tx_pcs_fifo_stop_wr ("n_wr_full"),
+ .hssi_10g_tx_pcs_frmgen_burst ("frmgen_burst_dis"),
+ .hssi_10g_tx_pcs_frmgen_bypass ("frmgen_bypass_en"),
+ .hssi_10g_tx_pcs_frmgen_clken ("frmgen_clk_dis"),
+ .hssi_10g_tx_pcs_frmgen_mfrm_length (2048),
+ .hssi_10g_tx_pcs_frmgen_pipeln ("frmgen_pipeln_en"),
+ .hssi_10g_tx_pcs_frmgen_pyld_ins ("frmgen_pyld_ins_dis"),
+ .hssi_10g_tx_pcs_frmgen_wordslip ("frmgen_wordslip_dis"),
+ .hssi_10g_tx_pcs_full_flag_type ("full_wr_side"),
+ .hssi_10g_tx_pcs_gb_pipeln_bypass ("disable"),
+ .hssi_10g_tx_pcs_gb_tx_idwidth ("width_64"),
+ .hssi_10g_tx_pcs_gb_tx_odwidth ("width_64"),
+ .hssi_10g_tx_pcs_gbred_clken ("gbred_clk_dis"),
+ .hssi_10g_tx_pcs_low_latency_en ("disable"),
+ .hssi_10g_tx_pcs_master_clk_sel ("master_tx_pma_clk"),
+ .hssi_10g_tx_pcs_pempty_flag_type ("pempty_rd_side"),
+ .hssi_10g_tx_pcs_pfull_flag_type ("pfull_wr_side"),
+ .hssi_10g_tx_pcs_phcomp_rd_del ("phcomp_rd_del2"),
+ .hssi_10g_tx_pcs_pld_if_type ("fifo"),
+ .hssi_10g_tx_pcs_prot_mode ("disable_mode"),
+ .hssi_10g_tx_pcs_pseudo_random ("all_0"),
+ .hssi_10g_tx_pcs_pseudo_seed_a ("288230376151711743"),
+ .hssi_10g_tx_pcs_pseudo_seed_b ("288230376151711743"),
+ .hssi_10g_tx_pcs_random_disp ("disable"),
+ .hssi_10g_tx_pcs_rdfifo_clken ("rdfifo_clk_dis"),
+ .hssi_10g_tx_pcs_scrm_bypass ("scrm_bypass_en"),
+ .hssi_10g_tx_pcs_scrm_clken ("scrm_clk_dis"),
+ .hssi_10g_tx_pcs_scrm_mode ("async"),
+ .hssi_10g_tx_pcs_scrm_pipeln ("enable"),
+ .hssi_10g_tx_pcs_sh_err ("sh_err_dis"),
+ .hssi_10g_tx_pcs_sop_mark ("sop_mark_dis"),
+ .hssi_10g_tx_pcs_stretch_num_stages ("zero_stage"),
+ .hssi_10g_tx_pcs_sup_mode ("user_mode"),
+ .hssi_10g_tx_pcs_test_mode ("test_off"),
+ .hssi_10g_tx_pcs_tx_scrm_err ("scrm_err_dis"),
+ .hssi_10g_tx_pcs_tx_scrm_width ("bit64"),
+ .hssi_10g_tx_pcs_tx_sh_location ("msb"),
+ .hssi_10g_tx_pcs_tx_sm_bypass ("tx_sm_bypass_en"),
+ .hssi_10g_tx_pcs_tx_sm_pipeln ("tx_sm_pipeln_en"),
+ .hssi_10g_tx_pcs_tx_testbus_sel ("tx_fifo_testbus1"),
+ .hssi_10g_tx_pcs_txfifo_empty ("empty_default"),
+ .hssi_10g_tx_pcs_txfifo_full ("full_default"),
+ .hssi_10g_tx_pcs_txfifo_mode ("phase_comp"),
+ .hssi_10g_tx_pcs_txfifo_pempty (2),
+ .hssi_10g_tx_pcs_txfifo_pfull (11),
+ .hssi_10g_tx_pcs_wr_clk_sel ("wr_tx_pld_clk"),
+ .hssi_10g_tx_pcs_wrfifo_clken ("wrfifo_clk_dis"),
+ .hssi_10g_tx_pcs_advanced_user_mode ("disable"),
+ .hssi_8g_rx_pcs_auto_error_replacement ("dis_err_replace"),
+ .hssi_8g_rx_pcs_bit_reversal ("dis_bit_reversal"),
+ .hssi_8g_rx_pcs_bonding_dft_en ("dft_dis"),
+ .hssi_8g_rx_pcs_bonding_dft_val ("dft_0"),
+ .hssi_8g_rx_pcs_bypass_pipeline_reg ("dis_bypass_pipeline"),
+ .hssi_8g_rx_pcs_byte_deserializer ("dis_bds"),
+ .hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask ("dis_rxvalid_mask"),
+ .hssi_8g_rx_pcs_clkcmp_pattern_n (0),
+ .hssi_8g_rx_pcs_clkcmp_pattern_p (0),
+ .hssi_8g_rx_pcs_clock_gate_bds_dec_asn ("dis_bds_dec_asn_clk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_cdr_eidle ("en_cdr_eidle_clk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk ("en_dw_pc_wrclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_dw_rm_rd ("en_dw_rm_rdclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_dw_rm_wr ("en_dw_rm_wrclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_dw_wa ("en_dw_wa_clk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_pc_rdclk ("dis_pc_rdclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk ("dis_sw_pc_wrclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_sw_rm_rd ("en_sw_rm_rdclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_sw_rm_wr ("en_sw_rm_wrclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_sw_wa ("dis_sw_wa_clk_gating"),
+ .hssi_8g_rx_pcs_clock_observation_in_pld_core ("internal_sw_wa_clk"),
+ .hssi_8g_rx_pcs_eidle_entry_eios ("dis_eidle_eios"),
+ .hssi_8g_rx_pcs_eidle_entry_iei ("dis_eidle_iei"),
+ .hssi_8g_rx_pcs_eidle_entry_sd ("dis_eidle_sd"),
+ .hssi_8g_rx_pcs_eightb_tenb_decoder ("en_8b10b_ibm"),
+ .hssi_8g_rx_pcs_err_flags_sel ("err_flags_wa"),
+ .hssi_8g_rx_pcs_fixed_pat_det ("dis_fixed_patdet"),
+ .hssi_8g_rx_pcs_fixed_pat_num (0),
+ .hssi_8g_rx_pcs_force_signal_detect ("en_force_signal_detect"),
+ .hssi_8g_rx_pcs_gen3_clk_en ("disable_clk"),
+ .hssi_8g_rx_pcs_gen3_rx_clk_sel ("rcvd_clk"),
+ .hssi_8g_rx_pcs_gen3_tx_clk_sel ("tx_pma_clk"),
+ .hssi_8g_rx_pcs_hip_mode ("dis_hip"),
+ .hssi_8g_rx_pcs_ibm_invalid_code ("dis_ibm_invalid_code"),
+ .hssi_8g_rx_pcs_invalid_code_flag_only ("dis_invalid_code_only"),
+ .hssi_8g_rx_pcs_pad_or_edb_error_replace ("replace_edb"),
+ .hssi_8g_rx_pcs_pcs_bypass ("dis_pcs_bypass"),
+ .hssi_8g_rx_pcs_phase_comp_rdptr ("disable_rdptr"),
+ .hssi_8g_rx_pcs_phase_compensation_fifo ("register_fifo"),
+ .hssi_8g_rx_pcs_pipe_if_enable ("dis_pipe_rx"),
+ .hssi_8g_rx_pcs_pma_dw ("ten_bit"),
+ .hssi_8g_rx_pcs_polinv_8b10b_dec ("dis_polinv_8b10b_dec"),
+ .hssi_8g_rx_pcs_prot_mode ("gige_1588"),
+ .hssi_8g_rx_pcs_rate_match ("dis_rm"),
+ .hssi_8g_rx_pcs_rate_match_del_thres ("dis_rm_del_thres"),
+ .hssi_8g_rx_pcs_rate_match_empty_thres ("dis_rm_empty_thres"),
+ .hssi_8g_rx_pcs_rate_match_full_thres ("dis_rm_full_thres"),
+ .hssi_8g_rx_pcs_rate_match_ins_thres ("dis_rm_ins_thres"),
+ .hssi_8g_rx_pcs_rate_match_start_thres ("dis_rm_start_thres"),
+ .hssi_8g_rx_pcs_rx_clk_free_running ("en_rx_clk_free_run"),
+ .hssi_8g_rx_pcs_rx_clk2 ("rcvd_clk_clk2"),
+ .hssi_8g_rx_pcs_rx_pcs_urst ("en_rx_pcs_urst"),
+ .hssi_8g_rx_pcs_rx_rcvd_clk ("rcvd_clk_rcvd_clk"),
+ .hssi_8g_rx_pcs_rx_rd_clk ("rx_clk"),
+ .hssi_8g_rx_pcs_rx_refclk ("dis_refclk_sel"),
+ .hssi_8g_rx_pcs_rx_wr_clk ("rx_clk2_div_1_2_4"),
+ .hssi_8g_rx_pcs_sup_mode ("user_mode"),
+ .hssi_8g_rx_pcs_symbol_swap ("dis_symbol_swap"),
+ .hssi_8g_rx_pcs_sync_sm_idle_eios ("dis_syncsm_idle"),
+ .hssi_8g_rx_pcs_test_bus_sel ("tx_testbus"),
+ .hssi_8g_rx_pcs_tx_rx_parallel_loopback ("dis_plpbk"),
+ .hssi_8g_rx_pcs_wa_boundary_lock_ctrl ("sync_sm"),
+ .hssi_8g_rx_pcs_wa_clk_slip_spacing (16),
+ .hssi_8g_rx_pcs_wa_det_latency_sync_status_beh ("dont_care_assert_sync"),
+ .hssi_8g_rx_pcs_wa_disp_err_flag ("en_disp_err_flag"),
+ .hssi_8g_rx_pcs_wa_kchar ("dis_kchar"),
+ .hssi_8g_rx_pcs_wa_pd ("wa_pd_7"),
+ .hssi_8g_rx_pcs_wa_pd_data ("124"),
+ .hssi_8g_rx_pcs_wa_pd_polarity ("dont_care_both_pol"),
+ .hssi_8g_rx_pcs_wa_pld_controlled ("dis_pld_ctrl"),
+ .hssi_8g_rx_pcs_wa_renumber_data (3),
+ .hssi_8g_rx_pcs_wa_rgnumber_data (3),
+ .hssi_8g_rx_pcs_wa_rknumber_data (3),
+ .hssi_8g_rx_pcs_wa_rosnumber_data (1),
+ .hssi_8g_rx_pcs_wa_rvnumber_data (0),
+ .hssi_8g_rx_pcs_wa_sync_sm_ctrl ("gige_sync_sm"),
+ .hssi_8g_rx_pcs_wait_cnt (0),
+ .hssi_8g_tx_pcs_bit_reversal ("dis_bit_reversal"),
+ .hssi_8g_tx_pcs_bonding_dft_en ("dft_dis"),
+ .hssi_8g_tx_pcs_bonding_dft_val ("dft_0"),
+ .hssi_8g_tx_pcs_bypass_pipeline_reg ("dis_bypass_pipeline"),
+ .hssi_8g_tx_pcs_byte_serializer ("dis_bs"),
+ .hssi_8g_tx_pcs_clock_gate_bs_enc ("dis_bs_enc_clk_gating"),
+ .hssi_8g_tx_pcs_clock_gate_dw_fifowr ("en_dw_fifowr_clk_gating"),
+ .hssi_8g_tx_pcs_clock_gate_fiford ("dis_fiford_clk_gating"),
+ .hssi_8g_tx_pcs_clock_gate_sw_fifowr ("en_sw_fifowr_clk_gating"),
+ .hssi_8g_tx_pcs_clock_observation_in_pld_core ("internal_refclk_b"),
+ .hssi_8g_tx_pcs_data_selection_8b10b_encoder_input ("gige_idle_conversion"),
+ .hssi_8g_tx_pcs_dynamic_clk_switch ("dis_dyn_clk_switch"),
+ .hssi_8g_tx_pcs_eightb_tenb_disp_ctrl ("dis_disp_ctrl"),
+ .hssi_8g_tx_pcs_eightb_tenb_encoder ("en_8b10b_ibm"),
+ .hssi_8g_tx_pcs_force_echar ("dis_force_echar"),
+ .hssi_8g_tx_pcs_force_kchar ("dis_force_kchar"),
+ .hssi_8g_tx_pcs_gen3_tx_clk_sel ("dis_tx_clk"),
+ .hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel ("dis_tx_pipe_clk"),
+ .hssi_8g_tx_pcs_hip_mode ("dis_hip"),
+ .hssi_8g_tx_pcs_pcs_bypass ("dis_pcs_bypass"),
+ .hssi_8g_tx_pcs_phase_comp_rdptr ("disable_rdptr"),
+ .hssi_8g_tx_pcs_phase_compensation_fifo ("register_fifo"),
+ .hssi_8g_tx_pcs_phfifo_write_clk_sel ("tx_clk"),
+ .hssi_8g_tx_pcs_pma_dw ("ten_bit"),
+ .hssi_8g_tx_pcs_prot_mode ("gige_1588"),
+ .hssi_8g_tx_pcs_refclk_b_clk_sel ("tx_pma_clock"),
+ .hssi_8g_tx_pcs_revloop_back_rm ("dis_rev_loopback_rx_rm"),
+ .hssi_8g_tx_pcs_sup_mode ("user_mode"),
+ .hssi_8g_tx_pcs_symbol_swap ("dis_symbol_swap"),
+ .hssi_8g_tx_pcs_tx_bitslip ("dis_tx_bitslip"),
+ .hssi_8g_tx_pcs_tx_compliance_controlled_disparity ("dis_txcompliance"),
+ .hssi_8g_tx_pcs_tx_fast_pld_reg ("dis_tx_fast_pld_reg"),
+ .hssi_8g_tx_pcs_txclk_freerun ("en_freerun_tx"),
+ .hssi_8g_tx_pcs_txpcs_urst ("en_txpcs_urst"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_hip_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_hrdrstctl_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx ("gige_1588_tx"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx ("individual_tx"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pma_dw_tx ("pma_10b_tx"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_fifo_mode_tx ("reg_tx"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_shared_fifo_width_tx ("single_tx"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_low_latency_en_tx ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_func_mode ("enable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_lpbk_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_frequency_rules_en ("enable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pma_tx_clk_hz (125000000),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_tx_clk_hz (0),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_uhsif_tx_clk_hz (0),
+ .hssi_tx_pld_pcs_interface_hd_fifo_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_fifo_prot_mode_tx ("non_teng_mode_tx"),
+ .hssi_tx_pld_pcs_interface_hd_fifo_shared_fifo_width_tx ("single_tx"),
+ .hssi_tx_pld_pcs_interface_hd_10g_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_10g_lpbk_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_10g_advanced_user_mode_tx ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_10g_pma_dw_tx ("pma_64b_tx"),
+ .hssi_tx_pld_pcs_interface_hd_10g_fifo_mode_tx ("fifo_tx"),
+ .hssi_tx_pld_pcs_interface_hd_10g_prot_mode_tx ("disabled_prot_mode_tx"),
+ .hssi_tx_pld_pcs_interface_hd_10g_low_latency_en_tx ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_10g_shared_fifo_width_tx ("single_tx"),
+ .hssi_tx_pld_pcs_interface_hd_8g_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_8g_lpbk_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx ("gige_1588_tx"),
+ .hssi_tx_pld_pcs_interface_hd_8g_hip_mode ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_8g_pma_dw_tx ("pma_10b_tx"),
+ .hssi_tx_pld_pcs_interface_hd_8g_fifo_mode_tx ("reg_tx"),
+ .hssi_tx_pld_pcs_interface_hd_g3_prot_mode ("disabled_prot_mode"),
+ .hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx ("disabled_prot_mode_tx"),
+ .hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_lpbk_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_sim_mode ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_prot_mode_tx ("eightg_only_pld_mode_tx"),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_pma_dw_tx ("pma_10b_tx"),
+ .hssi_tx_pld_pcs_interface_hd_pldif_prot_mode_tx ("eightg_and_g3_reg_mode_tx"),
+ .hssi_tx_pld_pcs_interface_hd_pldif_hrdrstctl_en ("disable"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_clk_source ("eightg"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_data_source ("hip_disable"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en ("delay1_clk_disable"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel ("pcs_tx_clk"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl ("delay1_path0"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel ("one_ff_delay"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en ("delay2_clk_disable"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl ("delay2_path0"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_output_sel ("teng_output"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel ("eightg_clk_out"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_hip_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_transparent_pcs_rx ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_hrdrstctl_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_prot_mode_rx ("gige_1588_rx"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx ("individual_rx"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pma_dw_rx ("pma_10b_rx"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pld_fifo_mode_rx ("reg_rx"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_shared_fifo_width_rx ("single_rx"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_low_latency_en_rx ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_func_mode ("enable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_lpbk_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_10g_advanced_user_mode_rx ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_frequency_rules_en ("enable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pma_rx_clk_hz (125000000),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pld_rx_clk_hz (0),
+ .hssi_rx_pld_pcs_interface_hd_chnl_fref_clk_hz (125000000),
+ .hssi_rx_pld_pcs_interface_hd_chnl_clklow_clk_hz (125000000),
+ .hssi_rx_pld_pcs_interface_hd_fifo_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_fifo_prot_mode_rx ("non_teng_mode_rx"),
+ .hssi_rx_pld_pcs_interface_hd_fifo_shared_fifo_width_rx ("single_rx"),
+ .hssi_rx_pld_pcs_interface_hd_10g_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_10g_lpbk_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_10g_pma_dw_rx ("pma_64b_rx"),
+ .hssi_rx_pld_pcs_interface_hd_10g_fifo_mode_rx ("fifo_rx"),
+ .hssi_rx_pld_pcs_interface_hd_10g_prot_mode_rx ("disabled_prot_mode_rx"),
+ .hssi_rx_pld_pcs_interface_hd_10g_low_latency_en_rx ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_10g_shared_fifo_width_rx ("single_rx"),
+ .hssi_rx_pld_pcs_interface_hd_10g_test_bus_mode ("rx"),
+ .hssi_rx_pld_pcs_interface_hd_8g_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_8g_lpbk_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_8g_prot_mode_rx ("gige_1588_rx"),
+ .hssi_rx_pld_pcs_interface_hd_8g_hip_mode ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_8g_pma_dw_rx ("pma_10b_rx"),
+ .hssi_rx_pld_pcs_interface_hd_8g_fifo_mode_rx ("reg_rx"),
+ .hssi_rx_pld_pcs_interface_hd_g3_prot_mode ("disabled_prot_mode"),
+ .hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx ("disabled_prot_mode_rx"),
+ .hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode ("tx"),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_lpbk_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_sim_mode ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_prot_mode_rx ("eightg_only_pld_mode_rx"),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_pma_dw_rx ("pma_10b_rx"),
+ .hssi_rx_pld_pcs_interface_hd_pldif_prot_mode_rx ("eightg_and_g3_reg_mode_rx"),
+ .hssi_rx_pld_pcs_interface_hd_pldif_hrdrstctl_en ("disable"),
+ .hssi_rx_pld_pcs_interface_pcs_rx_block_sel ("eightg"),
+ .hssi_rx_pld_pcs_interface_pcs_rx_clk_sel ("pcs_rx_clk"),
+ .hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en ("hip_rx_disable"),
+ .hssi_rx_pld_pcs_interface_pcs_rx_output_sel ("teng_output"),
+ .hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel ("eightg_clk_out"),
+ .hssi_common_pld_pcs_interface_dft_clk_out_en ("dft_clk_out_disable"),
+ .hssi_common_pld_pcs_interface_dft_clk_out_sel ("teng_rx_dft_clk"),
+ .hssi_common_pld_pcs_interface_hrdrstctrl_en ("hrst_dis"),
+ .hssi_common_pld_pcs_interface_pcs_testbus_block_sel ("pma_if"),
+ .hssi_rx_pcs_pma_interface_block_sel ("eight_g_pcs"),
+ .hssi_rx_pcs_pma_interface_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pcs_pma_interface_clkslip_sel ("pld"),
+ .hssi_rx_pcs_pma_interface_lpbk_en ("disable"),
+ .hssi_rx_pcs_pma_interface_master_clk_sel ("master_rx_pma_clk"),
+ .hssi_rx_pcs_pma_interface_pldif_datawidth_mode ("pldif_data_10bit"),
+ .hssi_rx_pcs_pma_interface_pma_dw_rx ("pma_10b_rx"),
+ .hssi_rx_pcs_pma_interface_pma_if_dft_en ("dft_dis"),
+ .hssi_rx_pcs_pma_interface_pma_if_dft_val ("dft_0"),
+ .hssi_rx_pcs_pma_interface_prbs_clken ("prbs_clk_dis"),
+ .hssi_rx_pcs_pma_interface_prbs_ver ("prbs_off"),
+ .hssi_rx_pcs_pma_interface_prbs9_dwidth ("prbs9_64b"),
+ .hssi_rx_pcs_pma_interface_prot_mode_rx ("eightg_only_pld_mode_rx"),
+ .hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion ("rx_dyn_polinv_dis"),
+ .hssi_rx_pcs_pma_interface_rx_lpbk_en ("lpbk_dis"),
+ .hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok ("force_sig_ok"),
+ .hssi_rx_pcs_pma_interface_rx_prbs_mask ("prbsmask128"),
+ .hssi_rx_pcs_pma_interface_rx_prbs_mode ("teng_mode"),
+ .hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel ("sel_sig_det"),
+ .hssi_rx_pcs_pma_interface_rx_static_polarity_inversion ("rx_stat_polinv_dis"),
+ .hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en ("uhsif_lpbk_dis"),
+ .hssi_rx_pcs_pma_interface_sup_mode ("user_mode"),
+ .hssi_tx_pcs_pma_interface_bypass_pma_txelecidle ("true"),
+ .hssi_tx_pcs_pma_interface_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pcs_pma_interface_lpbk_en ("disable"),
+ .hssi_tx_pcs_pma_interface_master_clk_sel ("master_tx_pma_clk"),
+ .hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx ("other_prot_mode"),
+ .hssi_tx_pcs_pma_interface_pldif_datawidth_mode ("pldif_data_10bit"),
+ .hssi_tx_pcs_pma_interface_pma_dw_tx ("pma_10b_tx"),
+ .hssi_tx_pcs_pma_interface_pma_if_dft_en ("dft_dis"),
+ .hssi_tx_pcs_pma_interface_pmagate_en ("pmagate_dis"),
+ .hssi_tx_pcs_pma_interface_prbs_clken ("prbs_clk_dis"),
+ .hssi_tx_pcs_pma_interface_prbs_gen_pat ("prbs_gen_dis"),
+ .hssi_tx_pcs_pma_interface_prbs9_dwidth ("prbs9_64b"),
+ .hssi_tx_pcs_pma_interface_prot_mode_tx ("eightg_only_pld_mode_tx"),
+ .hssi_tx_pcs_pma_interface_sq_wave_num ("sq_wave_default"),
+ .hssi_tx_pcs_pma_interface_sqwgen_clken ("sqwgen_clk_dis"),
+ .hssi_tx_pcs_pma_interface_sup_mode ("user_mode"),
+ .hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion ("tx_dyn_polinv_dis"),
+ .hssi_tx_pcs_pma_interface_tx_pma_data_sel ("eight_g_pcs"),
+ .hssi_tx_pcs_pma_interface_tx_static_polarity_inversion ("tx_stat_polinv_dis"),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock ("uhsif_filt_stepsz_b4lock_2"),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value (0),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock ("uhsif_filt_cntthr_b4lock_8"),
+ .hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period ("uhsif_dcn_test_period_4"),
+ .hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable ("uhsif_dcn_test_mode_disable"),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh ("uhsif_dzt_cnt_thr_2"),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable ("uhsif_dzt_disable"),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window ("uhsif_dzt_obr_win_16"),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size ("uhsif_dzt_skipsz_4"),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel ("uhsif_index_cram"),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin ("uhsif_dcn_margin_2"),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value (0),
+ .hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control ("uhsif_dft_dz_det_val_0"),
+ .hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control ("uhsif_dft_up_val_0"),
+ .hssi_tx_pcs_pma_interface_uhsif_enable ("uhsif_disable"),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock ("uhsif_lkd_segsz_aflock_512"),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock ("uhsif_lkd_segsz_b4lock_16"),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value (0),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value (0),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value (0),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value (0),
+ .hssi_common_pcs_pma_interface_asn_clk_enable ("false"),
+ .hssi_common_pcs_pma_interface_asn_enable ("dis_asn"),
+ .hssi_common_pcs_pma_interface_block_sel ("eight_g_pcs"),
+ .hssi_common_pcs_pma_interface_bypass_early_eios ("true"),
+ .hssi_common_pcs_pma_interface_bypass_pcie_switch ("true"),
+ .hssi_common_pcs_pma_interface_bypass_pma_ltr ("true"),
+ .hssi_common_pcs_pma_interface_bypass_pma_sw_done ("true"),
+ .hssi_common_pcs_pma_interface_bypass_ppm_lock ("false"),
+ .hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp ("true"),
+ .hssi_common_pcs_pma_interface_bypass_txdetectrx ("true"),
+ .hssi_common_pcs_pma_interface_cdr_control ("dis_cdr_ctrl"),
+ .hssi_common_pcs_pma_interface_cid_enable ("dis_cid_mode"),
+ .hssi_common_pcs_pma_interface_data_mask_count (0),
+ .hssi_common_pcs_pma_interface_data_mask_count_multi (0),
+ .hssi_common_pcs_pma_interface_dft_observation_clock_selection ("dft_clk_obsrv_tx0"),
+ .hssi_common_pcs_pma_interface_early_eios_counter (0),
+ .hssi_common_pcs_pma_interface_force_freqdet ("force_freqdet_dis"),
+ .hssi_common_pcs_pma_interface_free_run_clk_enable ("false"),
+ .hssi_common_pcs_pma_interface_ignore_sigdet_g23 ("false"),
+ .hssi_common_pcs_pma_interface_pc_en_counter (0),
+ .hssi_common_pcs_pma_interface_pc_rst_counter (0),
+ .hssi_common_pcs_pma_interface_pcie_hip_mode ("hip_disable"),
+ .hssi_common_pcs_pma_interface_ph_fifo_reg_mode ("phfifo_reg_mode_dis"),
+ .hssi_common_pcs_pma_interface_phfifo_flush_wait (0),
+ .hssi_common_pcs_pma_interface_pipe_if_g3pcs ("pipe_if_8gpcs"),
+ .hssi_common_pcs_pma_interface_pma_done_counter (0),
+ .hssi_common_pcs_pma_interface_pma_if_dft_en ("dft_dis"),
+ .hssi_common_pcs_pma_interface_pma_if_dft_val ("dft_0"),
+ .hssi_common_pcs_pma_interface_ppm_cnt_rst ("ppm_cnt_rst_dis"),
+ .hssi_common_pcs_pma_interface_ppm_deassert_early ("deassert_early_dis"),
+ .hssi_common_pcs_pma_interface_ppm_gen1_2_cnt ("cnt_32k"),
+ .hssi_common_pcs_pma_interface_ppm_post_eidle_delay ("cnt_200_cycles"),
+ .hssi_common_pcs_pma_interface_ppmsel ("ppmsel_100"),
+ .hssi_common_pcs_pma_interface_prot_mode ("other_protocols"),
+ .hssi_common_pcs_pma_interface_rxvalid_mask ("rxvalid_mask_dis"),
+ .hssi_common_pcs_pma_interface_sigdet_wait_counter (0),
+ .hssi_common_pcs_pma_interface_sigdet_wait_counter_multi (0),
+ .hssi_common_pcs_pma_interface_sim_mode ("disable"),
+ .hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en ("false"),
+ .hssi_common_pcs_pma_interface_sup_mode ("user_mode"),
+ .hssi_common_pcs_pma_interface_testout_sel ("asn_test"),
+ .hssi_common_pcs_pma_interface_wait_clk_on_off_timer (0),
+ .hssi_common_pcs_pma_interface_wait_pipe_synchronizing (0),
+ .hssi_common_pcs_pma_interface_wait_send_syncp_fbkp (0),
+ .hssi_common_pcs_pma_interface_ppm_det_buckets ("ppm_100_bucket"),
+ .hssi_fifo_rx_pcs_double_read_mode ("double_read_dis"),
+ .hssi_fifo_rx_pcs_prot_mode ("non_teng_mode"),
+ .hssi_fifo_tx_pcs_double_write_mode ("double_write_dis"),
+ .hssi_fifo_tx_pcs_prot_mode ("non_teng_mode"),
+ .hssi_pipe_gen3_bypass_rx_detection_enable ("false"),
+ .hssi_pipe_gen3_bypass_rx_preset (0),
+ .hssi_pipe_gen3_bypass_rx_preset_enable ("false"),
+ .hssi_pipe_gen3_bypass_tx_coefficent (0),
+ .hssi_pipe_gen3_bypass_tx_coefficent_enable ("false"),
+ .hssi_pipe_gen3_elecidle_delay_g3 (0),
+ .hssi_pipe_gen3_ind_error_reporting ("dis_ind_error_reporting"),
+ .hssi_pipe_gen3_mode ("disable_pcs"),
+ .hssi_pipe_gen3_phy_status_delay_g12 (0),
+ .hssi_pipe_gen3_phy_status_delay_g3 (0),
+ .hssi_pipe_gen3_phystatus_rst_toggle_g12 ("dis_phystatus_rst_toggle"),
+ .hssi_pipe_gen3_phystatus_rst_toggle_g3 ("dis_phystatus_rst_toggle_g3"),
+ .hssi_pipe_gen3_rate_match_pad_insertion ("dis_rm_fifo_pad_ins"),
+ .hssi_pipe_gen3_sup_mode ("user_mode"),
+ .hssi_pipe_gen3_test_out_sel ("disable_test_out"),
+ .hssi_pipe_gen1_2_elec_idle_delay_val (0),
+ .hssi_pipe_gen1_2_error_replace_pad ("replace_edb"),
+ .hssi_pipe_gen1_2_hip_mode ("dis_hip"),
+ .hssi_pipe_gen1_2_ind_error_reporting ("dis_ind_error_reporting"),
+ .hssi_pipe_gen1_2_phystatus_delay_val (0),
+ .hssi_pipe_gen1_2_phystatus_rst_toggle ("dis_phystatus_rst_toggle"),
+ .hssi_pipe_gen1_2_pipe_byte_de_serializer_en ("dont_care_bds"),
+ .hssi_pipe_gen1_2_prot_mode ("disabled_prot_mode"),
+ .hssi_pipe_gen1_2_rx_pipe_enable ("dis_pipe_rx"),
+ .hssi_pipe_gen1_2_rxdetect_bypass ("dis_rxdetect_bypass"),
+ .hssi_pipe_gen1_2_sup_mode ("user_mode"),
+ .hssi_pipe_gen1_2_tx_pipe_enable ("dis_pipe_tx"),
+ .hssi_pipe_gen1_2_txswing ("dis_txswing"),
+ .pma_adapt_adp_1s_ctle_bypass ("radp_1s_ctle_bypass_1"),
+ .pma_adapt_adp_4s_ctle_bypass ("radp_4s_ctle_bypass_1"),
+ .pma_adapt_adp_ctle_en ("radp_ctle_disable"),
+ .pma_adapt_adp_dfe_fltap_bypass ("radp_dfe_fltap_bypass_1"),
+ .pma_adapt_adp_dfe_fltap_en ("radp_dfe_fltap_disable"),
+ .pma_adapt_adp_dfe_fxtap_bypass ("radp_dfe_fxtap_bypass_1"),
+ .pma_adapt_adp_dfe_fxtap_en ("radp_dfe_fxtap_disable"),
+ .pma_adapt_adp_dfe_fxtap_hold_en ("radp_dfe_fxtap_not_held"),
+ .pma_adapt_adp_dfe_mode ("radp_dfe_mode_4"),
+ .pma_adapt_adp_vga_bypass ("radp_vga_bypass_1"),
+ .pma_adapt_adp_vga_en ("radp_vga_disable"),
+ .pma_adapt_adp_vref_bypass ("radp_vref_bypass_1"),
+ .pma_adapt_adp_vref_en ("radp_vref_disable"),
+ .pma_adapt_datarate ("1250000000 bps"),
+ .pma_adapt_prot_mode ("basic_rx"),
+ .pma_adapt_sup_mode ("user_mode"),
+ .pma_adapt_adp_ctle_adapt_cycle_window ("radp_ctle_adapt_cycle_window_7"),
+ .pma_adapt_odi_dfe_spec_en ("rodi_dfe_spec_en_0"),
+ .pma_adapt_adapt_mode ("manual"),
+ .pma_adapt_adp_onetime_dfe ("radp_onetime_dfe_0"),
+ .pma_adapt_adp_mode ("radp_mode_8"),
+ .pma_cdr_refclk_powerdown_mode ("powerup"),
+ .pma_cdr_refclk_refclk_select ("ref_iqclk0"),
+ .pma_cgb_bitslip_enable ("disable_bitslip"),
+ .pma_cgb_bonding_reset_enable ("disallow_bonding_reset"),
+ .pma_cgb_datarate ("1250000000 bps"),
+ .pma_cgb_pcie_gen3_bitwidth ("pciegen3_wide"),
+ .pma_cgb_prot_mode ("basic_tx"),
+ .pma_cgb_ser_mode ("ten_bit"),
+ .pma_cgb_sup_mode ("user_mode"),
+ .pma_cgb_x1_div_m_sel ("divby2"),
+ .pma_cgb_input_select_x1 ("fpll_bot"),
+ .pma_cgb_input_select_gen3 ("unused"),
+ .pma_cgb_input_select_xn ("unused"),
+ .pma_cgb_tx_ucontrol_en ("disable"),
+ .pma_rx_dfe_datarate ("1250000000 bps"),
+ .pma_rx_dfe_dft_en ("dft_disable"),
+ .pma_rx_dfe_pdb ("dfe_enable"),
+ .pma_rx_dfe_pdb_fixedtap ("fixtap_dfe_powerdown"),
+ .pma_rx_dfe_pdb_floattap ("floattap_dfe_powerdown"),
+ .pma_rx_dfe_pdb_fxtap4t7 ("fxtap4t7_powerdown"),
+ .pma_rx_dfe_sup_mode ("user_mode"),
+ .pma_rx_dfe_prot_mode ("basic_rx"),
+ .pma_rx_odi_datarate ("1250000000 bps"),
+ .pma_rx_odi_sup_mode ("user_mode"),
+ .pma_rx_odi_step_ctrl_sel ("dprio_mode"),
+ .pma_rx_odi_prot_mode ("basic_rx"),
+ .pma_rx_buf_bypass_eqz_stages_234 ("bypass_off"),
+ .pma_rx_buf_datarate ("1250000000 bps"),
+ .pma_rx_buf_diag_lp_en ("dlp_off"),
+ .pma_rx_buf_prot_mode ("basic_rx"),
+ .pma_rx_buf_qpi_enable ("non_qpi_mode"),
+ .pma_rx_buf_rx_refclk_divider ("bypass_divider"),
+ .pma_rx_buf_sup_mode ("user_mode"),
+ .pma_rx_buf_loopback_modes ("lpbk_disable"),
+ .pma_rx_buf_refclk_en ("disable"),
+ .pma_rx_buf_pm_tx_rx_pcie_gen ("non_pcie"),
+ .pma_rx_buf_pm_tx_rx_pcie_gen_bitwidth ("pcie_gen3_32b"),
+ .pma_rx_buf_pm_tx_rx_cvp_mode ("cvp_off"),
+ .pma_rx_buf_xrx_path_uc_cal_enable ("rx_cal_off"),
+ .pma_rx_buf_xrx_path_sup_mode ("user_mode"),
+ .pma_rx_buf_xrx_path_prot_mode ("basic_rx"),
+ .pma_rx_buf_xrx_path_datarate ("1250000000 bps"),
+ .pma_rx_buf_xrx_path_datawidth (10),
+ .pma_rx_buf_xrx_path_pma_rx_divclk_hz ("125000000"),
+ .pma_rx_sd_prot_mode ("basic_rx"),
+ .pma_rx_sd_sd_output_off (1),
+ .pma_rx_sd_sd_output_on (15),
+ .pma_rx_sd_sd_pdb ("sd_off"),
+ .pma_rx_sd_sup_mode ("user_mode"),
+ .pma_tx_ser_ser_clk_divtx_user_sel ("divtx_user_off"),
+ .pma_tx_ser_sup_mode ("user_mode"),
+ .pma_tx_ser_prot_mode ("basic_tx"),
+ .pma_tx_buf_datarate ("1250000000 bps"),
+ .pma_tx_buf_prot_mode ("basic_tx"),
+ .pma_tx_buf_rx_det ("mode_0"),
+ .pma_tx_buf_rx_det_output_sel ("rx_det_pcie_out"),
+ .pma_tx_buf_rx_det_pdb ("rx_det_off"),
+ .pma_tx_buf_sup_mode ("user_mode"),
+ .pma_tx_buf_user_fir_coeff_ctrl_sel ("ram_ctl"),
+ .pma_tx_buf_xtx_path_prot_mode ("basic_tx"),
+ .pma_tx_buf_xtx_path_datarate ("1250000000 bps"),
+ .pma_tx_buf_xtx_path_datawidth (10),
+ .pma_tx_buf_xtx_path_clock_divider_ratio (2),
+ .pma_tx_buf_xtx_path_pma_tx_divclk_hz ("125000000"),
+ .pma_tx_buf_xtx_path_tx_pll_clk_hz ("312500000"),
+ .pma_tx_buf_xtx_path_sup_mode ("user_mode"),
+ .cdr_pll_pma_width (10),
+ .cdr_pll_cgb_div (1),
+ .cdr_pll_is_cascaded_pll ("false"),
+ .cdr_pll_datarate ("1250000000 bps"),
+ .cdr_pll_lpd_counter (8),
+ .cdr_pll_lpfd_counter (1),
+ .cdr_pll_n_counter_scratch (1),
+ .cdr_pll_output_clock_frequency ("625000000 Hz"),
+ .cdr_pll_reference_clock_frequency ("125000000 hz"),
+ .cdr_pll_set_cdr_vco_speed (3),
+ .cdr_pll_set_cdr_vco_speed_fix (60),
+ .cdr_pll_vco_freq ("5000000000 Hz"),
+ .cdr_pll_atb_select_control ("atb_off"),
+ .cdr_pll_auto_reset_on ("auto_reset_off"),
+ .cdr_pll_bbpd_data_pattern_filter_select ("bbpd_data_pat_off"),
+ .cdr_pll_bw_sel ("medium"),
+ .cdr_pll_cdr_odi_select ("sel_cdr"),
+ .cdr_pll_cdr_phaselock_mode ("no_ignore_lock"),
+ .cdr_pll_cdr_powerdown_mode ("power_up"),
+ .cdr_pll_chgpmp_current_pd ("cp_current_pd_setting0"),
+ .cdr_pll_chgpmp_current_pfd ("cp_current_pfd_setting3"),
+ .cdr_pll_chgpmp_replicate ("false"),
+ .cdr_pll_chgpmp_testmode ("cp_test_disable"),
+ .cdr_pll_clklow_mux_select ("clklow_mux_cdr_fbclk"),
+ .cdr_pll_diag_loopback_enable ("false"),
+ .cdr_pll_disable_up_dn ("true"),
+ .cdr_pll_fref_clklow_div (1),
+ .cdr_pll_fref_mux_select ("fref_mux_cdr_refclk"),
+ .cdr_pll_gpon_lck2ref_control ("gpon_lck2ref_off"),
+ .cdr_pll_initial_settings ("true"),
+ .cdr_pll_lck2ref_delay_control ("lck2ref_delay_2"),
+ .cdr_pll_lf_resistor_pd ("lf_pd_setting0"),
+ .cdr_pll_lf_resistor_pfd ("lf_pfd_setting2"),
+ .cdr_pll_lf_ripple_cap ("lf_no_ripple"),
+ .cdr_pll_loop_filter_bias_select ("lpflt_bias_7"),
+ .cdr_pll_loopback_mode ("loopback_disabled"),
+ .cdr_pll_ltd_ltr_micro_controller_select ("ltd_ltr_pcs"),
+ .cdr_pll_m_counter (40),
+ .cdr_pll_n_counter (1),
+ .cdr_pll_pd_fastlock_mode ("false"),
+ .cdr_pll_pd_l_counter (8),
+ .cdr_pll_pfd_l_counter (1),
+ .cdr_pll_primary_use ("cdr"),
+ .cdr_pll_prot_mode ("basic_rx"),
+ .cdr_pll_reverse_serial_loopback ("no_loopback"),
+ .cdr_pll_set_cdr_v2i_enable ("true"),
+ .cdr_pll_set_cdr_vco_reset ("false"),
+ .cdr_pll_set_cdr_vco_speed_pciegen3 ("cdr_vco_max_speedbin_pciegen3"),
+ .cdr_pll_sup_mode ("user_mode"),
+ .cdr_pll_tx_pll_prot_mode ("txpll_unused"),
+ .cdr_pll_txpll_hclk_driver_enable ("false"),
+ .cdr_pll_vco_overrange_voltage ("vco_overrange_off"),
+ .cdr_pll_vco_underrange_voltage ("vco_underange_off"),
+ .cdr_pll_fb_select ("direct_fb"),
+ .cdr_pll_uc_ro_cal ("uc_ro_cal_on"),
+ .cdr_pll_iqclk_mux_sel ("power_down"),
+ .cdr_pll_pcie_gen ("non_pcie"),
+ .cdr_pll_set_cdr_input_freq_range (0),
+ .cdr_pll_chgpmp_current_dn_trim ("cp_current_trimming_dn_setting0"),
+ .cdr_pll_chgpmp_up_pd_trim_double ("normal_up_trim_current"),
+ .cdr_pll_chgpmp_current_up_pd ("cp_current_pd_up_setting4"),
+ .cdr_pll_chgpmp_current_up_trim ("cp_current_trimming_up_setting0"),
+ .cdr_pll_chgpmp_dn_pd_trim_double ("normal_dn_trim_current"),
+ .cdr_pll_cal_vco_count_length ("sel_8b_count"),
+ .cdr_pll_chgpmp_current_dn_pd ("cp_current_pd_dn_setting4"),
+ .pma_rx_deser_clkdiv_source ("vco_bypass_normal"),
+ .pma_rx_deser_clkdivrx_user_mode ("clkdivrx_user_clkdiv"),
+ .pma_rx_deser_datarate ("1250000000 bps"),
+ .pma_rx_deser_deser_factor (10),
+ .pma_rx_deser_force_clkdiv_for_testing ("normal_clkdiv"),
+ .pma_rx_deser_sdclk_enable ("false"),
+ .pma_rx_deser_sup_mode ("user_mode"),
+ .pma_rx_deser_rst_n_adapt_odi ("no_rst_adapt_odi"),
+ .pma_rx_deser_bitslip_bypass ("bs_bypass_yes"),
+ .pma_rx_deser_prot_mode ("basic_rx"),
+ .pma_rx_deser_pcie_gen ("non_pcie"),
+ .pma_rx_deser_pcie_gen_bitwidth ("pcie_gen3_32b")
+ ) i_nf_native_phyip_0 (
+ .tx_analogreset (tx_analogreset), // tx_analogreset.tx_analogreset
+ .tx_digitalreset (tx_digitalreset), // tx_digitalreset.tx_digitalreset
+ .rx_analogreset (rx_analogreset), // rx_analogreset.rx_analogreset
+ .rx_digitalreset (rx_digitalreset), // rx_digitalreset.rx_digitalreset
+ .tx_cal_busy (tx_cal_busy), // tx_cal_busy.tx_cal_busy
+ .rx_cal_busy (rx_cal_busy), // rx_cal_busy.rx_cal_busy
+ .tx_serial_clk0 (tx_serial_clk), // tx_serial_clk0.clk
+ .rx_cdr_refclk0 (rx_cdr_refclk), // rx_cdr_refclk0.clk
+ .tx_serial_data (i_nf_native_phyip_0_tx_serial_data_tx_serial_data), // tx_serial_data.tx_serial_data
+ .rx_serial_data (i_nf_native_phyip_terminator_0_rx_serial_data_rx_serial_data), // rx_serial_data.rx_serial_data
+ .rx_seriallpbken (i_nf_native_phyip_terminator_0_rx_seriallpbken_rx_seriallpbken), // rx_seriallpbken.rx_seriallpbken
+ .rx_set_locktodata (rx_set_locktodata), // rx_set_locktodata.rx_set_locktodata
+ .rx_set_locktoref (rx_set_locktoref), // rx_set_locktoref.rx_set_locktoref
+ .rx_is_lockedtoref (rx_is_lockedtoref), // rx_is_lockedtoref.rx_is_lockedtoref
+ .rx_is_lockedtodata (rx_is_lockedtodata), // rx_is_lockedtodata.rx_is_lockedtodata
+ .tx_coreclkin (i_nf_native_phyip_terminator_0_tx_coreclk_clk), // tx_coreclkin.clk
+ .rx_coreclkin (i_nf_native_phyip_terminator_0_rx_coreclk_clk), // rx_coreclkin.clk
+ .tx_clkout (i_nf_native_phyip_0_tx_clkout_clk), // tx_clkout.clk
+ .rx_clkout (i_nf_native_phyip_0_rx_clkout_clk), // rx_clkout.clk
+ .rx_pma_div_clkout (i_nf_native_phyip_0_rx_pma_div_clkout_clk), // rx_pma_div_clkout.clk
+ .tx_parallel_data ({i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[118],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[117],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[116],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[115],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[114],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[113],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[112],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[111],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[110],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[109],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[108],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[107],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[106],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[105],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[104],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[103],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[102],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[101],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[100],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[99],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[98],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[97],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[96],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[95],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[94],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[93],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[92],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[91],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[90],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[89],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[88],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[87],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[86],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[85],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[84],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[83],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[82],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[81],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[80],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[79],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[78],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[77],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[76],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[75],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[74],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[73],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[72],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[71],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[70],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[69],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[68],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[67],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[66],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[65],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[64],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[63],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[62],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[61],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[60],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[59],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[58],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[57],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[56],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[55],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[54],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[53],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[52],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[51],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[50],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[49],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[48],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[47],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[46],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[45],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[44],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[43],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[42],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[41],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[40],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[39],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[38],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[37],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[36],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[35],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[34],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[33],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[32],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[31],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[30],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[29],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[28],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[27],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[26],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[25],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[24],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[23],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[22],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[21],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[20],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[19],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[18],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[17],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[16],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[15],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[14],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[13],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[12],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[11],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[10],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[9],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[8],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[7],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[6],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[5],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[4],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[3],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[2],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[1],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[0],i_tse_pcs_0_tx_kchar_tx_datak,i_tse_pcs_0_tx_frame_tx_parallel_data[7],i_tse_pcs_0_tx_frame_tx_parallel_data[6],i_tse_pcs_0_tx_frame_tx_parallel_data[5],i_tse_pcs_0_tx_frame_tx_parallel_data[4],i_tse_pcs_0_tx_frame_tx_parallel_data[3],i_tse_pcs_0_tx_frame_tx_parallel_data[2],i_tse_pcs_0_tx_frame_tx_parallel_data[1],i_tse_pcs_0_tx_frame_tx_parallel_data[0]}), // tx_parallel_data.tx_parallel_data
+ .rx_parallel_data ({i_nf_native_phyip_0_rx_parallel_data[127],i_nf_native_phyip_0_rx_parallel_data[126],i_nf_native_phyip_0_rx_parallel_data[125],i_nf_native_phyip_0_rx_parallel_data[124],i_nf_native_phyip_0_rx_parallel_data[123],i_nf_native_phyip_0_rx_parallel_data[122],i_nf_native_phyip_0_rx_parallel_data[121],i_nf_native_phyip_0_rx_parallel_data[120],i_nf_native_phyip_0_rx_parallel_data[119],i_nf_native_phyip_0_rx_parallel_data[118],i_nf_native_phyip_0_rx_parallel_data[117],i_nf_native_phyip_0_rx_parallel_data[116],i_nf_native_phyip_0_rx_parallel_data[115],i_nf_native_phyip_0_rx_parallel_data[114],i_nf_native_phyip_0_rx_parallel_data[113],i_nf_native_phyip_0_rx_parallel_data[112],i_nf_native_phyip_0_rx_parallel_data[111],i_nf_native_phyip_0_rx_parallel_data[110],i_nf_native_phyip_0_rx_parallel_data[109],i_nf_native_phyip_0_rx_parallel_data[108],i_nf_native_phyip_0_rx_parallel_data[107],i_nf_native_phyip_0_rx_parallel_data[106],i_nf_native_phyip_0_rx_parallel_data[105],i_nf_native_phyip_0_rx_parallel_data[104],i_nf_native_phyip_0_rx_parallel_data[103],i_nf_native_phyip_0_rx_parallel_data[102],i_nf_native_phyip_0_rx_parallel_data[101],i_nf_native_phyip_0_rx_parallel_data[100],i_nf_native_phyip_0_rx_parallel_data[99],i_nf_native_phyip_0_rx_parallel_data[98],i_nf_native_phyip_0_rx_parallel_data[97],i_nf_native_phyip_0_rx_parallel_data[96],i_nf_native_phyip_0_rx_parallel_data[95],i_nf_native_phyip_0_rx_parallel_data[94],i_nf_native_phyip_0_rx_parallel_data[93],i_nf_native_phyip_0_rx_parallel_data[92],i_nf_native_phyip_0_rx_parallel_data[91],i_nf_native_phyip_0_rx_parallel_data[90],i_nf_native_phyip_0_rx_parallel_data[89],i_nf_native_phyip_0_rx_parallel_data[88],i_nf_native_phyip_0_rx_parallel_data[87],i_nf_native_phyip_0_rx_parallel_data[86],i_nf_native_phyip_0_rx_parallel_data[85],i_nf_native_phyip_0_rx_parallel_data[84],i_nf_native_phyip_0_rx_parallel_data[83],i_nf_native_phyip_0_rx_parallel_data[82],i_nf_native_phyip_0_rx_parallel_data[81],i_nf_native_phyip_0_rx_parallel_data[80],i_nf_native_phyip_0_rx_parallel_data[79],i_nf_native_phyip_0_rx_parallel_data[78],i_nf_native_phyip_0_rx_parallel_data[77],i_nf_native_phyip_0_rx_parallel_data[76],i_nf_native_phyip_0_rx_parallel_data[75],i_nf_native_phyip_0_rx_parallel_data[74],i_nf_native_phyip_0_rx_parallel_data[73],i_nf_native_phyip_0_rx_parallel_data[72],i_nf_native_phyip_0_rx_parallel_data[71],i_nf_native_phyip_0_rx_parallel_data[70],i_nf_native_phyip_0_rx_parallel_data[69],i_nf_native_phyip_0_rx_parallel_data[68],i_nf_native_phyip_0_rx_parallel_data[67],i_nf_native_phyip_0_rx_parallel_data[66],i_nf_native_phyip_0_rx_parallel_data[65],i_nf_native_phyip_0_rx_parallel_data[64],i_nf_native_phyip_0_rx_parallel_data[63],i_nf_native_phyip_0_rx_parallel_data[62],i_nf_native_phyip_0_rx_parallel_data[61],i_nf_native_phyip_0_rx_parallel_data[60],i_nf_native_phyip_0_rx_parallel_data[59],i_nf_native_phyip_0_rx_parallel_data[58],i_nf_native_phyip_0_rx_parallel_data[57],i_nf_native_phyip_0_rx_parallel_data[56],i_nf_native_phyip_0_rx_parallel_data[55],i_nf_native_phyip_0_rx_parallel_data[54],i_nf_native_phyip_0_rx_parallel_data[53],i_nf_native_phyip_0_rx_parallel_data[52],i_nf_native_phyip_0_rx_parallel_data[51],i_nf_native_phyip_0_rx_parallel_data[50],i_nf_native_phyip_0_rx_parallel_data[49],i_nf_native_phyip_0_rx_parallel_data[48],i_nf_native_phyip_0_rx_parallel_data[47],i_nf_native_phyip_0_rx_parallel_data[46],i_nf_native_phyip_0_rx_parallel_data[45],i_nf_native_phyip_0_rx_parallel_data[44],i_nf_native_phyip_0_rx_parallel_data[43],i_nf_native_phyip_0_rx_parallel_data[42],i_nf_native_phyip_0_rx_parallel_data[41],i_nf_native_phyip_0_rx_parallel_data[40],i_nf_native_phyip_0_rx_parallel_data[39],i_nf_native_phyip_0_rx_parallel_data[38],i_nf_native_phyip_0_rx_parallel_data[37],i_nf_native_phyip_0_rx_parallel_data[36],i_nf_native_phyip_0_rx_parallel_data[35],i_nf_native_phyip_0_rx_parallel_data[34],i_nf_native_phyip_0_rx_parallel_data[33],i_nf_native_phyip_0_rx_parallel_data[32],i_nf_native_phyip_0_rx_parallel_data[31],i_nf_native_phyip_0_rx_parallel_data[30],i_nf_native_phyip_0_rx_parallel_data[29],i_nf_native_phyip_0_rx_parallel_data[28],i_nf_native_phyip_0_rx_parallel_data[27],i_nf_native_phyip_0_rx_parallel_data[26],i_nf_native_phyip_0_rx_parallel_data[25],i_nf_native_phyip_0_rx_parallel_data[24],i_nf_native_phyip_0_rx_parallel_data[23],i_nf_native_phyip_0_rx_parallel_data[22],i_nf_native_phyip_0_rx_parallel_data[21],i_nf_native_phyip_0_rx_parallel_data[20],i_nf_native_phyip_0_rx_parallel_data[19],i_nf_native_phyip_0_rx_parallel_data[18],i_nf_native_phyip_0_rx_parallel_data[17],i_nf_native_phyip_0_rx_parallel_data[16],i_nf_native_phyip_0_rx_parallel_data[15],i_nf_native_phyip_0_rx_parallel_data[14],i_nf_native_phyip_0_rx_parallel_data[13],i_nf_native_phyip_0_rx_parallel_data[12],i_nf_native_phyip_0_rx_parallel_data[11],i_nf_native_phyip_0_rx_parallel_data[10],i_nf_native_phyip_0_rx_parallel_data[9],i_nf_native_phyip_0_rx_parallel_data[8],i_nf_native_phyip_0_rx_parallel_data[7],i_nf_native_phyip_0_rx_parallel_data[6],i_nf_native_phyip_0_rx_parallel_data[5],i_nf_native_phyip_0_rx_parallel_data[4],i_nf_native_phyip_0_rx_parallel_data[3],i_nf_native_phyip_0_rx_parallel_data[2],i_nf_native_phyip_0_rx_parallel_data[1],i_nf_native_phyip_0_rx_parallel_data[0]}), // rx_parallel_data.rx_parallel_data
+ .rx_std_bitslipboundarysel (i_nf_native_phyip_0_rx_std_bitslipboundarysel_rx_std_bitslipboundarysel), // rx_std_bitslipboundarysel.rx_std_bitslipboundarysel
+ .tx_analogreset_ack (), // (terminated)
+ .rx_analogreset_ack (), // (terminated)
+ .tx_serial_clk1 (1'b0), // (terminated)
+ .tx_serial_clk2 (1'b0), // (terminated)
+ .tx_serial_clk3 (1'b0), // (terminated)
+ .tx_bonding_clocks (6'b000000), // (terminated)
+ .tx_bonding_clocks1 (6'b000000), // (terminated)
+ .tx_bonding_clocks2 (6'b000000), // (terminated)
+ .tx_bonding_clocks3 (6'b000000), // (terminated)
+ .rx_cdr_refclk1 (1'b0), // (terminated)
+ .rx_cdr_refclk2 (1'b0), // (terminated)
+ .rx_cdr_refclk3 (1'b0), // (terminated)
+ .rx_cdr_refclk4 (1'b0), // (terminated)
+ .rx_pma_clkslip (1'b0), // (terminated)
+ .rx_pma_qpipulldn (1'b0), // (terminated)
+ .tx_pma_qpipulldn (1'b0), // (terminated)
+ .tx_pma_qpipullup (1'b0), // (terminated)
+ .tx_pma_txdetectrx (1'b0), // (terminated)
+ .tx_pma_elecidle (1'b0), // (terminated)
+ .tx_pma_rxfound (), // (terminated)
+ .rx_clklow (), // (terminated)
+ .rx_fref (), // (terminated)
+ .tx_pma_clkout (), // (terminated)
+ .tx_pma_div_clkout (), // (terminated)
+ .tx_pma_iqtxrx_clkout (), // (terminated)
+ .rx_pma_clkout (), // (terminated)
+ .rx_pma_iqtxrx_clkout (), // (terminated)
+ .tx_control (18'b000000000000000000), // (terminated)
+ .rx_control (), // (terminated)
+ .rx_bitslip (1'b0), // (terminated)
+ .rx_adapt_reset (1'b0), // (terminated)
+ .rx_adapt_start (1'b0), // (terminated)
+ .rx_prbs_err_clr (1'b0), // (terminated)
+ .rx_prbs_done (), // (terminated)
+ .rx_prbs_err (), // (terminated)
+ .tx_uhsif_clk (1'b0), // (terminated)
+ .tx_uhsif_clkout (), // (terminated)
+ .tx_uhsif_lock (), // (terminated)
+ .tx_std_pcfifo_full (), // (terminated)
+ .tx_std_pcfifo_empty (), // (terminated)
+ .rx_std_pcfifo_full (), // (terminated)
+ .rx_std_pcfifo_empty (), // (terminated)
+ .rx_std_bitrev_ena (1'b0), // (terminated)
+ .rx_std_byterev_ena (1'b0), // (terminated)
+ .tx_polinv (1'b0), // (terminated)
+ .rx_polinv (1'b0), // (terminated)
+ .tx_std_bitslipboundarysel (5'b00000), // (terminated)
+ .rx_std_wa_patternalign (1'b0), // (terminated)
+ .rx_std_wa_a1a2size (1'b0), // (terminated)
+ .rx_std_rmfifo_full (), // (terminated)
+ .rx_std_rmfifo_empty (), // (terminated)
+ .rx_std_signaldetect (), // (terminated)
+ .tx_enh_data_valid (1'b0), // (terminated)
+ .tx_enh_fifo_full (), // (terminated)
+ .tx_enh_fifo_pfull (), // (terminated)
+ .tx_enh_fifo_empty (), // (terminated)
+ .tx_enh_fifo_pempty (), // (terminated)
+ .tx_enh_fifo_cnt (), // (terminated)
+ .rx_enh_fifo_rd_en (1'b0), // (terminated)
+ .rx_enh_data_valid (), // (terminated)
+ .rx_enh_fifo_full (), // (terminated)
+ .rx_enh_fifo_pfull (), // (terminated)
+ .rx_enh_fifo_empty (), // (terminated)
+ .rx_enh_fifo_pempty (), // (terminated)
+ .rx_enh_fifo_del (), // (terminated)
+ .rx_enh_fifo_insert (), // (terminated)
+ .rx_enh_fifo_cnt (), // (terminated)
+ .rx_enh_fifo_align_val (), // (terminated)
+ .rx_enh_fifo_align_clr (1'b0), // (terminated)
+ .tx_enh_frame (), // (terminated)
+ .tx_enh_frame_burst_en (1'b0), // (terminated)
+ .tx_enh_frame_diag_status (2'b00), // (terminated)
+ .rx_enh_frame (), // (terminated)
+ .rx_enh_frame_lock (), // (terminated)
+ .rx_enh_frame_diag_status (), // (terminated)
+ .rx_enh_crc32_err (), // (terminated)
+ .rx_enh_highber (), // (terminated)
+ .rx_enh_highber_clr_cnt (1'b0), // (terminated)
+ .rx_enh_clr_errblk_count (1'b0), // (terminated)
+ .rx_enh_blk_lock (), // (terminated)
+ .tx_enh_bitslip (7'b0000000), // (terminated)
+ .tx_hip_data (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
+ .rx_hip_data (), // (terminated)
+ .hip_pipe_pclk (), // (terminated)
+ .hip_fixedclk (), // (terminated)
+ .hip_frefclk (), // (terminated)
+ .hip_ctrl (), // (terminated)
+ .hip_cal_done (), // (terminated)
+ .ltssm_detect_quiet (1'b0), // (terminated)
+ .ltssm_detect_active (1'b0), // (terminated)
+ .ltssm_rcvr_phase_two (1'b0), // (terminated)
+ .hip_reduce_counters (1'b0), // (terminated)
+ .pcie_rate (2'b00), // (terminated)
+ .pipe_rate (2'b00), // (terminated)
+ .pipe_sw_done (2'b00), // (terminated)
+ .pipe_sw (), // (terminated)
+ .pipe_hclk_in (1'b0), // (terminated)
+ .pipe_hclk_out (), // (terminated)
+ .pipe_g3_txdeemph (18'b000000000000000000), // (terminated)
+ .pipe_g3_rxpresethint (3'b000), // (terminated)
+ .pipe_rx_eidleinfersel (3'b000), // (terminated)
+ .pipe_rx_elecidle (), // (terminated)
+ .pipe_rx_polarity (1'b0), // (terminated)
+ .reconfig_clk (1'b0), // (terminated)
+ .reconfig_reset (1'b0), // (terminated)
+ .reconfig_write (1'b0), // (terminated)
+ .reconfig_read (1'b0), // (terminated)
+ .reconfig_address (10'b0000000000), // (terminated)
+ .reconfig_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .reconfig_readdata (), // (terminated)
+ .reconfig_waitrequest (), // (terminated)
+ .avmm_busy () // (terminated)
+ );
+
+ altera_eth_tse_nf_phyip_terminator #(
+ .ENABLE_TIMESTAMPING (0),
+ .UNUSED_RX_PARALLEL_DATA_WIDTH (114)
+ ) i_nf_native_phyip_terminator_0 (
+ .tx_clk (i_nf_native_phyip_0_tx_clkout_clk), // tx_clk.clk
+ .rx_clk (i_nf_native_phyip_0_rx_clkout_clk), // rx_clk.clk
+ .tx_coreclk (i_nf_native_phyip_terminator_0_tx_coreclk_clk), // tx_coreclk.clk
+ .rx_coreclk (i_nf_native_phyip_terminator_0_rx_coreclk_clk), // rx_coreclk.clk
+ .rx_recovered_clk (i_nf_native_phyip_0_rx_pma_div_clkout_clk), // rx_recovered_clk.clk
+ .rxp (rxp), // serial_connection.export
+ .txp (txp), // .export
+ .rx_recovclkout (rx_recovclkout), // serdes_control_connection.export
+ .rx_pcs_clk (i_nf_native_phyip_terminator_0_rx_pcs_clk_rx_pcs_clk), // rx_pcs_clk.rx_pcs_clk
+ .unused_tx_parallel_data (i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data), // unused_tx_parallel_data.unused_tx_parallel_data
+ .tx_serial_data (i_nf_native_phyip_0_tx_serial_data_tx_serial_data), // tx_serial_data.tx_serial_data
+ .rx_runlengthviolation (i_nf_native_phyip_terminator_0_rx_runlengthviolation_rx_runlengthviolation), // rx_runlengthviolation.rx_runlengthviolation
+ .rx_seriallpbken (i_nf_native_phyip_terminator_0_rx_seriallpbken_rx_seriallpbken), // rx_seriallpbken.rx_seriallpbken
+ .sd_loopback (i_tse_pcs_0_sd_loopback_sd_loopback), // sd_loopback.sd_loopback
+ .tx_pcs_clk (i_nf_native_phyip_terminator_0_tx_pcs_clk_tx_pcs_clk), // tx_pcs_clk.tx_pcs_clk
+ .rx_serial_data (i_nf_native_phyip_terminator_0_rx_serial_data_rx_serial_data), // rx_serial_data.rx_serial_data
+ .unused_rx_parallel_data (i_nf_native_phyip_0_unused_rx_parallel_data_unused_rx_parallel_data), // unused_rx_parallel_data.unused_rx_parallel_data
+ .rx_rmfifostatus (2'b00), // (terminated)
+ .rx_rmfifodatainserted (), // (terminated)
+ .rx_rmfifodatadeleted (), // (terminated)
+ .terminate_rx_recovered_clk (1'b0) // (terminated)
+ );
+
+ altera_reset_controller #(
+ .NUM_RESET_INPUTS (1),
+ .OUTPUT_RESET_SYNC_EDGES ("deassert"),
+ .SYNC_DEPTH (2),
+ .RESET_REQUEST_PRESENT (0),
+ .RESET_REQ_WAIT_TIME (1),
+ .MIN_RST_ASSERTION_TIME (3),
+ .RESET_REQ_EARLY_DSRT_TIME (1),
+ .USE_RESET_REQUEST_IN0 (0),
+ .USE_RESET_REQUEST_IN1 (0),
+ .USE_RESET_REQUEST_IN2 (0),
+ .USE_RESET_REQUEST_IN3 (0),
+ .USE_RESET_REQUEST_IN4 (0),
+ .USE_RESET_REQUEST_IN5 (0),
+ .USE_RESET_REQUEST_IN6 (0),
+ .USE_RESET_REQUEST_IN7 (0),
+ .USE_RESET_REQUEST_IN8 (0),
+ .USE_RESET_REQUEST_IN9 (0),
+ .USE_RESET_REQUEST_IN10 (0),
+ .USE_RESET_REQUEST_IN11 (0),
+ .USE_RESET_REQUEST_IN12 (0),
+ .USE_RESET_REQUEST_IN13 (0),
+ .USE_RESET_REQUEST_IN14 (0),
+ .USE_RESET_REQUEST_IN15 (0),
+ .ADAPT_RESET_REQUEST (0)
+ ) rst_controller (
+ .reset_in0 (reset), // reset_in0.reset
+ .clk (i_tse_pcs_0_pcs_transmit_clock_connection_clk), // clk.clk
+ .reset_out (rst_controller_reset_out_reset), // reset_out.reset
+ .reset_req (), // (terminated)
+ .reset_req_in0 (1'b0), // (terminated)
+ .reset_in1 (1'b0), // (terminated)
+ .reset_req_in1 (1'b0), // (terminated)
+ .reset_in2 (1'b0), // (terminated)
+ .reset_req_in2 (1'b0), // (terminated)
+ .reset_in3 (1'b0), // (terminated)
+ .reset_req_in3 (1'b0), // (terminated)
+ .reset_in4 (1'b0), // (terminated)
+ .reset_req_in4 (1'b0), // (terminated)
+ .reset_in5 (1'b0), // (terminated)
+ .reset_req_in5 (1'b0), // (terminated)
+ .reset_in6 (1'b0), // (terminated)
+ .reset_req_in6 (1'b0), // (terminated)
+ .reset_in7 (1'b0), // (terminated)
+ .reset_req_in7 (1'b0), // (terminated)
+ .reset_in8 (1'b0), // (terminated)
+ .reset_req_in8 (1'b0), // (terminated)
+ .reset_in9 (1'b0), // (terminated)
+ .reset_req_in9 (1'b0), // (terminated)
+ .reset_in10 (1'b0), // (terminated)
+ .reset_req_in10 (1'b0), // (terminated)
+ .reset_in11 (1'b0), // (terminated)
+ .reset_req_in11 (1'b0), // (terminated)
+ .reset_in12 (1'b0), // (terminated)
+ .reset_req_in12 (1'b0), // (terminated)
+ .reset_in13 (1'b0), // (terminated)
+ .reset_req_in13 (1'b0), // (terminated)
+ .reset_in14 (1'b0), // (terminated)
+ .reset_req_in14 (1'b0), // (terminated)
+ .reset_in15 (1'b0), // (terminated)
+ .reset_req_in15 (1'b0) // (terminated)
+ );
+
+ altera_reset_controller #(
+ .NUM_RESET_INPUTS (1),
+ .OUTPUT_RESET_SYNC_EDGES ("deassert"),
+ .SYNC_DEPTH (2),
+ .RESET_REQUEST_PRESENT (0),
+ .RESET_REQ_WAIT_TIME (1),
+ .MIN_RST_ASSERTION_TIME (3),
+ .RESET_REQ_EARLY_DSRT_TIME (1),
+ .USE_RESET_REQUEST_IN0 (0),
+ .USE_RESET_REQUEST_IN1 (0),
+ .USE_RESET_REQUEST_IN2 (0),
+ .USE_RESET_REQUEST_IN3 (0),
+ .USE_RESET_REQUEST_IN4 (0),
+ .USE_RESET_REQUEST_IN5 (0),
+ .USE_RESET_REQUEST_IN6 (0),
+ .USE_RESET_REQUEST_IN7 (0),
+ .USE_RESET_REQUEST_IN8 (0),
+ .USE_RESET_REQUEST_IN9 (0),
+ .USE_RESET_REQUEST_IN10 (0),
+ .USE_RESET_REQUEST_IN11 (0),
+ .USE_RESET_REQUEST_IN12 (0),
+ .USE_RESET_REQUEST_IN13 (0),
+ .USE_RESET_REQUEST_IN14 (0),
+ .USE_RESET_REQUEST_IN15 (0),
+ .ADAPT_RESET_REQUEST (0)
+ ) rst_controller_001 (
+ .reset_in0 (reset), // reset_in0.reset
+ .clk (i_tse_pcs_0_pcs_receive_clock_connection_clk), // clk.clk
+ .reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
+ .reset_req (), // (terminated)
+ .reset_req_in0 (1'b0), // (terminated)
+ .reset_in1 (1'b0), // (terminated)
+ .reset_req_in1 (1'b0), // (terminated)
+ .reset_in2 (1'b0), // (terminated)
+ .reset_req_in2 (1'b0), // (terminated)
+ .reset_in3 (1'b0), // (terminated)
+ .reset_req_in3 (1'b0), // (terminated)
+ .reset_in4 (1'b0), // (terminated)
+ .reset_req_in4 (1'b0), // (terminated)
+ .reset_in5 (1'b0), // (terminated)
+ .reset_req_in5 (1'b0), // (terminated)
+ .reset_in6 (1'b0), // (terminated)
+ .reset_req_in6 (1'b0), // (terminated)
+ .reset_in7 (1'b0), // (terminated)
+ .reset_req_in7 (1'b0), // (terminated)
+ .reset_in8 (1'b0), // (terminated)
+ .reset_req_in8 (1'b0), // (terminated)
+ .reset_in9 (1'b0), // (terminated)
+ .reset_req_in9 (1'b0), // (terminated)
+ .reset_in10 (1'b0), // (terminated)
+ .reset_req_in10 (1'b0), // (terminated)
+ .reset_in11 (1'b0), // (terminated)
+ .reset_req_in11 (1'b0), // (terminated)
+ .reset_in12 (1'b0), // (terminated)
+ .reset_req_in12 (1'b0), // (terminated)
+ .reset_in13 (1'b0), // (terminated)
+ .reset_req_in13 (1'b0), // (terminated)
+ .reset_in14 (1'b0), // (terminated)
+ .reset_req_in14 (1'b0), // (terminated)
+ .reset_in15 (1'b0), // (terminated)
+ .reset_req_in15 (1'b0) // (terminated)
+ );
+
+ assign i_nf_native_phyip_0_rx_patterndetect_rx_patterndetect = { i_nf_native_phyip_0_rx_parallel_data[12] };
+
+ assign i_nf_native_phyip_0_rx_parallel_data_rx_parallel_data = { i_nf_native_phyip_0_rx_parallel_data[7], i_nf_native_phyip_0_rx_parallel_data[6], i_nf_native_phyip_0_rx_parallel_data[5], i_nf_native_phyip_0_rx_parallel_data[4], i_nf_native_phyip_0_rx_parallel_data[3], i_nf_native_phyip_0_rx_parallel_data[2], i_nf_native_phyip_0_rx_parallel_data[1], i_nf_native_phyip_0_rx_parallel_data[0] };
+
+ assign i_nf_native_phyip_0_rx_disperr_rx_disperr = { i_nf_native_phyip_0_rx_parallel_data[11] };
+
+ assign i_nf_native_phyip_0_rx_errdetect_rx_errdetect = { i_nf_native_phyip_0_rx_parallel_data[9] };
+
+ assign i_nf_native_phyip_0_rx_syncstatus_rx_syncstatus = { i_nf_native_phyip_0_rx_parallel_data[10] };
+
+ assign i_nf_native_phyip_0_rx_runningdisp_rx_runningdisp = { i_nf_native_phyip_0_rx_parallel_data[15] };
+
+ assign i_nf_native_phyip_0_rx_datak_rx_datak = { i_nf_native_phyip_0_rx_parallel_data[8] };
+
+ assign i_nf_native_phyip_0_unused_rx_parallel_data_unused_rx_parallel_data = { i_nf_native_phyip_0_rx_parallel_data[127], i_nf_native_phyip_0_rx_parallel_data[126], i_nf_native_phyip_0_rx_parallel_data[125], i_nf_native_phyip_0_rx_parallel_data[124], i_nf_native_phyip_0_rx_parallel_data[123], i_nf_native_phyip_0_rx_parallel_data[122], i_nf_native_phyip_0_rx_parallel_data[121], i_nf_native_phyip_0_rx_parallel_data[120], i_nf_native_phyip_0_rx_parallel_data[119], i_nf_native_phyip_0_rx_parallel_data[118], i_nf_native_phyip_0_rx_parallel_data[117], i_nf_native_phyip_0_rx_parallel_data[116], i_nf_native_phyip_0_rx_parallel_data[115], i_nf_native_phyip_0_rx_parallel_data[114], i_nf_native_phyip_0_rx_parallel_data[113], i_nf_native_phyip_0_rx_parallel_data[112], i_nf_native_phyip_0_rx_parallel_data[111], i_nf_native_phyip_0_rx_parallel_data[110], i_nf_native_phyip_0_rx_parallel_data[109], i_nf_native_phyip_0_rx_parallel_data[108], i_nf_native_phyip_0_rx_parallel_data[107], i_nf_native_phyip_0_rx_parallel_data[106], i_nf_native_phyip_0_rx_parallel_data[105], i_nf_native_phyip_0_rx_parallel_data[104], i_nf_native_phyip_0_rx_parallel_data[103], i_nf_native_phyip_0_rx_parallel_data[102], i_nf_native_phyip_0_rx_parallel_data[101], i_nf_native_phyip_0_rx_parallel_data[100], i_nf_native_phyip_0_rx_parallel_data[99], i_nf_native_phyip_0_rx_parallel_data[98], i_nf_native_phyip_0_rx_parallel_data[97], i_nf_native_phyip_0_rx_parallel_data[96], i_nf_native_phyip_0_rx_parallel_data[95], i_nf_native_phyip_0_rx_parallel_data[94], i_nf_native_phyip_0_rx_parallel_data[93], i_nf_native_phyip_0_rx_parallel_data[92], i_nf_native_phyip_0_rx_parallel_data[91], i_nf_native_phyip_0_rx_parallel_data[90], i_nf_native_phyip_0_rx_parallel_data[89], i_nf_native_phyip_0_rx_parallel_data[88], i_nf_native_phyip_0_rx_parallel_data[87], i_nf_native_phyip_0_rx_parallel_data[86], i_nf_native_phyip_0_rx_parallel_data[85], i_nf_native_phyip_0_rx_parallel_data[84], i_nf_native_phyip_0_rx_parallel_data[83], i_nf_native_phyip_0_rx_parallel_data[82], i_nf_native_phyip_0_rx_parallel_data[81], i_nf_native_phyip_0_rx_parallel_data[80], i_nf_native_phyip_0_rx_parallel_data[79], i_nf_native_phyip_0_rx_parallel_data[78], i_nf_native_phyip_0_rx_parallel_data[77], i_nf_native_phyip_0_rx_parallel_data[76], i_nf_native_phyip_0_rx_parallel_data[75], i_nf_native_phyip_0_rx_parallel_data[74], i_nf_native_phyip_0_rx_parallel_data[73], i_nf_native_phyip_0_rx_parallel_data[72], i_nf_native_phyip_0_rx_parallel_data[71], i_nf_native_phyip_0_rx_parallel_data[70], i_nf_native_phyip_0_rx_parallel_data[69], i_nf_native_phyip_0_rx_parallel_data[68], i_nf_native_phyip_0_rx_parallel_data[67], i_nf_native_phyip_0_rx_parallel_data[66], i_nf_native_phyip_0_rx_parallel_data[65], i_nf_native_phyip_0_rx_parallel_data[64], i_nf_native_phyip_0_rx_parallel_data[63], i_nf_native_phyip_0_rx_parallel_data[62], i_nf_native_phyip_0_rx_parallel_data[61], i_nf_native_phyip_0_rx_parallel_data[60], i_nf_native_phyip_0_rx_parallel_data[59], i_nf_native_phyip_0_rx_parallel_data[58], i_nf_native_phyip_0_rx_parallel_data[57], i_nf_native_phyip_0_rx_parallel_data[56], i_nf_native_phyip_0_rx_parallel_data[55], i_nf_native_phyip_0_rx_parallel_data[54], i_nf_native_phyip_0_rx_parallel_data[53], i_nf_native_phyip_0_rx_parallel_data[52], i_nf_native_phyip_0_rx_parallel_data[51], i_nf_native_phyip_0_rx_parallel_data[50], i_nf_native_phyip_0_rx_parallel_data[49], i_nf_native_phyip_0_rx_parallel_data[48], i_nf_native_phyip_0_rx_parallel_data[47], i_nf_native_phyip_0_rx_parallel_data[46], i_nf_native_phyip_0_rx_parallel_data[45], i_nf_native_phyip_0_rx_parallel_data[44], i_nf_native_phyip_0_rx_parallel_data[43], i_nf_native_phyip_0_rx_parallel_data[42], i_nf_native_phyip_0_rx_parallel_data[41], i_nf_native_phyip_0_rx_parallel_data[40], i_nf_native_phyip_0_rx_parallel_data[39], i_nf_native_phyip_0_rx_parallel_data[38], i_nf_native_phyip_0_rx_parallel_data[37], i_nf_native_phyip_0_rx_parallel_data[36], i_nf_native_phyip_0_rx_parallel_data[35], i_nf_native_phyip_0_rx_parallel_data[34], i_nf_native_phyip_0_rx_parallel_data[33], i_nf_native_phyip_0_rx_parallel_data[32], i_nf_native_phyip_0_rx_parallel_data[31], i_nf_native_phyip_0_rx_parallel_data[30], i_nf_native_phyip_0_rx_parallel_data[29], i_nf_native_phyip_0_rx_parallel_data[28], i_nf_native_phyip_0_rx_parallel_data[27], i_nf_native_phyip_0_rx_parallel_data[26], i_nf_native_phyip_0_rx_parallel_data[25], i_nf_native_phyip_0_rx_parallel_data[24], i_nf_native_phyip_0_rx_parallel_data[23], i_nf_native_phyip_0_rx_parallel_data[22], i_nf_native_phyip_0_rx_parallel_data[21], i_nf_native_phyip_0_rx_parallel_data[20], i_nf_native_phyip_0_rx_parallel_data[19], i_nf_native_phyip_0_rx_parallel_data[18], i_nf_native_phyip_0_rx_parallel_data[17], i_nf_native_phyip_0_rx_parallel_data[16], i_nf_native_phyip_0_rx_parallel_data[14], i_nf_native_phyip_0_rx_parallel_data[13] };
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_2txhhaq_cfg.v b/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_2txhhaq_cfg.v
new file mode 100644
index 0000000000000000000000000000000000000000..26da19e269c169e74507017cc97ced5c22508b13
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_2txhhaq_cfg.v
@@ -0,0 +1,11 @@
+config arria10_hps_altera_eth_tse_221_2txhhaq_cfg;
+ design arria10_hps_altera_eth_tse_221_2txhhaq;
+ instance arria10_hps_altera_eth_tse_221_2txhhaq.i_tse_mac use arria10_hps_altera_eth_tse_mac_221.altera_eth_tse_mac;
+ instance arria10_hps_altera_eth_tse_221_2txhhaq.avalon_arbiter use arria10_hps_altera_eth_tse_avalon_arbiter_221.altera_eth_tse_avalon_arbiter;
+ instance arria10_hps_altera_eth_tse_221_2txhhaq.i_tse_pcs_0 use arria10_hps_altera_eth_tse_pcs_pma_nf_phyip_221.altera_eth_tse_pcs_pma_nf_phyip;
+ instance arria10_hps_altera_eth_tse_221_2txhhaq.i_nf_native_phyip_0 use arria10_hps_altera_xcvr_native_a10_221.arria10_hps_altera_xcvr_native_a10_221_sfv7jkq;
+ instance arria10_hps_altera_eth_tse_221_2txhhaq.i_nf_native_phyip_terminator_0 use arria10_hps_altera_eth_tse_nf_phyip_terminator_221.altera_eth_tse_nf_phyip_terminator;
+ instance arria10_hps_altera_eth_tse_221_2txhhaq.rst_controller use arria10_hps_altera_reset_controller_221.altera_reset_controller;
+ instance arria10_hps_altera_eth_tse_221_2txhhaq.rst_controller_001 use arria10_hps_altera_reset_controller_221.altera_reset_controller;
+endconfig
+
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_izmmkjq.v b/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_izmmkjq.v
new file mode 100644
index 0000000000000000000000000000000000000000..18aa432f9be04a902de4c308d5f6a05fba5fd85b
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_izmmkjq.v
@@ -0,0 +1,1720 @@
+// arria10_hps_altera_eth_tse_221_izmmkjq.v
+
+// This file was auto-generated from altera_eth_tse_hw.tcl. If you edit it your changes
+// will probably be lost.
+//
+// Generated using ACDS version 22.1 922
+
+`timescale 1 ps / 1 ps
+module arria10_hps_altera_eth_tse_221_izmmkjq (
+ input wire clk, // control_port_clock_connection.clk
+ input wire reset, // reset_connection.reset
+ output wire [31:0] reg_data_out, // control_port.readdata
+ input wire reg_rd, // .read
+ input wire [31:0] reg_data_in, // .writedata
+ input wire reg_wr, // .write
+ output wire reg_busy, // .waitrequest
+ input wire [7:0] reg_addr, // .address
+ input wire ff_rx_clk, // receive_clock_connection.clk
+ input wire ff_tx_clk, // transmit_clock_connection.clk
+ output wire [31:0] ff_rx_data, // receive.data
+ output wire ff_rx_eop, // .endofpacket
+ output wire [5:0] rx_err, // .error
+ output wire [1:0] ff_rx_mod, // .empty
+ input wire ff_rx_rdy, // .ready
+ output wire ff_rx_sop, // .startofpacket
+ output wire ff_rx_dval, // .valid
+ input wire [31:0] ff_tx_data, // transmit.data
+ input wire ff_tx_eop, // .endofpacket
+ input wire ff_tx_err, // .error
+ input wire [1:0] ff_tx_mod, // .empty
+ output wire ff_tx_rdy, // .ready
+ input wire ff_tx_sop, // .startofpacket
+ input wire ff_tx_wren, // .valid
+ output wire mdc, // mac_mdio_connection.mdc
+ input wire mdio_in, // .mdio_in
+ output wire mdio_out, // .mdio_out
+ output wire mdio_oen, // .mdio_oen
+ output wire magic_wakeup, // mac_misc_connection.magic_wakeup
+ input wire magic_sleep_n, // .magic_sleep_n
+ input wire ff_tx_crc_fwd, // .ff_tx_crc_fwd
+ output wire ff_tx_septy, // .ff_tx_septy
+ output wire tx_ff_uflow, // .tx_ff_uflow
+ output wire ff_tx_a_full, // .ff_tx_a_full
+ output wire ff_tx_a_empty, // .ff_tx_a_empty
+ output wire [17:0] rx_err_stat, // .rx_err_stat
+ output wire [3:0] rx_frm_type, // .rx_frm_type
+ output wire ff_rx_dsav, // .ff_rx_dsav
+ output wire ff_rx_a_full, // .ff_rx_a_full
+ output wire ff_rx_a_empty, // .ff_rx_a_empty
+ input wire ref_clk, // pcs_ref_clk_clock_connection.clk
+ output wire led_crs, // status_led_connection.crs
+ output wire led_link, // .link
+ output wire led_panel_link, // .panel_link
+ output wire led_col, // .col
+ output wire led_an, // .an
+ output wire led_char_err, // .char_err
+ output wire led_disp_err, // .disp_err
+ output wire rx_recovclkout, // serdes_control_connection.export
+ input wire rxp, // serial_connection.rxp
+ output wire txp, // .txp
+ input wire [0:0] tx_serial_clk, // tx_serial_clk.clk
+ input wire rx_cdr_refclk, // rx_cdr_refclk.clk
+ input wire [0:0] tx_analogreset, // tx_analogreset.tx_analogreset
+ input wire [0:0] tx_digitalreset, // tx_digitalreset.tx_digitalreset
+ input wire [0:0] rx_analogreset, // rx_analogreset.rx_analogreset
+ input wire [0:0] rx_digitalreset, // rx_digitalreset.rx_digitalreset
+ output wire [0:0] tx_cal_busy, // tx_cal_busy.tx_cal_busy
+ output wire [0:0] rx_cal_busy, // rx_cal_busy.rx_cal_busy
+ input wire [0:0] rx_set_locktodata, // rx_set_locktodata.rx_set_locktodata
+ input wire [0:0] rx_set_locktoref, // rx_set_locktoref.rx_set_locktoref
+ output wire [0:0] rx_is_lockedtoref, // rx_is_lockedtoref.rx_is_lockedtoref
+ output wire [0:0] rx_is_lockedtodata, // rx_is_lockedtodata.rx_is_lockedtodata
+ input wire [0:0] reconfig_clk, // reconfig_clk.clk
+ input wire [0:0] reconfig_reset, // reconfig_reset.reset
+ input wire [0:0] reconfig_write, // reconfig_avmm.write
+ input wire [0:0] reconfig_read, // .read
+ input wire [9:0] reconfig_address, // .address
+ input wire [31:0] reconfig_writedata, // .writedata
+ output wire [31:0] reconfig_readdata, // .readdata
+ output wire [0:0] reconfig_waitrequest // .waitrequest
+ );
+
+ wire [31:0] avalon_arbiter_av_mac_master_0_readdata; // i_tse_mac:reg_data_out -> avalon_arbiter:mac_readdata_0
+ wire avalon_arbiter_av_mac_master_0_waitrequest; // i_tse_mac:reg_busy -> avalon_arbiter:mac_waitrequest_0
+ wire [7:0] avalon_arbiter_av_mac_master_0_address; // avalon_arbiter:mac_address_0 -> i_tse_mac:reg_addr
+ wire avalon_arbiter_av_mac_master_0_read; // avalon_arbiter:mac_read_0 -> i_tse_mac:reg_rd
+ wire [31:0] avalon_arbiter_av_mac_master_0_writedata; // avalon_arbiter:mac_writedata_0 -> i_tse_mac:reg_data_in
+ wire avalon_arbiter_av_mac_master_0_write; // avalon_arbiter:mac_write_0 -> i_tse_mac:reg_wr
+ wire i_tse_pcs_0_sd_loopback_sd_loopback; // i_tse_pcs_0:sd_loopback -> i_nf_native_phyip_terminator_0:sd_loopback
+ wire i_nf_native_phyip_0_rx_patterndetect_rx_patterndetect; // i_nf_native_phyip_0:rx_patterndetect -> i_tse_pcs_0:rx_patterndetect
+ wire [7:0] i_nf_native_phyip_0_rx_parallel_data_rx_parallel_data; // i_nf_native_phyip_0:rx_parallel_data -> i_tse_pcs_0:rx_frame
+ wire i_tse_pcs_0_tx_kchar_tx_datak; // i_tse_pcs_0:tx_kchar -> i_nf_native_phyip_0:tx_datak
+ wire i_nf_native_phyip_0_rx_disperr_rx_disperr; // i_nf_native_phyip_0:rx_disperr -> i_tse_pcs_0:rx_disp_err
+ wire i_nf_native_phyip_0_rx_errdetect_rx_errdetect; // i_nf_native_phyip_0:rx_errdetect -> i_tse_pcs_0:rx_char_err_gx
+ wire i_nf_native_phyip_0_rx_syncstatus_rx_syncstatus; // i_nf_native_phyip_0:rx_syncstatus -> i_tse_pcs_0:rx_syncstatus
+ wire i_nf_native_phyip_0_rx_runningdisp_rx_runningdisp; // i_nf_native_phyip_0:rx_runningdisp -> i_tse_pcs_0:rx_runningdisp
+ wire i_nf_native_phyip_0_rx_datak_rx_datak; // i_nf_native_phyip_0:rx_datak -> i_tse_pcs_0:rx_kchar
+ wire [7:0] i_tse_pcs_0_tx_frame_tx_parallel_data; // i_tse_pcs_0:tx_frame -> i_nf_native_phyip_0:tx_parallel_data
+ wire [4:0] i_nf_native_phyip_0_rx_std_bitslipboundarysel_rx_std_bitslipboundarysel; // i_nf_native_phyip_0:rx_std_bitslipboundarysel -> i_tse_pcs_0:wa_boundary
+ wire i_nf_native_phyip_terminator_0_rx_runlengthviolation_rx_runlengthviolation; // i_nf_native_phyip_terminator_0:rx_runlengthviolation -> i_tse_pcs_0:rx_runlengthviolation
+ wire i_nf_native_phyip_terminator_0_tx_pcs_clk_tx_pcs_clk; // i_nf_native_phyip_terminator_0:tx_pcs_clk -> i_tse_pcs_0:tx_pcs_clk
+ wire i_nf_native_phyip_terminator_0_rx_pcs_clk_rx_pcs_clk; // i_nf_native_phyip_terminator_0:rx_pcs_clk -> i_tse_pcs_0:rx_pcs_clk
+ wire [118:0] i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data; // i_nf_native_phyip_terminator_0:unused_tx_parallel_data -> i_nf_native_phyip_0:unused_tx_parallel_data
+ wire [0:0] i_nf_native_phyip_0_tx_serial_data_tx_serial_data; // i_nf_native_phyip_0:tx_serial_data -> i_nf_native_phyip_terminator_0:tx_serial_data
+ wire [0:0] i_nf_native_phyip_0_tx_clkout_clk; // i_nf_native_phyip_0:tx_clkout -> i_nf_native_phyip_terminator_0:tx_clk
+ wire i_nf_native_phyip_terminator_0_rx_seriallpbken_rx_seriallpbken; // i_nf_native_phyip_terminator_0:rx_seriallpbken -> i_nf_native_phyip_0:rx_seriallpbken
+ wire [113:0] i_nf_native_phyip_0_unused_rx_parallel_data_unused_rx_parallel_data; // i_nf_native_phyip_0:unused_rx_parallel_data -> i_nf_native_phyip_terminator_0:unused_rx_parallel_data
+ wire i_nf_native_phyip_terminator_0_rx_serial_data_rx_serial_data; // i_nf_native_phyip_terminator_0:rx_serial_data -> i_nf_native_phyip_0:rx_serial_data
+ wire [0:0] i_nf_native_phyip_0_rx_clkout_clk; // i_nf_native_phyip_0:rx_clkout -> i_nf_native_phyip_terminator_0:rx_clk
+ wire [0:0] i_nf_native_phyip_0_rx_pma_div_clkout_clk; // i_nf_native_phyip_0:rx_pma_div_clkout -> i_nf_native_phyip_terminator_0:rx_recovered_clk
+ wire i_nf_native_phyip_terminator_0_tx_coreclk_clk; // i_nf_native_phyip_terminator_0:tx_coreclk -> i_nf_native_phyip_0:tx_coreclkin
+ wire i_nf_native_phyip_terminator_0_rx_coreclk_clk; // i_nf_native_phyip_terminator_0:rx_coreclk -> i_nf_native_phyip_0:rx_coreclkin
+ wire [15:0] avalon_arbiter_av_pcs_master_0_readdata; // i_tse_pcs_0:reg_data_out -> avalon_arbiter:pcs_readdata_0
+ wire avalon_arbiter_av_pcs_master_0_waitrequest; // i_tse_pcs_0:reg_busy -> avalon_arbiter:pcs_waitrequest_0
+ wire [4:0] avalon_arbiter_av_pcs_master_0_address; // avalon_arbiter:pcs_address_0 -> i_tse_pcs_0:reg_addr
+ wire avalon_arbiter_av_pcs_master_0_read; // avalon_arbiter:pcs_read_0 -> i_tse_pcs_0:reg_rd
+ wire [15:0] avalon_arbiter_av_pcs_master_0_writedata; // avalon_arbiter:pcs_writedata_0 -> i_tse_pcs_0:reg_data_in
+ wire avalon_arbiter_av_pcs_master_0_write; // avalon_arbiter:pcs_write_0 -> i_tse_pcs_0:reg_wr
+ wire i_tse_pcs_0_pcs_transmit_clock_connection_clk; // i_tse_pcs_0:tx_clk -> [i_tse_mac:tx_clk, rst_controller:clk]
+ wire i_tse_pcs_0_pcs_receive_clock_connection_clk; // i_tse_pcs_0:rx_clk -> [i_tse_mac:rx_clk, rst_controller_001:clk]
+ wire [7:0] i_tse_pcs_0_gmii_connection_gmii_rx_d; // i_tse_pcs_0:gmii_rx_d -> i_tse_mac:gm_rx_d
+ wire i_tse_pcs_0_gmii_connection_gmii_rx_err; // i_tse_pcs_0:gmii_rx_err -> i_tse_mac:gm_rx_err
+ wire i_tse_pcs_0_gmii_connection_gmii_rx_dv; // i_tse_pcs_0:gmii_rx_dv -> i_tse_mac:gm_rx_dv
+ wire [7:0] i_tse_mac_mac_gmii_connection_gmii_tx_d; // i_tse_mac:gm_tx_d -> i_tse_pcs_0:gmii_tx_d
+ wire i_tse_mac_mac_gmii_connection_gmii_tx_en; // i_tse_mac:gm_tx_en -> i_tse_pcs_0:gmii_tx_en
+ wire i_tse_mac_mac_gmii_connection_gmii_tx_err; // i_tse_mac:gm_tx_err -> i_tse_pcs_0:gmii_tx_err
+ wire i_tse_mac_mac_mii_connection_mii_tx_en; // i_tse_mac:m_tx_en -> i_tse_pcs_0:mii_tx_en
+ wire [3:0] i_tse_pcs_0_mii_connection_mii_rx_d; // i_tse_pcs_0:mii_rx_d -> i_tse_mac:m_rx_d
+ wire i_tse_pcs_0_mii_connection_mii_col; // i_tse_pcs_0:mii_col -> i_tse_mac:m_rx_col
+ wire [3:0] i_tse_mac_mac_mii_connection_mii_tx_d; // i_tse_mac:m_tx_d -> i_tse_pcs_0:mii_tx_d
+ wire i_tse_mac_mac_mii_connection_mii_tx_err; // i_tse_mac:m_tx_err -> i_tse_pcs_0:mii_tx_err
+ wire i_tse_pcs_0_mii_connection_mii_crs; // i_tse_pcs_0:mii_crs -> i_tse_mac:m_rx_crs
+ wire i_tse_pcs_0_mii_connection_mii_rx_err; // i_tse_pcs_0:mii_rx_err -> i_tse_mac:m_rx_err
+ wire i_tse_pcs_0_mii_connection_mii_rx_dv; // i_tse_pcs_0:mii_rx_dv -> i_tse_mac:m_rx_en
+ wire i_tse_pcs_0_sgmii_status_connection_set_1000; // i_tse_pcs_0:set_1000 -> i_tse_mac:set_1000
+ wire i_tse_pcs_0_sgmii_status_connection_set_10; // i_tse_pcs_0:set_10 -> i_tse_mac:set_10
+ wire i_tse_pcs_0_clock_enable_connection_tx_clkena; // i_tse_pcs_0:tx_clkena -> i_tse_mac:tx_clkena
+ wire i_tse_pcs_0_clock_enable_connection_rx_clkena; // i_tse_pcs_0:rx_clkena -> i_tse_mac:rx_clkena
+ wire rst_controller_reset_out_reset; // rst_controller:reset_out -> i_tse_pcs_0:reset_tx_clk
+ wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> i_tse_pcs_0:reset_rx_clk
+ wire [127:0] i_nf_native_phyip_0_rx_parallel_data; // port fragment
+
+ altera_eth_tse_mac #(
+ .ING_ADDR (11),
+ .ENABLE_MAC_RX_VLAN (0),
+ .ENABLE_SUP_ADDR (0),
+ .DEVICE_FAMILY ("ARRIA10"),
+ .INSERT_TA (0),
+ .ING_FIFO (2048),
+ .ENABLE_ECC (0),
+ .CRC32DWIDTH (8),
+ .ENABLE_ENA (32),
+ .SYNCHRONIZER_DEPTH (3),
+ .ENABLE_MAC_TX_VLAN (0),
+ .RESET_LEVEL (1),
+ .STAT_CNT_ENA (1),
+ .CUST_VERSION (0),
+ .CRC32S1L2_EXTERN (0),
+ .MBIT_ONLY (1),
+ .EG_ADDR (11),
+ .CORE_VERSION (5633),
+ .CRC32GENDELAY (6),
+ .EG_FIFO (2048),
+ .REDUCED_INTERFACE_ENA (0),
+ .ENABLE_MAGIC_DETECT (1),
+ .ENABLE_MDIO (1),
+ .ENABLE_MAC_TXADDR_SET (1),
+ .RAM_TYPE ("AUTO"),
+ .CRC32CHECK16BIT (0),
+ .ENABLE_LGTH_CHECK (1),
+ .ENABLE_MAC_FLOW_CTRL (0),
+ .ENABLE_SHIFT16 (1),
+ .USE_SYNC_RESET (1),
+ .REDUCED_CONTROL (0),
+ .MDIO_CLK_DIV (40),
+ .ENABLE_PADDING (1),
+ .ENABLE_GMII_LOOPBACK (0),
+ .GBIT_ONLY (1),
+ .ENA_HASH (0),
+ .ENABLE_EXTENDED_STAT_REG (0),
+ .ENABLE_HD_LOGIC (0)
+ ) i_tse_mac (
+ .clk (clk), // control_port_clock_connection.clk
+ .reset (reset), // reset_connection.reset
+ .reg_addr (avalon_arbiter_av_mac_master_0_address), // control_port.address
+ .reg_data_out (avalon_arbiter_av_mac_master_0_readdata), // .readdata
+ .reg_rd (avalon_arbiter_av_mac_master_0_read), // .read
+ .reg_data_in (avalon_arbiter_av_mac_master_0_writedata), // .writedata
+ .reg_wr (avalon_arbiter_av_mac_master_0_write), // .write
+ .reg_busy (avalon_arbiter_av_mac_master_0_waitrequest), // .waitrequest
+ .ff_tx_clk (ff_tx_clk), // transmit_clock_connection.clk
+ .ff_rx_clk (ff_rx_clk), // receive_clock_connection.clk
+ .ff_rx_data (ff_rx_data), // receive.data
+ .ff_rx_eop (ff_rx_eop), // .endofpacket
+ .rx_err (rx_err), // .error
+ .ff_rx_mod (ff_rx_mod), // .empty
+ .ff_rx_rdy (ff_rx_rdy), // .ready
+ .ff_rx_sop (ff_rx_sop), // .startofpacket
+ .ff_rx_dval (ff_rx_dval), // .valid
+ .ff_tx_data (ff_tx_data), // transmit.data
+ .ff_tx_eop (ff_tx_eop), // .endofpacket
+ .ff_tx_err (ff_tx_err), // .error
+ .ff_tx_mod (ff_tx_mod), // .empty
+ .ff_tx_rdy (ff_tx_rdy), // .ready
+ .ff_tx_sop (ff_tx_sop), // .startofpacket
+ .ff_tx_wren (ff_tx_wren), // .valid
+ .magic_wakeup (magic_wakeup), // mac_misc_connection.export
+ .magic_sleep_n (magic_sleep_n), // .export
+ .ff_tx_crc_fwd (ff_tx_crc_fwd), // .export
+ .ff_tx_septy (ff_tx_septy), // .export
+ .tx_ff_uflow (tx_ff_uflow), // .export
+ .ff_tx_a_full (ff_tx_a_full), // .export
+ .ff_tx_a_empty (ff_tx_a_empty), // .export
+ .rx_err_stat (rx_err_stat), // .export
+ .rx_frm_type (rx_frm_type), // .export
+ .ff_rx_dsav (ff_rx_dsav), // .export
+ .ff_rx_a_full (ff_rx_a_full), // .export
+ .ff_rx_a_empty (ff_rx_a_empty), // .export
+ .mdc (mdc), // mac_mdio_connection.mdc
+ .mdio_in (mdio_in), // .mdio_in
+ .mdio_out (mdio_out), // .mdio_out
+ .mdio_oen (mdio_oen), // .mdio_oen
+ .gm_rx_d (i_tse_pcs_0_gmii_connection_gmii_rx_d), // mac_gmii_connection.gmii_rx_d
+ .gm_rx_dv (i_tse_pcs_0_gmii_connection_gmii_rx_dv), // .gmii_rx_dv
+ .gm_rx_err (i_tse_pcs_0_gmii_connection_gmii_rx_err), // .gmii_rx_err
+ .gm_tx_d (i_tse_mac_mac_gmii_connection_gmii_tx_d), // .gmii_tx_d
+ .gm_tx_en (i_tse_mac_mac_gmii_connection_gmii_tx_en), // .gmii_tx_en
+ .gm_tx_err (i_tse_mac_mac_gmii_connection_gmii_tx_err), // .gmii_tx_err
+ .m_rx_d (i_tse_pcs_0_mii_connection_mii_rx_d), // mac_mii_connection.mii_rx_d
+ .m_rx_en (i_tse_pcs_0_mii_connection_mii_rx_dv), // .mii_rx_dv
+ .m_rx_err (i_tse_pcs_0_mii_connection_mii_rx_err), // .mii_rx_err
+ .m_tx_d (i_tse_mac_mac_mii_connection_mii_tx_d), // .mii_tx_d
+ .m_tx_en (i_tse_mac_mac_mii_connection_mii_tx_en), // .mii_tx_en
+ .m_tx_err (i_tse_mac_mac_mii_connection_mii_tx_err), // .mii_tx_err
+ .m_rx_crs (i_tse_pcs_0_mii_connection_mii_crs), // .mii_crs
+ .m_rx_col (i_tse_pcs_0_mii_connection_mii_col), // .mii_col
+ .set_10 (i_tse_pcs_0_sgmii_status_connection_set_10), // mac_status_connection.set_10
+ .set_1000 (i_tse_pcs_0_sgmii_status_connection_set_1000), // .set_1000
+ .rx_clkena (i_tse_pcs_0_clock_enable_connection_rx_clkena), // mac_clkena_connection.rx_clkena
+ .tx_clkena (i_tse_pcs_0_clock_enable_connection_tx_clkena), // .tx_clkena
+ .tx_clk (i_tse_pcs_0_pcs_transmit_clock_connection_clk), // pcs_mac_tx_clock_connection.clk
+ .rx_clk (i_tse_pcs_0_pcs_receive_clock_connection_clk), // pcs_mac_rx_clock_connection.clk
+ .xon_gen (1'b0), // (terminated)
+ .xoff_gen (1'b0), // (terminated)
+ .mac_eccstatus (), // (terminated)
+ .rgmii_out1_aclr (), // (terminated)
+ .rgmii_out1_din (), // (terminated)
+ .rgmii_in1_dout (2'b00), // (terminated)
+ .rgmii_in1_ck (), // (terminated)
+ .rgmii_out4_din (), // (terminated)
+ .rgmii_out4_ck (), // (terminated)
+ .rgmii_in1_pad (), // (terminated)
+ .rgmii_out4_aclr (), // (terminated)
+ .rgmii_out1_pad (1'b0), // (terminated)
+ .rgmii_out1_ck (), // (terminated)
+ .rgmii_in4_dout (8'b00000000), // (terminated)
+ .rgmii_in4_pad (), // (terminated)
+ .rgmii_out4_pad (4'b0000), // (terminated)
+ .rgmii_in4_ck (), // (terminated)
+ .rgmii_in (4'b0000), // (terminated)
+ .rgmii_out (), // (terminated)
+ .rx_control (1'b0), // (terminated)
+ .tx_control (), // (terminated)
+ .eth_mode (), // (terminated)
+ .ena_10 () // (terminated)
+ );
+
+ altera_eth_tse_avalon_arbiter #(
+ .MAX_CHANNELS (1),
+ .MAC_ONLY (0),
+ .SLAVE_ADDR_WIDTH (8)
+ ) avalon_arbiter (
+ .clk (clk), // clk.clk
+ .reset (reset), // reset.reset
+ .reg_data_out (reg_data_out), // av_slave.readdata
+ .reg_rd (reg_rd), // .read
+ .reg_data_in (reg_data_in), // .writedata
+ .reg_wr (reg_wr), // .write
+ .reg_busy (reg_busy), // .waitrequest
+ .reg_addr (reg_addr), // .address
+ .mac_address_0 (avalon_arbiter_av_mac_master_0_address), // av_mac_master_0.address
+ .mac_readdata_0 (avalon_arbiter_av_mac_master_0_readdata), // .readdata
+ .mac_read_0 (avalon_arbiter_av_mac_master_0_read), // .read
+ .mac_writedata_0 (avalon_arbiter_av_mac_master_0_writedata), // .writedata
+ .mac_write_0 (avalon_arbiter_av_mac_master_0_write), // .write
+ .mac_waitrequest_0 (avalon_arbiter_av_mac_master_0_waitrequest), // .waitrequest
+ .pcs_address_0 (avalon_arbiter_av_pcs_master_0_address), // av_pcs_master_0.address
+ .pcs_readdata_0 (avalon_arbiter_av_pcs_master_0_readdata), // .readdata
+ .pcs_read_0 (avalon_arbiter_av_pcs_master_0_read), // .read
+ .pcs_writedata_0 (avalon_arbiter_av_pcs_master_0_writedata), // .writedata
+ .pcs_write_0 (avalon_arbiter_av_pcs_master_0_write), // .write
+ .pcs_waitrequest_0 (avalon_arbiter_av_pcs_master_0_waitrequest), // .waitrequest
+ .mac_address_1 (), // (terminated)
+ .mac_readdata_1 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_1 (), // (terminated)
+ .mac_writedata_1 (), // (terminated)
+ .mac_write_1 (), // (terminated)
+ .mac_waitrequest_1 (1'b0), // (terminated)
+ .pcs_address_1 (), // (terminated)
+ .pcs_readdata_1 (16'b0000000000000000), // (terminated)
+ .pcs_read_1 (), // (terminated)
+ .pcs_writedata_1 (), // (terminated)
+ .pcs_write_1 (), // (terminated)
+ .pcs_waitrequest_1 (1'b0), // (terminated)
+ .mac_address_2 (), // (terminated)
+ .mac_readdata_2 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_2 (), // (terminated)
+ .mac_writedata_2 (), // (terminated)
+ .mac_write_2 (), // (terminated)
+ .mac_waitrequest_2 (1'b0), // (terminated)
+ .pcs_address_2 (), // (terminated)
+ .pcs_readdata_2 (16'b0000000000000000), // (terminated)
+ .pcs_read_2 (), // (terminated)
+ .pcs_writedata_2 (), // (terminated)
+ .pcs_write_2 (), // (terminated)
+ .pcs_waitrequest_2 (1'b0), // (terminated)
+ .mac_address_3 (), // (terminated)
+ .mac_readdata_3 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_3 (), // (terminated)
+ .mac_writedata_3 (), // (terminated)
+ .mac_write_3 (), // (terminated)
+ .mac_waitrequest_3 (1'b0), // (terminated)
+ .pcs_address_3 (), // (terminated)
+ .pcs_readdata_3 (16'b0000000000000000), // (terminated)
+ .pcs_read_3 (), // (terminated)
+ .pcs_writedata_3 (), // (terminated)
+ .pcs_write_3 (), // (terminated)
+ .pcs_waitrequest_3 (1'b0), // (terminated)
+ .mac_address_4 (), // (terminated)
+ .mac_readdata_4 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_4 (), // (terminated)
+ .mac_writedata_4 (), // (terminated)
+ .mac_write_4 (), // (terminated)
+ .mac_waitrequest_4 (1'b0), // (terminated)
+ .pcs_address_4 (), // (terminated)
+ .pcs_readdata_4 (16'b0000000000000000), // (terminated)
+ .pcs_read_4 (), // (terminated)
+ .pcs_writedata_4 (), // (terminated)
+ .pcs_write_4 (), // (terminated)
+ .pcs_waitrequest_4 (1'b0), // (terminated)
+ .mac_address_5 (), // (terminated)
+ .mac_readdata_5 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_5 (), // (terminated)
+ .mac_writedata_5 (), // (terminated)
+ .mac_write_5 (), // (terminated)
+ .mac_waitrequest_5 (1'b0), // (terminated)
+ .pcs_address_5 (), // (terminated)
+ .pcs_readdata_5 (16'b0000000000000000), // (terminated)
+ .pcs_read_5 (), // (terminated)
+ .pcs_writedata_5 (), // (terminated)
+ .pcs_write_5 (), // (terminated)
+ .pcs_waitrequest_5 (1'b0), // (terminated)
+ .mac_address_6 (), // (terminated)
+ .mac_readdata_6 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_6 (), // (terminated)
+ .mac_writedata_6 (), // (terminated)
+ .mac_write_6 (), // (terminated)
+ .mac_waitrequest_6 (1'b0), // (terminated)
+ .pcs_address_6 (), // (terminated)
+ .pcs_readdata_6 (16'b0000000000000000), // (terminated)
+ .pcs_read_6 (), // (terminated)
+ .pcs_writedata_6 (), // (terminated)
+ .pcs_write_6 (), // (terminated)
+ .pcs_waitrequest_6 (1'b0), // (terminated)
+ .mac_address_7 (), // (terminated)
+ .mac_readdata_7 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_7 (), // (terminated)
+ .mac_writedata_7 (), // (terminated)
+ .mac_write_7 (), // (terminated)
+ .mac_waitrequest_7 (1'b0), // (terminated)
+ .pcs_address_7 (), // (terminated)
+ .pcs_readdata_7 (16'b0000000000000000), // (terminated)
+ .pcs_read_7 (), // (terminated)
+ .pcs_writedata_7 (), // (terminated)
+ .pcs_write_7 (), // (terminated)
+ .pcs_waitrequest_7 (1'b0), // (terminated)
+ .mac_address_8 (), // (terminated)
+ .mac_readdata_8 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_8 (), // (terminated)
+ .mac_writedata_8 (), // (terminated)
+ .mac_write_8 (), // (terminated)
+ .mac_waitrequest_8 (1'b0), // (terminated)
+ .pcs_address_8 (), // (terminated)
+ .pcs_readdata_8 (16'b0000000000000000), // (terminated)
+ .pcs_read_8 (), // (terminated)
+ .pcs_writedata_8 (), // (terminated)
+ .pcs_write_8 (), // (terminated)
+ .pcs_waitrequest_8 (1'b0), // (terminated)
+ .mac_address_9 (), // (terminated)
+ .mac_readdata_9 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_9 (), // (terminated)
+ .mac_writedata_9 (), // (terminated)
+ .mac_write_9 (), // (terminated)
+ .mac_waitrequest_9 (1'b0), // (terminated)
+ .pcs_address_9 (), // (terminated)
+ .pcs_readdata_9 (16'b0000000000000000), // (terminated)
+ .pcs_read_9 (), // (terminated)
+ .pcs_writedata_9 (), // (terminated)
+ .pcs_write_9 (), // (terminated)
+ .pcs_waitrequest_9 (1'b0), // (terminated)
+ .mac_address_10 (), // (terminated)
+ .mac_readdata_10 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_10 (), // (terminated)
+ .mac_writedata_10 (), // (terminated)
+ .mac_write_10 (), // (terminated)
+ .mac_waitrequest_10 (1'b0), // (terminated)
+ .pcs_address_10 (), // (terminated)
+ .pcs_readdata_10 (16'b0000000000000000), // (terminated)
+ .pcs_read_10 (), // (terminated)
+ .pcs_writedata_10 (), // (terminated)
+ .pcs_write_10 (), // (terminated)
+ .pcs_waitrequest_10 (1'b0), // (terminated)
+ .mac_address_11 (), // (terminated)
+ .mac_readdata_11 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_11 (), // (terminated)
+ .mac_writedata_11 (), // (terminated)
+ .mac_write_11 (), // (terminated)
+ .mac_waitrequest_11 (1'b0), // (terminated)
+ .pcs_address_11 (), // (terminated)
+ .pcs_readdata_11 (16'b0000000000000000), // (terminated)
+ .pcs_read_11 (), // (terminated)
+ .pcs_writedata_11 (), // (terminated)
+ .pcs_write_11 (), // (terminated)
+ .pcs_waitrequest_11 (1'b0), // (terminated)
+ .mac_address_12 (), // (terminated)
+ .mac_readdata_12 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_12 (), // (terminated)
+ .mac_writedata_12 (), // (terminated)
+ .mac_write_12 (), // (terminated)
+ .mac_waitrequest_12 (1'b0), // (terminated)
+ .pcs_address_12 (), // (terminated)
+ .pcs_readdata_12 (16'b0000000000000000), // (terminated)
+ .pcs_read_12 (), // (terminated)
+ .pcs_writedata_12 (), // (terminated)
+ .pcs_write_12 (), // (terminated)
+ .pcs_waitrequest_12 (1'b0), // (terminated)
+ .mac_address_13 (), // (terminated)
+ .mac_readdata_13 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_13 (), // (terminated)
+ .mac_writedata_13 (), // (terminated)
+ .mac_write_13 (), // (terminated)
+ .mac_waitrequest_13 (1'b0), // (terminated)
+ .pcs_address_13 (), // (terminated)
+ .pcs_readdata_13 (16'b0000000000000000), // (terminated)
+ .pcs_read_13 (), // (terminated)
+ .pcs_writedata_13 (), // (terminated)
+ .pcs_write_13 (), // (terminated)
+ .pcs_waitrequest_13 (1'b0), // (terminated)
+ .mac_address_14 (), // (terminated)
+ .mac_readdata_14 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_14 (), // (terminated)
+ .mac_writedata_14 (), // (terminated)
+ .mac_write_14 (), // (terminated)
+ .mac_waitrequest_14 (1'b0), // (terminated)
+ .pcs_address_14 (), // (terminated)
+ .pcs_readdata_14 (16'b0000000000000000), // (terminated)
+ .pcs_read_14 (), // (terminated)
+ .pcs_writedata_14 (), // (terminated)
+ .pcs_write_14 (), // (terminated)
+ .pcs_waitrequest_14 (1'b0), // (terminated)
+ .mac_address_15 (), // (terminated)
+ .mac_readdata_15 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_15 (), // (terminated)
+ .mac_writedata_15 (), // (terminated)
+ .mac_write_15 (), // (terminated)
+ .mac_waitrequest_15 (1'b0), // (terminated)
+ .pcs_address_15 (), // (terminated)
+ .pcs_readdata_15 (16'b0000000000000000), // (terminated)
+ .pcs_read_15 (), // (terminated)
+ .pcs_writedata_15 (), // (terminated)
+ .pcs_write_15 (), // (terminated)
+ .pcs_waitrequest_15 (1'b0), // (terminated)
+ .mac_address_16 (), // (terminated)
+ .mac_readdata_16 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_16 (), // (terminated)
+ .mac_writedata_16 (), // (terminated)
+ .mac_write_16 (), // (terminated)
+ .mac_waitrequest_16 (1'b0), // (terminated)
+ .pcs_address_16 (), // (terminated)
+ .pcs_readdata_16 (16'b0000000000000000), // (terminated)
+ .pcs_read_16 (), // (terminated)
+ .pcs_writedata_16 (), // (terminated)
+ .pcs_write_16 (), // (terminated)
+ .pcs_waitrequest_16 (1'b0), // (terminated)
+ .mac_address_17 (), // (terminated)
+ .mac_readdata_17 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_17 (), // (terminated)
+ .mac_writedata_17 (), // (terminated)
+ .mac_write_17 (), // (terminated)
+ .mac_waitrequest_17 (1'b0), // (terminated)
+ .pcs_address_17 (), // (terminated)
+ .pcs_readdata_17 (16'b0000000000000000), // (terminated)
+ .pcs_read_17 (), // (terminated)
+ .pcs_writedata_17 (), // (terminated)
+ .pcs_write_17 (), // (terminated)
+ .pcs_waitrequest_17 (1'b0), // (terminated)
+ .mac_address_18 (), // (terminated)
+ .mac_readdata_18 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_18 (), // (terminated)
+ .mac_writedata_18 (), // (terminated)
+ .mac_write_18 (), // (terminated)
+ .mac_waitrequest_18 (1'b0), // (terminated)
+ .pcs_address_18 (), // (terminated)
+ .pcs_readdata_18 (16'b0000000000000000), // (terminated)
+ .pcs_read_18 (), // (terminated)
+ .pcs_writedata_18 (), // (terminated)
+ .pcs_write_18 (), // (terminated)
+ .pcs_waitrequest_18 (1'b0), // (terminated)
+ .mac_address_19 (), // (terminated)
+ .mac_readdata_19 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_19 (), // (terminated)
+ .mac_writedata_19 (), // (terminated)
+ .mac_write_19 (), // (terminated)
+ .mac_waitrequest_19 (1'b0), // (terminated)
+ .pcs_address_19 (), // (terminated)
+ .pcs_readdata_19 (16'b0000000000000000), // (terminated)
+ .pcs_read_19 (), // (terminated)
+ .pcs_writedata_19 (), // (terminated)
+ .pcs_write_19 (), // (terminated)
+ .pcs_waitrequest_19 (1'b0), // (terminated)
+ .mac_address_20 (), // (terminated)
+ .mac_readdata_20 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_20 (), // (terminated)
+ .mac_writedata_20 (), // (terminated)
+ .mac_write_20 (), // (terminated)
+ .mac_waitrequest_20 (1'b0), // (terminated)
+ .pcs_address_20 (), // (terminated)
+ .pcs_readdata_20 (16'b0000000000000000), // (terminated)
+ .pcs_read_20 (), // (terminated)
+ .pcs_writedata_20 (), // (terminated)
+ .pcs_write_20 (), // (terminated)
+ .pcs_waitrequest_20 (1'b0), // (terminated)
+ .mac_address_21 (), // (terminated)
+ .mac_readdata_21 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_21 (), // (terminated)
+ .mac_writedata_21 (), // (terminated)
+ .mac_write_21 (), // (terminated)
+ .mac_waitrequest_21 (1'b0), // (terminated)
+ .pcs_address_21 (), // (terminated)
+ .pcs_readdata_21 (16'b0000000000000000), // (terminated)
+ .pcs_read_21 (), // (terminated)
+ .pcs_writedata_21 (), // (terminated)
+ .pcs_write_21 (), // (terminated)
+ .pcs_waitrequest_21 (1'b0), // (terminated)
+ .mac_address_22 (), // (terminated)
+ .mac_readdata_22 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_22 (), // (terminated)
+ .mac_writedata_22 (), // (terminated)
+ .mac_write_22 (), // (terminated)
+ .mac_waitrequest_22 (1'b0), // (terminated)
+ .pcs_address_22 (), // (terminated)
+ .pcs_readdata_22 (16'b0000000000000000), // (terminated)
+ .pcs_read_22 (), // (terminated)
+ .pcs_writedata_22 (), // (terminated)
+ .pcs_write_22 (), // (terminated)
+ .pcs_waitrequest_22 (1'b0), // (terminated)
+ .mac_address_23 (), // (terminated)
+ .mac_readdata_23 (32'b00000000000000000000000000000000), // (terminated)
+ .mac_read_23 (), // (terminated)
+ .mac_writedata_23 (), // (terminated)
+ .mac_write_23 (), // (terminated)
+ .mac_waitrequest_23 (1'b0), // (terminated)
+ .pcs_address_23 (), // (terminated)
+ .pcs_readdata_23 (16'b0000000000000000), // (terminated)
+ .pcs_read_23 (), // (terminated)
+ .pcs_writedata_23 (), // (terminated)
+ .pcs_write_23 (), // (terminated)
+ .pcs_waitrequest_23 (1'b0) // (terminated)
+ );
+
+ altera_eth_tse_pcs_pma_nf_phyip #(
+ .ENABLE_TIMESTAMPING (0),
+ .DEV_VERSION (5633),
+ .ENABLE_ECC (0),
+ .DEVICE_FAMILY ("ARRIA10"),
+ .SYNCHRONIZER_DEPTH (3),
+ .ENABLE_CLK_SHARING (0),
+ .ENABLE_SGMII (1),
+ .PHY_IDENTIFIER (0)
+ ) i_tse_pcs_0 (
+ .clk (clk), // control_port_clock_connection.clk
+ .reset (reset), // reset_connection.reset
+ .reg_addr (avalon_arbiter_av_pcs_master_0_address), // control_port.address
+ .reg_data_out (avalon_arbiter_av_pcs_master_0_readdata), // .readdata
+ .reg_rd (avalon_arbiter_av_pcs_master_0_read), // .read
+ .reg_data_in (avalon_arbiter_av_pcs_master_0_writedata), // .writedata
+ .reg_wr (avalon_arbiter_av_pcs_master_0_write), // .write
+ .reg_busy (avalon_arbiter_av_pcs_master_0_waitrequest), // .waitrequest
+ .ref_clk (ref_clk), // pcs_ref_clk_clock_connection.clk
+ .rx_pcs_clk (i_nf_native_phyip_terminator_0_rx_pcs_clk_rx_pcs_clk), // rx_pcs_clk.rx_pcs_clk
+ .sd_loopback (i_tse_pcs_0_sd_loopback_sd_loopback), // sd_loopback.sd_loopback
+ .rx_disp_err (i_nf_native_phyip_0_rx_disperr_rx_disperr), // rx_disp_err.rx_disperr
+ .tx_pcs_clk (i_nf_native_phyip_terminator_0_tx_pcs_clk_tx_pcs_clk), // tx_pcs_clk.tx_pcs_clk
+ .rx_runningdisp (i_nf_native_phyip_0_rx_runningdisp_rx_runningdisp), // rx_runningdisp.rx_runningdisp
+ .rx_frame (i_nf_native_phyip_0_rx_parallel_data_rx_parallel_data), // rx_frame.rx_parallel_data
+ .rx_runlengthviolation (i_nf_native_phyip_terminator_0_rx_runlengthviolation_rx_runlengthviolation), // rx_runlengthviolation.rx_runlengthviolation
+ .rx_char_err_gx (i_nf_native_phyip_0_rx_errdetect_rx_errdetect), // rx_char_err_gx.rx_errdetect
+ .tx_frame (i_tse_pcs_0_tx_frame_tx_parallel_data), // tx_frame.tx_parallel_data
+ .rx_patterndetect (i_nf_native_phyip_0_rx_patterndetect_rx_patterndetect), // rx_patterndetect.rx_patterndetect
+ .rx_kchar (i_nf_native_phyip_0_rx_datak_rx_datak), // rx_kchar.rx_datak
+ .rx_syncstatus (i_nf_native_phyip_0_rx_syncstatus_rx_syncstatus), // rx_syncstatus.rx_syncstatus
+ .tx_kchar (i_tse_pcs_0_tx_kchar_tx_datak), // tx_kchar.tx_datak
+ .tx_clkena (i_tse_pcs_0_clock_enable_connection_tx_clkena), // clock_enable_connection.tx_clkena
+ .rx_clkena (i_tse_pcs_0_clock_enable_connection_rx_clkena), // .rx_clkena
+ .gmii_rx_dv (i_tse_pcs_0_gmii_connection_gmii_rx_dv), // gmii_connection.gmii_rx_dv
+ .gmii_rx_d (i_tse_pcs_0_gmii_connection_gmii_rx_d), // .gmii_rx_d
+ .gmii_rx_err (i_tse_pcs_0_gmii_connection_gmii_rx_err), // .gmii_rx_err
+ .gmii_tx_en (i_tse_mac_mac_gmii_connection_gmii_tx_en), // .gmii_tx_en
+ .gmii_tx_d (i_tse_mac_mac_gmii_connection_gmii_tx_d), // .gmii_tx_d
+ .gmii_tx_err (i_tse_mac_mac_gmii_connection_gmii_tx_err), // .gmii_tx_err
+ .mii_rx_dv (i_tse_pcs_0_mii_connection_mii_rx_dv), // mii_connection.mii_rx_dv
+ .mii_rx_d (i_tse_pcs_0_mii_connection_mii_rx_d), // .mii_rx_d
+ .mii_rx_err (i_tse_pcs_0_mii_connection_mii_rx_err), // .mii_rx_err
+ .mii_tx_en (i_tse_mac_mac_mii_connection_mii_tx_en), // .mii_tx_en
+ .mii_tx_d (i_tse_mac_mac_mii_connection_mii_tx_d), // .mii_tx_d
+ .mii_tx_err (i_tse_mac_mac_mii_connection_mii_tx_err), // .mii_tx_err
+ .mii_col (i_tse_pcs_0_mii_connection_mii_col), // .mii_col
+ .mii_crs (i_tse_pcs_0_mii_connection_mii_crs), // .mii_crs
+ .set_10 (i_tse_pcs_0_sgmii_status_connection_set_10), // sgmii_status_connection.set_10
+ .set_1000 (i_tse_pcs_0_sgmii_status_connection_set_1000), // .set_1000
+ .tx_clk (i_tse_pcs_0_pcs_transmit_clock_connection_clk), // pcs_transmit_clock_connection.clk
+ .rx_clk (i_tse_pcs_0_pcs_receive_clock_connection_clk), // pcs_receive_clock_connection.clk
+ .reset_tx_clk (rst_controller_reset_out_reset), // pcs_transmit_reset_connection.reset
+ .reset_rx_clk (rst_controller_001_reset_out_reset), // pcs_receive_reset_connection.reset
+ .led_crs (led_crs), // status_led_connection.export
+ .led_link (led_link), // .export
+ .led_panel_link (led_panel_link), // .export
+ .led_col (led_col), // .export
+ .led_an (led_an), // .export
+ .led_char_err (led_char_err), // .export
+ .led_disp_err (led_disp_err), // .export
+ .wa_boundary (i_nf_native_phyip_0_rx_std_bitslipboundarysel_rx_std_bitslipboundarysel), // wa_boundary.rx_std_bitslipboundarysel
+ .rx_rmfifodatadeleted (1'b0), // (terminated)
+ .rx_rmfifodatainserted (1'b0), // (terminated)
+ .set_100 (), // (terminated)
+ .hd_ena (), // (terminated)
+ .pcs_phase_measure_clk (1'b0), // (terminated)
+ .rx_latency_adj (), // (terminated)
+ .tx_latency_adj (), // (terminated)
+ .tx_ptp_alignment (), // (terminated)
+ .pcs_eccstatus () // (terminated)
+ );
+
+ arria10_hps_altera_xcvr_native_a10_221_iq5an3y #(
+ .device_revision ("20nm4"),
+ .duplex_mode ("duplex"),
+ .channels (1),
+ .enable_calibration (1),
+ .enable_analog_resets (1),
+ .enable_reset_sequence (1),
+ .bonded_mode ("not_bonded"),
+ .pcs_bonding_master (0),
+ .plls (1),
+ .number_physical_bonding_clocks (1),
+ .cdr_refclk_cnt (1),
+ .enable_hip (0),
+ .hip_cal_en ("disable"),
+ .rcfg_enable (1),
+ .rcfg_shared (0),
+ .rcfg_jtag_enable (0),
+ .rcfg_separate_avmm_busy (0),
+ .adme_prot_mode ("gige_1588"),
+ .adme_data_rate ("1250000000"),
+ .enable_pcie_dfe_ip (0),
+ .sim_reduced_counters (0),
+ .disable_continuous_dfe (0),
+ .dbg_embedded_debug_enable (0),
+ .dbg_capability_reg_enable (0),
+ .dbg_user_identifier (0),
+ .dbg_stat_soft_logic_enable (0),
+ .dbg_ctrl_soft_logic_enable (0),
+ .dbg_prbs_soft_logic_enable (0),
+ .dbg_odi_soft_logic_enable (0),
+ .rcfg_emb_strm_enable (0),
+ .rcfg_profile_cnt (2),
+ .hssi_gen3_rx_pcs_block_sync ("bypass_block_sync"),
+ .hssi_gen3_rx_pcs_block_sync_sm ("disable_blk_sync_sm"),
+ .hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn ("disable"),
+ .hssi_gen3_rx_pcs_lpbk_force ("lpbk_frce_dis"),
+ .hssi_gen3_rx_pcs_mode ("disable_pcs"),
+ .hssi_gen3_rx_pcs_rate_match_fifo ("bypass_rm_fifo"),
+ .hssi_gen3_rx_pcs_rate_match_fifo_latency ("low_latency"),
+ .hssi_gen3_rx_pcs_reverse_lpbk ("rev_lpbk_dis"),
+ .hssi_gen3_rx_pcs_rx_b4gb_par_lpbk ("b4gb_par_lpbk_dis"),
+ .hssi_gen3_rx_pcs_rx_force_balign ("dis_force_balign"),
+ .hssi_gen3_rx_pcs_rx_ins_del_one_skip ("ins_del_one_skip_dis"),
+ .hssi_gen3_rx_pcs_rx_num_fixed_pat (0),
+ .hssi_gen3_rx_pcs_rx_test_out_sel ("rx_test_out0"),
+ .hssi_gen3_rx_pcs_sup_mode ("user_mode"),
+ .hssi_gen3_tx_pcs_mode ("disable_pcs"),
+ .hssi_gen3_tx_pcs_reverse_lpbk ("rev_lpbk_dis"),
+ .hssi_gen3_tx_pcs_sup_mode ("user_mode"),
+ .hssi_gen3_tx_pcs_tx_bitslip (0),
+ .hssi_gen3_tx_pcs_tx_gbox_byp ("bypass_gbox"),
+ .hssi_krfec_rx_pcs_blksync_cor_en ("detect"),
+ .hssi_krfec_rx_pcs_bypass_gb ("bypass_dis"),
+ .hssi_krfec_rx_pcs_clr_ctrl ("both_enabled"),
+ .hssi_krfec_rx_pcs_ctrl_bit_reverse ("ctrl_bit_reverse_en"),
+ .hssi_krfec_rx_pcs_data_bit_reverse ("data_bit_reverse_dis"),
+ .hssi_krfec_rx_pcs_dv_start ("with_blklock"),
+ .hssi_krfec_rx_pcs_err_mark_type ("err_mark_10g"),
+ .hssi_krfec_rx_pcs_error_marking_en ("err_mark_dis"),
+ .hssi_krfec_rx_pcs_low_latency_en ("disable"),
+ .hssi_krfec_rx_pcs_lpbk_mode ("lpbk_dis"),
+ .hssi_krfec_rx_pcs_parity_invalid_enum (8),
+ .hssi_krfec_rx_pcs_parity_valid_num (4),
+ .hssi_krfec_rx_pcs_pipeln_blksync ("enable"),
+ .hssi_krfec_rx_pcs_pipeln_descrm ("disable"),
+ .hssi_krfec_rx_pcs_pipeln_errcorrect ("disable"),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_ind ("enable"),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_lfsr ("disable"),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_loc ("disable"),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_pat ("disable"),
+ .hssi_krfec_rx_pcs_pipeln_gearbox ("enable"),
+ .hssi_krfec_rx_pcs_pipeln_syndrm ("enable"),
+ .hssi_krfec_rx_pcs_pipeln_trans_dec ("disable"),
+ .hssi_krfec_rx_pcs_prot_mode ("disable_mode"),
+ .hssi_krfec_rx_pcs_receive_order ("receive_lsb"),
+ .hssi_krfec_rx_pcs_rx_testbus_sel ("overall"),
+ .hssi_krfec_rx_pcs_signal_ok_en ("sig_ok_en"),
+ .hssi_krfec_rx_pcs_sup_mode ("user_mode"),
+ .hssi_krfec_tx_pcs_burst_err ("burst_err_dis"),
+ .hssi_krfec_tx_pcs_burst_err_len ("burst_err_len1"),
+ .hssi_krfec_tx_pcs_ctrl_bit_reverse ("ctrl_bit_reverse_en"),
+ .hssi_krfec_tx_pcs_data_bit_reverse ("data_bit_reverse_dis"),
+ .hssi_krfec_tx_pcs_enc_frame_query ("enc_query_dis"),
+ .hssi_krfec_tx_pcs_low_latency_en ("disable"),
+ .hssi_krfec_tx_pcs_pipeln_encoder ("enable"),
+ .hssi_krfec_tx_pcs_pipeln_scrambler ("enable"),
+ .hssi_krfec_tx_pcs_prot_mode ("disable_mode"),
+ .hssi_krfec_tx_pcs_sup_mode ("user_mode"),
+ .hssi_krfec_tx_pcs_transcode_err ("trans_err_dis"),
+ .hssi_krfec_tx_pcs_transmit_order ("transmit_lsb"),
+ .hssi_krfec_tx_pcs_tx_testbus_sel ("overall"),
+ .hssi_10g_rx_pcs_align_del ("align_del_dis"),
+ .hssi_10g_rx_pcs_ber_bit_err_total_cnt ("bit_err_total_cnt_10g"),
+ .hssi_10g_rx_pcs_ber_clken ("ber_clk_dis"),
+ .hssi_10g_rx_pcs_ber_xus_timer_window (19530),
+ .hssi_10g_rx_pcs_bitslip_mode ("bitslip_dis"),
+ .hssi_10g_rx_pcs_blksync_bitslip_type ("bitslip_comb"),
+ .hssi_10g_rx_pcs_blksync_bitslip_wait_cnt (1),
+ .hssi_10g_rx_pcs_blksync_bitslip_wait_type ("bitslip_cnt"),
+ .hssi_10g_rx_pcs_blksync_bypass ("blksync_bypass_en"),
+ .hssi_10g_rx_pcs_blksync_clken ("blksync_clk_dis"),
+ .hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt ("enum_invalid_sh_cnt_10g"),
+ .hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock ("knum_sh_cnt_postlock_10g"),
+ .hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock ("knum_sh_cnt_prelock_10g"),
+ .hssi_10g_rx_pcs_blksync_pipeln ("blksync_pipeln_dis"),
+ .hssi_10g_rx_pcs_clr_errblk_cnt_en ("disable"),
+ .hssi_10g_rx_pcs_control_del ("control_del_none"),
+ .hssi_10g_rx_pcs_crcchk_bypass ("crcchk_bypass_en"),
+ .hssi_10g_rx_pcs_crcchk_clken ("crcchk_clk_dis"),
+ .hssi_10g_rx_pcs_crcchk_inv ("crcchk_inv_en"),
+ .hssi_10g_rx_pcs_crcchk_pipeln ("crcchk_pipeln_en"),
+ .hssi_10g_rx_pcs_crcflag_pipeln ("crcflag_pipeln_en"),
+ .hssi_10g_rx_pcs_ctrl_bit_reverse ("ctrl_bit_reverse_dis"),
+ .hssi_10g_rx_pcs_data_bit_reverse ("data_bit_reverse_dis"),
+ .hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass ("dec_64b66b_rxsm_bypass_en"),
+ .hssi_10g_rx_pcs_dec64b66b_clken ("dec64b66b_clk_dis"),
+ .hssi_10g_rx_pcs_descrm_bypass ("descrm_bypass_en"),
+ .hssi_10g_rx_pcs_descrm_clken ("descrm_clk_dis"),
+ .hssi_10g_rx_pcs_descrm_mode ("async"),
+ .hssi_10g_rx_pcs_descrm_pipeln ("enable"),
+ .hssi_10g_rx_pcs_dft_clk_out_sel ("rx_master_clk"),
+ .hssi_10g_rx_pcs_dis_signal_ok ("dis_signal_ok_en"),
+ .hssi_10g_rx_pcs_dispchk_bypass ("dispchk_bypass_en"),
+ .hssi_10g_rx_pcs_empty_flag_type ("empty_rd_side"),
+ .hssi_10g_rx_pcs_fast_path ("fast_path_en"),
+ .hssi_10g_rx_pcs_fec_clken ("fec_clk_dis"),
+ .hssi_10g_rx_pcs_fec_enable ("fec_dis"),
+ .hssi_10g_rx_pcs_fifo_double_read ("fifo_double_read_dis"),
+ .hssi_10g_rx_pcs_fifo_stop_rd ("n_rd_empty"),
+ .hssi_10g_rx_pcs_fifo_stop_wr ("n_wr_full"),
+ .hssi_10g_rx_pcs_force_align ("force_align_dis"),
+ .hssi_10g_rx_pcs_frmsync_bypass ("frmsync_bypass_en"),
+ .hssi_10g_rx_pcs_frmsync_clken ("frmsync_clk_dis"),
+ .hssi_10g_rx_pcs_frmsync_enum_scrm ("enum_scrm_default"),
+ .hssi_10g_rx_pcs_frmsync_enum_sync ("enum_sync_default"),
+ .hssi_10g_rx_pcs_frmsync_flag_type ("location_only"),
+ .hssi_10g_rx_pcs_frmsync_knum_sync ("knum_sync_default"),
+ .hssi_10g_rx_pcs_frmsync_mfrm_length (2048),
+ .hssi_10g_rx_pcs_frmsync_pipeln ("frmsync_pipeln_en"),
+ .hssi_10g_rx_pcs_full_flag_type ("full_wr_side"),
+ .hssi_10g_rx_pcs_gb_rx_idwidth ("width_64"),
+ .hssi_10g_rx_pcs_gb_rx_odwidth ("width_64"),
+ .hssi_10g_rx_pcs_gbexp_clken ("gbexp_clk_dis"),
+ .hssi_10g_rx_pcs_low_latency_en ("disable"),
+ .hssi_10g_rx_pcs_lpbk_mode ("lpbk_dis"),
+ .hssi_10g_rx_pcs_master_clk_sel ("master_rx_pma_clk"),
+ .hssi_10g_rx_pcs_pempty_flag_type ("pempty_rd_side"),
+ .hssi_10g_rx_pcs_pfull_flag_type ("pfull_wr_side"),
+ .hssi_10g_rx_pcs_phcomp_rd_del ("phcomp_rd_del2"),
+ .hssi_10g_rx_pcs_pld_if_type ("fifo"),
+ .hssi_10g_rx_pcs_prot_mode ("disable_mode"),
+ .hssi_10g_rx_pcs_rand_clken ("rand_clk_dis"),
+ .hssi_10g_rx_pcs_rd_clk_sel ("rd_rx_pld_clk"),
+ .hssi_10g_rx_pcs_rdfifo_clken ("rdfifo_clk_dis"),
+ .hssi_10g_rx_pcs_rx_fifo_write_ctrl ("blklock_stops"),
+ .hssi_10g_rx_pcs_rx_scrm_width ("bit64"),
+ .hssi_10g_rx_pcs_rx_sh_location ("msb"),
+ .hssi_10g_rx_pcs_rx_signal_ok_sel ("synchronized_ver"),
+ .hssi_10g_rx_pcs_rx_sm_bypass ("rx_sm_bypass_en"),
+ .hssi_10g_rx_pcs_rx_sm_hiber ("rx_sm_hiber_en"),
+ .hssi_10g_rx_pcs_rx_sm_pipeln ("rx_sm_pipeln_en"),
+ .hssi_10g_rx_pcs_rx_testbus_sel ("rx_fifo_testbus1"),
+ .hssi_10g_rx_pcs_rx_true_b2b ("b2b"),
+ .hssi_10g_rx_pcs_rxfifo_empty ("empty_default"),
+ .hssi_10g_rx_pcs_rxfifo_full ("full_default"),
+ .hssi_10g_rx_pcs_rxfifo_mode ("phase_comp"),
+ .hssi_10g_rx_pcs_rxfifo_pempty (2),
+ .hssi_10g_rx_pcs_rxfifo_pfull (23),
+ .hssi_10g_rx_pcs_stretch_num_stages ("zero_stage"),
+ .hssi_10g_rx_pcs_sup_mode ("user_mode"),
+ .hssi_10g_rx_pcs_test_mode ("test_off"),
+ .hssi_10g_rx_pcs_wrfifo_clken ("wrfifo_clk_dis"),
+ .hssi_10g_rx_pcs_advanced_user_mode ("disable"),
+ .hssi_10g_tx_pcs_bitslip_en ("bitslip_dis"),
+ .hssi_10g_tx_pcs_bonding_dft_en ("dft_dis"),
+ .hssi_10g_tx_pcs_bonding_dft_val ("dft_0"),
+ .hssi_10g_tx_pcs_crcgen_bypass ("crcgen_bypass_en"),
+ .hssi_10g_tx_pcs_crcgen_clken ("crcgen_clk_dis"),
+ .hssi_10g_tx_pcs_crcgen_err ("crcgen_err_dis"),
+ .hssi_10g_tx_pcs_crcgen_inv ("crcgen_inv_en"),
+ .hssi_10g_tx_pcs_ctrl_bit_reverse ("ctrl_bit_reverse_dis"),
+ .hssi_10g_tx_pcs_data_bit_reverse ("data_bit_reverse_dis"),
+ .hssi_10g_tx_pcs_dft_clk_out_sel ("tx_master_clk"),
+ .hssi_10g_tx_pcs_dispgen_bypass ("dispgen_bypass_en"),
+ .hssi_10g_tx_pcs_dispgen_clken ("dispgen_clk_dis"),
+ .hssi_10g_tx_pcs_dispgen_err ("dispgen_err_dis"),
+ .hssi_10g_tx_pcs_dispgen_pipeln ("dispgen_pipeln_dis"),
+ .hssi_10g_tx_pcs_empty_flag_type ("empty_rd_side"),
+ .hssi_10g_tx_pcs_enc_64b66b_txsm_bypass ("enc_64b66b_txsm_bypass_en"),
+ .hssi_10g_tx_pcs_enc64b66b_txsm_clken ("enc64b66b_txsm_clk_dis"),
+ .hssi_10g_tx_pcs_fastpath ("fastpath_en"),
+ .hssi_10g_tx_pcs_fec_clken ("fec_clk_dis"),
+ .hssi_10g_tx_pcs_fec_enable ("fec_dis"),
+ .hssi_10g_tx_pcs_fifo_double_write ("fifo_double_write_dis"),
+ .hssi_10g_tx_pcs_fifo_reg_fast ("fifo_reg_fast_dis"),
+ .hssi_10g_tx_pcs_fifo_stop_rd ("rd_empty"),
+ .hssi_10g_tx_pcs_fifo_stop_wr ("n_wr_full"),
+ .hssi_10g_tx_pcs_frmgen_burst ("frmgen_burst_dis"),
+ .hssi_10g_tx_pcs_frmgen_bypass ("frmgen_bypass_en"),
+ .hssi_10g_tx_pcs_frmgen_clken ("frmgen_clk_dis"),
+ .hssi_10g_tx_pcs_frmgen_mfrm_length (2048),
+ .hssi_10g_tx_pcs_frmgen_pipeln ("frmgen_pipeln_en"),
+ .hssi_10g_tx_pcs_frmgen_pyld_ins ("frmgen_pyld_ins_dis"),
+ .hssi_10g_tx_pcs_frmgen_wordslip ("frmgen_wordslip_dis"),
+ .hssi_10g_tx_pcs_full_flag_type ("full_wr_side"),
+ .hssi_10g_tx_pcs_gb_pipeln_bypass ("disable"),
+ .hssi_10g_tx_pcs_gb_tx_idwidth ("width_64"),
+ .hssi_10g_tx_pcs_gb_tx_odwidth ("width_64"),
+ .hssi_10g_tx_pcs_gbred_clken ("gbred_clk_dis"),
+ .hssi_10g_tx_pcs_low_latency_en ("disable"),
+ .hssi_10g_tx_pcs_master_clk_sel ("master_tx_pma_clk"),
+ .hssi_10g_tx_pcs_pempty_flag_type ("pempty_rd_side"),
+ .hssi_10g_tx_pcs_pfull_flag_type ("pfull_wr_side"),
+ .hssi_10g_tx_pcs_phcomp_rd_del ("phcomp_rd_del2"),
+ .hssi_10g_tx_pcs_pld_if_type ("fifo"),
+ .hssi_10g_tx_pcs_prot_mode ("disable_mode"),
+ .hssi_10g_tx_pcs_pseudo_random ("all_0"),
+ .hssi_10g_tx_pcs_pseudo_seed_a ("288230376151711743"),
+ .hssi_10g_tx_pcs_pseudo_seed_b ("288230376151711743"),
+ .hssi_10g_tx_pcs_random_disp ("disable"),
+ .hssi_10g_tx_pcs_rdfifo_clken ("rdfifo_clk_dis"),
+ .hssi_10g_tx_pcs_scrm_bypass ("scrm_bypass_en"),
+ .hssi_10g_tx_pcs_scrm_clken ("scrm_clk_dis"),
+ .hssi_10g_tx_pcs_scrm_mode ("async"),
+ .hssi_10g_tx_pcs_scrm_pipeln ("enable"),
+ .hssi_10g_tx_pcs_sh_err ("sh_err_dis"),
+ .hssi_10g_tx_pcs_sop_mark ("sop_mark_dis"),
+ .hssi_10g_tx_pcs_stretch_num_stages ("zero_stage"),
+ .hssi_10g_tx_pcs_sup_mode ("user_mode"),
+ .hssi_10g_tx_pcs_test_mode ("test_off"),
+ .hssi_10g_tx_pcs_tx_scrm_err ("scrm_err_dis"),
+ .hssi_10g_tx_pcs_tx_scrm_width ("bit64"),
+ .hssi_10g_tx_pcs_tx_sh_location ("msb"),
+ .hssi_10g_tx_pcs_tx_sm_bypass ("tx_sm_bypass_en"),
+ .hssi_10g_tx_pcs_tx_sm_pipeln ("tx_sm_pipeln_en"),
+ .hssi_10g_tx_pcs_tx_testbus_sel ("tx_fifo_testbus1"),
+ .hssi_10g_tx_pcs_txfifo_empty ("empty_default"),
+ .hssi_10g_tx_pcs_txfifo_full ("full_default"),
+ .hssi_10g_tx_pcs_txfifo_mode ("phase_comp"),
+ .hssi_10g_tx_pcs_txfifo_pempty (2),
+ .hssi_10g_tx_pcs_txfifo_pfull (11),
+ .hssi_10g_tx_pcs_wr_clk_sel ("wr_tx_pld_clk"),
+ .hssi_10g_tx_pcs_wrfifo_clken ("wrfifo_clk_dis"),
+ .hssi_10g_tx_pcs_advanced_user_mode ("disable"),
+ .hssi_8g_rx_pcs_auto_error_replacement ("dis_err_replace"),
+ .hssi_8g_rx_pcs_bit_reversal ("dis_bit_reversal"),
+ .hssi_8g_rx_pcs_bonding_dft_en ("dft_dis"),
+ .hssi_8g_rx_pcs_bonding_dft_val ("dft_0"),
+ .hssi_8g_rx_pcs_bypass_pipeline_reg ("dis_bypass_pipeline"),
+ .hssi_8g_rx_pcs_byte_deserializer ("dis_bds"),
+ .hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask ("dis_rxvalid_mask"),
+ .hssi_8g_rx_pcs_clkcmp_pattern_n (0),
+ .hssi_8g_rx_pcs_clkcmp_pattern_p (0),
+ .hssi_8g_rx_pcs_clock_gate_bds_dec_asn ("dis_bds_dec_asn_clk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_cdr_eidle ("en_cdr_eidle_clk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk ("en_dw_pc_wrclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_dw_rm_rd ("en_dw_rm_rdclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_dw_rm_wr ("en_dw_rm_wrclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_dw_wa ("en_dw_wa_clk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_pc_rdclk ("dis_pc_rdclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk ("dis_sw_pc_wrclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_sw_rm_rd ("en_sw_rm_rdclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_sw_rm_wr ("en_sw_rm_wrclk_gating"),
+ .hssi_8g_rx_pcs_clock_gate_sw_wa ("dis_sw_wa_clk_gating"),
+ .hssi_8g_rx_pcs_clock_observation_in_pld_core ("internal_sw_wa_clk"),
+ .hssi_8g_rx_pcs_eidle_entry_eios ("dis_eidle_eios"),
+ .hssi_8g_rx_pcs_eidle_entry_iei ("dis_eidle_iei"),
+ .hssi_8g_rx_pcs_eidle_entry_sd ("dis_eidle_sd"),
+ .hssi_8g_rx_pcs_eightb_tenb_decoder ("en_8b10b_ibm"),
+ .hssi_8g_rx_pcs_err_flags_sel ("err_flags_wa"),
+ .hssi_8g_rx_pcs_fixed_pat_det ("dis_fixed_patdet"),
+ .hssi_8g_rx_pcs_fixed_pat_num (0),
+ .hssi_8g_rx_pcs_force_signal_detect ("en_force_signal_detect"),
+ .hssi_8g_rx_pcs_gen3_clk_en ("disable_clk"),
+ .hssi_8g_rx_pcs_gen3_rx_clk_sel ("rcvd_clk"),
+ .hssi_8g_rx_pcs_gen3_tx_clk_sel ("tx_pma_clk"),
+ .hssi_8g_rx_pcs_hip_mode ("dis_hip"),
+ .hssi_8g_rx_pcs_ibm_invalid_code ("dis_ibm_invalid_code"),
+ .hssi_8g_rx_pcs_invalid_code_flag_only ("dis_invalid_code_only"),
+ .hssi_8g_rx_pcs_pad_or_edb_error_replace ("replace_edb"),
+ .hssi_8g_rx_pcs_pcs_bypass ("dis_pcs_bypass"),
+ .hssi_8g_rx_pcs_phase_comp_rdptr ("disable_rdptr"),
+ .hssi_8g_rx_pcs_phase_compensation_fifo ("register_fifo"),
+ .hssi_8g_rx_pcs_pipe_if_enable ("dis_pipe_rx"),
+ .hssi_8g_rx_pcs_pma_dw ("ten_bit"),
+ .hssi_8g_rx_pcs_polinv_8b10b_dec ("dis_polinv_8b10b_dec"),
+ .hssi_8g_rx_pcs_prot_mode ("gige_1588"),
+ .hssi_8g_rx_pcs_rate_match ("dis_rm"),
+ .hssi_8g_rx_pcs_rate_match_del_thres ("dis_rm_del_thres"),
+ .hssi_8g_rx_pcs_rate_match_empty_thres ("dis_rm_empty_thres"),
+ .hssi_8g_rx_pcs_rate_match_full_thres ("dis_rm_full_thres"),
+ .hssi_8g_rx_pcs_rate_match_ins_thres ("dis_rm_ins_thres"),
+ .hssi_8g_rx_pcs_rate_match_start_thres ("dis_rm_start_thres"),
+ .hssi_8g_rx_pcs_rx_clk_free_running ("en_rx_clk_free_run"),
+ .hssi_8g_rx_pcs_rx_clk2 ("rcvd_clk_clk2"),
+ .hssi_8g_rx_pcs_rx_pcs_urst ("en_rx_pcs_urst"),
+ .hssi_8g_rx_pcs_rx_rcvd_clk ("rcvd_clk_rcvd_clk"),
+ .hssi_8g_rx_pcs_rx_rd_clk ("rx_clk"),
+ .hssi_8g_rx_pcs_rx_refclk ("dis_refclk_sel"),
+ .hssi_8g_rx_pcs_rx_wr_clk ("rx_clk2_div_1_2_4"),
+ .hssi_8g_rx_pcs_sup_mode ("user_mode"),
+ .hssi_8g_rx_pcs_symbol_swap ("dis_symbol_swap"),
+ .hssi_8g_rx_pcs_sync_sm_idle_eios ("dis_syncsm_idle"),
+ .hssi_8g_rx_pcs_test_bus_sel ("tx_testbus"),
+ .hssi_8g_rx_pcs_tx_rx_parallel_loopback ("dis_plpbk"),
+ .hssi_8g_rx_pcs_wa_boundary_lock_ctrl ("sync_sm"),
+ .hssi_8g_rx_pcs_wa_clk_slip_spacing (16),
+ .hssi_8g_rx_pcs_wa_det_latency_sync_status_beh ("dont_care_assert_sync"),
+ .hssi_8g_rx_pcs_wa_disp_err_flag ("en_disp_err_flag"),
+ .hssi_8g_rx_pcs_wa_kchar ("dis_kchar"),
+ .hssi_8g_rx_pcs_wa_pd ("wa_pd_7"),
+ .hssi_8g_rx_pcs_wa_pd_data ("124"),
+ .hssi_8g_rx_pcs_wa_pd_polarity ("dont_care_both_pol"),
+ .hssi_8g_rx_pcs_wa_pld_controlled ("dis_pld_ctrl"),
+ .hssi_8g_rx_pcs_wa_renumber_data (3),
+ .hssi_8g_rx_pcs_wa_rgnumber_data (3),
+ .hssi_8g_rx_pcs_wa_rknumber_data (3),
+ .hssi_8g_rx_pcs_wa_rosnumber_data (1),
+ .hssi_8g_rx_pcs_wa_rvnumber_data (0),
+ .hssi_8g_rx_pcs_wa_sync_sm_ctrl ("gige_sync_sm"),
+ .hssi_8g_rx_pcs_wait_cnt (0),
+ .hssi_8g_tx_pcs_bit_reversal ("dis_bit_reversal"),
+ .hssi_8g_tx_pcs_bonding_dft_en ("dft_dis"),
+ .hssi_8g_tx_pcs_bonding_dft_val ("dft_0"),
+ .hssi_8g_tx_pcs_bypass_pipeline_reg ("dis_bypass_pipeline"),
+ .hssi_8g_tx_pcs_byte_serializer ("dis_bs"),
+ .hssi_8g_tx_pcs_clock_gate_bs_enc ("dis_bs_enc_clk_gating"),
+ .hssi_8g_tx_pcs_clock_gate_dw_fifowr ("en_dw_fifowr_clk_gating"),
+ .hssi_8g_tx_pcs_clock_gate_fiford ("dis_fiford_clk_gating"),
+ .hssi_8g_tx_pcs_clock_gate_sw_fifowr ("en_sw_fifowr_clk_gating"),
+ .hssi_8g_tx_pcs_clock_observation_in_pld_core ("internal_refclk_b"),
+ .hssi_8g_tx_pcs_data_selection_8b10b_encoder_input ("gige_idle_conversion"),
+ .hssi_8g_tx_pcs_dynamic_clk_switch ("dis_dyn_clk_switch"),
+ .hssi_8g_tx_pcs_eightb_tenb_disp_ctrl ("dis_disp_ctrl"),
+ .hssi_8g_tx_pcs_eightb_tenb_encoder ("en_8b10b_ibm"),
+ .hssi_8g_tx_pcs_force_echar ("dis_force_echar"),
+ .hssi_8g_tx_pcs_force_kchar ("dis_force_kchar"),
+ .hssi_8g_tx_pcs_gen3_tx_clk_sel ("dis_tx_clk"),
+ .hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel ("dis_tx_pipe_clk"),
+ .hssi_8g_tx_pcs_hip_mode ("dis_hip"),
+ .hssi_8g_tx_pcs_pcs_bypass ("dis_pcs_bypass"),
+ .hssi_8g_tx_pcs_phase_comp_rdptr ("disable_rdptr"),
+ .hssi_8g_tx_pcs_phase_compensation_fifo ("register_fifo"),
+ .hssi_8g_tx_pcs_phfifo_write_clk_sel ("tx_clk"),
+ .hssi_8g_tx_pcs_pma_dw ("ten_bit"),
+ .hssi_8g_tx_pcs_prot_mode ("gige_1588"),
+ .hssi_8g_tx_pcs_refclk_b_clk_sel ("tx_pma_clock"),
+ .hssi_8g_tx_pcs_revloop_back_rm ("dis_rev_loopback_rx_rm"),
+ .hssi_8g_tx_pcs_sup_mode ("user_mode"),
+ .hssi_8g_tx_pcs_symbol_swap ("dis_symbol_swap"),
+ .hssi_8g_tx_pcs_tx_bitslip ("dis_tx_bitslip"),
+ .hssi_8g_tx_pcs_tx_compliance_controlled_disparity ("dis_txcompliance"),
+ .hssi_8g_tx_pcs_tx_fast_pld_reg ("dis_tx_fast_pld_reg"),
+ .hssi_8g_tx_pcs_txclk_freerun ("en_freerun_tx"),
+ .hssi_8g_tx_pcs_txpcs_urst ("en_txpcs_urst"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_hip_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_hrdrstctl_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx ("gige_1588_tx"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx ("individual_tx"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pma_dw_tx ("pma_10b_tx"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_fifo_mode_tx ("reg_tx"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_shared_fifo_width_tx ("single_tx"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_low_latency_en_tx ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_func_mode ("enable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_lpbk_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_frequency_rules_en ("enable"),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pma_tx_clk_hz (125000000),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_tx_clk_hz (0),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_uhsif_tx_clk_hz (0),
+ .hssi_tx_pld_pcs_interface_hd_fifo_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_fifo_prot_mode_tx ("non_teng_mode_tx"),
+ .hssi_tx_pld_pcs_interface_hd_fifo_shared_fifo_width_tx ("single_tx"),
+ .hssi_tx_pld_pcs_interface_hd_10g_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_10g_lpbk_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_10g_advanced_user_mode_tx ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_10g_pma_dw_tx ("pma_64b_tx"),
+ .hssi_tx_pld_pcs_interface_hd_10g_fifo_mode_tx ("fifo_tx"),
+ .hssi_tx_pld_pcs_interface_hd_10g_prot_mode_tx ("disabled_prot_mode_tx"),
+ .hssi_tx_pld_pcs_interface_hd_10g_low_latency_en_tx ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_10g_shared_fifo_width_tx ("single_tx"),
+ .hssi_tx_pld_pcs_interface_hd_8g_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_8g_lpbk_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx ("gige_1588_tx"),
+ .hssi_tx_pld_pcs_interface_hd_8g_hip_mode ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_8g_pma_dw_tx ("pma_10b_tx"),
+ .hssi_tx_pld_pcs_interface_hd_8g_fifo_mode_tx ("reg_tx"),
+ .hssi_tx_pld_pcs_interface_hd_g3_prot_mode ("disabled_prot_mode"),
+ .hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx ("disabled_prot_mode_tx"),
+ .hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_lpbk_en ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_sim_mode ("disable"),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_prot_mode_tx ("eightg_only_pld_mode_tx"),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_pma_dw_tx ("pma_10b_tx"),
+ .hssi_tx_pld_pcs_interface_hd_pldif_prot_mode_tx ("eightg_and_g3_reg_mode_tx"),
+ .hssi_tx_pld_pcs_interface_hd_pldif_hrdrstctl_en ("disable"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_clk_source ("eightg"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_data_source ("hip_disable"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en ("delay1_clk_disable"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel ("pcs_tx_clk"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl ("delay1_path0"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel ("one_ff_delay"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en ("delay2_clk_disable"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl ("delay2_path0"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_output_sel ("teng_output"),
+ .hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel ("eightg_clk_out"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_hip_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_transparent_pcs_rx ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_hrdrstctl_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_prot_mode_rx ("gige_1588_rx"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx ("individual_rx"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pma_dw_rx ("pma_10b_rx"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pld_fifo_mode_rx ("reg_rx"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_shared_fifo_width_rx ("single_rx"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_low_latency_en_rx ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_func_mode ("enable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_lpbk_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_10g_advanced_user_mode_rx ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_frequency_rules_en ("enable"),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pma_rx_clk_hz (125000000),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pld_rx_clk_hz (0),
+ .hssi_rx_pld_pcs_interface_hd_chnl_fref_clk_hz (125000000),
+ .hssi_rx_pld_pcs_interface_hd_chnl_clklow_clk_hz (125000000),
+ .hssi_rx_pld_pcs_interface_hd_fifo_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_fifo_prot_mode_rx ("non_teng_mode_rx"),
+ .hssi_rx_pld_pcs_interface_hd_fifo_shared_fifo_width_rx ("single_rx"),
+ .hssi_rx_pld_pcs_interface_hd_10g_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_10g_lpbk_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_10g_pma_dw_rx ("pma_64b_rx"),
+ .hssi_rx_pld_pcs_interface_hd_10g_fifo_mode_rx ("fifo_rx"),
+ .hssi_rx_pld_pcs_interface_hd_10g_prot_mode_rx ("disabled_prot_mode_rx"),
+ .hssi_rx_pld_pcs_interface_hd_10g_low_latency_en_rx ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_10g_shared_fifo_width_rx ("single_rx"),
+ .hssi_rx_pld_pcs_interface_hd_10g_test_bus_mode ("rx"),
+ .hssi_rx_pld_pcs_interface_hd_8g_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_8g_lpbk_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_8g_prot_mode_rx ("gige_1588_rx"),
+ .hssi_rx_pld_pcs_interface_hd_8g_hip_mode ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_8g_pma_dw_rx ("pma_10b_rx"),
+ .hssi_rx_pld_pcs_interface_hd_8g_fifo_mode_rx ("reg_rx"),
+ .hssi_rx_pld_pcs_interface_hd_g3_prot_mode ("disabled_prot_mode"),
+ .hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx ("disabled_prot_mode_rx"),
+ .hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode ("tx"),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_lpbk_en ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_sim_mode ("disable"),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_prot_mode_rx ("eightg_only_pld_mode_rx"),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_pma_dw_rx ("pma_10b_rx"),
+ .hssi_rx_pld_pcs_interface_hd_pldif_prot_mode_rx ("eightg_and_g3_reg_mode_rx"),
+ .hssi_rx_pld_pcs_interface_hd_pldif_hrdrstctl_en ("disable"),
+ .hssi_rx_pld_pcs_interface_pcs_rx_block_sel ("eightg"),
+ .hssi_rx_pld_pcs_interface_pcs_rx_clk_sel ("pcs_rx_clk"),
+ .hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en ("hip_rx_disable"),
+ .hssi_rx_pld_pcs_interface_pcs_rx_output_sel ("teng_output"),
+ .hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel ("eightg_clk_out"),
+ .hssi_common_pld_pcs_interface_dft_clk_out_en ("dft_clk_out_disable"),
+ .hssi_common_pld_pcs_interface_dft_clk_out_sel ("teng_rx_dft_clk"),
+ .hssi_common_pld_pcs_interface_hrdrstctrl_en ("hrst_dis"),
+ .hssi_common_pld_pcs_interface_pcs_testbus_block_sel ("pma_if"),
+ .hssi_rx_pcs_pma_interface_block_sel ("eight_g_pcs"),
+ .hssi_rx_pcs_pma_interface_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_rx_pcs_pma_interface_clkslip_sel ("pld"),
+ .hssi_rx_pcs_pma_interface_lpbk_en ("disable"),
+ .hssi_rx_pcs_pma_interface_master_clk_sel ("master_rx_pma_clk"),
+ .hssi_rx_pcs_pma_interface_pldif_datawidth_mode ("pldif_data_10bit"),
+ .hssi_rx_pcs_pma_interface_pma_dw_rx ("pma_10b_rx"),
+ .hssi_rx_pcs_pma_interface_pma_if_dft_en ("dft_dis"),
+ .hssi_rx_pcs_pma_interface_pma_if_dft_val ("dft_0"),
+ .hssi_rx_pcs_pma_interface_prbs_clken ("prbs_clk_dis"),
+ .hssi_rx_pcs_pma_interface_prbs_ver ("prbs_off"),
+ .hssi_rx_pcs_pma_interface_prbs9_dwidth ("prbs9_64b"),
+ .hssi_rx_pcs_pma_interface_prot_mode_rx ("eightg_only_pld_mode_rx"),
+ .hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion ("rx_dyn_polinv_dis"),
+ .hssi_rx_pcs_pma_interface_rx_lpbk_en ("lpbk_dis"),
+ .hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok ("force_sig_ok"),
+ .hssi_rx_pcs_pma_interface_rx_prbs_mask ("prbsmask128"),
+ .hssi_rx_pcs_pma_interface_rx_prbs_mode ("teng_mode"),
+ .hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel ("sel_sig_det"),
+ .hssi_rx_pcs_pma_interface_rx_static_polarity_inversion ("rx_stat_polinv_dis"),
+ .hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en ("uhsif_lpbk_dis"),
+ .hssi_rx_pcs_pma_interface_sup_mode ("user_mode"),
+ .hssi_tx_pcs_pma_interface_bypass_pma_txelecidle ("true"),
+ .hssi_tx_pcs_pma_interface_channel_operation_mode ("tx_rx_pair_enabled"),
+ .hssi_tx_pcs_pma_interface_lpbk_en ("disable"),
+ .hssi_tx_pcs_pma_interface_master_clk_sel ("master_tx_pma_clk"),
+ .hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx ("other_prot_mode"),
+ .hssi_tx_pcs_pma_interface_pldif_datawidth_mode ("pldif_data_10bit"),
+ .hssi_tx_pcs_pma_interface_pma_dw_tx ("pma_10b_tx"),
+ .hssi_tx_pcs_pma_interface_pma_if_dft_en ("dft_dis"),
+ .hssi_tx_pcs_pma_interface_pmagate_en ("pmagate_dis"),
+ .hssi_tx_pcs_pma_interface_prbs_clken ("prbs_clk_dis"),
+ .hssi_tx_pcs_pma_interface_prbs_gen_pat ("prbs_gen_dis"),
+ .hssi_tx_pcs_pma_interface_prbs9_dwidth ("prbs9_64b"),
+ .hssi_tx_pcs_pma_interface_prot_mode_tx ("eightg_only_pld_mode_tx"),
+ .hssi_tx_pcs_pma_interface_sq_wave_num ("sq_wave_default"),
+ .hssi_tx_pcs_pma_interface_sqwgen_clken ("sqwgen_clk_dis"),
+ .hssi_tx_pcs_pma_interface_sup_mode ("user_mode"),
+ .hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion ("tx_dyn_polinv_dis"),
+ .hssi_tx_pcs_pma_interface_tx_pma_data_sel ("eight_g_pcs"),
+ .hssi_tx_pcs_pma_interface_tx_static_polarity_inversion ("tx_stat_polinv_dis"),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock ("uhsif_filt_stepsz_b4lock_2"),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value (0),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock ("uhsif_filt_cntthr_b4lock_8"),
+ .hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period ("uhsif_dcn_test_period_4"),
+ .hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable ("uhsif_dcn_test_mode_disable"),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh ("uhsif_dzt_cnt_thr_2"),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable ("uhsif_dzt_disable"),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window ("uhsif_dzt_obr_win_16"),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size ("uhsif_dzt_skipsz_4"),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel ("uhsif_index_cram"),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin ("uhsif_dcn_margin_2"),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value (0),
+ .hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control ("uhsif_dft_dz_det_val_0"),
+ .hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control ("uhsif_dft_up_val_0"),
+ .hssi_tx_pcs_pma_interface_uhsif_enable ("uhsif_disable"),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock ("uhsif_lkd_segsz_aflock_512"),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock ("uhsif_lkd_segsz_b4lock_16"),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value (0),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value (0),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value (0),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value (0),
+ .hssi_common_pcs_pma_interface_asn_clk_enable ("false"),
+ .hssi_common_pcs_pma_interface_asn_enable ("dis_asn"),
+ .hssi_common_pcs_pma_interface_block_sel ("eight_g_pcs"),
+ .hssi_common_pcs_pma_interface_bypass_early_eios ("true"),
+ .hssi_common_pcs_pma_interface_bypass_pcie_switch ("true"),
+ .hssi_common_pcs_pma_interface_bypass_pma_ltr ("true"),
+ .hssi_common_pcs_pma_interface_bypass_pma_sw_done ("true"),
+ .hssi_common_pcs_pma_interface_bypass_ppm_lock ("false"),
+ .hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp ("true"),
+ .hssi_common_pcs_pma_interface_bypass_txdetectrx ("true"),
+ .hssi_common_pcs_pma_interface_cdr_control ("dis_cdr_ctrl"),
+ .hssi_common_pcs_pma_interface_cid_enable ("dis_cid_mode"),
+ .hssi_common_pcs_pma_interface_data_mask_count (0),
+ .hssi_common_pcs_pma_interface_data_mask_count_multi (0),
+ .hssi_common_pcs_pma_interface_dft_observation_clock_selection ("dft_clk_obsrv_tx0"),
+ .hssi_common_pcs_pma_interface_early_eios_counter (0),
+ .hssi_common_pcs_pma_interface_force_freqdet ("force_freqdet_dis"),
+ .hssi_common_pcs_pma_interface_free_run_clk_enable ("false"),
+ .hssi_common_pcs_pma_interface_ignore_sigdet_g23 ("false"),
+ .hssi_common_pcs_pma_interface_pc_en_counter (0),
+ .hssi_common_pcs_pma_interface_pc_rst_counter (0),
+ .hssi_common_pcs_pma_interface_pcie_hip_mode ("hip_disable"),
+ .hssi_common_pcs_pma_interface_ph_fifo_reg_mode ("phfifo_reg_mode_dis"),
+ .hssi_common_pcs_pma_interface_phfifo_flush_wait (0),
+ .hssi_common_pcs_pma_interface_pipe_if_g3pcs ("pipe_if_8gpcs"),
+ .hssi_common_pcs_pma_interface_pma_done_counter (0),
+ .hssi_common_pcs_pma_interface_pma_if_dft_en ("dft_dis"),
+ .hssi_common_pcs_pma_interface_pma_if_dft_val ("dft_0"),
+ .hssi_common_pcs_pma_interface_ppm_cnt_rst ("ppm_cnt_rst_dis"),
+ .hssi_common_pcs_pma_interface_ppm_deassert_early ("deassert_early_dis"),
+ .hssi_common_pcs_pma_interface_ppm_gen1_2_cnt ("cnt_32k"),
+ .hssi_common_pcs_pma_interface_ppm_post_eidle_delay ("cnt_200_cycles"),
+ .hssi_common_pcs_pma_interface_ppmsel ("ppmsel_100"),
+ .hssi_common_pcs_pma_interface_prot_mode ("other_protocols"),
+ .hssi_common_pcs_pma_interface_rxvalid_mask ("rxvalid_mask_dis"),
+ .hssi_common_pcs_pma_interface_sigdet_wait_counter (0),
+ .hssi_common_pcs_pma_interface_sigdet_wait_counter_multi (0),
+ .hssi_common_pcs_pma_interface_sim_mode ("disable"),
+ .hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en ("false"),
+ .hssi_common_pcs_pma_interface_sup_mode ("user_mode"),
+ .hssi_common_pcs_pma_interface_testout_sel ("asn_test"),
+ .hssi_common_pcs_pma_interface_wait_clk_on_off_timer (0),
+ .hssi_common_pcs_pma_interface_wait_pipe_synchronizing (0),
+ .hssi_common_pcs_pma_interface_wait_send_syncp_fbkp (0),
+ .hssi_common_pcs_pma_interface_ppm_det_buckets ("ppm_100_bucket"),
+ .hssi_fifo_rx_pcs_double_read_mode ("double_read_dis"),
+ .hssi_fifo_rx_pcs_prot_mode ("non_teng_mode"),
+ .hssi_fifo_tx_pcs_double_write_mode ("double_write_dis"),
+ .hssi_fifo_tx_pcs_prot_mode ("non_teng_mode"),
+ .hssi_pipe_gen3_bypass_rx_detection_enable ("false"),
+ .hssi_pipe_gen3_bypass_rx_preset (0),
+ .hssi_pipe_gen3_bypass_rx_preset_enable ("false"),
+ .hssi_pipe_gen3_bypass_tx_coefficent (0),
+ .hssi_pipe_gen3_bypass_tx_coefficent_enable ("false"),
+ .hssi_pipe_gen3_elecidle_delay_g3 (0),
+ .hssi_pipe_gen3_ind_error_reporting ("dis_ind_error_reporting"),
+ .hssi_pipe_gen3_mode ("disable_pcs"),
+ .hssi_pipe_gen3_phy_status_delay_g12 (0),
+ .hssi_pipe_gen3_phy_status_delay_g3 (0),
+ .hssi_pipe_gen3_phystatus_rst_toggle_g12 ("dis_phystatus_rst_toggle"),
+ .hssi_pipe_gen3_phystatus_rst_toggle_g3 ("dis_phystatus_rst_toggle_g3"),
+ .hssi_pipe_gen3_rate_match_pad_insertion ("dis_rm_fifo_pad_ins"),
+ .hssi_pipe_gen3_sup_mode ("user_mode"),
+ .hssi_pipe_gen3_test_out_sel ("disable_test_out"),
+ .hssi_pipe_gen1_2_elec_idle_delay_val (0),
+ .hssi_pipe_gen1_2_error_replace_pad ("replace_edb"),
+ .hssi_pipe_gen1_2_hip_mode ("dis_hip"),
+ .hssi_pipe_gen1_2_ind_error_reporting ("dis_ind_error_reporting"),
+ .hssi_pipe_gen1_2_phystatus_delay_val (0),
+ .hssi_pipe_gen1_2_phystatus_rst_toggle ("dis_phystatus_rst_toggle"),
+ .hssi_pipe_gen1_2_pipe_byte_de_serializer_en ("dont_care_bds"),
+ .hssi_pipe_gen1_2_prot_mode ("disabled_prot_mode"),
+ .hssi_pipe_gen1_2_rx_pipe_enable ("dis_pipe_rx"),
+ .hssi_pipe_gen1_2_rxdetect_bypass ("dis_rxdetect_bypass"),
+ .hssi_pipe_gen1_2_sup_mode ("user_mode"),
+ .hssi_pipe_gen1_2_tx_pipe_enable ("dis_pipe_tx"),
+ .hssi_pipe_gen1_2_txswing ("dis_txswing"),
+ .pma_adapt_adp_1s_ctle_bypass ("radp_1s_ctle_bypass_1"),
+ .pma_adapt_adp_4s_ctle_bypass ("radp_4s_ctle_bypass_1"),
+ .pma_adapt_adp_ctle_en ("radp_ctle_disable"),
+ .pma_adapt_adp_dfe_fltap_bypass ("radp_dfe_fltap_bypass_1"),
+ .pma_adapt_adp_dfe_fltap_en ("radp_dfe_fltap_disable"),
+ .pma_adapt_adp_dfe_fxtap_bypass ("radp_dfe_fxtap_bypass_1"),
+ .pma_adapt_adp_dfe_fxtap_en ("radp_dfe_fxtap_disable"),
+ .pma_adapt_adp_dfe_fxtap_hold_en ("radp_dfe_fxtap_not_held"),
+ .pma_adapt_adp_dfe_mode ("radp_dfe_mode_4"),
+ .pma_adapt_adp_vga_bypass ("radp_vga_bypass_1"),
+ .pma_adapt_adp_vga_en ("radp_vga_disable"),
+ .pma_adapt_adp_vref_bypass ("radp_vref_bypass_1"),
+ .pma_adapt_adp_vref_en ("radp_vref_disable"),
+ .pma_adapt_datarate ("1250000000 bps"),
+ .pma_adapt_prot_mode ("basic_rx"),
+ .pma_adapt_sup_mode ("user_mode"),
+ .pma_adapt_adp_ctle_adapt_cycle_window ("radp_ctle_adapt_cycle_window_7"),
+ .pma_adapt_odi_dfe_spec_en ("rodi_dfe_spec_en_0"),
+ .pma_adapt_adapt_mode ("manual"),
+ .pma_adapt_adp_onetime_dfe ("radp_onetime_dfe_0"),
+ .pma_adapt_adp_mode ("radp_mode_8"),
+ .pma_cdr_refclk_powerdown_mode ("powerup"),
+ .pma_cdr_refclk_refclk_select ("ref_iqclk0"),
+ .pma_cgb_bitslip_enable ("disable_bitslip"),
+ .pma_cgb_bonding_reset_enable ("disallow_bonding_reset"),
+ .pma_cgb_datarate ("1250000000 bps"),
+ .pma_cgb_pcie_gen3_bitwidth ("pciegen3_wide"),
+ .pma_cgb_prot_mode ("basic_tx"),
+ .pma_cgb_ser_mode ("ten_bit"),
+ .pma_cgb_sup_mode ("user_mode"),
+ .pma_cgb_x1_div_m_sel ("divby2"),
+ .pma_cgb_input_select_x1 ("fpll_bot"),
+ .pma_cgb_input_select_gen3 ("unused"),
+ .pma_cgb_input_select_xn ("unused"),
+ .pma_cgb_tx_ucontrol_en ("disable"),
+ .pma_rx_dfe_datarate ("1250000000 bps"),
+ .pma_rx_dfe_dft_en ("dft_disable"),
+ .pma_rx_dfe_pdb ("dfe_enable"),
+ .pma_rx_dfe_pdb_fixedtap ("fixtap_dfe_powerdown"),
+ .pma_rx_dfe_pdb_floattap ("floattap_dfe_powerdown"),
+ .pma_rx_dfe_pdb_fxtap4t7 ("fxtap4t7_powerdown"),
+ .pma_rx_dfe_sup_mode ("user_mode"),
+ .pma_rx_dfe_prot_mode ("basic_rx"),
+ .pma_rx_odi_datarate ("1250000000 bps"),
+ .pma_rx_odi_sup_mode ("user_mode"),
+ .pma_rx_odi_step_ctrl_sel ("dprio_mode"),
+ .pma_rx_odi_prot_mode ("basic_rx"),
+ .pma_rx_buf_bypass_eqz_stages_234 ("bypass_off"),
+ .pma_rx_buf_datarate ("1250000000 bps"),
+ .pma_rx_buf_diag_lp_en ("dlp_off"),
+ .pma_rx_buf_prot_mode ("basic_rx"),
+ .pma_rx_buf_qpi_enable ("non_qpi_mode"),
+ .pma_rx_buf_rx_refclk_divider ("bypass_divider"),
+ .pma_rx_buf_sup_mode ("user_mode"),
+ .pma_rx_buf_loopback_modes ("lpbk_disable"),
+ .pma_rx_buf_refclk_en ("disable"),
+ .pma_rx_buf_pm_tx_rx_pcie_gen ("non_pcie"),
+ .pma_rx_buf_pm_tx_rx_pcie_gen_bitwidth ("pcie_gen3_32b"),
+ .pma_rx_buf_pm_tx_rx_cvp_mode ("cvp_off"),
+ .pma_rx_buf_xrx_path_uc_cal_enable ("rx_cal_off"),
+ .pma_rx_buf_xrx_path_sup_mode ("user_mode"),
+ .pma_rx_buf_xrx_path_prot_mode ("basic_rx"),
+ .pma_rx_buf_xrx_path_datarate ("1250000000 bps"),
+ .pma_rx_buf_xrx_path_datawidth (10),
+ .pma_rx_buf_xrx_path_pma_rx_divclk_hz ("125000000"),
+ .pma_rx_sd_prot_mode ("basic_rx"),
+ .pma_rx_sd_sd_output_off (1),
+ .pma_rx_sd_sd_output_on (15),
+ .pma_rx_sd_sd_pdb ("sd_off"),
+ .pma_rx_sd_sup_mode ("user_mode"),
+ .pma_tx_ser_ser_clk_divtx_user_sel ("divtx_user_off"),
+ .pma_tx_ser_sup_mode ("user_mode"),
+ .pma_tx_ser_prot_mode ("basic_tx"),
+ .pma_tx_buf_datarate ("1250000000 bps"),
+ .pma_tx_buf_prot_mode ("basic_tx"),
+ .pma_tx_buf_rx_det ("mode_0"),
+ .pma_tx_buf_rx_det_output_sel ("rx_det_pcie_out"),
+ .pma_tx_buf_rx_det_pdb ("rx_det_off"),
+ .pma_tx_buf_sup_mode ("user_mode"),
+ .pma_tx_buf_user_fir_coeff_ctrl_sel ("ram_ctl"),
+ .pma_tx_buf_xtx_path_prot_mode ("basic_tx"),
+ .pma_tx_buf_xtx_path_datarate ("1250000000 bps"),
+ .pma_tx_buf_xtx_path_datawidth (10),
+ .pma_tx_buf_xtx_path_clock_divider_ratio (2),
+ .pma_tx_buf_xtx_path_pma_tx_divclk_hz ("125000000"),
+ .pma_tx_buf_xtx_path_tx_pll_clk_hz ("312500000"),
+ .pma_tx_buf_xtx_path_sup_mode ("user_mode"),
+ .cdr_pll_pma_width (10),
+ .cdr_pll_cgb_div (1),
+ .cdr_pll_is_cascaded_pll ("false"),
+ .cdr_pll_datarate ("1250000000 bps"),
+ .cdr_pll_lpd_counter (8),
+ .cdr_pll_lpfd_counter (1),
+ .cdr_pll_n_counter_scratch (1),
+ .cdr_pll_output_clock_frequency ("625000000 Hz"),
+ .cdr_pll_reference_clock_frequency ("125000000 hz"),
+ .cdr_pll_set_cdr_vco_speed (3),
+ .cdr_pll_set_cdr_vco_speed_fix (60),
+ .cdr_pll_vco_freq ("5000000000 Hz"),
+ .cdr_pll_atb_select_control ("atb_off"),
+ .cdr_pll_auto_reset_on ("auto_reset_off"),
+ .cdr_pll_bbpd_data_pattern_filter_select ("bbpd_data_pat_off"),
+ .cdr_pll_bw_sel ("medium"),
+ .cdr_pll_cdr_odi_select ("sel_cdr"),
+ .cdr_pll_cdr_phaselock_mode ("no_ignore_lock"),
+ .cdr_pll_cdr_powerdown_mode ("power_up"),
+ .cdr_pll_chgpmp_current_pd ("cp_current_pd_setting0"),
+ .cdr_pll_chgpmp_current_pfd ("cp_current_pfd_setting3"),
+ .cdr_pll_chgpmp_replicate ("false"),
+ .cdr_pll_chgpmp_testmode ("cp_test_disable"),
+ .cdr_pll_clklow_mux_select ("clklow_mux_cdr_fbclk"),
+ .cdr_pll_diag_loopback_enable ("false"),
+ .cdr_pll_disable_up_dn ("true"),
+ .cdr_pll_fref_clklow_div (1),
+ .cdr_pll_fref_mux_select ("fref_mux_cdr_refclk"),
+ .cdr_pll_gpon_lck2ref_control ("gpon_lck2ref_off"),
+ .cdr_pll_initial_settings ("true"),
+ .cdr_pll_lck2ref_delay_control ("lck2ref_delay_2"),
+ .cdr_pll_lf_resistor_pd ("lf_pd_setting0"),
+ .cdr_pll_lf_resistor_pfd ("lf_pfd_setting2"),
+ .cdr_pll_lf_ripple_cap ("lf_no_ripple"),
+ .cdr_pll_loop_filter_bias_select ("lpflt_bias_7"),
+ .cdr_pll_loopback_mode ("loopback_disabled"),
+ .cdr_pll_ltd_ltr_micro_controller_select ("ltd_ltr_pcs"),
+ .cdr_pll_m_counter (40),
+ .cdr_pll_n_counter (1),
+ .cdr_pll_pd_fastlock_mode ("false"),
+ .cdr_pll_pd_l_counter (8),
+ .cdr_pll_pfd_l_counter (1),
+ .cdr_pll_primary_use ("cdr"),
+ .cdr_pll_prot_mode ("basic_rx"),
+ .cdr_pll_reverse_serial_loopback ("no_loopback"),
+ .cdr_pll_set_cdr_v2i_enable ("true"),
+ .cdr_pll_set_cdr_vco_reset ("false"),
+ .cdr_pll_set_cdr_vco_speed_pciegen3 ("cdr_vco_max_speedbin_pciegen3"),
+ .cdr_pll_sup_mode ("user_mode"),
+ .cdr_pll_tx_pll_prot_mode ("txpll_unused"),
+ .cdr_pll_txpll_hclk_driver_enable ("false"),
+ .cdr_pll_vco_overrange_voltage ("vco_overrange_off"),
+ .cdr_pll_vco_underrange_voltage ("vco_underange_off"),
+ .cdr_pll_fb_select ("direct_fb"),
+ .cdr_pll_uc_ro_cal ("uc_ro_cal_on"),
+ .cdr_pll_iqclk_mux_sel ("power_down"),
+ .cdr_pll_pcie_gen ("non_pcie"),
+ .cdr_pll_set_cdr_input_freq_range (0),
+ .cdr_pll_chgpmp_current_dn_trim ("cp_current_trimming_dn_setting0"),
+ .cdr_pll_chgpmp_up_pd_trim_double ("normal_up_trim_current"),
+ .cdr_pll_chgpmp_current_up_pd ("cp_current_pd_up_setting4"),
+ .cdr_pll_chgpmp_current_up_trim ("cp_current_trimming_up_setting0"),
+ .cdr_pll_chgpmp_dn_pd_trim_double ("normal_dn_trim_current"),
+ .cdr_pll_cal_vco_count_length ("sel_8b_count"),
+ .cdr_pll_chgpmp_current_dn_pd ("cp_current_pd_dn_setting4"),
+ .pma_rx_deser_clkdiv_source ("vco_bypass_normal"),
+ .pma_rx_deser_clkdivrx_user_mode ("clkdivrx_user_clkdiv"),
+ .pma_rx_deser_datarate ("1250000000 bps"),
+ .pma_rx_deser_deser_factor (10),
+ .pma_rx_deser_force_clkdiv_for_testing ("normal_clkdiv"),
+ .pma_rx_deser_sdclk_enable ("false"),
+ .pma_rx_deser_sup_mode ("user_mode"),
+ .pma_rx_deser_rst_n_adapt_odi ("no_rst_adapt_odi"),
+ .pma_rx_deser_bitslip_bypass ("bs_bypass_yes"),
+ .pma_rx_deser_prot_mode ("basic_rx"),
+ .pma_rx_deser_pcie_gen ("non_pcie"),
+ .pma_rx_deser_pcie_gen_bitwidth ("pcie_gen3_32b")
+ ) i_nf_native_phyip_0 (
+ .tx_analogreset (tx_analogreset), // tx_analogreset.tx_analogreset
+ .tx_digitalreset (tx_digitalreset), // tx_digitalreset.tx_digitalreset
+ .rx_analogreset (rx_analogreset), // rx_analogreset.rx_analogreset
+ .rx_digitalreset (rx_digitalreset), // rx_digitalreset.rx_digitalreset
+ .tx_cal_busy (tx_cal_busy), // tx_cal_busy.tx_cal_busy
+ .rx_cal_busy (rx_cal_busy), // rx_cal_busy.rx_cal_busy
+ .tx_serial_clk0 (tx_serial_clk), // tx_serial_clk0.clk
+ .rx_cdr_refclk0 (rx_cdr_refclk), // rx_cdr_refclk0.clk
+ .tx_serial_data (i_nf_native_phyip_0_tx_serial_data_tx_serial_data), // tx_serial_data.tx_serial_data
+ .rx_serial_data (i_nf_native_phyip_terminator_0_rx_serial_data_rx_serial_data), // rx_serial_data.rx_serial_data
+ .rx_seriallpbken (i_nf_native_phyip_terminator_0_rx_seriallpbken_rx_seriallpbken), // rx_seriallpbken.rx_seriallpbken
+ .rx_set_locktodata (rx_set_locktodata), // rx_set_locktodata.rx_set_locktodata
+ .rx_set_locktoref (rx_set_locktoref), // rx_set_locktoref.rx_set_locktoref
+ .rx_is_lockedtoref (rx_is_lockedtoref), // rx_is_lockedtoref.rx_is_lockedtoref
+ .rx_is_lockedtodata (rx_is_lockedtodata), // rx_is_lockedtodata.rx_is_lockedtodata
+ .tx_coreclkin (i_nf_native_phyip_terminator_0_tx_coreclk_clk), // tx_coreclkin.clk
+ .rx_coreclkin (i_nf_native_phyip_terminator_0_rx_coreclk_clk), // rx_coreclkin.clk
+ .tx_clkout (i_nf_native_phyip_0_tx_clkout_clk), // tx_clkout.clk
+ .rx_clkout (i_nf_native_phyip_0_rx_clkout_clk), // rx_clkout.clk
+ .rx_pma_div_clkout (i_nf_native_phyip_0_rx_pma_div_clkout_clk), // rx_pma_div_clkout.clk
+ .tx_parallel_data ({i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[118],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[117],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[116],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[115],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[114],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[113],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[112],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[111],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[110],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[109],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[108],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[107],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[106],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[105],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[104],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[103],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[102],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[101],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[100],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[99],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[98],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[97],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[96],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[95],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[94],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[93],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[92],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[91],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[90],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[89],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[88],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[87],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[86],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[85],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[84],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[83],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[82],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[81],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[80],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[79],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[78],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[77],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[76],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[75],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[74],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[73],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[72],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[71],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[70],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[69],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[68],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[67],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[66],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[65],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[64],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[63],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[62],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[61],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[60],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[59],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[58],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[57],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[56],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[55],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[54],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[53],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[52],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[51],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[50],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[49],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[48],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[47],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[46],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[45],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[44],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[43],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[42],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[41],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[40],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[39],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[38],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[37],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[36],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[35],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[34],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[33],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[32],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[31],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[30],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[29],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[28],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[27],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[26],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[25],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[24],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[23],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[22],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[21],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[20],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[19],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[18],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[17],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[16],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[15],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[14],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[13],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[12],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[11],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[10],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[9],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[8],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[7],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[6],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[5],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[4],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[3],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[2],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[1],i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data[0],i_tse_pcs_0_tx_kchar_tx_datak,i_tse_pcs_0_tx_frame_tx_parallel_data[7],i_tse_pcs_0_tx_frame_tx_parallel_data[6],i_tse_pcs_0_tx_frame_tx_parallel_data[5],i_tse_pcs_0_tx_frame_tx_parallel_data[4],i_tse_pcs_0_tx_frame_tx_parallel_data[3],i_tse_pcs_0_tx_frame_tx_parallel_data[2],i_tse_pcs_0_tx_frame_tx_parallel_data[1],i_tse_pcs_0_tx_frame_tx_parallel_data[0]}), // tx_parallel_data.tx_parallel_data
+ .rx_parallel_data ({i_nf_native_phyip_0_rx_parallel_data[127],i_nf_native_phyip_0_rx_parallel_data[126],i_nf_native_phyip_0_rx_parallel_data[125],i_nf_native_phyip_0_rx_parallel_data[124],i_nf_native_phyip_0_rx_parallel_data[123],i_nf_native_phyip_0_rx_parallel_data[122],i_nf_native_phyip_0_rx_parallel_data[121],i_nf_native_phyip_0_rx_parallel_data[120],i_nf_native_phyip_0_rx_parallel_data[119],i_nf_native_phyip_0_rx_parallel_data[118],i_nf_native_phyip_0_rx_parallel_data[117],i_nf_native_phyip_0_rx_parallel_data[116],i_nf_native_phyip_0_rx_parallel_data[115],i_nf_native_phyip_0_rx_parallel_data[114],i_nf_native_phyip_0_rx_parallel_data[113],i_nf_native_phyip_0_rx_parallel_data[112],i_nf_native_phyip_0_rx_parallel_data[111],i_nf_native_phyip_0_rx_parallel_data[110],i_nf_native_phyip_0_rx_parallel_data[109],i_nf_native_phyip_0_rx_parallel_data[108],i_nf_native_phyip_0_rx_parallel_data[107],i_nf_native_phyip_0_rx_parallel_data[106],i_nf_native_phyip_0_rx_parallel_data[105],i_nf_native_phyip_0_rx_parallel_data[104],i_nf_native_phyip_0_rx_parallel_data[103],i_nf_native_phyip_0_rx_parallel_data[102],i_nf_native_phyip_0_rx_parallel_data[101],i_nf_native_phyip_0_rx_parallel_data[100],i_nf_native_phyip_0_rx_parallel_data[99],i_nf_native_phyip_0_rx_parallel_data[98],i_nf_native_phyip_0_rx_parallel_data[97],i_nf_native_phyip_0_rx_parallel_data[96],i_nf_native_phyip_0_rx_parallel_data[95],i_nf_native_phyip_0_rx_parallel_data[94],i_nf_native_phyip_0_rx_parallel_data[93],i_nf_native_phyip_0_rx_parallel_data[92],i_nf_native_phyip_0_rx_parallel_data[91],i_nf_native_phyip_0_rx_parallel_data[90],i_nf_native_phyip_0_rx_parallel_data[89],i_nf_native_phyip_0_rx_parallel_data[88],i_nf_native_phyip_0_rx_parallel_data[87],i_nf_native_phyip_0_rx_parallel_data[86],i_nf_native_phyip_0_rx_parallel_data[85],i_nf_native_phyip_0_rx_parallel_data[84],i_nf_native_phyip_0_rx_parallel_data[83],i_nf_native_phyip_0_rx_parallel_data[82],i_nf_native_phyip_0_rx_parallel_data[81],i_nf_native_phyip_0_rx_parallel_data[80],i_nf_native_phyip_0_rx_parallel_data[79],i_nf_native_phyip_0_rx_parallel_data[78],i_nf_native_phyip_0_rx_parallel_data[77],i_nf_native_phyip_0_rx_parallel_data[76],i_nf_native_phyip_0_rx_parallel_data[75],i_nf_native_phyip_0_rx_parallel_data[74],i_nf_native_phyip_0_rx_parallel_data[73],i_nf_native_phyip_0_rx_parallel_data[72],i_nf_native_phyip_0_rx_parallel_data[71],i_nf_native_phyip_0_rx_parallel_data[70],i_nf_native_phyip_0_rx_parallel_data[69],i_nf_native_phyip_0_rx_parallel_data[68],i_nf_native_phyip_0_rx_parallel_data[67],i_nf_native_phyip_0_rx_parallel_data[66],i_nf_native_phyip_0_rx_parallel_data[65],i_nf_native_phyip_0_rx_parallel_data[64],i_nf_native_phyip_0_rx_parallel_data[63],i_nf_native_phyip_0_rx_parallel_data[62],i_nf_native_phyip_0_rx_parallel_data[61],i_nf_native_phyip_0_rx_parallel_data[60],i_nf_native_phyip_0_rx_parallel_data[59],i_nf_native_phyip_0_rx_parallel_data[58],i_nf_native_phyip_0_rx_parallel_data[57],i_nf_native_phyip_0_rx_parallel_data[56],i_nf_native_phyip_0_rx_parallel_data[55],i_nf_native_phyip_0_rx_parallel_data[54],i_nf_native_phyip_0_rx_parallel_data[53],i_nf_native_phyip_0_rx_parallel_data[52],i_nf_native_phyip_0_rx_parallel_data[51],i_nf_native_phyip_0_rx_parallel_data[50],i_nf_native_phyip_0_rx_parallel_data[49],i_nf_native_phyip_0_rx_parallel_data[48],i_nf_native_phyip_0_rx_parallel_data[47],i_nf_native_phyip_0_rx_parallel_data[46],i_nf_native_phyip_0_rx_parallel_data[45],i_nf_native_phyip_0_rx_parallel_data[44],i_nf_native_phyip_0_rx_parallel_data[43],i_nf_native_phyip_0_rx_parallel_data[42],i_nf_native_phyip_0_rx_parallel_data[41],i_nf_native_phyip_0_rx_parallel_data[40],i_nf_native_phyip_0_rx_parallel_data[39],i_nf_native_phyip_0_rx_parallel_data[38],i_nf_native_phyip_0_rx_parallel_data[37],i_nf_native_phyip_0_rx_parallel_data[36],i_nf_native_phyip_0_rx_parallel_data[35],i_nf_native_phyip_0_rx_parallel_data[34],i_nf_native_phyip_0_rx_parallel_data[33],i_nf_native_phyip_0_rx_parallel_data[32],i_nf_native_phyip_0_rx_parallel_data[31],i_nf_native_phyip_0_rx_parallel_data[30],i_nf_native_phyip_0_rx_parallel_data[29],i_nf_native_phyip_0_rx_parallel_data[28],i_nf_native_phyip_0_rx_parallel_data[27],i_nf_native_phyip_0_rx_parallel_data[26],i_nf_native_phyip_0_rx_parallel_data[25],i_nf_native_phyip_0_rx_parallel_data[24],i_nf_native_phyip_0_rx_parallel_data[23],i_nf_native_phyip_0_rx_parallel_data[22],i_nf_native_phyip_0_rx_parallel_data[21],i_nf_native_phyip_0_rx_parallel_data[20],i_nf_native_phyip_0_rx_parallel_data[19],i_nf_native_phyip_0_rx_parallel_data[18],i_nf_native_phyip_0_rx_parallel_data[17],i_nf_native_phyip_0_rx_parallel_data[16],i_nf_native_phyip_0_rx_parallel_data[15],i_nf_native_phyip_0_rx_parallel_data[14],i_nf_native_phyip_0_rx_parallel_data[13],i_nf_native_phyip_0_rx_parallel_data[12],i_nf_native_phyip_0_rx_parallel_data[11],i_nf_native_phyip_0_rx_parallel_data[10],i_nf_native_phyip_0_rx_parallel_data[9],i_nf_native_phyip_0_rx_parallel_data[8],i_nf_native_phyip_0_rx_parallel_data[7],i_nf_native_phyip_0_rx_parallel_data[6],i_nf_native_phyip_0_rx_parallel_data[5],i_nf_native_phyip_0_rx_parallel_data[4],i_nf_native_phyip_0_rx_parallel_data[3],i_nf_native_phyip_0_rx_parallel_data[2],i_nf_native_phyip_0_rx_parallel_data[1],i_nf_native_phyip_0_rx_parallel_data[0]}), // rx_parallel_data.rx_parallel_data
+ .rx_std_bitslipboundarysel (i_nf_native_phyip_0_rx_std_bitslipboundarysel_rx_std_bitslipboundarysel), // rx_std_bitslipboundarysel.rx_std_bitslipboundarysel
+ .reconfig_clk (reconfig_clk), // reconfig_clk.clk
+ .reconfig_reset (reconfig_reset), // reconfig_reset.reset
+ .reconfig_write (reconfig_write), // reconfig_avmm.write
+ .reconfig_read (reconfig_read), // .read
+ .reconfig_address (reconfig_address), // .address
+ .reconfig_writedata (reconfig_writedata), // .writedata
+ .reconfig_readdata (reconfig_readdata), // .readdata
+ .reconfig_waitrequest (reconfig_waitrequest), // .waitrequest
+ .tx_analogreset_ack (), // (terminated)
+ .rx_analogreset_ack (), // (terminated)
+ .tx_serial_clk1 (1'b0), // (terminated)
+ .tx_serial_clk2 (1'b0), // (terminated)
+ .tx_serial_clk3 (1'b0), // (terminated)
+ .tx_bonding_clocks (6'b000000), // (terminated)
+ .tx_bonding_clocks1 (6'b000000), // (terminated)
+ .tx_bonding_clocks2 (6'b000000), // (terminated)
+ .tx_bonding_clocks3 (6'b000000), // (terminated)
+ .rx_cdr_refclk1 (1'b0), // (terminated)
+ .rx_cdr_refclk2 (1'b0), // (terminated)
+ .rx_cdr_refclk3 (1'b0), // (terminated)
+ .rx_cdr_refclk4 (1'b0), // (terminated)
+ .rx_pma_clkslip (1'b0), // (terminated)
+ .rx_pma_qpipulldn (1'b0), // (terminated)
+ .tx_pma_qpipulldn (1'b0), // (terminated)
+ .tx_pma_qpipullup (1'b0), // (terminated)
+ .tx_pma_txdetectrx (1'b0), // (terminated)
+ .tx_pma_elecidle (1'b0), // (terminated)
+ .tx_pma_rxfound (), // (terminated)
+ .rx_clklow (), // (terminated)
+ .rx_fref (), // (terminated)
+ .tx_pma_clkout (), // (terminated)
+ .tx_pma_div_clkout (), // (terminated)
+ .tx_pma_iqtxrx_clkout (), // (terminated)
+ .rx_pma_clkout (), // (terminated)
+ .rx_pma_iqtxrx_clkout (), // (terminated)
+ .tx_control (18'b000000000000000000), // (terminated)
+ .rx_control (), // (terminated)
+ .rx_bitslip (1'b0), // (terminated)
+ .rx_adapt_reset (1'b0), // (terminated)
+ .rx_adapt_start (1'b0), // (terminated)
+ .rx_prbs_err_clr (1'b0), // (terminated)
+ .rx_prbs_done (), // (terminated)
+ .rx_prbs_err (), // (terminated)
+ .tx_uhsif_clk (1'b0), // (terminated)
+ .tx_uhsif_clkout (), // (terminated)
+ .tx_uhsif_lock (), // (terminated)
+ .tx_std_pcfifo_full (), // (terminated)
+ .tx_std_pcfifo_empty (), // (terminated)
+ .rx_std_pcfifo_full (), // (terminated)
+ .rx_std_pcfifo_empty (), // (terminated)
+ .rx_std_bitrev_ena (1'b0), // (terminated)
+ .rx_std_byterev_ena (1'b0), // (terminated)
+ .tx_polinv (1'b0), // (terminated)
+ .rx_polinv (1'b0), // (terminated)
+ .tx_std_bitslipboundarysel (5'b00000), // (terminated)
+ .rx_std_wa_patternalign (1'b0), // (terminated)
+ .rx_std_wa_a1a2size (1'b0), // (terminated)
+ .rx_std_rmfifo_full (), // (terminated)
+ .rx_std_rmfifo_empty (), // (terminated)
+ .rx_std_signaldetect (), // (terminated)
+ .tx_enh_data_valid (1'b0), // (terminated)
+ .tx_enh_fifo_full (), // (terminated)
+ .tx_enh_fifo_pfull (), // (terminated)
+ .tx_enh_fifo_empty (), // (terminated)
+ .tx_enh_fifo_pempty (), // (terminated)
+ .tx_enh_fifo_cnt (), // (terminated)
+ .rx_enh_fifo_rd_en (1'b0), // (terminated)
+ .rx_enh_data_valid (), // (terminated)
+ .rx_enh_fifo_full (), // (terminated)
+ .rx_enh_fifo_pfull (), // (terminated)
+ .rx_enh_fifo_empty (), // (terminated)
+ .rx_enh_fifo_pempty (), // (terminated)
+ .rx_enh_fifo_del (), // (terminated)
+ .rx_enh_fifo_insert (), // (terminated)
+ .rx_enh_fifo_cnt (), // (terminated)
+ .rx_enh_fifo_align_val (), // (terminated)
+ .rx_enh_fifo_align_clr (1'b0), // (terminated)
+ .tx_enh_frame (), // (terminated)
+ .tx_enh_frame_burst_en (1'b0), // (terminated)
+ .tx_enh_frame_diag_status (2'b00), // (terminated)
+ .rx_enh_frame (), // (terminated)
+ .rx_enh_frame_lock (), // (terminated)
+ .rx_enh_frame_diag_status (), // (terminated)
+ .rx_enh_crc32_err (), // (terminated)
+ .rx_enh_highber (), // (terminated)
+ .rx_enh_highber_clr_cnt (1'b0), // (terminated)
+ .rx_enh_clr_errblk_count (1'b0), // (terminated)
+ .rx_enh_blk_lock (), // (terminated)
+ .tx_enh_bitslip (7'b0000000), // (terminated)
+ .tx_hip_data (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
+ .rx_hip_data (), // (terminated)
+ .hip_pipe_pclk (), // (terminated)
+ .hip_fixedclk (), // (terminated)
+ .hip_frefclk (), // (terminated)
+ .hip_ctrl (), // (terminated)
+ .hip_cal_done (), // (terminated)
+ .ltssm_detect_quiet (1'b0), // (terminated)
+ .ltssm_detect_active (1'b0), // (terminated)
+ .ltssm_rcvr_phase_two (1'b0), // (terminated)
+ .hip_reduce_counters (1'b0), // (terminated)
+ .pcie_rate (2'b00), // (terminated)
+ .pipe_rate (2'b00), // (terminated)
+ .pipe_sw_done (2'b00), // (terminated)
+ .pipe_sw (), // (terminated)
+ .pipe_hclk_in (1'b0), // (terminated)
+ .pipe_hclk_out (), // (terminated)
+ .pipe_g3_txdeemph (18'b000000000000000000), // (terminated)
+ .pipe_g3_rxpresethint (3'b000), // (terminated)
+ .pipe_rx_eidleinfersel (3'b000), // (terminated)
+ .pipe_rx_elecidle (), // (terminated)
+ .pipe_rx_polarity (1'b0), // (terminated)
+ .avmm_busy () // (terminated)
+ );
+
+ altera_eth_tse_nf_phyip_terminator #(
+ .ENABLE_TIMESTAMPING (0),
+ .UNUSED_RX_PARALLEL_DATA_WIDTH (114)
+ ) i_nf_native_phyip_terminator_0 (
+ .tx_clk (i_nf_native_phyip_0_tx_clkout_clk), // tx_clk.clk
+ .rx_clk (i_nf_native_phyip_0_rx_clkout_clk), // rx_clk.clk
+ .tx_coreclk (i_nf_native_phyip_terminator_0_tx_coreclk_clk), // tx_coreclk.clk
+ .rx_coreclk (i_nf_native_phyip_terminator_0_rx_coreclk_clk), // rx_coreclk.clk
+ .rx_recovered_clk (i_nf_native_phyip_0_rx_pma_div_clkout_clk), // rx_recovered_clk.clk
+ .rxp (rxp), // serial_connection.export
+ .txp (txp), // .export
+ .rx_recovclkout (rx_recovclkout), // serdes_control_connection.export
+ .rx_pcs_clk (i_nf_native_phyip_terminator_0_rx_pcs_clk_rx_pcs_clk), // rx_pcs_clk.rx_pcs_clk
+ .unused_tx_parallel_data (i_nf_native_phyip_terminator_0_unused_tx_parallel_data_unused_tx_parallel_data), // unused_tx_parallel_data.unused_tx_parallel_data
+ .tx_serial_data (i_nf_native_phyip_0_tx_serial_data_tx_serial_data), // tx_serial_data.tx_serial_data
+ .rx_runlengthviolation (i_nf_native_phyip_terminator_0_rx_runlengthviolation_rx_runlengthviolation), // rx_runlengthviolation.rx_runlengthviolation
+ .rx_seriallpbken (i_nf_native_phyip_terminator_0_rx_seriallpbken_rx_seriallpbken), // rx_seriallpbken.rx_seriallpbken
+ .sd_loopback (i_tse_pcs_0_sd_loopback_sd_loopback), // sd_loopback.sd_loopback
+ .tx_pcs_clk (i_nf_native_phyip_terminator_0_tx_pcs_clk_tx_pcs_clk), // tx_pcs_clk.tx_pcs_clk
+ .rx_serial_data (i_nf_native_phyip_terminator_0_rx_serial_data_rx_serial_data), // rx_serial_data.rx_serial_data
+ .unused_rx_parallel_data (i_nf_native_phyip_0_unused_rx_parallel_data_unused_rx_parallel_data), // unused_rx_parallel_data.unused_rx_parallel_data
+ .rx_rmfifostatus (2'b00), // (terminated)
+ .rx_rmfifodatainserted (), // (terminated)
+ .rx_rmfifodatadeleted (), // (terminated)
+ .terminate_rx_recovered_clk (1'b0) // (terminated)
+ );
+
+ altera_reset_controller #(
+ .NUM_RESET_INPUTS (1),
+ .OUTPUT_RESET_SYNC_EDGES ("deassert"),
+ .SYNC_DEPTH (2),
+ .RESET_REQUEST_PRESENT (0),
+ .RESET_REQ_WAIT_TIME (1),
+ .MIN_RST_ASSERTION_TIME (3),
+ .RESET_REQ_EARLY_DSRT_TIME (1),
+ .USE_RESET_REQUEST_IN0 (0),
+ .USE_RESET_REQUEST_IN1 (0),
+ .USE_RESET_REQUEST_IN2 (0),
+ .USE_RESET_REQUEST_IN3 (0),
+ .USE_RESET_REQUEST_IN4 (0),
+ .USE_RESET_REQUEST_IN5 (0),
+ .USE_RESET_REQUEST_IN6 (0),
+ .USE_RESET_REQUEST_IN7 (0),
+ .USE_RESET_REQUEST_IN8 (0),
+ .USE_RESET_REQUEST_IN9 (0),
+ .USE_RESET_REQUEST_IN10 (0),
+ .USE_RESET_REQUEST_IN11 (0),
+ .USE_RESET_REQUEST_IN12 (0),
+ .USE_RESET_REQUEST_IN13 (0),
+ .USE_RESET_REQUEST_IN14 (0),
+ .USE_RESET_REQUEST_IN15 (0),
+ .ADAPT_RESET_REQUEST (0)
+ ) rst_controller (
+ .reset_in0 (reset), // reset_in0.reset
+ .clk (i_tse_pcs_0_pcs_transmit_clock_connection_clk), // clk.clk
+ .reset_out (rst_controller_reset_out_reset), // reset_out.reset
+ .reset_req (), // (terminated)
+ .reset_req_in0 (1'b0), // (terminated)
+ .reset_in1 (1'b0), // (terminated)
+ .reset_req_in1 (1'b0), // (terminated)
+ .reset_in2 (1'b0), // (terminated)
+ .reset_req_in2 (1'b0), // (terminated)
+ .reset_in3 (1'b0), // (terminated)
+ .reset_req_in3 (1'b0), // (terminated)
+ .reset_in4 (1'b0), // (terminated)
+ .reset_req_in4 (1'b0), // (terminated)
+ .reset_in5 (1'b0), // (terminated)
+ .reset_req_in5 (1'b0), // (terminated)
+ .reset_in6 (1'b0), // (terminated)
+ .reset_req_in6 (1'b0), // (terminated)
+ .reset_in7 (1'b0), // (terminated)
+ .reset_req_in7 (1'b0), // (terminated)
+ .reset_in8 (1'b0), // (terminated)
+ .reset_req_in8 (1'b0), // (terminated)
+ .reset_in9 (1'b0), // (terminated)
+ .reset_req_in9 (1'b0), // (terminated)
+ .reset_in10 (1'b0), // (terminated)
+ .reset_req_in10 (1'b0), // (terminated)
+ .reset_in11 (1'b0), // (terminated)
+ .reset_req_in11 (1'b0), // (terminated)
+ .reset_in12 (1'b0), // (terminated)
+ .reset_req_in12 (1'b0), // (terminated)
+ .reset_in13 (1'b0), // (terminated)
+ .reset_req_in13 (1'b0), // (terminated)
+ .reset_in14 (1'b0), // (terminated)
+ .reset_req_in14 (1'b0), // (terminated)
+ .reset_in15 (1'b0), // (terminated)
+ .reset_req_in15 (1'b0) // (terminated)
+ );
+
+ altera_reset_controller #(
+ .NUM_RESET_INPUTS (1),
+ .OUTPUT_RESET_SYNC_EDGES ("deassert"),
+ .SYNC_DEPTH (2),
+ .RESET_REQUEST_PRESENT (0),
+ .RESET_REQ_WAIT_TIME (1),
+ .MIN_RST_ASSERTION_TIME (3),
+ .RESET_REQ_EARLY_DSRT_TIME (1),
+ .USE_RESET_REQUEST_IN0 (0),
+ .USE_RESET_REQUEST_IN1 (0),
+ .USE_RESET_REQUEST_IN2 (0),
+ .USE_RESET_REQUEST_IN3 (0),
+ .USE_RESET_REQUEST_IN4 (0),
+ .USE_RESET_REQUEST_IN5 (0),
+ .USE_RESET_REQUEST_IN6 (0),
+ .USE_RESET_REQUEST_IN7 (0),
+ .USE_RESET_REQUEST_IN8 (0),
+ .USE_RESET_REQUEST_IN9 (0),
+ .USE_RESET_REQUEST_IN10 (0),
+ .USE_RESET_REQUEST_IN11 (0),
+ .USE_RESET_REQUEST_IN12 (0),
+ .USE_RESET_REQUEST_IN13 (0),
+ .USE_RESET_REQUEST_IN14 (0),
+ .USE_RESET_REQUEST_IN15 (0),
+ .ADAPT_RESET_REQUEST (0)
+ ) rst_controller_001 (
+ .reset_in0 (reset), // reset_in0.reset
+ .clk (i_tse_pcs_0_pcs_receive_clock_connection_clk), // clk.clk
+ .reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
+ .reset_req (), // (terminated)
+ .reset_req_in0 (1'b0), // (terminated)
+ .reset_in1 (1'b0), // (terminated)
+ .reset_req_in1 (1'b0), // (terminated)
+ .reset_in2 (1'b0), // (terminated)
+ .reset_req_in2 (1'b0), // (terminated)
+ .reset_in3 (1'b0), // (terminated)
+ .reset_req_in3 (1'b0), // (terminated)
+ .reset_in4 (1'b0), // (terminated)
+ .reset_req_in4 (1'b0), // (terminated)
+ .reset_in5 (1'b0), // (terminated)
+ .reset_req_in5 (1'b0), // (terminated)
+ .reset_in6 (1'b0), // (terminated)
+ .reset_req_in6 (1'b0), // (terminated)
+ .reset_in7 (1'b0), // (terminated)
+ .reset_req_in7 (1'b0), // (terminated)
+ .reset_in8 (1'b0), // (terminated)
+ .reset_req_in8 (1'b0), // (terminated)
+ .reset_in9 (1'b0), // (terminated)
+ .reset_req_in9 (1'b0), // (terminated)
+ .reset_in10 (1'b0), // (terminated)
+ .reset_req_in10 (1'b0), // (terminated)
+ .reset_in11 (1'b0), // (terminated)
+ .reset_req_in11 (1'b0), // (terminated)
+ .reset_in12 (1'b0), // (terminated)
+ .reset_req_in12 (1'b0), // (terminated)
+ .reset_in13 (1'b0), // (terminated)
+ .reset_req_in13 (1'b0), // (terminated)
+ .reset_in14 (1'b0), // (terminated)
+ .reset_req_in14 (1'b0), // (terminated)
+ .reset_in15 (1'b0), // (terminated)
+ .reset_req_in15 (1'b0) // (terminated)
+ );
+
+ assign i_nf_native_phyip_0_rx_patterndetect_rx_patterndetect = { i_nf_native_phyip_0_rx_parallel_data[12] };
+
+ assign i_nf_native_phyip_0_rx_parallel_data_rx_parallel_data = { i_nf_native_phyip_0_rx_parallel_data[7], i_nf_native_phyip_0_rx_parallel_data[6], i_nf_native_phyip_0_rx_parallel_data[5], i_nf_native_phyip_0_rx_parallel_data[4], i_nf_native_phyip_0_rx_parallel_data[3], i_nf_native_phyip_0_rx_parallel_data[2], i_nf_native_phyip_0_rx_parallel_data[1], i_nf_native_phyip_0_rx_parallel_data[0] };
+
+ assign i_nf_native_phyip_0_rx_disperr_rx_disperr = { i_nf_native_phyip_0_rx_parallel_data[11] };
+
+ assign i_nf_native_phyip_0_rx_errdetect_rx_errdetect = { i_nf_native_phyip_0_rx_parallel_data[9] };
+
+ assign i_nf_native_phyip_0_rx_syncstatus_rx_syncstatus = { i_nf_native_phyip_0_rx_parallel_data[10] };
+
+ assign i_nf_native_phyip_0_rx_runningdisp_rx_runningdisp = { i_nf_native_phyip_0_rx_parallel_data[15] };
+
+ assign i_nf_native_phyip_0_rx_datak_rx_datak = { i_nf_native_phyip_0_rx_parallel_data[8] };
+
+ assign i_nf_native_phyip_0_unused_rx_parallel_data_unused_rx_parallel_data = { i_nf_native_phyip_0_rx_parallel_data[127], i_nf_native_phyip_0_rx_parallel_data[126], i_nf_native_phyip_0_rx_parallel_data[125], i_nf_native_phyip_0_rx_parallel_data[124], i_nf_native_phyip_0_rx_parallel_data[123], i_nf_native_phyip_0_rx_parallel_data[122], i_nf_native_phyip_0_rx_parallel_data[121], i_nf_native_phyip_0_rx_parallel_data[120], i_nf_native_phyip_0_rx_parallel_data[119], i_nf_native_phyip_0_rx_parallel_data[118], i_nf_native_phyip_0_rx_parallel_data[117], i_nf_native_phyip_0_rx_parallel_data[116], i_nf_native_phyip_0_rx_parallel_data[115], i_nf_native_phyip_0_rx_parallel_data[114], i_nf_native_phyip_0_rx_parallel_data[113], i_nf_native_phyip_0_rx_parallel_data[112], i_nf_native_phyip_0_rx_parallel_data[111], i_nf_native_phyip_0_rx_parallel_data[110], i_nf_native_phyip_0_rx_parallel_data[109], i_nf_native_phyip_0_rx_parallel_data[108], i_nf_native_phyip_0_rx_parallel_data[107], i_nf_native_phyip_0_rx_parallel_data[106], i_nf_native_phyip_0_rx_parallel_data[105], i_nf_native_phyip_0_rx_parallel_data[104], i_nf_native_phyip_0_rx_parallel_data[103], i_nf_native_phyip_0_rx_parallel_data[102], i_nf_native_phyip_0_rx_parallel_data[101], i_nf_native_phyip_0_rx_parallel_data[100], i_nf_native_phyip_0_rx_parallel_data[99], i_nf_native_phyip_0_rx_parallel_data[98], i_nf_native_phyip_0_rx_parallel_data[97], i_nf_native_phyip_0_rx_parallel_data[96], i_nf_native_phyip_0_rx_parallel_data[95], i_nf_native_phyip_0_rx_parallel_data[94], i_nf_native_phyip_0_rx_parallel_data[93], i_nf_native_phyip_0_rx_parallel_data[92], i_nf_native_phyip_0_rx_parallel_data[91], i_nf_native_phyip_0_rx_parallel_data[90], i_nf_native_phyip_0_rx_parallel_data[89], i_nf_native_phyip_0_rx_parallel_data[88], i_nf_native_phyip_0_rx_parallel_data[87], i_nf_native_phyip_0_rx_parallel_data[86], i_nf_native_phyip_0_rx_parallel_data[85], i_nf_native_phyip_0_rx_parallel_data[84], i_nf_native_phyip_0_rx_parallel_data[83], i_nf_native_phyip_0_rx_parallel_data[82], i_nf_native_phyip_0_rx_parallel_data[81], i_nf_native_phyip_0_rx_parallel_data[80], i_nf_native_phyip_0_rx_parallel_data[79], i_nf_native_phyip_0_rx_parallel_data[78], i_nf_native_phyip_0_rx_parallel_data[77], i_nf_native_phyip_0_rx_parallel_data[76], i_nf_native_phyip_0_rx_parallel_data[75], i_nf_native_phyip_0_rx_parallel_data[74], i_nf_native_phyip_0_rx_parallel_data[73], i_nf_native_phyip_0_rx_parallel_data[72], i_nf_native_phyip_0_rx_parallel_data[71], i_nf_native_phyip_0_rx_parallel_data[70], i_nf_native_phyip_0_rx_parallel_data[69], i_nf_native_phyip_0_rx_parallel_data[68], i_nf_native_phyip_0_rx_parallel_data[67], i_nf_native_phyip_0_rx_parallel_data[66], i_nf_native_phyip_0_rx_parallel_data[65], i_nf_native_phyip_0_rx_parallel_data[64], i_nf_native_phyip_0_rx_parallel_data[63], i_nf_native_phyip_0_rx_parallel_data[62], i_nf_native_phyip_0_rx_parallel_data[61], i_nf_native_phyip_0_rx_parallel_data[60], i_nf_native_phyip_0_rx_parallel_data[59], i_nf_native_phyip_0_rx_parallel_data[58], i_nf_native_phyip_0_rx_parallel_data[57], i_nf_native_phyip_0_rx_parallel_data[56], i_nf_native_phyip_0_rx_parallel_data[55], i_nf_native_phyip_0_rx_parallel_data[54], i_nf_native_phyip_0_rx_parallel_data[53], i_nf_native_phyip_0_rx_parallel_data[52], i_nf_native_phyip_0_rx_parallel_data[51], i_nf_native_phyip_0_rx_parallel_data[50], i_nf_native_phyip_0_rx_parallel_data[49], i_nf_native_phyip_0_rx_parallel_data[48], i_nf_native_phyip_0_rx_parallel_data[47], i_nf_native_phyip_0_rx_parallel_data[46], i_nf_native_phyip_0_rx_parallel_data[45], i_nf_native_phyip_0_rx_parallel_data[44], i_nf_native_phyip_0_rx_parallel_data[43], i_nf_native_phyip_0_rx_parallel_data[42], i_nf_native_phyip_0_rx_parallel_data[41], i_nf_native_phyip_0_rx_parallel_data[40], i_nf_native_phyip_0_rx_parallel_data[39], i_nf_native_phyip_0_rx_parallel_data[38], i_nf_native_phyip_0_rx_parallel_data[37], i_nf_native_phyip_0_rx_parallel_data[36], i_nf_native_phyip_0_rx_parallel_data[35], i_nf_native_phyip_0_rx_parallel_data[34], i_nf_native_phyip_0_rx_parallel_data[33], i_nf_native_phyip_0_rx_parallel_data[32], i_nf_native_phyip_0_rx_parallel_data[31], i_nf_native_phyip_0_rx_parallel_data[30], i_nf_native_phyip_0_rx_parallel_data[29], i_nf_native_phyip_0_rx_parallel_data[28], i_nf_native_phyip_0_rx_parallel_data[27], i_nf_native_phyip_0_rx_parallel_data[26], i_nf_native_phyip_0_rx_parallel_data[25], i_nf_native_phyip_0_rx_parallel_data[24], i_nf_native_phyip_0_rx_parallel_data[23], i_nf_native_phyip_0_rx_parallel_data[22], i_nf_native_phyip_0_rx_parallel_data[21], i_nf_native_phyip_0_rx_parallel_data[20], i_nf_native_phyip_0_rx_parallel_data[19], i_nf_native_phyip_0_rx_parallel_data[18], i_nf_native_phyip_0_rx_parallel_data[17], i_nf_native_phyip_0_rx_parallel_data[16], i_nf_native_phyip_0_rx_parallel_data[14], i_nf_native_phyip_0_rx_parallel_data[13] };
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_izmmkjq_cfg.v b/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_izmmkjq_cfg.v
new file mode 100644
index 0000000000000000000000000000000000000000..d9b75570518dd88c2b4bbdff04ff6a045e3af530
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_221/synth/arria10_hps_altera_eth_tse_221_izmmkjq_cfg.v
@@ -0,0 +1,11 @@
+config arria10_hps_altera_eth_tse_221_izmmkjq_cfg;
+ design arria10_hps_altera_eth_tse_221_izmmkjq;
+ instance arria10_hps_altera_eth_tse_221_izmmkjq.i_tse_mac use arria10_hps_altera_eth_tse_mac_221.altera_eth_tse_mac;
+ instance arria10_hps_altera_eth_tse_221_izmmkjq.avalon_arbiter use arria10_hps_altera_eth_tse_avalon_arbiter_221.altera_eth_tse_avalon_arbiter;
+ instance arria10_hps_altera_eth_tse_221_izmmkjq.i_tse_pcs_0 use arria10_hps_altera_eth_tse_pcs_pma_nf_phyip_221.altera_eth_tse_pcs_pma_nf_phyip;
+ instance arria10_hps_altera_eth_tse_221_izmmkjq.i_nf_native_phyip_0 use arria10_hps_altera_xcvr_native_a10_221.arria10_hps_altera_xcvr_native_a10_221_iq5an3y;
+ instance arria10_hps_altera_eth_tse_221_izmmkjq.i_nf_native_phyip_terminator_0 use arria10_hps_altera_eth_tse_nf_phyip_terminator_221.altera_eth_tse_nf_phyip_terminator;
+ instance arria10_hps_altera_eth_tse_221_izmmkjq.rst_controller use arria10_hps_altera_reset_controller_221.altera_reset_controller;
+ instance arria10_hps_altera_eth_tse_221_izmmkjq.rst_controller_001 use arria10_hps_altera_reset_controller_221.altera_reset_controller;
+endconfig
+
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_avalon_arbiter_221/synth/altera_eth_tse_avalon_arbiter.v b/quartus/qsys/arria10_hps/altera_eth_tse_avalon_arbiter_221/synth/altera_eth_tse_avalon_arbiter.v
new file mode 100644
index 0000000000000000000000000000000000000000..db1fad08700f3be38ae8c4a9e300f773037458dc
Binary files /dev/null and b/quartus/qsys/arria10_hps/altera_eth_tse_avalon_arbiter_221/synth/altera_eth_tse_avalon_arbiter.v differ
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_mac.sdc b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_mac.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..b5fadb7c85c12790a92ed918f8edaed713da0984
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_mac.sdc
@@ -0,0 +1,303 @@
+# (C) 2001-2023 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any output
+# files from any of the foregoing (including device programming or simulation
+# files), and any associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License Subscription
+# Agreement, Intel FPGA IP License Agreement, or other applicable
+# license agreement, including, without limitation, that your use is for the
+# sole purpose of programming logic devices manufactured by Intel and sold by
+# Intel or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+
+# CORE_PARAMETERS
+set IS_SMALLMAC 0
+set ENABLE_SUP_ADDR 0
+set ENABLE_MAC_FLOW_CTRL 0
+set ENABLE_MAGIC_DETECT 1
+set ENABLE_HD_LOGIC 0
+set ENABLE_ENA 32
+set ENABLE_GMII_LOOPBACK 0
+set STAT_CNT_ENA 1
+
+set old_mode [set_project_mode -get_mode_value always_show_entity_name]
+set_project_mode -always_show_entity_name on
+
+# Function to constraint non-std_synchronizer path
+proc altera_eth_tse_constraint_net_delay {from_reg to_reg max_net_delay} {
+
+ set_net_delay -from [get_pins -compatibility_mode ${from_reg}|q] -to [get_registers ${to_reg}] -max $max_net_delay
+
+ if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
+ set_max_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] 100ns
+ set_min_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] -100ns
+ } else {
+ # Relax the fitter effort
+ set_max_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] 8ns
+ set_min_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] -100ns
+ }
+
+}
+
+# Function to constraint std_synchronizer
+proc altera_eth_tse_constraint_std_sync {} {
+
+ altera_eth_tse_constraint_net_delay * *altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1 6ns
+
+}
+
+# Function to constraint pointers
+proc altera_eth_tse_constraint_ptr {from_path from_reg to_path to_reg max_skew max_net_delay} {
+
+ set_net_delay -from [get_pins -compatibility_mode *${from_path}|${from_reg}[*]|q] -to [get_registers *${to_path}|${to_reg}*] -max $max_net_delay
+
+ if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
+ # Check for instances
+ set inst [get_registers -nowarn *${from_path}|${from_reg}\[0\]]
+
+ # Check number of instances
+ set inst_num [llength [query_collection -report -all $inst]]
+ if {$inst_num > 0} {
+ # Uncomment line below for debug purpose
+ #puts "${inst_num} ${from_path}|${from_reg} instance(s) found"
+ } else {
+ # Uncomment line below for debug purpose
+ #puts "No ${from_path}|${from_reg} instance found"
+ }
+
+ # Constraint one instance at a time to avoid set_max_skew apply to all instances
+ foreach_in_collection each_inst_tmp $inst {
+ set each_inst [get_node_info -name $each_inst_tmp]
+ # Get the path to instance
+ regexp "(.*${from_path})(.*|)(${from_reg})" $each_inst reg_path inst_path inst_name reg_name
+
+ set_max_skew -from [get_registers ${inst_path}${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] $max_skew
+
+ set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] 100ns
+ set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] -100ns
+ }
+
+ } else {
+ # Relax the fitter effort
+ set_max_delay -from [get_registers *${from_path}|${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] 8ns
+ set_min_delay -from [get_registers *${from_path}|${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] -100ns
+ }
+
+}
+
+# Function to constraint clock crosser
+proc altera_eth_tse_constraint_clock_crosser {} {
+ set module_name altera_tse_clock_crosser
+
+ set from_reg1 in_data_toggle
+ set to_reg1 altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1
+
+ set from_reg2 in_data_buffer
+ set to_reg2 out_data_buffer
+
+ set from_reg3 out_data_toggle_flopped
+ set to_reg3 altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1
+
+ set max_skew 7.5ns
+
+ set max_delay1 6ns
+ set max_delay2 4ns
+ set max_delay3 6ns
+
+ # Check for clock crosser instances
+ set inst [get_registers -nowarn *${module_name}:*|${from_reg1}]
+
+ # Check number of instances
+ set inst_num [llength [query_collection -report -all $inst]]
+
+ # Apply constraint if clock crosser exist
+ if {$inst_num > 0} {
+
+ # Constraint one instance at a time to avoid set_max_skew apply to all instances
+ foreach_in_collection each_inst_tmp $inst {
+ set each_inst [get_node_info -name $each_inst_tmp]
+
+ # Get the path to instance
+ regexp "(.*${module_name})(:.*|)(${from_reg1})" $each_inst reg_path inst_path inst_name reg_name
+ # Check if data buffer of the clock crosser instance exists or get synthesized away
+ set reg2_collection [get_registers -nowarn ${inst_path}${inst_name}${to_reg2}[*]]
+ set reg2_num [llength [query_collection -report -all $reg2_collection]]
+
+ # Apply constraints common in both STA and FIT
+ set_net_delay -from [get_pins -compatibility_mode *${module_name}:*|${from_reg1}|q] -to [get_registers *${module_name}:*|${to_reg1}] -max $max_delay1
+ set_net_delay -from [get_pins -compatibility_mode *${module_name}:*|${from_reg3}|q] -to [get_registers *${module_name}:*|${to_reg3}] -max $max_delay3
+ if {$reg2_num > 0} {
+ set_net_delay -from [get_pins -compatibility_mode *${module_name}:*|${from_reg2}[*]|q] -to [get_registers *${module_name}:*|${to_reg2}[*]] -max $max_delay2
+ }
+
+ # Apply constraints specific to STA
+ if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
+ if {$reg2_num > 0} {
+ set_max_skew -from [get_registers "${inst_path}${inst_name}${from_reg1} ${inst_path}${inst_name}${from_reg2}[*]"] -to [get_registers "${inst_path}${inst_name}${to_reg1} ${inst_path}${inst_name}${to_reg2}[*]"] $max_skew
+
+ set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg2}[*]] -to [get_registers ${inst_path}${inst_name}${to_reg2}[*]] 100ns
+ set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg2}[*]] -to [get_registers ${inst_path}${inst_name}${to_reg2}[*]] -100ns
+ }
+
+ set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg1}] -to [get_registers ${inst_path}${inst_name}${to_reg1}] 100ns
+ set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg1}] -to [get_registers ${inst_path}${inst_name}${to_reg1}] -100ns
+
+ set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg3}] -to [get_registers ${inst_path}${inst_name}${to_reg3}] 100ns
+ set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg3}] -to [get_registers ${inst_path}${inst_name}${to_reg3}] -100ns
+
+ # Apply constraints specific to FIT
+ } else {
+ # Relax the fitter effort
+ set_max_delay -from [get_registers *${module_name}:*|${from_reg1}] -to [get_registers *${module_name}:*|${to_reg1}] 8ns
+ set_min_delay -from [get_registers *${module_name}:*|${from_reg1}] -to [get_registers *${module_name}:*|${to_reg1}] -100ns
+ if {$reg2_num > 0} {
+ set_max_delay -from [get_registers *${module_name}:*|${from_reg2}[*]] -to [get_registers *${module_name}:*|${to_reg2}[*]] 8ns
+ set_min_delay -from [get_registers *${module_name}:*|${from_reg2}[*]] -to [get_registers *${module_name}:*|${to_reg2}[*]] -100ns
+ }
+ set_max_delay -from [get_registers *${module_name}:*|${from_reg3}] -to [get_registers *${module_name}:*|${to_reg3}] 8ns
+ set_min_delay -from [get_registers *${module_name}:*|${from_reg3}] -to [get_registers *${module_name}:*|${to_reg3}] -100ns
+ }
+ }
+ }
+}
+
+# Constraint Standard Synchronizer
+altera_eth_tse_constraint_std_sync
+
+if {[expr $IS_SMALLMAC == 1]} {
+ # Small MAC
+ set_false_path -from [get_registers {*|altera_tse_register_map_small:U_REG|command_config[9]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map_small:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map_small:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+
+ set_false_path -from [get_registers {*|altera_tse_register_map_small:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map_small:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+} else {
+ # MAC with FIFO
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|command_config[9]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|frm_length[*]}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+
+ if {[expr ($ENABLE_SUP_ADDR == 1)]} {
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|command_config[16]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|command_config[17]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|command_config[18]}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_0*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_1*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_2*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_3*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_0*}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_1*}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_2*}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_3*}] -to [get_registers {*|altera_tse_mac_rx:U_RX|*}]
+
+ }
+
+ if {[expr ($ENABLE_MAC_FLOW_CTRL == 1)]} {
+ set_false_path -from [get_registers *|altera_tse_mac_rx:*|pause_quant_val*] -to [get_registers *|altera_tse_mac_tx:*|pause_latch*]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|pause_quant_reg*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|pause_quant_reg*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|holdoff_quant*}] -to [get_registers {*|altera_tse_mac_tx:U_TX|*}]
+ }
+
+ # Magic packet detection
+ if {[expr ($ENABLE_MAGIC_DETECT == 1)]} {
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_0[*]}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|mac_1[*]}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+
+ if {[expr ($ENABLE_SUP_ADDR == 1)]} {
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_0*}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_1*}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_2*}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+ set_false_path -from [get_registers {*|altera_tse_register_map:U_REG|smac_3*}] -to [get_registers {*|altera_tse_magic_detection:U_MAGIC|*}]
+ }
+ }
+
+ altera_eth_tse_constraint_clock_crosser
+
+}
+
+# FIFO at Avalon-ST user interface
+# The max skew and max net delay are set for maximum of 125 MHz for user clock domain
+# Transfer to user clock must be adjusted to smaller values if the user clock is running at clock faster than 125 MHz
+
+# From MAC TX Clock to TX User Clock
+altera_eth_tse_constraint_ptr altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_RD g_out altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:* din_s1 7.5ns 6ns
+# From TX User Clock to MAC TX Clock
+altera_eth_tse_constraint_ptr altera_tse_a_fifo_opt_1246:TX_DATA|altera_tse_gray_cnt:U_WRT g_out altera_tse_a_fifo_opt_1246:TX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:* din_s1 7.5ns 6ns
+
+# From RX User Clock to MAC RX Clock
+altera_eth_tse_constraint_ptr altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_RD g_out altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_1|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:* din_s1 7.5ns 6ns
+# From MAC RX Clock to RX User Clock
+altera_eth_tse_constraint_ptr altera_tse_a_fifo_opt_1246:RX_DATA|altera_tse_gray_cnt:U_WRT g_out altera_tse_a_fifo_opt_1246:RX_DATA|altera_eth_tse_std_synchronizer_bundle:U_SYNC_3|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:* din_s1 7.5ns 6ns
+
+# From TX User Clock to MAC TX Clock
+altera_eth_tse_constraint_ptr altera_tse_a_fifo_13:TX_STATUS|altera_tse_gray_cnt:U_WRT g_out altera_tse_a_fifo_13:TX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_2|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:* din_s1 7.5ns 6ns
+
+# From MAC RX Clock to RX User Clock
+altera_eth_tse_constraint_ptr altera_tse_a_fifo_34:RX_STATUS wr_g_ptr_reg altera_tse_a_fifo_34:RX_STATUS|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:* din_s1 7.5ns 6ns
+
+# GMII loopback
+if {[expr ($ENABLE_GMII_LOOPBACK == 1)]} {
+ altera_eth_tse_constraint_ptr altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_RD g_out altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_RD_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:* din_s1 7.5ns 6ns
+ altera_eth_tse_constraint_ptr altera_tse_a_fifo_24:U_LBFF|altera_tse_gray_cnt:U_WRT g_out altera_tse_a_fifo_24:U_LBFF|altera_eth_tse_std_synchronizer_bundle:U_SYNC_WR_G_PTR|altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:* din_s1 7.5ns 6ns
+}
+
+# Half duplex logic
+if {[expr ($ENABLE_HD_LOGIC == 1)]} {
+ if {[expr ($ENABLE_ENA == 8)]} {
+ set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+ set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+ set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+ set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [ get_registers *]
+ set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+ set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+ set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+ set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [ get_registers *]
+ set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|eop[1]]
+ set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|sop[1]]
+ set_max_delay 7.5 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_a_fifo_opt*:TX_DATA|altera_tse_altsyncram_dpm_fifo:U_RAM*|altsyncram*] -to [get_registers *|altera_tse_mac_tx:U_TX|rd_1[*]]
+ set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|*col*] -to [ get_registers *]
+ set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|*col*] -to [ get_registers *]
+ } else {
+ set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+ set_multicycle_path -setup 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+ set_multicycle_path -setup 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+ set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_altsyncram_dpm_fifo:U_RTSM|altsyncram*] -to [ get_registers *]
+ set_multicycle_path -hold 5 -from [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*] -to [ get_registers *]
+ set_multicycle_path -hold 5 -from [ get_registers *] -to [ get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|altera_tse_retransmit_cntl:U_RETR|*]
+ set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|dout_reg_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+ set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|eop_sft*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+ set_max_delay 7 -from [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_tx_min_ff:U_TXFF|sop_reg*] -to [get_registers *|altera_tse_top_w_fifo:U_MAC|altera_tse_top_1geth:U_GETH|altera_tse_mac_tx:U_TX|*]
+ }
+}
+
+#**************************************************************
+# Set False Path for altera_tse_reset_synchronizer
+#**************************************************************
+set tse_aclr_counter 0
+set tse_clrn_counter 0
+set tse_aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|aclr]
+set tse_clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|clrn]
+foreach_in_collection tse_aclr_pin $tse_aclr_collection {
+ set tse_aclr_counter [expr $tse_aclr_counter + 1]
+}
+foreach_in_collection tse_clrn_pin $tse_clrn_collection {
+ set tse_clrn_counter [expr $tse_clrn_counter + 1]
+}
+if {$tse_aclr_counter > 0} {
+ set_false_path -to [get_pins -compatibility_mode -nocase *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|aclr]
+}
+
+if {$tse_clrn_counter > 0} {
+ set_false_path -to [get_pins -compatibility_mode -nocase *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|clrn]
+}
+
+set_project_mode -always_show_entity_name $old_mode
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_mac.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_mac.v
new file mode 100644
index 0000000000000000000000000000000000000000..ac8f8472849ff896d44595a284caf6eaed4adaaa
Binary files /dev/null and b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_mac.v differ
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_ptp_std_synchronizer.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_ptp_std_synchronizer.v
new file mode 100644
index 0000000000000000000000000000000000000000..9de6cdc0ceaf9a38fa998e1749a00b1ef2f943d3
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_ptp_std_synchronizer.v
@@ -0,0 +1,40 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_eth_tse_ptp_std_synchronizer #(
+ parameter width = 1,
+ parameter depth = 3
+) (
+ input clk,
+ input reset_n,
+ input [width-1:0] din,
+ output [width-1:0] dout
+);
+
+genvar i;
+generate
+for (i = 0; i < width; i = i + 1) begin: nocut_sync
+ altera_std_synchronizer_nocut #(
+ .depth(depth)
+ ) std_sync_nocut (
+ .clk (clk),
+ .reset_n (reset_n),
+ .din (din[i]),
+ .dout (dout[i])
+ );
+end
+endgenerate
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_std_synchronizer.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_std_synchronizer.v
new file mode 100644
index 0000000000000000000000000000000000000000..d99ff9b59d1b3397a251874244d8d0a0db4d8ad7
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_std_synchronizer.v
@@ -0,0 +1,65 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+// START_FILE_HEADER ----------------------------------------------------------
+//
+// Filename : altera_eth_tse_std_synchronizer.v
+//
+// Description : Contains the simulation model for the altera_eth_tse_std_synchronizer
+//
+// Owner : Paul Scheidt
+//
+// Copyright (C) Altera Corporation 2008, All Rights Reserved
+//
+// END_FILE_HEADER ------------------------------------------------------------
+
+// START_MODULE_NAME-----------------------------------------------------------
+//
+// Module Name : altera_eth_tse_std_synchronizer
+//
+// Description : Single bit clock domain crossing synchronizer.
+// Composed of two or more flip flops connected in series.
+// Random metastable condition is simulated when the
+// __ALTERA_STD__METASTABLE_SIM macro is defined.
+// Use +define+__ALTERA_STD__METASTABLE_SIM argument
+// on the Verilog simulator compiler command line to
+// enable this mode. In addition, dfine the macro
+// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
+// with every metastable event generated in the synchronizer.
+//
+// Copyright (C) Altera Corporation 2009, All Rights Reserved
+// END_MODULE_NAME-------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_eth_tse_std_synchronizer #(
+ parameter depth = 3
+) (
+ input clk,
+ input reset_n,
+ input din,
+ output dout
+);
+
+ altera_std_synchronizer_nocut #(
+ .depth(depth)
+ ) std_sync_no_cut (
+ .clk (clk),
+ .reset_n (reset_n),
+ .din (din),
+ .dout (dout)
+ );
+
+endmodule
+
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_std_synchronizer_bundle.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_std_synchronizer_bundle.v
new file mode 100644
index 0000000000000000000000000000000000000000..1e62ffae8b975c3ccd80cb89a9ee3a8d7c76a087
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_eth_tse_std_synchronizer_bundle.v
@@ -0,0 +1,60 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Module Name : altera_eth_tse_std_synchronizer_bundle
+//
+// Description : Bundle of bit synchronizers.
+// WARNING: only use this to synchronize a bundle of
+// *independent* single bit signals or a Gray encoded
+// bus of signals. Also remember that pulses entering
+// the synchronizer will be swallowed upon a metastable
+// condition if the pulse width is shorter than twice
+// the synchronizing clock period.
+//
+
+`timescale 1 ps / 1 ps
+module altera_eth_tse_std_synchronizer_bundle (
+ clk,
+ reset_n,
+ din,
+ dout
+ );
+ // GLOBAL PARAMETER DECLARATION
+ parameter width = 1;
+ parameter depth = 3;
+
+ // INPUT PORT DECLARATION
+ input clk;
+ input reset_n;
+ input [width-1:0] din;
+
+ // OUTPUT PORT DECLARATION
+ output [width-1:0] dout;
+
+ generate
+ genvar i;
+ for (i=0; i<width; i=i+1)
+ begin : sync
+ altera_eth_tse_std_synchronizer #(.depth(depth))
+ u (
+ .clk(clk),
+ .reset_n(reset_n),
+ .din(din[i]),
+ .dout(dout[i])
+ );
+ end
+ endgenerate
+
+endmodule // altera_eth_tse_std_synchronizer_bundle
+// END OF MODULE
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_std_synchronizer_nocut.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_std_synchronizer_nocut.v
new file mode 100644
index 0000000000000000000000000000000000000000..547456984e65a6eea477d4c9749c288222f3c1e8
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_std_synchronizer_nocut.v
@@ -0,0 +1,195 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
+// $Revision: #8 $
+// $Date: 2009/02/18 $
+// $Author: pscheidt $
+//-----------------------------------------------------------------------------
+//
+// File: altera_std_synchronizer_nocut.v
+//
+// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
+// as altera_std_synchronizer.v, except that the embedded false
+// path constraint is removed in this module. If you use this
+// module, you will have to apply the appropriate timing
+// constraints.
+//
+// We expect to make this a standard Quartus atom eventually.
+//
+// Composed of two or more flip flops connected in series.
+// Random metastable condition is simulated when the
+// __ALTERA_STD__METASTABLE_SIM macro is defined.
+// Use +define+__ALTERA_STD__METASTABLE_SIM argument
+// on the Verilog simulator compiler command line to
+// enable this mode. In addition, define the macro
+// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
+// with every metastable event generated in the synchronizer.
+//
+// Copyright (C) Altera Corporation 2009, All Rights Reserved
+//-----------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_std_synchronizer_nocut (
+ clk,
+ reset_n,
+ din,
+ dout
+ );
+
+ parameter depth = 3; // This value must be >= 2 !
+ parameter rst_value = 0;
+
+ input clk;
+ input reset_n;
+ input din;
+ output dout;
+
+ // QuartusII synthesis directives:
+ // 1. Preserve all registers ie. do not touch them.
+ // 2. Do not merge other flip-flops with synchronizer flip-flops.
+ // QuartusII TimeQuest directives:
+ // 1. Identify all flip-flops in this module as members of the synchronizer
+ // to enable automatic metastability MTBF analysis.
+
+ (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
+
+ (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
+
+ //synthesis translate_off
+ initial begin
+ if (depth <2) begin
+ $display("%m: Error: synchronizer length: %0d less than 2.", depth);
+ end
+ end
+
+ // the first synchronizer register is either a simple D flop for synthesis
+ // and non-metastable simulation or a D flop with a method to inject random
+ // metastable events resulting in random delay of [0,1] cycles
+
+`ifdef __ALTERA_STD__METASTABLE_SIM
+
+ reg[31:0] RANDOM_SEED = 123456;
+ wire next_din_s1;
+ wire dout;
+ reg din_last;
+ reg random;
+ event metastable_event; // hook for debug monitoring
+
+ initial begin
+ $display("%m: Info: Metastable event injection simulation mode enabled");
+ end
+
+ always @(posedge clk) begin
+ if (reset_n == 0)
+ random <= $random(RANDOM_SEED);
+ else
+ random <= $random;
+ end
+
+ assign next_din_s1 = (din_last ^ din) ? random : din;
+
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_last <= (rst_value == 0)? 1'b0 : 1'b1;
+ else
+ din_last <= din;
+ end
+
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
+ else
+ din_s1 <= next_din_s1;
+ end
+
+`else
+
+ //synthesis translate_on
+ generate if (rst_value == 0)
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_s1 <= 1'b0;
+ else
+ din_s1 <= din;
+ end
+ endgenerate
+
+ generate if (rst_value == 1)
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_s1 <= 1'b1;
+ else
+ din_s1 <= din;
+ end
+ endgenerate
+ //synthesis translate_off
+
+`endif
+
+`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
+ always @(*) begin
+ if (reset_n && (din_last != din) && (random != din)) begin
+ $display("%m: Verbose Info: metastable event @ time %t", $time);
+ ->metastable_event;
+ end
+ end
+`endif
+
+ //synthesis translate_on
+
+ // the remaining synchronizer registers form a simple shift register
+ // of length depth-1
+ generate if (rst_value == 0)
+ if (depth < 3) begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b0}};
+ else
+ dreg <= din_s1;
+ end
+ end else begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b0}};
+ else
+ dreg <= {dreg[depth-3:0], din_s1};
+ end
+ end
+ endgenerate
+
+ generate if (rst_value == 1)
+ if (depth < 3) begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b1}};
+ else
+ dreg <= din_s1;
+ end
+ end else begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b1}};
+ else
+ dreg <= {dreg[depth-3:0], din_s1};
+ end
+ end
+ endgenerate
+
+ assign dout = dreg[depth-2];
+
+endmodule
+
+
+
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_false_path_marker.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_false_path_marker.v
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index 0000000000000000000000000000000000000000..f37df11b00c2b54a85aadb7dc28d091e9ae6d414
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_false_path_marker.v
@@ -0,0 +1,66 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+//
+// -----------------------------------------------
+// False path marker module
+// This module creates a level of flops for the
+// targetted clock, and cut the timing path to the
+// flops using embedded SDC constraint
+//
+// Only use this module to clock cross the path
+// that is being clock crossed properly by correct
+// concept.
+// -----------------------------------------------
+`timescale 1ns / 1ns
+
+module altera_tse_false_path_marker
+#(
+ parameter MARKER_WIDTH = 1
+)
+(
+ input reset,
+ input clk,
+ input [MARKER_WIDTH - 1 : 0] data_in,
+ output [MARKER_WIDTH - 1 : 0] data_out
+);
+
+(*preserve*) reg [MARKER_WIDTH - 1 : 0] data_out_reg;
+
+
+assign data_out = data_out_reg;
+
+always @(posedge clk or posedge reset)
+begin
+ if (reset)
+ begin
+ data_out_reg <= {MARKER_WIDTH{1'b0}};
+ end
+ else
+ begin
+ data_out_reg <= data_in;
+ end
+end
+
+endmodule
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_reset_synchronizer.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_reset_synchronizer.v
new file mode 100644
index 0000000000000000000000000000000000000000..18258fa0053db4adc3d33b0dfb433add671d3c67
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_reset_synchronizer.v
@@ -0,0 +1,100 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+// $Id: //acds/main/ip/merlin/altera_reset_controller/altera_tse_reset_synchronizer.v#7 $
+// $Revision: #7 $
+// $Date: 2010/04/27 $
+// $Author: jyeap $
+
+// -----------------------------------------------
+// Reset Synchronizer
+// -----------------------------------------------
+`timescale 1ns / 1ns
+
+module altera_tse_reset_synchronizer
+#(
+ parameter ASYNC_RESET = 1,
+ parameter DEPTH = 2
+)
+(
+ input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,R105\"" */,
+
+ input clk,
+ output reset_out
+);
+
+ // -----------------------------------------------
+ // Synchronizer register chain. We cannot reuse the
+ // standard synchronizer in this implementation
+ // because our timing constraints are different.
+ //
+ // Instead of cutting the timing path to the d-input
+ // on the first flop we need to cut the aclr input.
+ //
+ // We omit the "preserve" attribute on the final
+ // output register, so that the synthesis tool can
+ // duplicate it where needed.
+ // -----------------------------------------------
+ // Please check the false paths setting in TSE SDC
+
+ (*preserve*) reg [DEPTH-1:0] altera_tse_reset_synchronizer_chain;
+ reg altera_tse_reset_synchronizer_chain_out;
+
+ generate if (ASYNC_RESET) begin
+
+ // -----------------------------------------------
+ // Assert asynchronously, deassert synchronously.
+ // -----------------------------------------------
+ always @(posedge clk or posedge reset_in) begin
+ if (reset_in) begin
+ altera_tse_reset_synchronizer_chain <= {DEPTH{1'b1}};
+ altera_tse_reset_synchronizer_chain_out <= 1'b1;
+ end
+ else begin
+ altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
+ altera_tse_reset_synchronizer_chain[DEPTH-1] <= 0;
+ altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
+ end
+ end
+
+ assign reset_out = altera_tse_reset_synchronizer_chain_out;
+
+ end else begin
+
+ // -----------------------------------------------
+ // Assert synchronously, deassert synchronously.
+ // -----------------------------------------------
+ always @(posedge clk) begin
+ altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
+ altera_tse_reset_synchronizer_chain[DEPTH-1] <= reset_in;
+ altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
+ end
+
+ assign reset_out = altera_tse_reset_synchronizer_chain_out;
+
+ end
+ endgenerate
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_retransmit_cntl.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_retransmit_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..b5468800d8ed80baa61502b8cd890ec7dcb212b6
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_in1.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_in1.v
new file mode 100644
index 0000000000000000000000000000000000000000..40bf5846c1d2ac4f54cc76be12623b0ccf1a5a75
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_in1.v
@@ -0,0 +1,119 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// megafunction wizard: %ALTDDIO_IN%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_in
+
+// ============================================================
+// File Name: rgmii_in1.v
+// Megafunction Name(s):
+// altddio_in
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_in1 (
+ aclr,
+ datain,
+ inclock,
+ dataout_h,
+ dataout_l);
+
+ input aclr;
+ input datain;
+ input inclock;
+ output dataout_h;
+ output dataout_l;
+
+ wire [0:0] sub_wire0;
+ wire [0:0] sub_wire2;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire dataout_h = sub_wire1;
+ wire [0:0] sub_wire3 = sub_wire2[0:0];
+ wire dataout_l = sub_wire3;
+ wire sub_wire4 = datain;
+ wire sub_wire5 = sub_wire4;
+
+ altddio_in altddio_in_component (
+ .datain (sub_wire5),
+ .inclock (inclock),
+ .aclr (aclr),
+ .dataout_h (sub_wire0),
+ .dataout_l (sub_wire2),
+ .aset (1'b0),
+ .inclocken (1'b1));
+ defparam
+ altddio_in_component.intended_device_family = "Stratix II",
+ altddio_in_component.invert_input_clocks = "OFF",
+ altddio_in_component.lpm_type = "altddio_in",
+ altddio_in_component.width = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain 0 0 0 0 INPUT NODEFVAL datain
+// Retrieval info: USED_PORT: dataout_h 0 0 0 0 OUTPUT NODEFVAL dataout_h
+// Retrieval info: USED_PORT: dataout_l 0 0 0 0 OUTPUT NODEFVAL dataout_l
+// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
+// Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 0 0
+// Retrieval info: CONNECT: dataout_h 0 0 0 0 @dataout_h 0 0 1 0
+// Retrieval info: CONNECT: dataout_l 0 0 0 0 @dataout_l 0 0 1 0
+// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in1_bb.v TRUE
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_in4.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_in4.v
new file mode 100644
index 0000000000000000000000000000000000000000..f70ab7fcde9a81ccfde8c237be994faf775bbfb0
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_in4.v
@@ -0,0 +1,115 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// megafunction wizard: %ALTDDIO_IN%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_in
+
+// ============================================================
+// File Name: rgmii_in4.v
+// Megafunction Name(s):
+// altddio_in
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_in4 (
+ aclr,
+ datain,
+ inclock,
+ dataout_h,
+ dataout_l);
+
+ input aclr;
+ input [3:0] datain;
+ input inclock;
+ output [3:0] dataout_h;
+ output [3:0] dataout_l;
+
+ wire [3:0] sub_wire0;
+ wire [3:0] sub_wire1;
+ wire [3:0] dataout_h = sub_wire0[3:0];
+ wire [3:0] dataout_l = sub_wire1[3:0];
+
+ altddio_in altddio_in_component (
+ .datain (datain),
+ .inclock (inclock),
+ .aclr (aclr),
+ .dataout_h (sub_wire0),
+ .dataout_l (sub_wire1),
+ .aset (1'b0),
+ .inclocken (1'b1));
+ defparam
+ altddio_in_component.intended_device_family = "Stratix II",
+ altddio_in_component.invert_input_clocks = "OFF",
+ altddio_in_component.lpm_type = "altddio_in",
+ altddio_in_component.width = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INVERT_INPUT_CLOCKS NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: INVERT_INPUT_CLOCKS STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_in"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL datain[3..0]
+// Retrieval info: USED_PORT: dataout_h 0 0 4 0 OUTPUT NODEFVAL dataout_h[3..0]
+// Retrieval info: USED_PORT: dataout_l 0 0 4 0 OUTPUT NODEFVAL dataout_l[3..0]
+// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
+// Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
+// Retrieval info: CONNECT: dataout_h 0 0 4 0 @dataout_h 0 0 4 0
+// Retrieval info: CONNECT: dataout_l 0 0 4 0 @dataout_l 0 0 4 0
+// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_in4_bb.v TRUE
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_module.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_module.v
new file mode 100644
index 0000000000000000000000000000000000000000..1cd5d3f80e1783a865d0ed399768b1a7161617ec
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_module.v
@@ -0,0 +1,302 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_rgmii_module.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/MAC/mac/rgmii/altera_tse_rgmii_module.v,v $
+//
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// Check in by : $Author: psgswbuild $
+// Author : Arul Paniandi
+//
+// Project : Triple Speed Ethernet - 10/100/1000 MAC
+//
+// Description :
+//
+// Top level RGMII interface (receive and transmit) module.
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2006 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+// synthesis translate_off
+`timescale 1ns / 100ps
+// synthesis translate_on
+module altera_tse_rgmii_module /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D103\"" */ ( // new ports to cater for mii with RGMII interface are added
+ // inputs
+ rgmii_in,
+ speed,
+ //data
+ gm_tx_d,
+ m_tx_d,
+
+ //control
+ gm_tx_en,
+ m_tx_en,
+
+ gm_tx_err,
+ m_tx_err,
+
+ reset_rx_clk,
+ reset_tx_clk,
+ rx_clk,
+ rx_control,
+ tx_clk,
+
+ // outputs:
+ rgmii_out,
+
+ gm_rx_d,
+ m_rx_d,
+
+ gm_rx_dv,
+ m_rx_en,
+
+
+ gm_rx_err,
+ m_rx_err,
+
+ m_rx_col,
+ m_rx_crs,
+ tx_control
+ );
+
+ parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
+
+ output [ 3: 0] rgmii_out;
+ output [ 7: 0] gm_rx_d;
+ output [ 3: 0] m_rx_d;
+ output gm_rx_dv;
+ output m_rx_en;
+ output gm_rx_err;
+ output m_rx_err;
+ output m_rx_col;
+ output m_rx_crs;
+ output tx_control;
+
+ input [ 3: 0] rgmii_in;
+ input speed;
+ input [ 7: 0] gm_tx_d;
+ input [ 3: 0] m_tx_d;
+ input gm_tx_en;
+ input m_tx_en;
+ input gm_tx_err;
+ input m_tx_err;
+ input reset_rx_clk;
+ input reset_tx_clk;
+ input rx_clk;
+ input rx_control;
+ input tx_clk;
+
+ wire [ 3: 0] rgmii_out;
+ wire [ 7: 0] gm_rx_d;
+ wire gm_rx_dv;
+ wire m_rx_en;
+ wire gm_rx_err;
+ wire m_rx_err;
+ wire m_rx_col;
+ reg m_rx_col_reg;
+ reg m_rx_crs;
+
+ reg rx_dv;
+ reg rx_err;
+ wire tx_control;
+ //wire tx_err;
+ reg [ 7: 0] rgmii_out_4_wire;
+ reg rgmii_out_1_wire_inp1;
+ reg rgmii_out_1_wire_inp2;
+
+ wire [ 7:0 ] rgmii_in_4_wire;
+ reg [ 7:0 ] rgmii_in_4_reg;
+ reg [ 7:0 ] rgmii_in_4_temp_reg;
+ wire [ 1:0 ] rgmii_in_1_wire;
+ reg [ 1:0 ] rgmii_in_1_temp_reg;
+
+ wire speed_reg;
+
+ reg m_tx_en_reg1;
+ reg m_tx_en_reg2;
+ reg m_tx_en_reg3;
+ reg m_tx_en_reg4;
+
+ assign gm_rx_d = rgmii_in_4_reg;
+ assign m_rx_d = rgmii_in_4_reg[3:0]; // mii is only 4 bits, data are duplicated so we only take one nibble
+
+ altera_tse_rgmii_in4 the_rgmii_in4
+ (
+ .aclr (), //INPUT
+ .datain (rgmii_in), //INPUT
+ .dataout_h (rgmii_in_4_wire[7 : 4]), //OUTPUT
+ .dataout_l (rgmii_in_4_wire[3 : 0]), //OUTPUT
+ .inclock (rx_clk) //OUTPUT
+ );
+
+
+ altera_tse_rgmii_in1 the_rgmii_in1
+ (
+ .aclr (), //INPUT
+ .datain (rx_control), //INPUT
+ .dataout_h (rgmii_in_1_wire[1]), //INPUT rx_err
+ .dataout_l (rgmii_in_1_wire[0]), //OUTPUT rx_dv
+ .inclock (rx_clk) //OUTPUT
+ );
+
+
+always @(posedge rx_clk or posedge reset_rx_clk)
+ begin
+ if (reset_rx_clk == 1'b1) begin
+ rgmii_in_4_temp_reg <= {8{1'b0}};
+ rgmii_in_1_temp_reg <= {2{1'b0}};
+ end
+ else begin
+ rgmii_in_4_temp_reg <= rgmii_in_4_wire;
+ rgmii_in_1_temp_reg <= rgmii_in_1_wire;
+ end
+ end
+
+
+always @(posedge rx_clk or posedge reset_rx_clk)
+ begin
+ if (reset_rx_clk == 1'b1) begin
+ rgmii_in_4_reg <= {8{1'b0}};
+ rx_err <= 1'b0;
+ rx_dv <= 1'b0;
+ end
+ else begin
+ rgmii_in_4_reg <= {rgmii_in_4_wire[3:0], rgmii_in_4_temp_reg[7:4]};
+ rx_err <= rgmii_in_1_wire[0];
+ rx_dv <= rgmii_in_1_temp_reg[1];
+ end
+ end
+
+
+always @(rx_dv or rx_err or rgmii_in_4_reg)
+ begin
+ m_rx_crs = 1'b0;
+ if ((rx_dv == 1'b1) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'hFF ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0E ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h0F ) || (rx_dv == 1'b0 && rx_err == 1'b1 && rgmii_in_4_reg == 8'h1F ) )
+ begin
+ m_rx_crs = 1'b1; // read RGMII specification data sheet , table 4 for the conditions where CRS should go high
+ end
+ end
+
+always @(posedge tx_clk or posedge reset_tx_clk)
+begin
+ if(reset_tx_clk == 1'b1)
+ begin
+ m_tx_en_reg1 <= 1'b0;
+ m_tx_en_reg2 <= 1'b0;
+ m_tx_en_reg3 <= 1'b0;
+ m_tx_en_reg4 <= 1'b0;
+
+ end
+ else
+ begin
+ m_tx_en_reg1 <= m_tx_en;
+ m_tx_en_reg2 <= m_tx_en_reg1;
+ m_tx_en_reg3 <= m_tx_en_reg2;
+ m_tx_en_reg4 <= m_tx_en_reg3;
+ end
+
+end
+
+
+
+always @(m_tx_en_reg4 or m_rx_crs or rx_dv)
+begin
+ m_rx_col_reg = 1'b0;
+ if ( m_tx_en_reg4 == 1'b1 & (m_rx_crs == 1'b1 | rx_dv == 1'b1))
+ begin
+ m_rx_col_reg = 1'b1;
+ end
+end
+
+altera_eth_tse_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_1(
+ .clk(tx_clk), // INPUT
+ .reset_n(~reset_tx_clk), //INPUT
+ .din(m_rx_col_reg), //INPUT
+ .dout(m_rx_col));// OUTPUT
+
+altera_eth_tse_std_synchronizer #(SYNCHRONIZER_DEPTH) U_SYNC_2(
+ .clk(tx_clk), // INPUT
+ .reset_n(~reset_tx_clk), //INPUT
+ .din(speed), //INPUT
+ .dout(speed_reg));// OUTPUT
+
+
+ assign gm_rx_err = rx_err ^ rx_dv;
+ assign gm_rx_dv = rx_dv;
+
+ assign m_rx_err = rx_err ^ rx_dv;
+ assign m_rx_en = rx_dv;
+
+ // mux for Out 4
+ always @(*)
+ begin
+ case (speed_reg)
+ 1'b1: rgmii_out_4_wire = gm_tx_d;
+ 1'b0: rgmii_out_4_wire = {m_tx_d,m_tx_d};
+ endcase
+ end
+
+ // mux for Out 1
+ always @(*)
+ begin
+ case (speed_reg)
+ 1'b1:
+ begin
+ rgmii_out_1_wire_inp1 = gm_tx_en; // gigabit
+ rgmii_out_1_wire_inp2 = gm_tx_en ^ gm_tx_err;
+ end
+ 1'b0:
+ begin
+ rgmii_out_1_wire_inp1 = m_tx_en;
+ rgmii_out_1_wire_inp2 = m_tx_en ^ m_tx_err;
+ end
+ endcase
+ end
+
+
+ altera_tse_rgmii_out4 the_rgmii_out4
+ (
+ .aclr (reset_tx_clk), //INPUT
+ .datain_h (rgmii_out_4_wire[3 : 0]), //INPUT
+ .datain_l (rgmii_out_4_wire[7 : 4]), //INPUT
+ .dataout (rgmii_out), //INPUT
+ .outclock (tx_clk) //OUTPUT
+ );
+
+
+ //assign tx_err = gm_tx_en ^ gm_tx_err;
+
+ altera_tse_rgmii_out1 the_rgmii_out1
+ (
+ .aclr (reset_tx_clk), //INPUT
+ .datain_h (rgmii_out_1_wire_inp1), //INPUT
+ .datain_l (rgmii_out_1_wire_inp2), //INPUT
+ .dataout (tx_control), //INPUT
+ .outclock (tx_clk) //OUTPUT
+ );
+
+
+
+endmodule
+
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_out1.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_out1.v
new file mode 100644
index 0000000000000000000000000000000000000000..7be26eb1f65cf38192b35d78c9409ac27edf3061
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_out1.v
@@ -0,0 +1,123 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// megafunction wizard: %ALTDDIO_OUT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_out
+
+// ============================================================
+// File Name: rgmii_out1.v
+// Megafunction Name(s):
+// altddio_out
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_out1 (
+ aclr,
+ datain_h,
+ datain_l,
+ outclock,
+ dataout);
+
+ input aclr;
+ input datain_h;
+ input datain_l;
+ input outclock;
+ output dataout;
+
+ wire [0:0] sub_wire0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire dataout = sub_wire1;
+ wire sub_wire2 = datain_h;
+ wire sub_wire3 = sub_wire2;
+ wire sub_wire4 = datain_l;
+ wire sub_wire5 = sub_wire4;
+
+ altddio_out altddio_out_component (
+ .outclock (outclock),
+ .datain_h (sub_wire3),
+ .aclr (aclr),
+ .datain_l (sub_wire5),
+ .dataout (sub_wire0),
+ .aset (1'b0),
+ .oe (1'b1),
+ .outclocken (1'b1));
+ defparam
+ altddio_out_component.extend_oe_disable = "UNUSED",
+ altddio_out_component.intended_device_family = "Stratix II",
+ altddio_out_component.lpm_type = "altddio_out",
+ altddio_out_component.oe_reg = "UNUSED",
+ altddio_out_component.width = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: OE NUMERIC "0"
+// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
+// Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
+// Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
+// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
+// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
+// Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
+// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out1_bb.v TRUE
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_out4.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_out4.v
new file mode 100644
index 0000000000000000000000000000000000000000..df8c986e3693d47f929c2cf1183b82f4c1d123eb
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rgmii_out4.v
@@ -0,0 +1,118 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// megafunction wizard: %ALTDDIO_OUT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altddio_out
+
+// ============================================================
+// File Name: rgmii_out4.v
+// Megafunction Name(s):
+// altddio_out
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 6.0 Build 176 04/19/2006 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module altera_tse_rgmii_out4 (
+ aclr,
+ datain_h,
+ datain_l,
+ outclock,
+ dataout);
+
+ input aclr;
+ input [3:0] datain_h;
+ input [3:0] datain_l;
+ input outclock;
+ output [3:0] dataout;
+
+ wire [3:0] sub_wire0;
+ wire [3:0] dataout = sub_wire0[3:0];
+
+ altddio_out altddio_out_component (
+ .outclock (outclock),
+ .datain_h (datain_h),
+ .aclr (aclr),
+ .datain_l (datain_l),
+ .dataout (sub_wire0),
+ .aset (1'b0),
+ .oe (1'b1),
+ .outclocken (1'b1));
+ defparam
+ altddio_out_component.extend_oe_disable = "UNUSED",
+ altddio_out_component.intended_device_family = "Stratix II",
+ altddio_out_component.lpm_type = "altddio_out",
+ altddio_out_component.oe_reg = "UNUSED",
+ altddio_out_component.width = 4;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "0"
+// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: PRIVATE: OE NUMERIC "0"
+// Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+// Retrieval info: PRIVATE: WIDTH NUMERIC "4"
+// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+// Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+// Retrieval info: CONSTANT: WIDTH NUMERIC "4"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
+// Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
+// Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
+// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+// Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
+// Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
+// Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
+// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4.bsf TRUE FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rgmii_out4_bb.v TRUE
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_counter_cntl.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_counter_cntl.v
new file mode 100644
index 0000000000000000000000000000000000000000..051a03f3a9bcaac7cf9a239d6de8a89d7cccd7a0
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_ff.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_ff.v
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index 0000000000000000000000000000000000000000..90c9e69ffe8a586af9780639399d9ecb56ca783a
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_ff_cntrl.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_ff_cntrl.v
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index 0000000000000000000000000000000000000000..ece2634012ff2a7b3fe0860cfe28d20039b7cac2
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_ff_cntrl_32.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_ff_cntrl_32.v
new file mode 100644
index 0000000000000000000000000000000000000000..9c5d121fb28febb80976687e90a1a50bf5267bfe
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_ff_cntrl_32_shift16.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_ff_cntrl_32_shift16.v
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index 0000000000000000000000000000000000000000..bad5519e04f332e4b02ccbea5865db6089392c8f
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_ff_length.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_ff_length.v
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index 0000000000000000000000000000000000000000..736d61cdb88e8104d03b03d639c99571adce9712
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_min_ff.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_min_ff.v
new file mode 100644
index 0000000000000000000000000000000000000000..c4632e8204f30dadf45a0dc8f304b5de274d2efc
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_stat_extract.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_rx_stat_extract.v
new file mode 100644
index 0000000000000000000000000000000000000000..8d27d02f477f662d9f6834ab654fcc9d3105dacf
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_sdpm_altsyncram.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_sdpm_altsyncram.v
new file mode 100644
index 0000000000000000000000000000000000000000..717bc7cd238c9a4be33fa687865a3a4945275bb9
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_sdpm_gen.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_sdpm_gen.v
new file mode 100644
index 0000000000000000000000000000000000000000..9a1d96d2a42448d5e950386a03d2b0fe5c5899e6
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_shared_mac_control.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_shared_mac_control.v
new file mode 100644
index 0000000000000000000000000000000000000000..6f9047f03c96317fb962ef42f0b9a171e4922615
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_shared_register_map.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_shared_register_map.v
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index 0000000000000000000000000000000000000000..ff21a2986db3c2e6ff37e829fe743b9dd68940bc
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_timing_adapter32.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_timing_adapter32.v
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index 0000000000000000000000000000000000000000..62db57fd209609df21ff3831e63bff9fb3ab2e53
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_timing_adapter8.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_timing_adapter8.v
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index 0000000000000000000000000000000000000000..2b5419185b3a1e1408b0e2d1ab9061e0a2a935aa
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_timing_adapter_fifo32.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_timing_adapter_fifo32.v
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index 0000000000000000000000000000000000000000..9f67e0c8df90f151075ae556b667ecdbd42b1049
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_timing_adapter_fifo8.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_timing_adapter_fifo8.v
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index 0000000000000000000000000000000000000000..37135ae4f663409ef3a4dd5ea67760ee14190bbf
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_1geth.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_1geth.v
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_gen_host.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_gen_host.v
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_mdio.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_mdio.v
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_w_fifo.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_w_fifo.v
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_w_fifo_10_100_1000.ocp b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_w_fifo_10_100_1000.ocp
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_wo_fifo.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_wo_fifo.v
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_wo_fifo_10_100_1000.ocp b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_top_wo_fifo_10_100_1000.ocp
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_tx_min_ff.v b/quartus/qsys/arria10_hps/altera_eth_tse_mac_221/synth/altera_tse_tx_min_ff.v
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_nf_phyip_terminator_221/synth/altera_eth_tse_nf_phyip_terminator.v b/quartus/qsys/arria10_hps/altera_eth_tse_nf_phyip_terminator_221/synth/altera_eth_tse_nf_phyip_terminator.v
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_pcs_pma_nf_phyip.sdc b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_pcs_pma_nf_phyip.sdc
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index 0000000000000000000000000000000000000000..e8bbbe90445db24ce4c60bf81c25462339c7a528
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_pcs_pma_nf_phyip.sdc
@@ -0,0 +1,216 @@
+# (C) 2001-2023 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any output
+# files from any of the foregoing (including device programming or simulation
+# files), and any associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License Subscription
+# Agreement, Intel FPGA IP License Agreement, or other applicable
+# license agreement, including, without limitation, that your use is for the
+# sole purpose of programming logic devices manufactured by Intel and sold by
+# Intel or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+
+# CORE_PARAMETERS
+set IS_SGMII 1
+set CONNECT_TO_MAC 1
+set IS_INT_FIFO 1
+set IS_HD_LOGIC 0
+set ENABLE_TIMESTAMPING 0
+
+set old_mode [set_project_mode -get_mode_value always_show_entity_name]
+set_project_mode -always_show_entity_name on
+
+# Function to constraint non-std_synchronizer path
+proc altera_eth_tse_constraint_net_delay {from_reg to_reg max_net_delay} {
+
+ set_net_delay -from [get_pins -compatibility_mode ${from_reg}|q] -to [get_registers ${to_reg}] -max $max_net_delay
+
+ if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
+ set_max_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] 100ns
+ set_min_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] -100ns
+ } else {
+ # Relax the fitter effort
+ set_max_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] 8ns
+ set_min_delay -from [get_registers ${from_reg}] -to [get_registers ${to_reg}] -100ns
+ }
+
+}
+
+# Function to constraint std_synchronizer
+proc altera_eth_tse_constraint_std_sync {} {
+
+ altera_eth_tse_constraint_net_delay * *altera_eth_tse_std_synchronizer:*|altera_std_synchronizer_nocut:*|din_s1 6ns
+
+}
+
+# Function to constraint pointers
+proc altera_eth_tse_constraint_ptr {from_path from_reg to_path to_reg max_skew max_net_delay} {
+
+ set_net_delay -from [get_pins -compatibility_mode *${from_path}|${from_reg}[*]|q] -to [get_registers *${to_path}|${to_reg}*] -max $max_net_delay
+
+ if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
+ # Check for instances
+ set inst [get_registers -nowarn *${from_path}|${from_reg}\[0\]]
+
+ # Check number of instances
+ set inst_num [llength [query_collection -report -all $inst]]
+ if {$inst_num > 0} {
+ # Uncomment line below for debug purpose
+ #puts "${inst_num} ${from_path}|${from_reg} instance(s) found"
+ } else {
+ # Uncomment line below for debug purpose
+ #puts "No ${from_path}|${from_reg} instance found"
+ }
+
+ # Constraint one instance at a time to avoid set_max_skew apply to all instances
+ foreach_in_collection each_inst_tmp $inst {
+ set each_inst [get_node_info -name $each_inst_tmp]
+ # Get the path to instance
+ regexp "(.*${from_path})(.*|)(${from_reg})" $each_inst reg_path inst_path inst_name reg_name
+
+ set_max_skew -from [get_registers ${inst_path}${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] $max_skew
+
+ set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] 100ns
+ set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] -100ns
+ }
+
+ } else {
+ # Relax the fitter effort
+ set_max_delay -from [get_registers *${from_path}|${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] 8ns
+ set_min_delay -from [get_registers *${from_path}|${from_reg}[*]] -to [get_registers *${to_path}|${to_reg}*] -100ns
+ }
+
+}
+
+# Function to constraint clock crosser
+proc altera_eth_tse_constraint_clock_crosser {} {
+ set module_name altera_tse_clock_crosser
+
+ set from_reg1 in_data_toggle
+ set to_reg1 altera_eth_tse_std_synchronizer:in_to_out_synchronizer|altera_std_synchronizer_nocut:*|din_s1
+
+ set from_reg2 in_data_buffer
+ set to_reg2 out_data_buffer
+
+ set from_reg3 out_data_toggle_flopped
+ set to_reg3 altera_eth_tse_std_synchronizer:out_to_in_synchronizer|altera_std_synchronizer_nocut:*|din_s1
+
+ set max_skew 7.5ns
+
+ set max_delay1 6ns
+ set max_delay2 4ns
+ set max_delay3 6ns
+
+ set_net_delay -from [get_pins -compatibility_mode *${module_name}:*|${from_reg1}|q] -to [get_registers *${module_name}:*|${to_reg1}] -max $max_delay1
+ set_net_delay -from [get_pins -compatibility_mode *${module_name}:*|${from_reg2}[*]|q] -to [get_registers *${module_name}:*|${to_reg2}[*]] -max $max_delay2
+ set_net_delay -from [get_pins -compatibility_mode *${module_name}:*|${from_reg3}|q] -to [get_registers *${module_name}:*|${to_reg3}] -max $max_delay3
+
+ if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
+ # Check for instances
+ set inst [get_registers -nowarn *${module_name}:*|${from_reg1}]
+
+ # Check number of instances
+ set inst_num [llength [query_collection -report -all $inst]]
+ if {$inst_num > 0} {
+ # Uncomment line below for debug purpose
+ #puts "${inst_num} ${module_name} instance(s) found"
+ } else {
+ # Uncomment line below for debug purpose
+ #puts "No ${module_name} instance found"
+ }
+
+ # Constraint one instance at a time to avoid set_max_skew apply to all instances
+ foreach_in_collection each_inst_tmp $inst {
+ set each_inst [get_node_info -name $each_inst_tmp]
+ # Get the path to instance
+ regexp "(.*${module_name})(:.*|)(${from_reg1})" $each_inst reg_path inst_path inst_name reg_name
+
+ # Check if unused data buffer get synthesized away
+ set reg2_collection [get_registers -nowarn ${inst_path}${inst_name}${to_reg2}[*]]
+ set reg2_num [llength [query_collection -report -all $reg2_collection]]
+
+ if {$reg2_num > 0} {
+ set_max_skew -from [get_registers "${inst_path}${inst_name}${from_reg1} ${inst_path}${inst_name}${from_reg2}[*]"] -to [get_registers "${inst_path}${inst_name}${to_reg1} ${inst_path}${inst_name}${to_reg2}[*]"] $max_skew
+
+ set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg2}[*]] -to [get_registers ${inst_path}${inst_name}${to_reg2}[*]] 100ns
+ set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg2}[*]] -to [get_registers ${inst_path}${inst_name}${to_reg2}[*]] -100ns
+ }
+
+ set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg1}] -to [get_registers ${inst_path}${inst_name}${to_reg1}] 100ns
+ set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg1}] -to [get_registers ${inst_path}${inst_name}${to_reg1}] -100ns
+
+ set_max_delay -from [get_registers ${inst_path}${inst_name}${from_reg3}] -to [get_registers ${inst_path}${inst_name}${to_reg3}] 100ns
+ set_min_delay -from [get_registers ${inst_path}${inst_name}${from_reg3}] -to [get_registers ${inst_path}${inst_name}${to_reg3}] -100ns
+ }
+
+ } else {
+ # Relax the fitter effort
+ set_max_delay -from [get_registers *${module_name}:*|${from_reg1}] -to [get_registers *${module_name}:*|${to_reg1}] 8ns
+ set_min_delay -from [get_registers *${module_name}:*|${from_reg1}] -to [get_registers *${module_name}:*|${to_reg1}] -100ns
+
+ set_max_delay -from [get_registers *${module_name}:*|${from_reg2}[*]] -to [get_registers *${module_name}:*|${to_reg2}[*]] 8ns
+ set_min_delay -from [get_registers *${module_name}:*|${from_reg2}[*]] -to [get_registers *${module_name}:*|${to_reg2}[*]] -100ns
+
+ set_max_delay -from [get_registers *${module_name}:*|${from_reg3}] -to [get_registers *${module_name}:*|${to_reg3}] 8ns
+ set_min_delay -from [get_registers *${module_name}:*|${from_reg3}] -to [get_registers *${module_name}:*|${to_reg3}] -100ns
+ }
+
+}
+
+# Constraint Standard Synchronizer
+altera_eth_tse_constraint_std_sync
+
+if { [ expr ($IS_SGMII == 1)] } {
+ altera_eth_tse_constraint_ptr altera_tse_a_fifo_24:*|altera_tse_gray_cnt:U_RD g_out altera_tse_a_fifo_24:*altera_std_synchronizer_nocut:* din_s1 7.5ns 6ns
+ altera_eth_tse_constraint_ptr altera_tse_a_fifo_24:*|altera_tse_gray_cnt:U_WRT g_out altera_tse_a_fifo_24:*altera_std_synchronizer_nocut:* din_s1 7.5ns 6ns
+
+ if {[expr ($CONNECT_TO_MAC == 1)]} {
+ if {[expr ($IS_INT_FIFO == 0)]} {
+ if {[expr ($IS_HD_LOGIC == 1)]} {
+ altera_eth_tse_constraint_net_delay *altera_tse_top_sgmii*:U_SGMII|altera_tse_colision_detect:U_COL|state* *altera_tse_fifoless_mac_tx:U_TX|gm_rx_col_reg* 6ns
+ }
+ }
+ }
+}
+
+if {[expr ($ENABLE_TIMESTAMPING == 1)]} {
+ set regs [get_registers -nowarn *altera_tse_ph_calculator:*|altera_eth_tse_ptp_std_synchronizer:U_SYNC_WR_PTR|altera_std_synchronizer_nocut:*|din_s1]
+ if {[llength [query_collection -report -all $regs]] > 0} {
+ altera_eth_tse_constraint_ptr altera_tse_ph_calculator:phase_calculator.ph_cal_inst wr_ptr_sample altera_tse_ph_calculator:*|altera_eth_tse_ptp_std_synchronizer:U_SYNC_WR_PTR|altera_std_synchronizer_nocut:* din_s1 4.5ns 3ns
+ }
+
+ set regs [get_registers -nowarn *altera_tse_ph_calculator:*|altera_eth_tse_ptp_std_synchronizer:U_SYNC_RD_PTR|altera_std_synchronizer_nocut:*|din_s1]
+ if {[llength [query_collection -report -all $regs]] > 0} {
+ altera_eth_tse_constraint_ptr altera_tse_ph_calculator:phase_calculator.ph_cal_inst rd_ptr_sample altera_tse_ph_calculator:*|altera_eth_tse_ptp_std_synchronizer:U_SYNC_RD_PTR|altera_std_synchronizer_nocut:* din_s1 4.5ns 3ns
+ }
+}
+
+# Clock Crosser
+altera_eth_tse_constraint_clock_crosser
+
+# False path marker used in auto negotiation module
+altera_eth_tse_constraint_net_delay * *altera_tse_false_path_marker:*|data_out_reg* 6ns
+
+#**************************************************************
+# Set False Path for altera_tse_reset_synchronizer
+#**************************************************************
+set tse_aclr_counter 0
+set tse_clrn_counter 0
+set tse_aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|aclr]
+set tse_clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|clrn]
+foreach_in_collection tse_aclr_pin $tse_aclr_collection {
+ set tse_aclr_counter [expr $tse_aclr_counter + 1]
+}
+foreach_in_collection tse_clrn_pin $tse_clrn_collection {
+ set tse_clrn_counter [expr $tse_clrn_counter + 1]
+}
+if {$tse_aclr_counter > 0} {
+ set_false_path -to [get_pins -compatibility_mode -nocase *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|aclr]
+}
+
+if {$tse_clrn_counter > 0} {
+ set_false_path -to [get_pins -compatibility_mode -nocase *|altera_tse_reset_synchronizer:*|altera_tse_reset_synchronizer_chain*|clrn]
+}
+
+set_project_mode -always_show_entity_name $old_mode
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_pcs_pma_nf_phyip.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_pcs_pma_nf_phyip.v
new file mode 100644
index 0000000000000000000000000000000000000000..f8bf55defbe0b6d01a851cc80dc92ff75a1a8f0b
Binary files /dev/null and b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_pcs_pma_nf_phyip.v differ
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_ptp_std_synchronizer.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_ptp_std_synchronizer.v
new file mode 100644
index 0000000000000000000000000000000000000000..9de6cdc0ceaf9a38fa998e1749a00b1ef2f943d3
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_ptp_std_synchronizer.v
@@ -0,0 +1,40 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ns / 1ns
+
+module altera_eth_tse_ptp_std_synchronizer #(
+ parameter width = 1,
+ parameter depth = 3
+) (
+ input clk,
+ input reset_n,
+ input [width-1:0] din,
+ output [width-1:0] dout
+);
+
+genvar i;
+generate
+for (i = 0; i < width; i = i + 1) begin: nocut_sync
+ altera_std_synchronizer_nocut #(
+ .depth(depth)
+ ) std_sync_nocut (
+ .clk (clk),
+ .reset_n (reset_n),
+ .din (din[i]),
+ .dout (dout[i])
+ );
+end
+endgenerate
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_std_synchronizer.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_std_synchronizer.v
new file mode 100644
index 0000000000000000000000000000000000000000..d99ff9b59d1b3397a251874244d8d0a0db4d8ad7
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_std_synchronizer.v
@@ -0,0 +1,65 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+// START_FILE_HEADER ----------------------------------------------------------
+//
+// Filename : altera_eth_tse_std_synchronizer.v
+//
+// Description : Contains the simulation model for the altera_eth_tse_std_synchronizer
+//
+// Owner : Paul Scheidt
+//
+// Copyright (C) Altera Corporation 2008, All Rights Reserved
+//
+// END_FILE_HEADER ------------------------------------------------------------
+
+// START_MODULE_NAME-----------------------------------------------------------
+//
+// Module Name : altera_eth_tse_std_synchronizer
+//
+// Description : Single bit clock domain crossing synchronizer.
+// Composed of two or more flip flops connected in series.
+// Random metastable condition is simulated when the
+// __ALTERA_STD__METASTABLE_SIM macro is defined.
+// Use +define+__ALTERA_STD__METASTABLE_SIM argument
+// on the Verilog simulator compiler command line to
+// enable this mode. In addition, dfine the macro
+// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
+// with every metastable event generated in the synchronizer.
+//
+// Copyright (C) Altera Corporation 2009, All Rights Reserved
+// END_MODULE_NAME-------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_eth_tse_std_synchronizer #(
+ parameter depth = 3
+) (
+ input clk,
+ input reset_n,
+ input din,
+ output dout
+);
+
+ altera_std_synchronizer_nocut #(
+ .depth(depth)
+ ) std_sync_no_cut (
+ .clk (clk),
+ .reset_n (reset_n),
+ .din (din),
+ .dout (dout)
+ );
+
+endmodule
+
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_std_synchronizer_bundle.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_std_synchronizer_bundle.v
new file mode 100644
index 0000000000000000000000000000000000000000..1e62ffae8b975c3ccd80cb89a9ee3a8d7c76a087
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_eth_tse_std_synchronizer_bundle.v
@@ -0,0 +1,60 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Module Name : altera_eth_tse_std_synchronizer_bundle
+//
+// Description : Bundle of bit synchronizers.
+// WARNING: only use this to synchronize a bundle of
+// *independent* single bit signals or a Gray encoded
+// bus of signals. Also remember that pulses entering
+// the synchronizer will be swallowed upon a metastable
+// condition if the pulse width is shorter than twice
+// the synchronizing clock period.
+//
+
+`timescale 1 ps / 1 ps
+module altera_eth_tse_std_synchronizer_bundle (
+ clk,
+ reset_n,
+ din,
+ dout
+ );
+ // GLOBAL PARAMETER DECLARATION
+ parameter width = 1;
+ parameter depth = 3;
+
+ // INPUT PORT DECLARATION
+ input clk;
+ input reset_n;
+ input [width-1:0] din;
+
+ // OUTPUT PORT DECLARATION
+ output [width-1:0] dout;
+
+ generate
+ genvar i;
+ for (i=0; i<width; i=i+1)
+ begin : sync
+ altera_eth_tse_std_synchronizer #(.depth(depth))
+ u (
+ .clk(clk),
+ .reset_n(reset_n),
+ .din(din[i]),
+ .dout(dout[i])
+ );
+ end
+ endgenerate
+
+endmodule // altera_eth_tse_std_synchronizer_bundle
+// END OF MODULE
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_std_synchronizer_nocut.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_std_synchronizer_nocut.v
new file mode 100644
index 0000000000000000000000000000000000000000..547456984e65a6eea477d4c9749c288222f3c1e8
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_std_synchronizer_nocut.v
@@ -0,0 +1,195 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
+// $Revision: #8 $
+// $Date: 2009/02/18 $
+// $Author: pscheidt $
+//-----------------------------------------------------------------------------
+//
+// File: altera_std_synchronizer_nocut.v
+//
+// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
+// as altera_std_synchronizer.v, except that the embedded false
+// path constraint is removed in this module. If you use this
+// module, you will have to apply the appropriate timing
+// constraints.
+//
+// We expect to make this a standard Quartus atom eventually.
+//
+// Composed of two or more flip flops connected in series.
+// Random metastable condition is simulated when the
+// __ALTERA_STD__METASTABLE_SIM macro is defined.
+// Use +define+__ALTERA_STD__METASTABLE_SIM argument
+// on the Verilog simulator compiler command line to
+// enable this mode. In addition, define the macro
+// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
+// with every metastable event generated in the synchronizer.
+//
+// Copyright (C) Altera Corporation 2009, All Rights Reserved
+//-----------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_std_synchronizer_nocut (
+ clk,
+ reset_n,
+ din,
+ dout
+ );
+
+ parameter depth = 3; // This value must be >= 2 !
+ parameter rst_value = 0;
+
+ input clk;
+ input reset_n;
+ input din;
+ output dout;
+
+ // QuartusII synthesis directives:
+ // 1. Preserve all registers ie. do not touch them.
+ // 2. Do not merge other flip-flops with synchronizer flip-flops.
+ // QuartusII TimeQuest directives:
+ // 1. Identify all flip-flops in this module as members of the synchronizer
+ // to enable automatic metastability MTBF analysis.
+
+ (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
+
+ (* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
+
+ //synthesis translate_off
+ initial begin
+ if (depth <2) begin
+ $display("%m: Error: synchronizer length: %0d less than 2.", depth);
+ end
+ end
+
+ // the first synchronizer register is either a simple D flop for synthesis
+ // and non-metastable simulation or a D flop with a method to inject random
+ // metastable events resulting in random delay of [0,1] cycles
+
+`ifdef __ALTERA_STD__METASTABLE_SIM
+
+ reg[31:0] RANDOM_SEED = 123456;
+ wire next_din_s1;
+ wire dout;
+ reg din_last;
+ reg random;
+ event metastable_event; // hook for debug monitoring
+
+ initial begin
+ $display("%m: Info: Metastable event injection simulation mode enabled");
+ end
+
+ always @(posedge clk) begin
+ if (reset_n == 0)
+ random <= $random(RANDOM_SEED);
+ else
+ random <= $random;
+ end
+
+ assign next_din_s1 = (din_last ^ din) ? random : din;
+
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_last <= (rst_value == 0)? 1'b0 : 1'b1;
+ else
+ din_last <= din;
+ end
+
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_s1 <= (rst_value == 0)? 1'b0 : 1'b1;
+ else
+ din_s1 <= next_din_s1;
+ end
+
+`else
+
+ //synthesis translate_on
+ generate if (rst_value == 0)
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_s1 <= 1'b0;
+ else
+ din_s1 <= din;
+ end
+ endgenerate
+
+ generate if (rst_value == 1)
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ din_s1 <= 1'b1;
+ else
+ din_s1 <= din;
+ end
+ endgenerate
+ //synthesis translate_off
+
+`endif
+
+`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
+ always @(*) begin
+ if (reset_n && (din_last != din) && (random != din)) begin
+ $display("%m: Verbose Info: metastable event @ time %t", $time);
+ ->metastable_event;
+ end
+ end
+`endif
+
+ //synthesis translate_on
+
+ // the remaining synchronizer registers form a simple shift register
+ // of length depth-1
+ generate if (rst_value == 0)
+ if (depth < 3) begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b0}};
+ else
+ dreg <= din_s1;
+ end
+ end else begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b0}};
+ else
+ dreg <= {dreg[depth-3:0], din_s1};
+ end
+ end
+ endgenerate
+
+ generate if (rst_value == 1)
+ if (depth < 3) begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b1}};
+ else
+ dreg <= din_s1;
+ end
+ end else begin
+ always @(posedge clk or negedge reset_n) begin
+ if (reset_n == 0)
+ dreg <= {depth-1{1'b1}};
+ else
+ dreg <= {dreg[depth-3:0], din_s1};
+ end
+ end
+ endgenerate
+
+ assign dout = dreg[depth-2];
+
+endmodule
+
+
+
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_a_fifo_13.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_a_fifo_13.v
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index 0000000000000000000000000000000000000000..0c69333b8e15bec70987f7d786d68e431c557e15
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_false_path_marker.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_false_path_marker.v
new file mode 100644
index 0000000000000000000000000000000000000000..f37df11b00c2b54a85aadb7dc28d091e9ae6d414
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_false_path_marker.v
@@ -0,0 +1,66 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+//
+// -----------------------------------------------
+// False path marker module
+// This module creates a level of flops for the
+// targetted clock, and cut the timing path to the
+// flops using embedded SDC constraint
+//
+// Only use this module to clock cross the path
+// that is being clock crossed properly by correct
+// concept.
+// -----------------------------------------------
+`timescale 1ns / 1ns
+
+module altera_tse_false_path_marker
+#(
+ parameter MARKER_WIDTH = 1
+)
+(
+ input reset,
+ input clk,
+ input [MARKER_WIDTH - 1 : 0] data_in,
+ output [MARKER_WIDTH - 1 : 0] data_out
+);
+
+(*preserve*) reg [MARKER_WIDTH - 1 : 0] data_out_reg;
+
+
+assign data_out = data_out_reg;
+
+always @(posedge clk or posedge reset)
+begin
+ if (reset)
+ begin
+ data_out_reg <= {MARKER_WIDTH{1'b0}};
+ end
+ else
+ begin
+ data_out_reg <= data_in;
+ end
+end
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_gray_cnt.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_gray_cnt.v
new file mode 100644
index 0000000000000000000000000000000000000000..42d6d04b49f448efdc52f6687c52a2c3cc98a581
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_gxb_aligned_rxsync.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_gxb_aligned_rxsync.v
new file mode 100644
index 0000000000000000000000000000000000000000..37ccd0637859ee3b5131591d7f4752bc8fffcec4
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_gxb_aligned_rxsync.v
@@ -0,0 +1,310 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+//
+// Revision Control Information
+//
+// $RCSfile: altera_tse_alt2gxb_aligned_rxsync.v,v $
+// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/strxii_pcs/verilog/altera_tse_alt2gxb_aligned_rxsync.v,v $
+//
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// Check in by : $Author: psgswbuild $
+// Author : Siew Kong NG
+//
+// Project : Triple Speed Ethernet - 1000 BASE-X PCS
+//
+// Description :
+//
+// RX_SYNC alignment for Alt2gxb, Alt4gxb
+
+//
+// ALTERA Confidential and Proprietary
+// Copyright 2007 (c) Altera Corporation
+// All rights reserved
+//
+// -------------------------------------------------------------------------
+// -------------------------------------------------------------------------
+
+`timescale 1ns/1ns
+module altera_tse_gxb_aligned_rxsync (
+
+ input clk,
+ input reset,
+
+ input [7:0] alt_dataout,
+ input alt_sync,
+ input alt_disperr,
+ input alt_ctrldetect,
+ input alt_errdetect,
+ input alt_rmfifodatadeleted,
+ input alt_rmfifodatainserted,
+ input alt_runlengthviolation,
+ input alt_patterndetect,
+ input alt_runningdisp,
+
+ output reg [7:0] altpcs_dataout,
+ output altpcs_sync,
+ output reg altpcs_disperr,
+ output reg altpcs_ctrldetect,
+ output reg altpcs_errdetect,
+ output reg altpcs_rmfifodatadeleted,
+ output reg altpcs_rmfifodatainserted,
+ output reg altpcs_carrierdetect) ;
+ parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
+
+ //-------------------------------------------------------------------------------
+ // intermediate wires
+
+
+ //reg altpcs_dataout
+
+ // pipelined 1
+ reg [7:0] alt_dataout_reg1;
+ reg alt_sync_reg1;
+ reg alt_sync_reg2;
+ reg alt_disperr_reg1;
+ reg alt_ctrldetect_reg1;
+ reg alt_errdetect_reg1;
+ reg alt_rmfifodatadeleted_reg1;
+ reg alt_rmfifodatainserted_reg1;
+ reg alt_patterndetect_reg1;
+ reg alt_runningdisp_reg1;
+ reg alt_runlengthviolation_latched;
+ //-------------------------------------------------------------------------------
+
+ always @(posedge reset or posedge clk)
+ begin
+ if (reset == 1'b1)
+ begin
+ // pipelined 1
+ alt_dataout_reg1 <= 8'h0;
+ alt_sync_reg1 <= 1'b0;
+ alt_disperr_reg1 <= 1'b0;
+ alt_ctrldetect_reg1 <= 1'b0;
+ alt_errdetect_reg1 <= 1'b0;
+ alt_rmfifodatadeleted_reg1 <= 1'b0;
+ alt_rmfifodatainserted_reg1 <= 1'b0;
+ alt_patterndetect_reg1 <= 1'b0;
+ alt_runningdisp_reg1 <= 1'b0;
+ end
+ else
+ begin
+ // pipelined 1
+ alt_dataout_reg1 <= alt_dataout;
+ alt_sync_reg1 <= alt_sync;
+ alt_disperr_reg1 <= alt_disperr;
+ alt_ctrldetect_reg1 <= alt_ctrldetect;
+ alt_errdetect_reg1 <= alt_errdetect;
+ alt_rmfifodatadeleted_reg1 <= alt_rmfifodatadeleted;
+ alt_rmfifodatainserted_reg1 <= alt_rmfifodatainserted;
+ alt_patterndetect_reg1 <= alt_patterndetect;
+ alt_runningdisp_reg1 <= alt_runningdisp;
+ end
+
+ end
+
+generate if ( DEVICE_FAMILY == "STRATIXIIGX" || DEVICE_FAMILY == "ARRIAGX" )
+begin
+ always @ (posedge reset or posedge clk)
+ begin
+ if (reset == 1'b1)
+ begin
+ altpcs_dataout <= 8'h0;
+ altpcs_disperr <= 1'b1;
+ altpcs_ctrldetect <= 1'b0;
+ altpcs_errdetect <= 1'b1;
+ altpcs_rmfifodatadeleted <= 1'b0;
+ altpcs_rmfifodatainserted <= 1'b0;
+ end
+ else
+ begin
+ if (alt_sync == 1'b1 )
+ begin
+ altpcs_dataout <= alt_dataout_reg1;
+ altpcs_disperr <= alt_disperr_reg1;
+ altpcs_ctrldetect <= alt_ctrldetect_reg1;
+ altpcs_errdetect <= alt_errdetect_reg1;
+ altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
+ altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
+ end
+ else
+ begin
+ altpcs_dataout <= 8'h0;
+ altpcs_disperr <= 1'b1;
+ altpcs_ctrldetect <= 1'b0;
+ altpcs_errdetect <= 1'b1;
+ altpcs_rmfifodatadeleted <= 1'b0;
+ altpcs_rmfifodatainserted <= 1'b0;
+ end
+ end
+ end
+ assign altpcs_sync = alt_sync_reg1;
+end
+else if ( DEVICE_FAMILY == "STRATIXIV" || DEVICE_FAMILY == "ARRIAIIGX" || DEVICE_FAMILY == "CYCLONEIVGX" || DEVICE_FAMILY == "HARDCOPYIV" || DEVICE_FAMILY == "ARRIAIIGZ" || DEVICE_FAMILY == "STRATIXV" || DEVICE_FAMILY == "ARRIAV" || DEVICE_FAMILY == "ARRIAVGZ" || DEVICE_FAMILY == "CYCLONEV" || DEVICE_FAMILY == "ARRIA10")
+begin
+ always @ (posedge reset or posedge clk)
+ begin
+ if (reset == 1'b1)
+ begin
+ altpcs_dataout <= 8'h0;
+ altpcs_disperr <= 1'b1;
+ altpcs_ctrldetect <= 1'b0;
+ altpcs_errdetect <= 1'b1;
+ altpcs_rmfifodatadeleted <= 1'b0;
+ altpcs_rmfifodatainserted <= 1'b0;
+ alt_sync_reg2 <= 1'b0;
+ end
+ else
+ begin
+ altpcs_dataout <= alt_dataout_reg1;
+ altpcs_disperr <= alt_disperr_reg1;
+ altpcs_ctrldetect <= alt_ctrldetect_reg1;
+ altpcs_errdetect <= alt_errdetect_reg1;
+ altpcs_rmfifodatadeleted <= alt_rmfifodatadeleted_reg1;
+ altpcs_rmfifodatainserted <= alt_rmfifodatainserted_reg1;
+ alt_sync_reg2 <= alt_sync_reg1 ;
+ end
+
+ end
+
+
+ assign altpcs_sync = alt_sync_reg2;
+end
+endgenerate
+
+
+
+
+
+ //latched runlength violation assertion for "carrier_detect" signal generation block
+ //reset the latch value after carrier_detect goes de-asserted
+// always @ (altpcs_carrierdetect or alt_runlengthviolation or alt_sync_reg1)
+// begin
+// if (altpcs_carrierdetect == 1'b0)
+// begin
+// alt_runlengthviolation_latched <= 1'b0;
+// end
+// else
+// begin
+// if (alt_runlengthviolation == 1'b1 & alt_sync_reg1 == 1'b1)
+// begin
+// alt_runlengthviolation_latched <= 1'b1;
+// end
+// end
+// end
+
+ always @ (posedge reset or posedge clk)
+ begin
+ if (reset == 1'b1)
+ begin
+ alt_runlengthviolation_latched <= 1'b0;
+ end
+ else
+ begin
+ if ((altpcs_carrierdetect == 1'b0) | (alt_sync == 1'b0))
+ begin
+ alt_runlengthviolation_latched <= 1'b0;
+ end
+ else
+ begin
+ if ((alt_runlengthviolation == 1'b1) & (alt_sync == 1'b1))
+ begin
+ alt_runlengthviolation_latched <= 1'b1;
+ end
+ end
+ end
+ end
+
+ // carrier_detect signal generation
+ always @ (posedge reset or posedge clk)
+ begin
+ if (reset == 1'b1)
+ begin
+ altpcs_carrierdetect <= 1'b1;
+ end
+ else
+
+ // This portion of code is to workaround the issue with PHYIP (hard PCS) for not implementing the carrier_detect,
+ // which suppose to be implemented based on 10b character, not 8b.
+ //
+ // The real challenge is to detect the /INVALID/ 10b code group
+ //
+ // This is the Table 36.3.2.1 in UNH test plan
+ // =====================================================
+ // RD- code-group RD+ code-group
+ // =====================================================
+ // 001111 1010 /K28.5/ 110000 0101 /K28.5/
+ // 001111 1011 /INVALID/ 110000 0100 /INVALID/
+ // 001111 1000 /K28.7/ 110000 0111 /K28.7/
+ // 001111 1110 /INVALID/ 110000 0001 /INVALID/
+ // 001111 0010 /K28.4/ 110000 1101 /K28.4/
+ // 001110 1010 /D28.5/ 110001 0101 /D3.2/
+ // 001101 1010 /D12.5/ 110010 0101 /D19.2/
+ // 001011 1010 /D20.5/ 110100 0101 /D11.2/
+ // 000111 1010 /D7.5/ 111000 0101 /D7.2/
+ // 011111 1010 /INVALID/ 100000 0101 /INVALID/
+ // 101111 1010 /INVALID/ 010000 0101 /INVALID/
+
+ begin
+ if ( (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
+ & alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h1C & alt_ctrldetect_reg1 == 1'b1 & alt_errdetect_reg1 == 1'b1
+ & alt_disperr_reg1 ==1'b1 & alt_patterndetect_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b1 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hFC & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h9C & alt_ctrldetect_reg1 == 1'b1 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hBC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hAC & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hB4 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA7 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b1 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA1 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b1 & alt_runlengthviolation_latched == 1'b1 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'hA2 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b1
+ & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)|
+ (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
+ (alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)) ) |
+
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h43 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h53 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h4B & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h47 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b0 ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h41 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b0 & alt_runlengthviolation_latched == 1'b1
+ & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
+ (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1 )) ) |
+ (alt_sync_reg1 == 1'b1 & alt_dataout_reg1 == 8'h42 & alt_ctrldetect_reg1 == 1'b0 & alt_patterndetect_reg1 == 1'b0
+ & alt_runningdisp_reg1 == 1'b0 & ((alt_runningdisp == 1'b1 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b0)|
+ (alt_runningdisp == 1'b0 & alt_errdetect_reg1 == 1'b1 & alt_disperr_reg1 == 1'b1)) )
+ )
+
+ begin
+ altpcs_carrierdetect <= 1'b0;
+ end
+ else
+ begin
+ altpcs_carrierdetect <= 1'b1;
+ end
+ end
+
+ end
+
+
+
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_mdio_reg.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_mdio_reg.v
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_reset_ctrl_lego.sv b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_reset_ctrl_lego.sv
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index 0000000000000000000000000000000000000000..60847e3510728e4c4c2872203468d6c3d9ed96e1
--- /dev/null
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@@ -0,0 +1,272 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+//
+// Reset controller building block.
+//
+// Handles a single reset stage. Can be daisy-chained with other blocks for purely sequential resets.
+// Options include reset pulse length in clock cycles, and a counter for sdone stability checking.
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module altera_tse_reset_ctrl_lego
+#(
+ parameter reset_hold_til_rdone = 0, // 1 means reset stays high until rdone arrives
+ // 0 means fixed pulse length, defined by reset_hold_cycles
+ parameter reset_hold_cycles = 1, // reset pulse length in clock cycles
+ parameter sdone_delay_cycles = 0, // optional delay from rdone received til sdone sent to next block
+ parameter rdone_is_edge_sensitive = 0 // default is level sensitive rdone
+)
+(
+ // clocks and PLLs
+ input wire clock,
+ input wire start,
+ input wire aclr, // active-high asynchronous reset
+ output wire reset,
+ input wire rdone, // reset done signal
+ output reg sdone // sequence done for this lego
+);
+ localparam max_precision = 32; // VCS requires this declaration outside the function
+ function integer ceil_log2;
+ input [max_precision-1:0] input_num;
+ integer i;
+ reg [max_precision-1:0] try_result;
+ begin
+ i = 0;
+ try_result = 1;
+ while ((try_result << i) < input_num && i < max_precision)
+ i = i + 1;
+ ceil_log2 = i;
+ end
+ endfunction
+
+ // How many bits are needed for 'reset_hold_cycles' counter?
+ localparam rhc_bits = ceil_log2(reset_hold_cycles);
+ localparam rhc_load_constant = (1 << rhc_bits) | (reset_hold_cycles-1);
+ // How many bits are needed for 'sdone_delay_cycles' counter?
+ localparam sdc_bits = ceil_log2(sdone_delay_cycles);
+ localparam sdc_load_constant = (1 << sdc_bits)
+ | ((rdone_is_edge_sensitive == 1 && sdone_delay_cycles > 1) ? sdone_delay_cycles-2 : sdone_delay_cycles-1);
+ localparam sdone_stable_cycles = (sdone_delay_cycles > 1 ? sdone_delay_cycles+1 : 0);
+
+ wire spulse; // synchronous detection of 'start' 0-to-1 transition
+ wire rhold;
+ wire timed_reset_in_progress;
+ wire rinit_next; // combinatorial input to rinit DFF
+ wire rdonei; // internal selector between rdone and rdsave (rdone_is_edge_sensitive==1)
+ wire rdpulse; // synchronous detection of 'rdone' 0-to-1 transition, when rdone_is_edge_sensitive==1
+
+ reg zstart; // delayed value of 'start' input, used for detection of 0-to-1 transition
+ reg rinit; // state bit that indicates sequence is in progress
+
+
+ // 'start' input, detect 0-to-1 transition that triggers sequence
+ assign spulse = start & ~zstart;
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ zstart <= 0;
+ else
+ zstart <= start;
+
+ // rinit state bit, triggered by spulse, waits while rhold = 1
+ assign rinit_next = spulse | (rinit & (rhold | ~rdonei | rdpulse)) | timed_reset_in_progress;
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ rinit <= 1;
+ else
+ rinit <= rinit_next;
+
+ // optional internal 'rdone' generation logic, if rdone_is_edge_sensitive==1
+ generate
+ if (rdone_is_edge_sensitive == 0) begin
+ assign rdpulse = 0;
+ assign rdonei = rdone;
+ end
+ else begin
+ // instantiate synchronous edge-detection logic for rdone
+ reg zrdone; // for edge-sensitive rdone, detect 0-to-1 transition synchronously
+ reg rdsave; // for edge-sensitive rdone, use this as internal rdone
+ always @(posedge clock or posedge aclr) begin
+ if (aclr == 1'b1) begin
+ zrdone <= 0;
+ rdsave <= 0;
+ end
+ else begin
+ zrdone <= rdone; // previous value of rdone for synchronous edge detection
+ rdsave <= ~spulse & (rdpulse | rdsave);
+ end
+ end
+ assign rdpulse = rdone & ~zrdone;
+ assign rdonei = rdsave;
+ end
+ endgenerate
+
+ // rhold depends on sdone_delay_cycles and rdone_is_edge_sensitive
+ generate
+ if (sdone_delay_cycles == 0 || (sdone_delay_cycles == 1 && rdone_is_edge_sensitive == 1))
+ assign rhold = ~rdonei; // sdone_delay_cycles=0
+ else begin
+ // declare only when needed to avoid Quartus synthesis warnings
+ reg [sdc_bits:0] rhold_reg; // for sdone_delay_cycles > 0
+ if (sdone_delay_cycles == 1) begin
+ always @(posedge clock or posedge aclr) begin
+ if (aclr == 1'b1)
+ rhold_reg <= 0;
+ else
+ rhold_reg <= ~(rinit & rdonei);
+ end
+ assign rhold = rhold_reg[0]; // sdone_delay_cycles=1
+ end
+ else begin
+ // need to count cycles to make sure rdone is stable
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr == 1'b1)
+ rhold_reg <= 0;
+ else if ((rinit & rdonei & ~rdpulse) == 0)
+ // keep load value until rinit & rdone both high, and no new rdone pulses
+ rhold_reg <= sdc_load_constant[sdc_bits:0];
+ else
+ rhold_reg <= rhold_reg - 1'b1;
+ end
+ assign rhold = rhold_reg[sdc_bits]; // sdone_delay_cycles > 1
+ end
+ end
+ endgenerate
+
+ // sdone state bit indicates that reset sequence completed. Clear again on 'start'
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ sdone <= 0;
+ else
+ sdone <= ~spulse & (sdone | (rinit & ~rinit_next));
+
+ // reset pulse generation logic depends on 2 parameters
+ generate
+ if (reset_hold_til_rdone == 1) begin
+ assign reset = rinit;
+ assign timed_reset_in_progress = 0;
+ end
+ else if (reset_hold_cycles < 1) begin // 0 is legal, but catch negative (illegal) values too
+ assign reset = spulse;
+ assign timed_reset_in_progress = 0;
+ end
+ else begin
+ // declare only when needed to avoid Quartus synthesis warnings
+ reg [rhc_bits:0] zspulse; // bits for reset pulse if fixed length
+ assign timed_reset_in_progress = zspulse[rhc_bits];
+ assign reset = zspulse[rhc_bits];
+
+ if (reset_hold_cycles == 1)
+ // a single-cycle reset pulse needs 1 register
+ always @(posedge clock or posedge aclr)
+ if (aclr == 1'b1)
+ zspulse <= 1;
+ else
+ zspulse <= spulse;
+ else begin
+ // multi-cycle reset pulse needs a counter
+ always @(posedge clock or posedge aclr)
+ begin
+ if (aclr == 1'b1)
+ zspulse <= {rhc_bits + 1 { 1'b1}};
+ else if (spulse == 1)
+ zspulse <= rhc_load_constant[rhc_bits:0];
+ else if (zspulse[rhc_bits] == 1)
+ zspulse <= zspulse - 1'b1;
+ end
+ end
+ end
+ endgenerate
+
+// generate
+// case (reset_hold_til_rdone)
+// 0 : m1 U1 (a, b, c);
+// 2 : m2 U1 (a, b, c);
+// default : m3 U1 (a, b, c);
+// endcase
+// endgenerate
+
+ // general assertions
+ //synopsys translate_off
+ // vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
+`ifdef ALTERA_XCVR_ASSERTIONS
+ // when rdone is edge sensitive, last rdone +ve edge triggers sdone +ve edge,
+ // 'sdone_delay_cycles' later. "##1 1" is an always-true cycle to match $rise(sdone)
+ sequence rdone_last_edge;
+ @(posedge clock) $rose(rdone) ##1 !$rose(rdone) [*sdone_delay_cycles] ##1 1;
+ endsequence
+
+ // when rdone is level sensitive, stable rdone for 'sdone_delay_cycles' consecutive cycles
+ // triggers sdone +ve edge. "##1 1" is an always-true cycle to match $rise(sdone)
+ sequence rdone_stable_level;
+ @(posedge clock) rdone [*(sdone_delay_cycles+1)] ##1 1;
+ endsequence
+
+// Most assertions aren't valid when 'aclr' is active
+//`define assert_awake(arg) assert property (disable iff (aclr) arg )
+ always @(aclr)
+ if (aclr) $assertkill;
+ else $asserton;
+
+ generate
+ always @(posedge clock) begin
+ // A rising edge on start will result in reset high within 1 clock cycle
+ assert property ($rose(start & ~aclr) |-> ##[0:1] reset);
+ // A rising edge on reset will result in sdone low within 1 clock cycle
+ assert property ($rose(reset) |-> ##[0:1] !sdone);
+
+ // assertions for optional behavior: reset pulse length options
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles > 1)
+ // Verify fixed-length reset pulse option
+ assert property ($rose(reset) |-> reset [*reset_hold_cycles] ##1 !reset)
+ else $error("Reset pulse length should be %d", reset_hold_cycles);
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles == 1)
+ // Verify fixed 1-length reset pulse option
+ assert property ($rose(reset) |=> !reset);
+ if (reset_hold_til_rdone == 0 && reset_hold_cycles == 0)
+ // Verify minimal-length reset pulse option, which mirrors 'start' edge detection
+ assert property ($rose(start & ~aclr) |-> reset ##1 !reset);
+ if (reset_hold_til_rdone == 1) begin
+ // with hold-til-rdone, reset should not deassert until after rdone asserts, then deassert immediately
+ assert property ($rose(reset) && !rdone |=> $stable(reset) [*0:$] ##1 (reset && rdone) ##1 !reset);
+ assert property ($rose(reset) && rdone ##1 rdone [*sdone_delay_cycles] |=> !reset); // rdone was already high
+ //assert property ($rose(reset) && !rdone |-> ##[0:$] rdone ##1 !reset);
+ end
+
+ // assertions for optional behavior: sdone delay options and rdone edge sensitive option
+ if (rdone_is_edge_sensitive == 1)
+ // rdone edge-sensitive option only has an effect when sdone_delay_cycles > 0
+ assert property ($rose(sdone) |-> rdone_last_edge.ended);
+ if (rdone_is_edge_sensitive == 0)
+ // rdone defaults to level-sensitive
+ assert property ($rose(sdone) |-> (rdone_stable_level.ended or $past($fell(reset),1)));
+ end
+ endgenerate
+`endif // ALTERA_XCVR_ASSERTIONS
+ //synopsys translate_on
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_reset_sequencer.sv b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_reset_sequencer.sv
new file mode 100644
index 0000000000000000000000000000000000000000..8df83d2604556f241e4d688a9b6668251d1e3786
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_reset_sequencer.sv
@@ -0,0 +1,189 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Reset controller for Stratix IV transceivers with RX CDR in auto-lock mode.
+//
+// Uses altera_tse_reset_ctrl_lego to handle each reset stage, with 3 required for the overall sequence.
+// Parameter defaults for pll-powerdown and lock-to-data-auto timers assume 50 MHz system clock
+//
+// $Header$
+//
+
+`timescale 1 ns / 1 ns
+
+module altera_tse_reset_sequencer
+#(
+ parameter sys_clk_in_mhz = 50 // needed for 1us and 4us delay timers
+)
+(
+ // User inputs and outputs
+ input wire clock,
+ input wire reset_all,
+ input wire reset_tx_digital,
+ input wire reset_rx_digital,
+ input wire powerdown_all,
+ output wire tx_ready,
+ output wire rx_ready,
+
+ // I/O to Stratix IV transceiver control & status
+ output wire pll_powerdown, // reset TX PLL
+ output wire tx_digitalreset, // reset TX PCS
+ output wire rx_analogreset, // reset RX PMA
+ output wire rx_digitalreset, // reset RX PCS
+ output wire gxb_powerdown, // powerdown whole quad
+ input wire pll_is_locked, // TX PLL is locked status
+ input wire rx_oc_busy, // RX channel offset cancellation status
+ input wire rx_is_lockedtodata, // RX CDR PLL is locked to data status
+ input wire manual_mode // 0=Automatically reset RX after loss of rx_is_lockedtodata
+);
+
+localparam clk_in_mhz =
+`ifdef QUARTUS__SIMGEN
+ 2; // simulation-only value
+`elsif ALTERA_RESERVED_QIS
+ sys_clk_in_mhz; // use real counter lengths for normal Quartus synthesis
+`else
+ 2; // simulation-only value
+`endif
+localparam t_pll_powerdown = clk_in_mhz; // 1 us minimum
+localparam t_ltd_auto = clk_in_mhz*4; // 4 us minimum
+
+
+wire pll_is_locked_r; // pll_is_locked resynchronized
+wire rx_oc_busy_r; // rx_oc_busy resynchronized
+wire rx_is_lockedtodata_r; // rx_is_lockedtodata resynchronized
+wire manual_mode_r; // manual_mode resynchonized
+
+wire sdone_lego_pll_powerdown; // 'sequence done' output of pll_powerdown lego
+wire sdone_lego_tx_digitalreset;// 'sequence done' output of tx_digitalreset lego
+wire sdone_lego_rx_digitalreset;// 'sequence done' output of rx_digitalreset lego
+wire sdone_lego_rx_analogreset; // 'sequence done' output of rx_analogreset lego
+wire wire_tx_digital_only_reset;// reset output for TX digital-only
+wire wire_rx_digital_only_reset;// reset output for RX digital-only
+wire wire_tx_digitalreset; // TX digital full-reset source
+wire wire_rx_digitalreset; // RX digital full-reset source
+wire wire_rx_digital_retrigger; // Trigger new RX digital sequence after main sequence completes, and lose lock-to-data
+
+
+// Resynchronize input signals
+altera_tse_xcvr_resync #(
+ .WIDTH(4)
+ ) altera_tse_xcvr_resync_inst (
+ .clk (clock),
+ .d ({pll_is_locked ,rx_oc_busy ,rx_is_lockedtodata ,manual_mode }),
+ .q ({pll_is_locked_r,rx_oc_busy_r,rx_is_lockedtodata_r,manual_mode_r})
+);
+
+
+// First reset ctrl sequencer lego is for pll_powerdown generation
+altera_tse_reset_ctrl_lego #(
+ .reset_hold_cycles(t_pll_powerdown) // hold pll_powerdown for 1us
+ ) lego_pll_powerdown ( .clock(clock),
+ .start(reset_all), // Do not use resynched version of reset_all here
+ .aclr(powerdown_all),
+ .reset(pll_powerdown),
+ .rdone(pll_is_locked_r),
+ .sdone(sdone_lego_pll_powerdown));
+
+// next reset ctrl sequencer lego is for tx_digitalreset generation
+altera_tse_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1) // hold until rdone arrives for this test case
+ ) lego_tx_digitalreset ( .clock(clock),
+ .start(reset_all),
+ .aclr(powerdown_all),
+ .reset(wire_tx_digitalreset),
+ .rdone(sdone_lego_pll_powerdown),
+ .sdone(sdone_lego_tx_digitalreset));
+
+// next reset ctrl sequencer lego is for rx_analogreset generation
+altera_tse_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1), // hold until rdone arrives for this test case
+ .sdone_delay_cycles(2) // hold rx_analogreset 2 parallel_clock cycles after offset cancellation done
+ ) lego_rx_analogreset ( .clock(clock),
+ .start(reset_all),
+ .aclr(powerdown_all),
+ .reset(rx_analogreset),
+ .rdone(sdone_lego_tx_digitalreset & ~rx_oc_busy_r),
+ .sdone(sdone_lego_rx_analogreset));
+
+// last reset ctrl sequencer lego is for rx_digitalreset generation
+altera_tse_reset_ctrl_lego #(
+ .reset_hold_til_rdone(1), // hold until rdone arrives for this test case
+ .sdone_delay_cycles(t_ltd_auto) // hold rx_digitalreset for 4us
+ ) lego_rx_digitalreset ( .clock(clock),
+ .start(~manual_mode & reset_all | wire_rx_digital_retrigger),
+ .aclr(powerdown_all),
+ .reset(wire_rx_digitalreset),
+ .rdone(sdone_lego_rx_analogreset & rx_is_lockedtodata_r),
+ .sdone(sdone_lego_rx_digitalreset));
+
+//////////// digital-only reset ////////////
+// separate reset ctrl sequencer lego for digital-only reset generation
+altera_tse_reset_ctrl_lego #(
+ .reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
+ ) lego_tx_digitalonly ( .clock(clock),
+ .start(reset_tx_digital | reset_all),
+ .aclr(powerdown_all),
+ .reset(wire_tx_digital_only_reset),
+ .rdone(sdone_lego_tx_digitalreset),
+ .sdone(tx_ready)); // TX status indicator for user
+
+altera_tse_reset_ctrl_lego #(
+ .reset_hold_cycles(3) // hold 2 parallel clock cycles (assumes sysclk slower or same freq as parallel clock)
+ ) lego_rx_digitalonly ( .clock(clock),
+ .start(reset_rx_digital | (reset_all & ~manual_mode) | wire_rx_digital_retrigger),
+ .aclr(powerdown_all),
+ .reset(wire_rx_digital_only_reset),
+ .rdone(sdone_lego_rx_digitalreset),
+ .sdone(rx_ready)); // RX status indicator for user
+
+// digital resets have 2 possible sources: full-reset or digital-only
+assign tx_digitalreset = wire_tx_digitalreset | wire_tx_digital_only_reset;
+assign rx_digitalreset = wire_rx_digitalreset | wire_rx_digital_only_reset;
+
+// re-trigger RX digital sequence when main sequence is complete (indicated by sdone_lego_rx_digitalreset)
+// not manual mode, and lose lock-to-data
+assign wire_rx_digital_retrigger = ~manual_mode & sdone_lego_rx_digitalreset & ~rx_is_lockedtodata_r;
+
+// Quad power-down
+assign gxb_powerdown = powerdown_all;
+
+
+////////////////////////
+// general assertions
+//synopsys translate_off
+// vlog/vcs/ncverilog: +define+ALTERA_XCVR_ASSERTIONS
+`ifdef ALTERA_XCVR_ASSERTIONS
+always @(posedge clock) begin
+ // reset_all starts by triggering CMU PLL powerdown
+ assert property ($rose(reset_all) |=> $rose(pll_powerdown));
+ // While CMU PLL powerdown is asserted, all other resets must be asserted
+ assert property (pll_powerdown |-> (tx_digitalreset & rx_analogreset & rx_digitalreset));
+ // While rx_analogreset is asserted, rx_digitalreset must be asserted
+ assert property (rx_analogreset |-> rx_digitalreset);
+ // When pll_is_locked is asserted, tx_digitalreset must be deasserted
+ assert property ($rose(pll_is_locked_r) |-> ##[0:2] !tx_digitalreset);
+ // During a reset, rx_digitalreset should remain high for t_ltd_auto after rx_is_lockedtodata rising edge
+ assert property ($rose(rx_is_lockedtodata_r) |-> rx_digitalreset [*(t_ltd_auto+1)] ##1 !rx_digitalreset);
+ // reset_tx_digital results in only a brief pulse on tx_digitalreset
+ assert property ($rose(reset_tx_digital) |=> tx_digitalreset [*3] );
+ assert property ($rose(reset_tx_digital) & tx_ready |=> tx_digitalreset [*3] ##1 ~tx_digitalreset ##1 $rose(tx_ready) );
+ // reset_rx_digital results in only a brief pulse on rx_digitalreset
+ assert property ($rose(reset_rx_digital) |=> rx_digitalreset [*3] );
+ assert property ($rose(reset_rx_digital) & rx_ready |=> rx_digitalreset [*3] ##1 ~rx_digitalreset ##1 $rose(rx_ready) );
+end
+`endif
+//synopsys translate_on
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_reset_synchronizer.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_reset_synchronizer.v
new file mode 100644
index 0000000000000000000000000000000000000000..18258fa0053db4adc3d33b0dfb433add671d3c67
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_reset_synchronizer.v
@@ -0,0 +1,100 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2010 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+// $Id: //acds/main/ip/merlin/altera_reset_controller/altera_tse_reset_synchronizer.v#7 $
+// $Revision: #7 $
+// $Date: 2010/04/27 $
+// $Author: jyeap $
+
+// -----------------------------------------------
+// Reset Synchronizer
+// -----------------------------------------------
+`timescale 1ns / 1ns
+
+module altera_tse_reset_synchronizer
+#(
+ parameter ASYNC_RESET = 1,
+ parameter DEPTH = 2
+)
+(
+ input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,R105\"" */,
+
+ input clk,
+ output reset_out
+);
+
+ // -----------------------------------------------
+ // Synchronizer register chain. We cannot reuse the
+ // standard synchronizer in this implementation
+ // because our timing constraints are different.
+ //
+ // Instead of cutting the timing path to the d-input
+ // on the first flop we need to cut the aclr input.
+ //
+ // We omit the "preserve" attribute on the final
+ // output register, so that the synthesis tool can
+ // duplicate it where needed.
+ // -----------------------------------------------
+ // Please check the false paths setting in TSE SDC
+
+ (*preserve*) reg [DEPTH-1:0] altera_tse_reset_synchronizer_chain;
+ reg altera_tse_reset_synchronizer_chain_out;
+
+ generate if (ASYNC_RESET) begin
+
+ // -----------------------------------------------
+ // Assert asynchronously, deassert synchronously.
+ // -----------------------------------------------
+ always @(posedge clk or posedge reset_in) begin
+ if (reset_in) begin
+ altera_tse_reset_synchronizer_chain <= {DEPTH{1'b1}};
+ altera_tse_reset_synchronizer_chain_out <= 1'b1;
+ end
+ else begin
+ altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
+ altera_tse_reset_synchronizer_chain[DEPTH-1] <= 0;
+ altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
+ end
+ end
+
+ assign reset_out = altera_tse_reset_synchronizer_chain_out;
+
+ end else begin
+
+ // -----------------------------------------------
+ // Assert synchronously, deassert synchronously.
+ // -----------------------------------------------
+ always @(posedge clk) begin
+ altera_tse_reset_synchronizer_chain[DEPTH-2:0] <= altera_tse_reset_synchronizer_chain[DEPTH-1:1];
+ altera_tse_reset_synchronizer_chain[DEPTH-1] <= reset_in;
+ altera_tse_reset_synchronizer_chain_out <= altera_tse_reset_synchronizer_chain[0];
+ end
+
+ assign reset_out = altera_tse_reset_synchronizer_chain_out;
+
+ end
+ endgenerate
+
+endmodule
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diff --git a/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_xcvr_resync.v b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_xcvr_resync.v
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index 0000000000000000000000000000000000000000..53763ef6efd7a070d77b90e6e9a6f166d7bafd46
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_eth_tse_pcs_pma_nf_phyip_221/synth/altera_tse_xcvr_resync.v
@@ -0,0 +1,87 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Module: altera_tse_xcvr_resync
+//
+// Description:
+// A general purpose resynchronization module.
+//
+// Parameters:
+// SYNC_CHAIN_LENGTH
+// - Specifies the length of the synchronizer chain for metastability
+// retiming.
+// WIDTH
+// - Specifies the number of bits you want to synchronize. Controls the width of the
+// d and q ports.
+// SLOW_CLOCK - USE WITH CAUTION.
+// - Leaving this setting at its default will create a standard resynch circuit that
+// merely passes the input data through a chain of flip-flops. This setting assumes
+// that the input data has a pulse width longer than one clock cycle sufficient to
+// satisfy setup and hold requirements on at least one clock edge.
+// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
+// circuit that will capture the input data regardless of the pulse width and
+// its relationship to the clock. However it is more difficult to apply static
+// timing constraints as it ties the data input to the clock input of the flop.
+// This implementation assumes the data rate is slow enough
+//
+
+`timescale 1ns/1ns
+module altera_tse_xcvr_resync #(
+ parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
+ parameter WIDTH = 1, // Number of bits to resync
+ parameter SLOW_CLOCK = 0 // See description above
+ ) (
+ input wire clk,
+ input wire [WIDTH-1:0] d,
+ output wire [WIDTH-1:0] q
+ );
+
+localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
+
+genvar ig;
+
+// Generate a synchronizer chain for each bit
+generate begin
+ for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
+ wire d_in; // Input to sychronization chain.
+ reg [INT_LEN-1:0] r = {INT_LEN{1'b0}};
+ wire [INT_LEN :0] next_r; // One larger real chain
+
+ assign q[ig] = r[INT_LEN-1]; // Output signal
+ assign next_r = {r,d_in};
+
+ always @(posedge clk)
+ r <= next_r[INT_LEN-1:0];
+
+ // Generate asynchronous capture circuit if specified.
+ if(SLOW_CLOCK == 0) begin
+ assign d_in = d[ig];
+ end else begin
+ wire d_clk;
+ reg d_r;
+ wire clr_n;
+
+ assign d_clk = d[ig];
+ assign d_in = d_r;
+ assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
+
+ // Asynchronously latch the input signal.
+ always @(posedge d_clk or negedge clr_n)
+ if(!clr_n) d_r <= 1'b0;
+ else if(d_clk) d_r <= 1'b1;
+ end // SLOW_CLOCK
+ end // for loop
+end // generate
+endgenerate
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_merlin_demultiplexer_221/synth/arria10_hps_altera_merlin_demultiplexer_221_d6tse3y.sv b/quartus/qsys/arria10_hps/altera_merlin_demultiplexer_221/synth/arria10_hps_altera_merlin_demultiplexer_221_d6tse3y.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2a8e5fff156cc7999085ebaec76f1117244b187e
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_merlin_demultiplexer_221/synth/arria10_hps_altera_merlin_demultiplexer_221_d6tse3y.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: arria10_hps_altera_merlin_demultiplexer_221_d6tse3y
+// ST_DATA_W: 157
+// ST_CHANNEL_W: 2
+// NUM_OUTPUTS: 2
+// VALID_WIDTH: 2
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module arria10_hps_altera_merlin_demultiplexer_221_d6tse3y
+(
+ // -------------------
+ // Sink
+ // -------------------
+ input [2-1 : 0] sink_valid,
+ input [157-1 : 0] sink_data, // ST_DATA_W=157
+ input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Sources
+ // -------------------
+ output reg src0_valid,
+ output reg [157-1 : 0] src0_data, // ST_DATA_W=157
+ output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
+ output reg src0_startofpacket,
+ output reg src0_endofpacket,
+ input src0_ready,
+
+ output reg src1_valid,
+ output reg [157-1 : 0] src1_data, // ST_DATA_W=157
+ output reg [2-1 : 0] src1_channel, // ST_CHANNEL_W=2
+ output reg src1_startofpacket,
+ output reg src1_endofpacket,
+ input src1_ready,
+
+
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+ input clk,
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+ input reset
+
+);
+
+ localparam NUM_OUTPUTS = 2;
+ wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+ // -------------------
+ // Demux
+ // -------------------
+ always @* begin
+ src0_data = sink_data;
+ src0_startofpacket = sink_startofpacket;
+ src0_endofpacket = sink_endofpacket;
+ src0_channel = sink_channel >> NUM_OUTPUTS;
+
+ src0_valid = sink_channel[0] && sink_valid[0];
+
+ src1_data = sink_data;
+ src1_startofpacket = sink_startofpacket;
+ src1_endofpacket = sink_endofpacket;
+ src1_channel = sink_channel >> NUM_OUTPUTS;
+
+ src1_valid = sink_channel[1] && sink_valid[1];
+
+ end
+
+ // -------------------
+ // Backpressure
+ // -------------------
+ assign ready_vector[0] = src0_ready;
+ assign ready_vector[1] = src1_ready;
+
+ assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
diff --git a/quartus/qsys/arria10_hps/altera_merlin_demultiplexer_221/synth/arria10_hps_altera_merlin_demultiplexer_221_yx3jwsy.sv b/quartus/qsys/arria10_hps/altera_merlin_demultiplexer_221/synth/arria10_hps_altera_merlin_demultiplexer_221_yx3jwsy.sv
new file mode 100644
index 0000000000000000000000000000000000000000..732c076a41402a64a02b3b94e1a927a806ba3454
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_merlin_demultiplexer_221/synth/arria10_hps_altera_merlin_demultiplexer_221_yx3jwsy.sv
@@ -0,0 +1,115 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -------------------------------------
+// Merlin Demultiplexer
+//
+// Asserts valid on the appropriate output
+// given a one-hot channel signal.
+// -------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: arria10_hps_altera_merlin_demultiplexer_221_yx3jwsy
+// ST_DATA_W: 157
+// ST_CHANNEL_W: 2
+// NUM_OUTPUTS: 2
+// VALID_WIDTH: 1
+// ------------------------------------------
+
+//------------------------------------------
+// Message Supression Used
+// QIS Warnings
+// 15610 - Warning: Design contains x input pin(s) that do not drive logic
+//------------------------------------------
+
+module arria10_hps_altera_merlin_demultiplexer_221_yx3jwsy
+(
+ // -------------------
+ // Sink
+ // -------------------
+ input [1-1 : 0] sink_valid,
+ input [157-1 : 0] sink_data, // ST_DATA_W=157
+ input [2-1 : 0] sink_channel, // ST_CHANNEL_W=2
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Sources
+ // -------------------
+ output reg src0_valid,
+ output reg [157-1 : 0] src0_data, // ST_DATA_W=157
+ output reg [2-1 : 0] src0_channel, // ST_CHANNEL_W=2
+ output reg src0_startofpacket,
+ output reg src0_endofpacket,
+ input src0_ready,
+
+ output reg src1_valid,
+ output reg [157-1 : 0] src1_data, // ST_DATA_W=157
+ output reg [2-1 : 0] src1_channel, // ST_CHANNEL_W=2
+ output reg src1_startofpacket,
+ output reg src1_endofpacket,
+ input src1_ready,
+
+
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
+ input clk,
+ (*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
+ input reset
+
+);
+
+ localparam NUM_OUTPUTS = 2;
+ wire [NUM_OUTPUTS - 1 : 0] ready_vector;
+
+ // -------------------
+ // Demux
+ // -------------------
+ always @* begin
+ src0_data = sink_data;
+ src0_startofpacket = sink_startofpacket;
+ src0_endofpacket = sink_endofpacket;
+ src0_channel = sink_channel >> NUM_OUTPUTS;
+
+ src0_valid = sink_channel[0] && sink_valid;
+
+ src1_data = sink_data;
+ src1_startofpacket = sink_startofpacket;
+ src1_endofpacket = sink_endofpacket;
+ src1_channel = sink_channel >> NUM_OUTPUTS;
+
+ src1_valid = sink_channel[1] && sink_valid;
+
+ end
+
+ // -------------------
+ // Backpressure
+ // -------------------
+ assign ready_vector[0] = src0_ready;
+ assign ready_vector[1] = src1_ready;
+
+ assign sink_ready = |(sink_channel & ready_vector);
+
+endmodule
+
diff --git a/quartus/qsys/arria10_hps/altera_merlin_multiplexer_221/synth/arria10_hps_altera_merlin_multiplexer_221_h6k2nza.sv b/quartus/qsys/arria10_hps/altera_merlin_multiplexer_221/synth/arria10_hps_altera_merlin_multiplexer_221_h6k2nza.sv
new file mode 100644
index 0000000000000000000000000000000000000000..7f530c42161a4b2602565a80b5331361c58f381c
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_merlin_multiplexer_221/synth/arria10_hps_altera_merlin_multiplexer_221_h6k2nza.sv
@@ -0,0 +1,345 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// (C) 2001-2014 Altera Corporation. All rights reserved.
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// ------------------------------------------
+// Merlin Multiplexer
+// ------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+// ------------------------------------------
+// Generation parameters:
+// output_name: arria10_hps_altera_merlin_multiplexer_221_h6k2nza
+// NUM_INPUTS: 2
+// ARBITRATION_SHARES: 1 1
+// ARBITRATION_SCHEME "no-arb"
+// PIPELINE_ARB: 0
+// PKT_TRANS_LOCK: 108 (arbitration locking enabled)
+// ST_DATA_W: 157
+// ST_CHANNEL_W: 2
+// ------------------------------------------
+
+module arria10_hps_altera_merlin_multiplexer_221_h6k2nza
+(
+ // ----------------------
+ // Sinks
+ // ----------------------
+ input sink0_valid,
+ input [157-1 : 0] sink0_data,
+ input [2-1: 0] sink0_channel,
+ input sink0_startofpacket,
+ input sink0_endofpacket,
+ output sink0_ready,
+
+ input sink1_valid,
+ input [157-1 : 0] sink1_data,
+ input [2-1: 0] sink1_channel,
+ input sink1_startofpacket,
+ input sink1_endofpacket,
+ output sink1_ready,
+
+
+ // ----------------------
+ // Source
+ // ----------------------
+ output src_valid,
+ output [157-1 : 0] src_data,
+ output [2-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready,
+
+ // ----------------------
+ // Clock & Reset
+ // ----------------------
+ input clk,
+ input reset
+);
+ localparam PAYLOAD_W = 157 + 2 + 2;
+ localparam NUM_INPUTS = 2;
+ localparam SHARE_COUNTER_W = 1;
+ localparam PIPELINE_ARB = 0;
+ localparam ST_DATA_W = 157;
+ localparam ST_CHANNEL_W = 2;
+ localparam PKT_TRANS_LOCK = 108;
+
+ // ------------------------------------------
+ // Signals
+ // ------------------------------------------
+ wire [NUM_INPUTS - 1 : 0] request;
+ wire [NUM_INPUTS - 1 : 0] valid;
+ wire [NUM_INPUTS - 1 : 0] grant;
+ wire [NUM_INPUTS - 1 : 0] next_grant;
+ reg [NUM_INPUTS - 1 : 0] saved_grant;
+ reg [PAYLOAD_W - 1 : 0] src_payload;
+ wire last_cycle;
+ reg packet_in_progress;
+ reg update_grant;
+
+ wire [PAYLOAD_W - 1 : 0] sink0_payload;
+ wire [PAYLOAD_W - 1 : 0] sink1_payload;
+
+ assign valid[0] = sink0_valid;
+ assign valid[1] = sink1_valid;
+
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Grant Logic & Updates
+ // ------------------------------------------
+ // ------------------------------------------
+ reg [NUM_INPUTS - 1 : 0] lock;
+ always @* begin
+ lock[0] = sink0_data[108];
+ lock[1] = sink1_data[108];
+ end
+
+ assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
+
+ // ------------------------------------------
+ // We're working on a packet at any time valid is high, except
+ // when this is the endofpacket.
+ // ------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ packet_in_progress <= 1'b0;
+ end
+ else begin
+ if (last_cycle)
+ packet_in_progress <= 1'b0;
+ else if (src_valid)
+ packet_in_progress <= 1'b1;
+ end
+ end
+
+
+ // ------------------------------------------
+ // Shares
+ //
+ // Special case: all-equal shares _should_ be optimized into assigning a
+ // constant to next_grant_share.
+ // Special case: all-1's shares _should_ result in the share counter
+ // being optimized away.
+ // ------------------------------------------
+ // Input | arb shares | counter load value
+ // 0 | 1 | 0
+ // 1 | 1 | 0
+ wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
+ wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
+
+ // ------------------------------------------
+ // Choose the share value corresponding to the grant.
+ // ------------------------------------------
+ reg [SHARE_COUNTER_W - 1 : 0] next_grant_share;
+ always @* begin
+ next_grant_share =
+ share_0 & { SHARE_COUNTER_W {next_grant[0]} } |
+ share_1 & { SHARE_COUNTER_W {next_grant[1]} };
+ end
+
+ // ------------------------------------------
+ // Flag to indicate first packet of an arb sequence.
+ // ------------------------------------------
+ wire grant_changed = ~packet_in_progress && ~(|(saved_grant & valid));
+ reg first_packet_r;
+ wire first_packet = grant_changed | first_packet_r;
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ first_packet_r <= 1'b0;
+ end
+ else begin
+ if (update_grant)
+ first_packet_r <= 1'b1;
+ else if (last_cycle)
+ first_packet_r <= 1'b0;
+ else if (grant_changed)
+ first_packet_r <= 1'b1;
+ end
+ end
+
+ // ------------------------------------------
+ // Compute the next share-count value.
+ // ------------------------------------------
+ reg [SHARE_COUNTER_W - 1 : 0] p1_share_count;
+ reg [SHARE_COUNTER_W - 1 : 0] share_count;
+ reg share_count_zero_flag;
+
+ always @* begin
+ if (first_packet) begin
+ p1_share_count = next_grant_share;
+ end
+ else begin
+ // Update the counter, but don't decrement below 0.
+ p1_share_count = share_count_zero_flag ? '0 : share_count - 1'b1;
+ end
+ end
+
+ // ------------------------------------------
+ // Update the share counter and share-counter=zero flag.
+ // ------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ share_count <= '0;
+ share_count_zero_flag <= 1'b1;
+ end
+ else begin
+ if (last_cycle) begin
+ share_count <= p1_share_count;
+ share_count_zero_flag <= (p1_share_count == '0);
+ end
+ end
+ end
+
+ // ------------------------------------------
+ // For each input, maintain a final_packet signal which goes active for the
+ // last packet of a full-share packet sequence. Example: if I have 4
+ // shares and I'm continuously requesting, final_packet is active in the
+ // 4th packet.
+ // ------------------------------------------
+ wire final_packet_0 = 1'b1;
+
+ wire final_packet_1 = 1'b1;
+
+
+ // ------------------------------------------
+ // Concatenate all final_packet signals (wire or reg) into a handy vector.
+ // ------------------------------------------
+ wire [NUM_INPUTS - 1 : 0] final_packet = {
+ final_packet_1,
+ final_packet_0
+ };
+
+ // ------------------------------------------
+ // ------------------------------------------
+ wire p1_done = |(final_packet & grant);
+
+ // ------------------------------------------
+ // Flag for the first cycle of packets within an
+ // arb sequence
+ // ------------------------------------------
+ reg first_cycle;
+ always @(posedge clk, posedge reset) begin
+ if (reset)
+ first_cycle <= 0;
+ else
+ first_cycle <= last_cycle && ~p1_done;
+ end
+
+
+ always @* begin
+ update_grant = 0;
+
+ // ------------------------------------------
+ // No arbitration pipeline, update grant whenever
+ // the current arb winner has consumed all shares,
+ // or all requests are low
+ // ------------------------------------------
+ update_grant = (last_cycle && p1_done) || (first_cycle && ~(|valid));
+ update_grant = last_cycle;
+ end
+
+ wire save_grant;
+ assign save_grant = 1;
+ assign grant = next_grant;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset)
+ saved_grant <= '0;
+ else if (save_grant)
+ saved_grant <= next_grant;
+ end
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Arbitrator
+ // ------------------------------------------
+ // ------------------------------------------
+
+ // ------------------------------------------
+ // Create a request vector that stays high during
+ // the packet for unpipelined arbitration.
+ //
+ // The pipelined arbitration scheme does not require
+ // request to be held high during the packet.
+ // ------------------------------------------
+ assign request = valid;
+
+ wire [NUM_INPUTS - 1 : 0] next_grant_from_arb;
+
+ altera_merlin_arbitrator
+ #(
+ .NUM_REQUESTERS(NUM_INPUTS),
+ .SCHEME ("no-arb"),
+ .PIPELINE (0)
+ ) arb (
+ .clk (clk),
+ .reset (reset),
+ .request (request),
+ .grant (next_grant_from_arb),
+ .save_top_priority (src_valid),
+ .increment_top_priority (update_grant)
+ );
+
+ assign next_grant = next_grant_from_arb;
+
+ // ------------------------------------------
+ // ------------------------------------------
+ // Mux
+ //
+ // Implemented as a sum of products.
+ // ------------------------------------------
+ // ------------------------------------------
+
+ assign sink0_ready = src_ready && grant[0];
+ assign sink1_ready = src_ready && grant[1];
+
+ assign src_valid = |(grant & valid);
+
+ always @* begin
+ src_payload =
+ sink0_payload & {PAYLOAD_W {grant[0]} } |
+ sink1_payload & {PAYLOAD_W {grant[1]} };
+ end
+
+ // ------------------------------------------
+ // Mux Payload Mapping
+ // ------------------------------------------
+
+ assign sink0_payload = {sink0_channel,sink0_data,
+ sink0_startofpacket,sink0_endofpacket};
+ assign sink1_payload = {sink1_channel,sink1_data,
+ sink1_startofpacket,sink1_endofpacket};
+
+ assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
+endmodule
+
+
diff --git a/quartus/qsys/arria10_hps/altera_merlin_router_221/synth/arria10_hps_altera_merlin_router_221_qdda7ra.sv b/quartus/qsys/arria10_hps/altera_merlin_router_221/synth/arria10_hps_altera_merlin_router_221_qdda7ra.sv
new file mode 100644
index 0000000000000000000000000000000000000000..107a58636887374e15f047d11c3aeada10995851
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_merlin_router_221/synth/arria10_hps_altera_merlin_router_221_qdda7ra.sv
@@ -0,0 +1,227 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module arria10_hps_altera_merlin_router_221_qdda7ra_default_decode
+ #(
+ parameter DEFAULT_CHANNEL = 0,
+ DEFAULT_WR_CHANNEL = -1,
+ DEFAULT_RD_CHANNEL = -1,
+ DEFAULT_DESTID = 0
+ )
+ (output [140 - 140 : 0] default_destination_id,
+ output [2-1 : 0] default_wr_channel,
+ output [2-1 : 0] default_rd_channel,
+ output [2-1 : 0] default_src_channel
+ );
+
+ assign default_destination_id =
+ DEFAULT_DESTID[140 - 140 : 0];
+
+ generate
+ if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+ assign default_src_channel = '0;
+ end
+ else begin : default_channel_assignment
+ assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
+ end
+ endgenerate
+
+ generate
+ if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+ assign default_wr_channel = '0;
+ assign default_rd_channel = '0;
+ end
+ else begin : default_rw_channel_assignment
+ assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
+ assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
+ end
+ endgenerate
+
+endmodule
+
+
+module arria10_hps_altera_merlin_router_221_qdda7ra
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Command Sink (Input)
+ // -------------------
+ input sink_valid,
+ input [157-1 : 0] sink_data,
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Command Source (Output)
+ // -------------------
+ output src_valid,
+ output reg [157-1 : 0] src_data,
+ output reg [2-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready
+);
+
+ // -------------------------------------------------------
+ // Local parameters and variables
+ // -------------------------------------------------------
+ localparam PKT_ADDR_H = 103;
+ localparam PKT_ADDR_L = 72;
+ localparam PKT_DEST_ID_H = 140;
+ localparam PKT_DEST_ID_L = 140;
+ localparam PKT_PROTECTION_H = 147;
+ localparam PKT_PROTECTION_L = 145;
+ localparam ST_DATA_W = 157;
+ localparam ST_CHANNEL_W = 2;
+ localparam DECODER_TYPE = 0;
+
+ localparam PKT_TRANS_WRITE = 106;
+ localparam PKT_TRANS_READ = 107;
+
+ localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+ localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+ // -------------------------------------------------------
+ // Figure out the number of bits to mask off for each slave span
+ // during address decoding
+ // -------------------------------------------------------
+ localparam PAD0 = log2ceil(64'h400 - 64'h0);
+ localparam PAD1 = log2ceil(64'h800 - 64'h400);
+ // -------------------------------------------------------
+ // Work out which address bits are significant based on the
+ // address range of the slaves. If the required width is too
+ // large or too small, we use the address field width instead.
+ // -------------------------------------------------------
+ localparam ADDR_RANGE = 64'h800;
+ localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+ localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+ (RANGE_ADDR_WIDTH == 0) ?
+ PKT_ADDR_H :
+ PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+ localparam RG = RANGE_ADDR_WIDTH-1;
+ localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+ reg [PKT_ADDR_W-1 : 0] address;
+ always @* begin
+ address = {PKT_ADDR_W{1'b0}};
+ address [REAL_ADDRESS_RANGE:0] = sink_data[OPTIMIZED_ADDR_H : PKT_ADDR_L];
+ end
+
+ // -------------------------------------------------------
+ // Pass almost everything through, untouched
+ // -------------------------------------------------------
+ assign sink_ready = src_ready;
+ assign src_valid = sink_valid;
+ assign src_startofpacket = sink_startofpacket;
+ assign src_endofpacket = sink_endofpacket;
+ wire [PKT_DEST_ID_W-1:0] default_destid;
+ wire [2-1 : 0] default_src_channel;
+
+
+
+
+
+
+ arria10_hps_altera_merlin_router_221_qdda7ra_default_decode the_default_decode(
+ .default_destination_id (default_destid),
+ .default_wr_channel (),
+ .default_rd_channel (),
+ .default_src_channel (default_src_channel)
+ );
+
+ always @* begin
+ src_data = sink_data;
+ src_channel = default_src_channel;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+ // --------------------------------------------------
+ // Address Decoder
+ // Sets the channel and destination ID based on the address
+ // --------------------------------------------------
+
+ // ( 0x0 .. 0x400 )
+ if ( {address[RG:PAD0],{PAD0{1'b0}}} == 11'h0 ) begin
+ src_channel = 2'b01;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+ end
+
+ // ( 0x400 .. 0x800 )
+ if ( {address[RG:PAD1],{PAD1{1'b0}}} == 11'h400 ) begin
+ src_channel = 2'b10;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
+ end
+
+end
+
+
+ // --------------------------------------------------
+ // Ceil(log2()) function
+ // --------------------------------------------------
+ function integer log2ceil;
+ input reg[65:0] val;
+ reg [65:0] i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
+
+
diff --git a/quartus/qsys/arria10_hps/altera_merlin_router_221/synth/arria10_hps_altera_merlin_router_221_qfjs35a.sv b/quartus/qsys/arria10_hps/altera_merlin_router_221/synth/arria10_hps_altera_merlin_router_221_qfjs35a.sv
new file mode 100644
index 0000000000000000000000000000000000000000..9073ac65a4479133f9a3b113b533297ea747b08c
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_merlin_router_221/synth/arria10_hps_altera_merlin_router_221_qfjs35a.sv
@@ -0,0 +1,216 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+// Your use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License Subscription
+// Agreement, Altera MegaCore Function License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -------------------------------------------------------
+// Merlin Router
+//
+// Asserts the appropriate one-hot encoded channel based on
+// either (a) the address or (b) the dest id. The DECODER_TYPE
+// parameter controls this behaviour. 0 means address decoder,
+// 1 means dest id decoder.
+//
+// In the case of (a), it also sets the destination id.
+// -------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+module arria10_hps_altera_merlin_router_221_qfjs35a_default_decode
+ #(
+ parameter DEFAULT_CHANNEL = 0,
+ DEFAULT_WR_CHANNEL = -1,
+ DEFAULT_RD_CHANNEL = -1,
+ DEFAULT_DESTID = 0
+ )
+ (output [140 - 140 : 0] default_destination_id,
+ output [2-1 : 0] default_wr_channel,
+ output [2-1 : 0] default_rd_channel,
+ output [2-1 : 0] default_src_channel
+ );
+
+ assign default_destination_id =
+ DEFAULT_DESTID[140 - 140 : 0];
+
+ generate
+ if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
+ assign default_src_channel = '0;
+ end
+ else begin : default_channel_assignment
+ assign default_src_channel = 2'b1 << DEFAULT_CHANNEL;
+ end
+ endgenerate
+
+ generate
+ if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
+ assign default_wr_channel = '0;
+ assign default_rd_channel = '0;
+ end
+ else begin : default_rw_channel_assignment
+ assign default_wr_channel = 2'b1 << DEFAULT_WR_CHANNEL;
+ assign default_rd_channel = 2'b1 << DEFAULT_RD_CHANNEL;
+ end
+ endgenerate
+
+endmodule
+
+
+module arria10_hps_altera_merlin_router_221_qfjs35a
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Command Sink (Input)
+ // -------------------
+ input sink_valid,
+ input [157-1 : 0] sink_data,
+ input sink_startofpacket,
+ input sink_endofpacket,
+ output sink_ready,
+
+ // -------------------
+ // Command Source (Output)
+ // -------------------
+ output src_valid,
+ output reg [157-1 : 0] src_data,
+ output reg [2-1 : 0] src_channel,
+ output src_startofpacket,
+ output src_endofpacket,
+ input src_ready
+);
+
+ // -------------------------------------------------------
+ // Local parameters and variables
+ // -------------------------------------------------------
+ localparam PKT_ADDR_H = 103;
+ localparam PKT_ADDR_L = 72;
+ localparam PKT_DEST_ID_H = 140;
+ localparam PKT_DEST_ID_L = 140;
+ localparam PKT_PROTECTION_H = 147;
+ localparam PKT_PROTECTION_L = 145;
+ localparam ST_DATA_W = 157;
+ localparam ST_CHANNEL_W = 2;
+ localparam DECODER_TYPE = 0;
+
+ localparam PKT_TRANS_WRITE = 106;
+ localparam PKT_TRANS_READ = 107;
+
+ localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
+ localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
+
+
+
+ // -------------------------------------------------------
+ // Figure out the number of bits to mask off for each slave span
+ // during address decoding
+ // -------------------------------------------------------
+ localparam PAD0 = log2ceil(64'h400 - 64'h0);
+ // -------------------------------------------------------
+ // Work out which address bits are significant based on the
+ // address range of the slaves. If the required width is too
+ // large or too small, we use the address field width instead.
+ // -------------------------------------------------------
+ localparam ADDR_RANGE = 64'h400;
+ localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
+ localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
+ (RANGE_ADDR_WIDTH == 0) ?
+ PKT_ADDR_H :
+ PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
+
+ localparam RG = RANGE_ADDR_WIDTH;
+ localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
+
+
+ // -------------------------------------------------------
+ // Pass almost everything through, untouched
+ // -------------------------------------------------------
+ assign sink_ready = src_ready;
+ assign src_valid = sink_valid;
+ assign src_startofpacket = sink_startofpacket;
+ assign src_endofpacket = sink_endofpacket;
+ wire [PKT_DEST_ID_W-1:0] default_destid;
+ wire [2-1 : 0] default_src_channel;
+
+
+
+
+
+
+ arria10_hps_altera_merlin_router_221_qfjs35a_default_decode the_default_decode(
+ .default_destination_id (default_destid),
+ .default_wr_channel (),
+ .default_rd_channel (),
+ .default_src_channel (default_src_channel)
+ );
+
+ always @* begin
+ src_data = sink_data;
+ src_channel = default_src_channel;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = default_destid;
+
+ // --------------------------------------------------
+ // Address Decoder
+ // Sets the channel and destination ID based on the address
+ // --------------------------------------------------
+
+
+ // ( 0 .. 400 )
+ src_channel = 2'b1;
+ src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
+
+
+
+end
+
+
+ // --------------------------------------------------
+ // Ceil(log2()) function
+ // --------------------------------------------------
+ function integer log2ceil;
+ input reg[65:0] val;
+ reg [65:0] i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
+
+
diff --git a/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_avalon_sc_fifo.v b/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_avalon_sc_fifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..cf8576af6b5e450cb1277a56f25328cb56ff82e0
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_avalon_sc_fifo.v
@@ -0,0 +1,915 @@
+// -----------------------------------------------------------
+// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
+// use of Altera Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any
+// output files any of the foregoing (including device programming or
+// simulation files), and any associated documentation or information are
+// expressly subject to the terms and conditions of the Altera Program
+// License Subscription Agreement or other applicable license agreement,
+// including, without limitation, that your use is for the sole purpose
+// of programming logic devices manufactured by Altera and sold by Altera
+// or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+//
+// Description: Single clock Avalon-ST FIFO.
+// -----------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+
+//altera message_off 10036
+module altera_avalon_sc_fifo
+#(
+ // --------------------------------------------------
+ // Parameters
+ // --------------------------------------------------
+ parameter SYMBOLS_PER_BEAT = 1,
+ parameter BITS_PER_SYMBOL = 8,
+ parameter FIFO_DEPTH = 16,
+ parameter CHANNEL_WIDTH = 0,
+ parameter ERROR_WIDTH = 0,
+ parameter USE_PACKETS = 0,
+ parameter USE_FILL_LEVEL = 0,
+ parameter USE_STORE_FORWARD = 0,
+ parameter USE_ALMOST_FULL_IF = 0,
+ parameter USE_ALMOST_EMPTY_IF = 0,
+
+ // --------------------------------------------------
+ // Empty latency is defined as the number of cycles
+ // required for a write to deassert the empty flag.
+ // For example, a latency of 1 means that the empty
+ // flag is deasserted on the cycle after a write.
+ //
+ // Another way to think of it is the latency for a
+ // write to propagate to the output.
+ //
+ // An empty latency of 0 implies lookahead, which is
+ // only implemented for the register-based FIFO.
+ // --------------------------------------------------
+ parameter EMPTY_LATENCY = 3,
+ parameter USE_MEMORY_BLOCKS = 1,
+
+ // --------------------------------------------------
+ // Internal Parameters
+ // --------------------------------------------------
+ parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
+ parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
+)
+(
+ // --------------------------------------------------
+ // Ports
+ // --------------------------------------------------
+ input clk,
+ input reset,
+
+ input [DATA_WIDTH-1: 0] in_data,
+ input in_valid,
+ input in_startofpacket,
+ input in_endofpacket,
+ input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
+ input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
+ input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
+ output in_ready,
+
+ output [DATA_WIDTH-1 : 0] out_data,
+ output reg out_valid,
+ output out_startofpacket,
+ output out_endofpacket,
+ output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
+ output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
+ output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
+ input out_ready,
+
+ input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
+ input csr_write,
+ input csr_read,
+ input [31 : 0] csr_writedata,
+ output reg [31 : 0] csr_readdata,
+
+ output wire almost_full_data,
+ output wire almost_empty_data
+);
+
+ // --------------------------------------------------
+ // Local Parameters
+ // --------------------------------------------------
+ localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
+ localparam DEPTH = FIFO_DEPTH;
+ localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
+ localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
+ 2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
+ DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
+
+ // --------------------------------------------------
+ // Internal Signals
+ // --------------------------------------------------
+ genvar i;
+
+ reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
+ reg [ADDR_WIDTH-1 : 0] wr_ptr;
+ reg [ADDR_WIDTH-1 : 0] rd_ptr;
+ reg [DEPTH-1 : 0] mem_used;
+
+ wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
+ wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
+ wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
+ wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
+
+ wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
+
+ wire read;
+ wire write;
+
+ reg empty;
+ reg next_empty;
+ reg full;
+ reg next_full;
+
+ wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
+ wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
+ wire [PAYLOAD_WIDTH-1 : 0] in_payload;
+ reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
+ reg [PAYLOAD_WIDTH-1 : 0] out_payload;
+
+ reg internal_out_valid;
+ wire internal_out_ready;
+
+ reg [ADDR_WIDTH : 0] fifo_fill_level;
+ reg [ADDR_WIDTH : 0] fill_level;
+
+ reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
+ wire [ADDR_WIDTH-1 : 0] curr_sop_ptr;
+ reg [23:0] almost_full_threshold;
+ reg [23:0] almost_empty_threshold;
+ reg [23:0] cut_through_threshold;
+ reg [15:0] pkt_cnt;
+ reg drop_on_error_en;
+ reg error_in_pkt;
+ reg pkt_has_started;
+ reg sop_has_left_fifo;
+ reg fifo_too_small_r;
+ reg pkt_cnt_eq_zero;
+ reg pkt_cnt_eq_one;
+
+ wire wait_for_threshold;
+ reg pkt_mode;
+ wire wait_for_pkt;
+ wire ok_to_forward;
+ wire in_pkt_eop_arrive;
+ wire out_pkt_leave;
+ wire in_pkt_start;
+ wire in_pkt_error;
+ wire drop_on_error;
+ wire fifo_too_small;
+ wire out_pkt_sop_leave;
+ wire [31:0] max_fifo_size;
+ reg fifo_fill_level_lt_cut_through_threshold;
+
+ // --------------------------------------------------
+ // Define Payload
+ //
+ // Icky part where we decide which signals form the
+ // payload to the FIFO with generate blocks.
+ // --------------------------------------------------
+ generate
+ if (EMPTY_WIDTH > 0) begin : gen_blk1
+ assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
+ assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
+ end
+ else begin : gen_blk1_else
+ assign out_empty = in_error;
+ assign in_packet_signals = {in_startofpacket, in_endofpacket};
+ assign {out_startofpacket, out_endofpacket} = out_packet_signals;
+ end
+ endgenerate
+
+ generate
+ if (USE_PACKETS) begin : gen_blk2
+ if (ERROR_WIDTH > 0) begin : gen_blk3
+ if (CHANNEL_WIDTH > 0) begin : gen_blk4
+ assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
+ assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
+ end
+ else begin : gen_blk4_else
+ assign out_channel = in_channel;
+ assign in_payload = {in_packet_signals, in_data, in_error};
+ assign {out_packet_signals, out_data, out_error} = out_payload;
+ end
+ end
+ else begin : gen_blk3_else
+ assign out_error = in_error;
+ if (CHANNEL_WIDTH > 0) begin : gen_blk5
+ assign in_payload = {in_packet_signals, in_data, in_channel};
+ assign {out_packet_signals, out_data, out_channel} = out_payload;
+ end
+ else begin : gen_blk5_else
+ assign out_channel = in_channel;
+ assign in_payload = {in_packet_signals, in_data};
+ assign {out_packet_signals, out_data} = out_payload;
+ end
+ end
+ end
+ else begin : gen_blk2_else
+ assign out_packet_signals = 0;
+ if (ERROR_WIDTH > 0) begin : gen_blk6
+ if (CHANNEL_WIDTH > 0) begin : gen_blk7
+ assign in_payload = {in_data, in_error, in_channel};
+ assign {out_data, out_error, out_channel} = out_payload;
+ end
+ else begin : gen_blk7_else
+ assign out_channel = in_channel;
+ assign in_payload = {in_data, in_error};
+ assign {out_data, out_error} = out_payload;
+ end
+ end
+ else begin : gen_blk6_else
+ assign out_error = in_error;
+ if (CHANNEL_WIDTH > 0) begin : gen_blk8
+ assign in_payload = {in_data, in_channel};
+ assign {out_data, out_channel} = out_payload;
+ end
+ else begin : gen_blk8_else
+ assign out_channel = in_channel;
+ assign in_payload = in_data;
+ assign out_data = out_payload;
+ end
+ end
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Memory-based FIFO storage
+ //
+ // To allow a ready latency of 0, the read index is
+ // obtained from the next read pointer and memory
+ // outputs are unregistered.
+ //
+ // If the empty latency is 1, we infer bypass logic
+ // around the memory so writes propagate to the
+ // outputs on the next cycle.
+ //
+ // Do not change the way this is coded: Quartus needs
+ // a perfect match to the template, and any attempt to
+ // refactor the two always blocks into one will break
+ // memory inference.
+ // --------------------------------------------------
+ generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk9
+
+ if (EMPTY_LATENCY == 1) begin : gen_blk10
+
+ always @(posedge clk) begin
+ if (in_valid && in_ready)
+ mem[wr_ptr] = in_payload;
+
+ internal_out_payload = mem[mem_rd_ptr];
+ end
+
+ end else begin : gen_blk10_else
+
+ always @(posedge clk) begin
+ if (in_valid && in_ready)
+ mem[wr_ptr] <= in_payload;
+
+ internal_out_payload <= mem[mem_rd_ptr];
+ end
+
+ end
+
+ assign mem_rd_ptr = next_rd_ptr;
+
+ end else begin : gen_blk9_else
+
+ // --------------------------------------------------
+ // Register-based FIFO storage
+ //
+ // Uses a shift register as the storage element. Each
+ // shift register slot has a bit which indicates if
+ // the slot is occupied (credit to Sam H for the idea).
+ // The occupancy bits are contiguous and start from the
+ // lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
+ // FIFO.
+ //
+ // Each slot is enabled during a read or when it
+ // is unoccupied. New data is always written to every
+ // going-to-be-empty slot (we keep track of which ones
+ // are actually useful with the occupancy bits). On a
+ // read we shift occupied slots.
+ //
+ // The exception is the last slot, which always gets
+ // new data when it is unoccupied.
+ // --------------------------------------------------
+ for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ mem[i] <= 0;
+ end
+ else if (read || !mem_used[i]) begin
+ if (!mem_used[i+1])
+ mem[i] <= in_payload;
+ else
+ mem[i] <= mem[i+1];
+ end
+ end
+ end
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ mem[DEPTH-1] <= 0;
+ end
+ else begin
+ if (DEPTH == 1) begin
+ if (write)
+ mem[DEPTH-1] <= in_payload;
+ end
+ else if (!mem_used[DEPTH-1])
+ mem[DEPTH-1] <= in_payload;
+ end
+ end
+
+ end
+ endgenerate
+
+ assign read = internal_out_ready && internal_out_valid && ok_to_forward;
+ assign write = in_ready && in_valid;
+
+ // --------------------------------------------------
+ // Pointer Management
+ // --------------------------------------------------
+ generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk11
+
+ assign incremented_wr_ptr = wr_ptr + 1'b1;
+ assign incremented_rd_ptr = rd_ptr + 1'b1;
+ assign next_wr_ptr = drop_on_error ? curr_sop_ptr : write ? incremented_wr_ptr : wr_ptr;
+ assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ wr_ptr <= 0;
+ rd_ptr <= 0;
+ end
+ else begin
+ wr_ptr <= next_wr_ptr;
+ rd_ptr <= next_rd_ptr;
+ end
+ end
+
+ end else begin : gen_blk11_else
+
+ // --------------------------------------------------
+ // Shift Register Occupancy Bits
+ //
+ // Consider a 4-deep FIFO with 2 entries: 0011
+ // On a read and write, do not modify the bits.
+ // On a write, left-shift the bits to get 0111.
+ // On a read, right-shift the bits to get 0001.
+ //
+ // Also, on a write we set bit0 (the head), while
+ // clearing the tail on a read.
+ // --------------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ mem_used[0] <= 0;
+ end
+ else begin
+ if (write ^ read) begin
+ if (write)
+ mem_used[0] <= 1;
+ else if (read) begin
+ if (DEPTH > 1)
+ mem_used[0] <= mem_used[1];
+ else
+ mem_used[0] <= 0;
+ end
+ end
+ end
+ end
+
+ if (DEPTH > 1) begin : gen_blk12
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ mem_used[DEPTH-1] <= 0;
+ end
+ else begin
+ if (write ^ read) begin
+ mem_used[DEPTH-1] <= 0;
+ if (write)
+ mem_used[DEPTH-1] <= mem_used[DEPTH-2];
+ end
+ end
+ end
+ end
+
+ for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ mem_used[i] <= 0;
+ end
+ else begin
+ if (write ^ read) begin
+ if (write)
+ mem_used[i] <= mem_used[i-1];
+ else if (read)
+ mem_used[i] <= mem_used[i+1];
+ end
+ end
+ end
+ end
+
+ end
+ endgenerate
+
+
+ // --------------------------------------------------
+ // Memory FIFO Status Management
+ //
+ // Generates the full and empty signals from the
+ // pointers. The FIFO is full when the next write
+ // pointer will be equal to the read pointer after
+ // a write. Reading from a FIFO clears full.
+ //
+ // The FIFO is empty when the next read pointer will
+ // be equal to the write pointer after a read. Writing
+ // to a FIFO clears empty.
+ //
+ // A simultaneous read and write must not change any of
+ // the empty or full flags unless there is a drop on error event.
+ // --------------------------------------------------
+ generate if (USE_MEMORY_BLOCKS == 1) begin : gen_blk13
+
+ always @* begin
+ next_full = full;
+ next_empty = empty;
+
+ if (read && !write) begin
+ next_full = 1'b0;
+
+ if (incremented_rd_ptr == wr_ptr)
+ next_empty = 1'b1;
+ end
+
+ if (write && !read) begin
+ if (!drop_on_error)
+ next_empty = 1'b0;
+ else if (curr_sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
+ next_empty = 1'b1;
+
+ if (incremented_wr_ptr == rd_ptr && !drop_on_error)
+ next_full = 1'b1;
+ end
+
+ if (write && read && drop_on_error) begin
+ if (curr_sop_ptr == next_rd_ptr)
+ next_empty = 1'b1;
+ end
+ end
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ empty <= 1;
+ full <= 0;
+ end
+ else begin
+ empty <= next_empty;
+ full <= next_full;
+ end
+ end
+
+ end else begin : gen_blk13_else
+ // --------------------------------------------------
+ // Register FIFO Status Management
+ //
+ // Full when the tail occupancy bit is 1. Empty when
+ // the head occupancy bit is 0.
+ // --------------------------------------------------
+ always @* begin
+ full = mem_used[DEPTH-1];
+ empty = !mem_used[0];
+
+ // ------------------------------------------
+ // For a single slot FIFO, reading clears the
+ // full status immediately.
+ // ------------------------------------------
+ if (DEPTH == 1)
+ full = mem_used[0] && !read;
+
+ internal_out_payload = mem[0];
+
+ // ------------------------------------------
+ // Writes clear empty immediately for lookahead modes.
+ // Note that we use in_valid instead of write to avoid
+ // combinational loops (in lookahead mode, qualifying
+ // with in_ready is meaningless).
+ //
+ // In a 1-deep FIFO, a possible combinational loop runs
+ // from write -> out_valid -> out_ready -> write
+ // ------------------------------------------
+ if (EMPTY_LATENCY == 0) begin
+ empty = !mem_used[0] && !in_valid;
+
+ if (!mem_used[0] && in_valid)
+ internal_out_payload = in_payload;
+ end
+ end
+
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Avalon-ST Signals
+ //
+ // The in_ready signal is straightforward.
+ //
+ // To match memory latency when empty latency > 1,
+ // out_valid assertions must be delayed by one clock
+ // cycle.
+ //
+ // Note: out_valid deassertions must not be delayed or
+ // the FIFO will underflow.
+ // --------------------------------------------------
+ assign in_ready = !full;
+ assign internal_out_ready = out_ready || !out_valid;
+
+ generate if (EMPTY_LATENCY > 1) begin : gen_blk14
+ always @(posedge clk or posedge reset) begin
+ if (reset)
+ internal_out_valid <= 0;
+ else begin
+ internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
+
+ if (read) begin
+ if (incremented_rd_ptr == wr_ptr)
+ internal_out_valid <= 1'b0;
+ end
+ end
+ end
+ end else begin : gen_blk14_else
+ always @* begin
+ internal_out_valid = !empty & ok_to_forward;
+ end
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Single Output Pipeline Stage
+ //
+ // This output pipeline stage is enabled if the FIFO's
+ // empty latency is set to 3 (default). It is disabled
+ // for all other allowed latencies.
+ //
+ // Reason: The memory outputs are unregistered, so we have to
+ // register the output or fmax will drop if combinatorial
+ // logic is present on the output datapath.
+ //
+ // Q: The Avalon-ST spec says that I have to register my outputs
+ // But isn't the memory counted as a register?
+ // A: The path from the address lookup to the memory output is
+ // slow. Registering the memory outputs is a good idea.
+ //
+ // The registers get packed into the memory by the fitter
+ // which means minimal resources are consumed (the result
+ // is a altsyncram with registered outputs, available on
+ // all modern Altera devices).
+ //
+ // This output stage acts as an extra slot in the FIFO,
+ // and complicates the fill level.
+ // --------------------------------------------------
+ generate if (EMPTY_LATENCY == 3) begin : gen_blk15
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ out_valid <= 0;
+ out_payload <= 0;
+ end
+ else begin
+ if (internal_out_ready) begin
+ out_valid <= internal_out_valid & ok_to_forward;
+ out_payload <= internal_out_payload;
+ end
+ end
+ end
+ end
+ else begin : gen_blk15_else
+ always @* begin
+ out_valid = internal_out_valid;
+ out_payload = internal_out_payload;
+ end
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Fill Level
+ //
+ // The fill level is calculated from the next write
+ // and read pointers to avoid unnecessary latency
+ // and logic.
+ //
+ // However, if the store-and-forward mode of the FIFO
+ // is enabled, the fill level is an up-down counter
+ // for fmax optimization reasons.
+ //
+ // If the output pipeline is enabled, the fill level
+ // must account for it, or we'll always be off by one.
+ // This may, or may not be important depending on the
+ // application.
+ //
+ // For now, we'll always calculate the exact fill level
+ // at the cost of an extra adder when the output stage
+ // is enabled.
+ // --------------------------------------------------
+ generate if (USE_FILL_LEVEL) begin : gen_blk16
+ wire [31:0] depth32;
+ assign depth32 = DEPTH;
+
+ if (USE_STORE_FORWARD) begin
+
+ reg [ADDR_WIDTH : 0] curr_packet_len_less_one;
+
+ // --------------------------------------------------
+ // We only drop on endofpacket. As long as we don't add to the fill
+ // level on the dropped endofpacket cycle, we can simply subtract
+ // (packet length - 1) from the fill level for dropped packets.
+ // --------------------------------------------------
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ curr_packet_len_less_one <= 0;
+ end else begin
+ if (write) begin
+ curr_packet_len_less_one <= curr_packet_len_less_one + 1'b1;
+ if (in_endofpacket)
+ curr_packet_len_less_one <= 0;
+ end
+ end
+ end
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ fifo_fill_level <= 0;
+ end else if (drop_on_error) begin
+ fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one;
+ if (read)
+ fifo_fill_level <= fifo_fill_level - curr_packet_len_less_one - 1'b1;
+ end else if (write && !read) begin
+ fifo_fill_level <= fifo_fill_level + 1'b1;
+ end else if (read && !write) begin
+ fifo_fill_level <= fifo_fill_level - 1'b1;
+ end
+ end
+
+ end else begin
+
+ always @(posedge clk or posedge reset) begin
+ if (reset)
+ fifo_fill_level <= 0;
+ else if (next_full & !drop_on_error)
+ fifo_fill_level <= depth32[ADDR_WIDTH:0];
+ else begin
+ fifo_fill_level[ADDR_WIDTH] <= 1'b0;
+ fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
+ end
+ end
+
+ end
+
+ always @* begin
+ fill_level = fifo_fill_level;
+
+ if (EMPTY_LATENCY == 3)
+ fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
+ end
+ end
+ else begin : gen_blk16_else
+ always @* begin
+ fill_level = 0;
+ end
+ end
+ endgenerate
+
+ generate if (USE_ALMOST_FULL_IF) begin : gen_blk17
+ assign almost_full_data = (fill_level >= almost_full_threshold);
+ end
+ else
+ assign almost_full_data = 0;
+ endgenerate
+
+ generate if (USE_ALMOST_EMPTY_IF) begin : gen_blk18
+ assign almost_empty_data = (fill_level <= almost_empty_threshold);
+ end
+ else
+ assign almost_empty_data = 0;
+ endgenerate
+
+ // --------------------------------------------------
+ // Avalon-MM Status & Control Connection Point
+ //
+ // Register map:
+ //
+ // | Addr | RW | 31 - 0 |
+ // | 0 | R | Fill level |
+ //
+ // The registering of this connection point means
+ // that there is a cycle of latency between
+ // reads/writes and the updating of the fill level.
+ // --------------------------------------------------
+ generate if (USE_STORE_FORWARD) begin : gen_blk19
+ assign max_fifo_size = FIFO_DEPTH - 1;
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ almost_full_threshold <= max_fifo_size[23 : 0];
+ almost_empty_threshold <= 0;
+ cut_through_threshold <= 0;
+ drop_on_error_en <= 0;
+ csr_readdata <= 0;
+ pkt_mode <= 1'b1;
+ end
+ else begin
+ if (csr_read) begin
+ csr_readdata <= 32'b0;
+ if (csr_address == 5)
+ csr_readdata <= {31'b0, drop_on_error_en};
+ else if (csr_address == 4)
+ csr_readdata <= {8'b0, cut_through_threshold};
+ else if (csr_address == 3)
+ csr_readdata <= {8'b0, almost_empty_threshold};
+ else if (csr_address == 2)
+ csr_readdata <= {8'b0, almost_full_threshold};
+ else if (csr_address == 0)
+ csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+ end
+ else if (csr_write) begin
+ if(csr_address == 3'b101)
+ drop_on_error_en <= csr_writedata[0];
+ else if(csr_address == 3'b100) begin
+ cut_through_threshold <= csr_writedata[23:0];
+ pkt_mode <= (csr_writedata[23:0] == 0);
+ end
+ else if(csr_address == 3'b011)
+ almost_empty_threshold <= csr_writedata[23:0];
+ else if(csr_address == 3'b010)
+ almost_full_threshold <= csr_writedata[23:0];
+ end
+ end
+ end
+ end
+ else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin : gen_blk19_else1
+ assign max_fifo_size = FIFO_DEPTH - 1;
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ almost_full_threshold <= max_fifo_size[23 : 0];
+ almost_empty_threshold <= 0;
+ csr_readdata <= 0;
+ end
+ else begin
+ if (csr_read) begin
+ csr_readdata <= 32'b0;
+ if (csr_address == 3)
+ csr_readdata <= {8'b0, almost_empty_threshold};
+ else if (csr_address == 2)
+ csr_readdata <= {8'b0, almost_full_threshold};
+ else if (csr_address == 0)
+ csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+ end
+ else if (csr_write) begin
+ if(csr_address == 3'b011)
+ almost_empty_threshold <= csr_writedata[23:0];
+ else if(csr_address == 3'b010)
+ almost_full_threshold <= csr_writedata[23:0];
+ end
+ end
+ end
+ end
+ else begin : gen_blk19_else2
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ csr_readdata <= 0;
+ end
+ else if (csr_read) begin
+ csr_readdata <= 0;
+
+ if (csr_address == 0)
+ csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
+ end
+ end
+ end
+ endgenerate
+
+ // --------------------------------------------------
+ // Store and forward logic
+ // --------------------------------------------------
+ // if the fifo gets full before the entire packet or the
+ // cut-threshold condition is met then start sending out
+ // data in order to avoid dead-lock situation
+
+ generate if (USE_STORE_FORWARD) begin : gen_blk20
+ assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
+ assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
+ assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
+ ~wait_for_threshold) | fifo_too_small_r;
+ assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
+ assign in_pkt_start = in_valid & in_ready & in_startofpacket;
+ assign in_pkt_error = in_valid & in_ready & |in_error;
+ assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
+ assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
+ assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
+
+ // count packets coming and going into the fifo
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ pkt_cnt <= 0;
+ pkt_has_started <= 0;
+ sop_has_left_fifo <= 0;
+ fifo_too_small_r <= 0;
+ pkt_cnt_eq_zero <= 1'b1;
+ pkt_cnt_eq_one <= 1'b0;
+ fifo_fill_level_lt_cut_through_threshold <= 1'b1;
+ end
+ else begin
+ fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
+ fifo_too_small_r <= fifo_too_small;
+
+ if( in_pkt_eop_arrive )
+ sop_has_left_fifo <= 1'b0;
+ else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
+ sop_has_left_fifo <= 1'b1;
+
+ if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
+ pkt_cnt <= pkt_cnt + 1'b1;
+ pkt_cnt_eq_zero <= 0;
+ if (pkt_cnt == 0)
+ pkt_cnt_eq_one <= 1'b1;
+ else
+ pkt_cnt_eq_one <= 1'b0;
+ end
+ else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
+ pkt_cnt <= pkt_cnt - 1'b1;
+ if (pkt_cnt == 1)
+ pkt_cnt_eq_zero <= 1'b1;
+ else
+ pkt_cnt_eq_zero <= 1'b0;
+ if (pkt_cnt == 2)
+ pkt_cnt_eq_one <= 1'b1;
+ else
+ pkt_cnt_eq_one <= 1'b0;
+ end
+
+ if (in_pkt_start)
+ pkt_has_started <= 1'b1;
+ else if (in_pkt_eop_arrive)
+ pkt_has_started <= 1'b0;
+ end
+ end
+
+ // drop on error logic
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ sop_ptr <= 0;
+ error_in_pkt <= 0;
+ end
+ else begin
+ // save the location of the SOP
+ if ( in_pkt_start )
+ sop_ptr <= wr_ptr;
+
+ // remember if error in pkt
+ // log error only if packet has already started
+ if (in_pkt_eop_arrive)
+ error_in_pkt <= 1'b0;
+ else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
+ error_in_pkt <= 1'b1;
+ end
+ end
+
+ assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
+ ~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
+
+ assign curr_sop_ptr = (write && in_startofpacket && in_endofpacket) ? wr_ptr : sop_ptr;
+
+ end
+ else begin : gen_blk20_else
+ assign ok_to_forward = 1'b1;
+ assign drop_on_error = 1'b0;
+ if (ADDR_WIDTH <= 1)
+ assign curr_sop_ptr = 1'b0;
+ else
+ assign curr_sop_ptr = {ADDR_WIDTH - 1 { 1'b0 }};
+ end
+ endgenerate
+
+
+ // --------------------------------------------------
+ // Calculates the log2ceil of the input value
+ // --------------------------------------------------
+ function integer log2ceil;
+ input integer val;
+ reg[31:0] i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i[30:0] << 1;
+ end
+ end
+ endfunction
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_avalon_st_pipeline_base.v b/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_avalon_st_pipeline_base.v
new file mode 100644
index 0000000000000000000000000000000000000000..8485f07832b6caefff070d4128bb467089080833
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_avalon_st_pipeline_base.v
@@ -0,0 +1,139 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $File: //acds/rel/22.1std/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+//------------------------------------------------------------------------------
+
+`timescale 1ns / 1ns
+
+module altera_avalon_st_pipeline_base (
+ clk,
+ reset,
+ in_ready,
+ in_valid,
+ in_data,
+ out_ready,
+ out_valid,
+ out_data
+ );
+
+ parameter SYMBOLS_PER_BEAT = 1;
+ parameter BITS_PER_SYMBOL = 8;
+ parameter PIPELINE_READY = 1;
+ localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
+
+ input clk;
+ input reset;
+
+ output in_ready;
+ input in_valid;
+ input [DATA_WIDTH-1:0] in_data;
+
+ input out_ready;
+ output out_valid;
+ output [DATA_WIDTH-1:0] out_data;
+
+ reg full0;
+ reg full1;
+ reg [DATA_WIDTH-1:0] data0;
+ reg [DATA_WIDTH-1:0] data1;
+
+ assign out_valid = full1;
+ assign out_data = data1;
+
+ generate if (PIPELINE_READY == 1)
+ begin : REGISTERED_READY_PLINE
+
+ assign in_ready = !full0;
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ data0 <= {DATA_WIDTH{1'b0}};
+ data1 <= {DATA_WIDTH{1'b0}};
+ end else begin
+ // ----------------------------
+ // always load the second slot if we can
+ // ----------------------------
+ if (~full0)
+ data0 <= in_data;
+ // ----------------------------
+ // first slot is loaded either from the second,
+ // or with new data
+ // ----------------------------
+ if (~full1 || (out_ready && out_valid)) begin
+ if (full0)
+ data1 <= data0;
+ else
+ data1 <= in_data;
+ end
+ end
+ end
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ full0 <= 1'b0;
+ full1 <= 1'b0;
+ end else begin
+ // no data in pipeline
+ if (~full0 & ~full1) begin
+ if (in_valid) begin
+ full1 <= 1'b1;
+ end
+ end // ~f1 & ~f0
+
+ // one datum in pipeline
+ if (full1 & ~full0) begin
+ if (in_valid & ~out_ready) begin
+ full0 <= 1'b1;
+ end
+ // back to empty
+ if (~in_valid & out_ready) begin
+ full1 <= 1'b0;
+ end
+ end // f1 & ~f0
+
+ // two data in pipeline
+ if (full1 & full0) begin
+ // go back to one datum state
+ if (out_ready) begin
+ full0 <= 1'b0;
+ end
+ end // end go back to one datum stage
+ end
+ end
+
+ end
+ else
+ begin : UNREGISTERED_READY_PLINE
+
+ // in_ready will be a pass through of the out_ready signal as it is not registered
+ assign in_ready = (~full1) | out_ready;
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ data1 <= 'b0;
+ full1 <= 1'b0;
+ end
+ else begin
+ if (in_ready) begin
+ data1 <= in_data;
+ full1 <= in_valid;
+ end
+ end
+ end
+ end
+ endgenerate
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_merlin_reorder_memory.sv b/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_merlin_reorder_memory.sv
new file mode 100644
index 0000000000000000000000000000000000000000..a94ae77d71d5eee75446f5f1c28a9c820f4db94d
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_merlin_reorder_memory.sv
@@ -0,0 +1,297 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_reorder_memory.sv#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// ------------------------------------------------------------------
+// Merlin Order Memory: this stores responses from slave
+// and do reorder. The memory structure is normal memory
+// with many segments for different responses that master
+// can handle.
+// The number of segment is the number of MAX_OUTSTANDING_RESPONSE
+// ------------------------------------------------------------------
+
+`timescale 1 ns / 1 ns
+module altera_merlin_reorder_memory
+#(
+ parameter DATA_W = 32,
+ ADDR_H_W = 4, // width to represent how many segments
+ ADDR_L_W = 4,
+ VALID_W = 4,
+ NUM_SEGMENT = 4,
+ DEPTH = 16
+
+)
+
+(
+ // -------------------
+ // Clock
+ // -------------------
+ input clk,
+ input reset,
+ // -------------------
+ // Signals
+ // -------------------
+ input [DATA_W - 1 : 0] in_data,
+ input in_valid,
+ output in_ready,
+
+ output reg [DATA_W - 1 : 0] out_data,
+ output reg out_valid,
+ input out_ready,
+ // --------------------------------------------
+ // wr_segment: select write portion of memory
+ // rd_segment: select read portion of memory
+ // --------------------------------------------
+ input [ADDR_H_W - 1 : 0] wr_segment,
+ input [ADDR_H_W - 1 : 0] rd_segment
+
+);
+
+ // -------------------------------------
+ // Local parameter
+ // -------------------------------------
+ localparam SEGMENT_W = ADDR_H_W;
+
+ wire [ADDR_H_W + ADDR_L_W - 1 : 0] mem_wr_addr;
+ reg [ADDR_H_W + ADDR_L_W - 1 : 0] mem_rd_addr;
+ wire [ADDR_L_W - 1 : 0] mem_wr_ptr;
+ wire [ADDR_L_W - 1 : 0] mem_rd_ptr;
+ reg [ADDR_L_W - 1 : 0] mem_next_rd_ptr;
+ reg [DATA_W - 1 : 0] out_payload;
+
+ wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_in_ready;
+ wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_in_valid;
+ wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_out_valid;
+ wire [NUM_SEGMENT - 1 : 0] pointer_ctrl_out_ready;
+ wire [ADDR_L_W - 1 : 0] pointer_ctrl_wr_ptr [NUM_SEGMENT];
+ wire [ADDR_L_W - 1 : 0] pointer_ctrl_rd_ptr [NUM_SEGMENT];
+ wire [ADDR_L_W - 1 : 0] pointer_ctrl_next_rd_ptr [NUM_SEGMENT];
+
+ // ---------------------------------
+ // Memory storage
+ // ---------------------------------
+ (* ramstyle="no_rw_check" *) reg [DATA_W - 1 : 0] mem [DEPTH - 1 : 0];
+ always @(posedge clk) begin
+ if (in_valid && in_ready)
+ mem[mem_wr_addr] = in_data;
+ out_payload = mem[mem_rd_addr];
+ end
+ //assign mem_rd_addr = {rd_segment, mem_next_rd_ptr};
+
+ always_comb
+ begin
+ out_data = out_payload;
+ out_valid = pointer_ctrl_out_valid[rd_segment];
+ end
+ // ---------------------------------
+ // Memory addresses
+ // ---------------------------------
+ assign mem_wr_ptr = pointer_ctrl_wr_ptr[wr_segment];
+ //assign mem_rd_ptr = pointer_ctrl_rd_ptr[rd_segment];
+ //assign mem_next_rd_ptr = pointer_ctrl_next_rd_ptr[rd_segment];
+
+ assign mem_wr_addr = {wr_segment, mem_wr_ptr};
+
+ // ---------------------------------------------------------------------------
+ // Bcos want, empty latency, mean assert read the data will appear on out_data.
+ // And need to jump around different segment of the memory.
+ // So when seeing endofpacket for this current segment, the read address
+ // will jump to next segment at first read address, so that the data will be ready
+ // it is okay to jump to next segment as this is the sequence of all transaction
+ // and they just increment. (standing at segment 0, then for sure next segment 1)
+ // ----------------------------------------------------------------------------
+ wire endofpacket;
+ assign endofpacket = out_payload[0];
+ wire [ADDR_H_W - 1: 0] next_rd_segment;
+ assign next_rd_segment = ((rd_segment + 1'b1) == NUM_SEGMENT) ? '0 : rd_segment + 1'b1;
+
+ always_comb
+ begin
+ if (out_valid && out_ready && endofpacket)
+ begin
+ mem_next_rd_ptr = pointer_ctrl_rd_ptr[next_rd_segment];
+ //mem_rd_addr = {rd_segment + 1'b1, mem_next_rd_ptr};
+ mem_rd_addr = {next_rd_segment, mem_next_rd_ptr};
+
+ end
+ else
+ begin
+ mem_next_rd_ptr = pointer_ctrl_next_rd_ptr[rd_segment];
+ mem_rd_addr = {rd_segment, mem_next_rd_ptr};
+ end
+ end
+
+
+ // ---------------------------------
+ // Output signals
+ // ---------------------------------
+ assign in_ready = pointer_ctrl_in_ready[wr_segment];
+
+ // ---------------------------------
+ // Control signals for each segment
+ // ---------------------------------
+ genvar j;
+ generate
+ for (j = 0; j < NUM_SEGMENT; j = j + 1)
+ begin : pointer_signal
+ assign pointer_ctrl_in_valid[j] = (wr_segment == j) && in_valid;
+ assign pointer_ctrl_out_ready[j] = (rd_segment == j) && out_ready;
+
+ end
+ endgenerate
+
+ // ---------------------------------
+ // Seperate write and read pointer
+ // for each segment in memory
+ // ---------------------------------
+ genvar i;
+ generate
+ for (i = 0; i < NUM_SEGMENT; i = i + 1)
+ begin : each_segment_pointer_controller
+ memory_pointer_controller
+ #(
+ .ADDR_W (ADDR_L_W)
+ ) reorder_memory_pointer_controller
+ (
+ .clk (clk),
+ .reset (reset),
+ .in_ready (pointer_ctrl_in_ready[i]),
+ .in_valid (pointer_ctrl_in_valid[i]),
+ .out_ready (pointer_ctrl_out_ready[i]),
+ .out_valid (pointer_ctrl_out_valid[i]),
+ .wr_pointer (pointer_ctrl_wr_ptr[i]),
+ .rd_pointer (pointer_ctrl_rd_ptr[i]),
+ .next_rd_pointer (pointer_ctrl_next_rd_ptr[i])
+ );
+ end // block: each_segment_pointer_controller
+ endgenerate
+endmodule
+
+
+module memory_pointer_controller
+#(
+ parameter ADDR_W = 4
+)
+(
+ // -------------------
+ // Clock
+ // -------------------
+ input clk,
+ input reset,
+ // -------------------
+ // Signals
+ // -------------------
+ output reg in_ready,
+ input in_valid,
+ input out_ready,
+ output reg out_valid,
+ // -------------------------------
+ // Output write and read pointer
+ // -------------------------------
+ output [ADDR_W - 1 : 0] wr_pointer,
+ output [ADDR_W - 1 : 0] rd_pointer,
+ output [ADDR_W - 1 : 0] next_rd_pointer
+);
+
+ reg [ADDR_W - 1 : 0] incremented_wr_ptr;
+ reg [ADDR_W - 1 : 0] incremented_rd_ptr;
+ reg [ADDR_W - 1 : 0] wr_ptr;
+ reg [ADDR_W - 1 : 0] rd_ptr;
+ reg [ADDR_W - 1 : 0] next_wr_ptr;
+ reg [ADDR_W - 1 : 0] next_rd_ptr;
+ reg full, empty, next_full, next_empty;
+ reg read, write, internal_out_ready, internal_out_valid;
+
+ assign incremented_wr_ptr = wr_ptr + 1'b1;
+ assign incremented_rd_ptr = rd_ptr + 1'b1;
+ assign next_wr_ptr = write ? incremented_wr_ptr : wr_ptr;
+ assign next_rd_ptr = read ? incremented_rd_ptr : rd_ptr;
+ assign wr_pointer = wr_ptr;
+ assign rd_pointer = rd_ptr;
+ assign next_rd_pointer = next_rd_ptr;
+
+ // -------------------------------
+ // Define write and read signals
+ // --------------------------------
+ // internal read, if it has any valid data
+ // and output are ready to accepts data then a read will be performed.
+ // -------------------------------
+ //assign read = internal_out_ready && internal_out_valid;
+ assign read = internal_out_ready && !empty;
+ assign write = in_ready && in_valid;
+
+ always_ff @(posedge clk or posedge reset)
+ begin
+ if (reset)
+ begin
+ wr_ptr <= 0;
+ rd_ptr <= 0;
+ end
+ else
+ begin
+ wr_ptr <= next_wr_ptr;
+ rd_ptr <= next_rd_ptr;
+ end
+ end
+ // ---------------------------------------------------------------------------
+ // Generate full/empty signal for memory
+ // if read and next read pointer same as write, set empty, write will clear empty
+ // if write and next write pointer same as read, set full, read will clear full
+ // -----------------------------------------------------------------------------
+ always_comb
+ begin
+ next_full = full;
+ next_empty = empty;
+ if (read && !write)
+ begin
+ next_full = 1'b0;
+ if (incremented_rd_ptr == wr_ptr)
+ next_empty = 1'b1;
+ end
+ if (write && !read)
+ begin
+ next_empty = 1'b0;
+ if (incremented_wr_ptr == rd_ptr)
+ next_full = 1'b1;
+ end
+ end // always_comb
+
+ always_ff @(posedge clk or posedge reset)
+ begin
+ if (reset)
+ begin
+ empty <= 1;
+ full <= 0;
+ end
+ else
+ begin
+ empty <= next_empty;
+ full <= next_full;
+ end
+ end
+
+ // --------------------
+ // Control signals
+ // --------------------
+ always_comb
+ begin
+ in_ready = !full;
+ out_valid = !empty;
+ internal_out_ready = out_ready;
+ end // always_comb
+endmodule
+
diff --git a/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_merlin_traffic_limiter.sv b/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_merlin_traffic_limiter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..26971b1c783b026f144fd1a7c97f2c1bf8625634
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_merlin_traffic_limiter_221/synth/altera_merlin_traffic_limiter.sv
@@ -0,0 +1,787 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// $Id: //acds/rel/22.1std/ip/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter.sv#1 $
+// $Revision: #1 $
+// $Date: 2021/10/27 $
+// $Author: psgswbuild $
+
+// -----------------------------------------------------
+// Merlin Traffic Limiter
+//
+// Ensures that non-posted transaction responses are returned
+// in order of request. Out-of-order responses can happen
+// when a master does a non-posted transaction on a slave
+// while responses are pending from a different slave.
+//
+// Examples:
+// 1) read to any latent slave, followed by a read to a
+// variable-latent slave
+// 2) read to any fixed-latency slave, followed by a read
+// to another fixed-latency slave whose fixed latency is smaller.
+// 3) non-posted write to any latent slave, followed by a non-posted
+// write or read to any variable-latent slave.
+//
+// This component has two implementation modes that ensure
+// response order, controlled by the REORDER parameter.
+//
+// 0) Backpressure to prevent a master from switching slaves
+// until all outstanding responses have returned. We also
+// have to suppress the non-posted transaction, obviously.
+//
+// 1) Reorder the responses as they return using a memory
+// block.
+// -----------------------------------------------------
+
+`timescale 1 ns / 1 ns
+
+// altera message_off 10036
+module altera_merlin_traffic_limiter
+#(
+ parameter
+ PKT_TRANS_POSTED = 1,
+ PKT_DEST_ID_H = 0,
+ PKT_DEST_ID_L = 0,
+ PKT_SRC_ID_H = 0,
+ PKT_SRC_ID_L = 0,
+ PKT_BYTE_CNT_H = 0,
+ PKT_BYTE_CNT_L = 0,
+ PKT_BYTEEN_H = 0,
+ PKT_BYTEEN_L = 0,
+ PKT_TRANS_WRITE = 0,
+ PKT_TRANS_READ = 0,
+ ST_DATA_W = 72,
+ ST_CHANNEL_W = 32,
+
+ MAX_OUTSTANDING_RESPONSES = 1,
+ PIPELINED = 0,
+ ENFORCE_ORDER = 1,
+
+ // -------------------------------------
+ // internal: allows optimization between this
+ // component and the demux
+ // -------------------------------------
+ VALID_WIDTH = 1,
+
+ // -------------------------------------
+ // Prevents all RAW and WAR hazards by waiting for
+ // responses to return before issuing a command
+ // with different direction.
+ //
+ // This is intended for Avalon masters which are
+ // connected to AXI slaves, because of the differing
+ // ordering models for the protocols.
+ //
+ // If PREVENT_HAZARDS is 1, then the current implementation
+ // needs to know whether incoming writes will be posted or
+ // not at compile-time. Only one of SUPPORTS_POSTED_WRITES
+ // and SUPPORTS_NONPOSTED_WRITES can be 1.
+ //
+ // When PREVENT_HAZARDS is 0 there is no such restriction.
+ //
+ // It is possible to be less restrictive for memories.
+ // -------------------------------------
+ PREVENT_HAZARDS = 0,
+
+ // -------------------------------------
+ // Used only when hazard prevention is on, but may be used
+ // for optimization work in the future.
+ // -------------------------------------
+ SUPPORTS_POSTED_WRITES = 1,
+ SUPPORTS_NONPOSTED_WRITES = 0,
+
+ // -------------------------------------------------
+ // Enables the reorder buffer which allows a master to
+ // switch slaves while responses are pending.
+ // Reponses will be reordered following command issue order.
+ // -------------------------------------------------
+ REORDER = 0
+)
+(
+ // -------------------
+ // Clock & Reset
+ // -------------------
+ input clk,
+ input reset,
+
+ // -------------------
+ // Command
+ // -------------------
+ input cmd_sink_valid,
+ input [ST_DATA_W-1 : 0] cmd_sink_data,
+ input [ST_CHANNEL_W-1 : 0] cmd_sink_channel,
+ input cmd_sink_startofpacket,
+ input cmd_sink_endofpacket,
+ output cmd_sink_ready,
+
+ output reg [VALID_WIDTH-1 : 0] cmd_src_valid,
+ output reg [ST_DATA_W-1 : 0] cmd_src_data,
+ output reg [ST_CHANNEL_W-1 : 0] cmd_src_channel,
+ output reg cmd_src_startofpacket,
+ output reg cmd_src_endofpacket,
+ input cmd_src_ready,
+
+ // -------------------
+ // Response
+ // -------------------
+ input rsp_sink_valid,
+ input [ST_DATA_W-1 : 0] rsp_sink_data,
+ input [ST_CHANNEL_W-1 : 0] rsp_sink_channel,
+ input rsp_sink_startofpacket,
+ input rsp_sink_endofpacket,
+ output reg rsp_sink_ready,
+
+ output reg rsp_src_valid,
+ output reg [ST_DATA_W-1 : 0] rsp_src_data,
+ output reg [ST_CHANNEL_W-1 : 0] rsp_src_channel,
+ output reg rsp_src_startofpacket,
+ output reg rsp_src_endofpacket,
+ input rsp_src_ready
+);
+
+ // -------------------------------------
+ // Local Parameters
+ // -------------------------------------
+ localparam DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1;
+ localparam COUNTER_W = log2ceil(MAX_OUTSTANDING_RESPONSES + 1);
+ localparam PAYLOAD_W = ST_DATA_W + ST_CHANNEL_W + 4;
+ localparam NUMSYMBOLS = PKT_BYTEEN_H - PKT_BYTEEN_L + 1;
+ localparam MAX_DEST_ID = 1 << (DEST_ID_W);
+ localparam PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1;
+
+ // -------------------------------------------------------
+ // Memory Parameters
+ // ------------------------------------------------------
+ localparam MAX_BYTE_CNT = 1 << (PKT_BYTE_CNT_W);
+ localparam MAX_BURST_LENGTH = log2ceil(MAX_BYTE_CNT/NUMSYMBOLS);
+
+ // Memory stores packet width, including sop and eop
+ localparam MEM_W = ST_DATA_W + ST_CHANNEL_W + 1 + 1;
+ localparam MEM_DEPTH = MAX_OUTSTANDING_RESPONSES * (MAX_BYTE_CNT/NUMSYMBOLS);
+
+ // -----------------------------------------------------
+ // Input Stage
+ //
+ // Figure out if the destination id has changed
+ // -----------------------------------------------------
+ wire stage1_dest_changed;
+ wire stage1_trans_changed;
+ wire [PAYLOAD_W-1 : 0] stage1_payload;
+ wire in_nonposted_cmd;
+ reg [ST_CHANNEL_W-1:0] last_channel;
+ wire [DEST_ID_W-1 : 0] dest_id;
+ reg [DEST_ID_W-1 : 0] last_dest_id;
+ reg was_write;
+ wire is_write;
+ wire suppress;
+ wire save_dest_id;
+
+ wire suppress_change_dest_id;
+ wire suppress_max_outstanding;
+ wire suppress_change_trans_but_not_dest;
+ wire suppress_change_trans_for_one_slave;
+
+ generate if (PREVENT_HAZARDS == 1) begin : convert_posted_to_nonposted_block
+ assign in_nonposted_cmd = 1'b1;
+ end else begin : non_posted_cmd_assignment_block
+ assign in_nonposted_cmd = (cmd_sink_data[PKT_TRANS_POSTED] == 0);
+ end
+ endgenerate
+
+ // ------------------------------------
+ // Optimization: for the unpipelined case, we can save the destid if
+ // this is an unsuppressed nonposted command. This eliminates
+ // dependence on the backpressure signal.
+ //
+ // Not a problem for the pipelined case.
+ // ------------------------------------
+ generate
+ if (PIPELINED) begin : pipelined_save_dest_id
+ assign save_dest_id = cmd_sink_valid & cmd_sink_ready & in_nonposted_cmd;
+ end else begin : unpipelined_save_dest_id
+ assign save_dest_id = cmd_sink_valid & ~(suppress_change_dest_id | suppress_max_outstanding) & in_nonposted_cmd;
+ end
+ endgenerate
+
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ last_dest_id <= 0;
+ last_channel <= 0;
+ was_write <= 0;
+ end
+ else if (save_dest_id) begin
+ last_dest_id <= dest_id;
+ last_channel <= cmd_sink_channel;
+ was_write <= is_write;
+ end
+ end
+
+ assign dest_id = cmd_sink_data[PKT_DEST_ID_H:PKT_DEST_ID_L];
+ assign is_write = cmd_sink_data[PKT_TRANS_WRITE];
+ assign stage1_dest_changed = (last_dest_id != dest_id);
+ assign stage1_trans_changed = (was_write != is_write);
+
+ assign stage1_payload = {
+ cmd_sink_data,
+ cmd_sink_channel,
+ cmd_sink_startofpacket,
+ cmd_sink_endofpacket,
+ stage1_dest_changed,
+ stage1_trans_changed };
+
+ // -----------------------------------------------------
+ // (Optional) pipeline between input and output
+ // -----------------------------------------------------
+ wire stage2_valid;
+ reg stage2_ready;
+ wire [PAYLOAD_W-1 : 0] stage2_payload;
+
+ generate
+ if (PIPELINED == 1) begin : pipelined_limiter
+ altera_avalon_st_pipeline_base
+ #(
+ .BITS_PER_SYMBOL(PAYLOAD_W)
+ ) stage1_pipe (
+ .clk (clk),
+ .reset (reset),
+ .in_ready (cmd_sink_ready),
+ .in_valid (cmd_sink_valid),
+ .in_data (stage1_payload),
+ .out_valid (stage2_valid),
+ .out_ready (stage2_ready),
+ .out_data (stage2_payload)
+ );
+ end else begin : unpipelined_limiter
+ assign stage2_valid = cmd_sink_valid;
+ assign stage2_payload = stage1_payload;
+ assign cmd_sink_ready = stage2_ready;
+ end
+ endgenerate
+
+ // -----------------------------------------------------
+ // Output Stage
+ // -----------------------------------------------------
+ wire [ST_DATA_W-1 : 0] stage2_data;
+ wire [ST_CHANNEL_W-1:0] stage2_channel;
+ wire stage2_startofpacket;
+ wire stage2_endofpacket;
+ wire stage2_dest_changed;
+ wire stage2_trans_changed;
+ reg has_pending_responses;
+ reg [COUNTER_W-1 : 0] pending_response_count;
+ reg [COUNTER_W-1 : 0] next_pending_response_count;
+ wire nonposted_cmd;
+ wire nonposted_cmd_accepted;
+ wire response_accepted;
+ wire response_sink_accepted;
+ wire response_src_accepted;
+ wire count_is_1;
+ wire count_is_0;
+ reg internal_valid;
+ wire [VALID_WIDTH-1:0] wide_valid;
+
+ assign { stage2_data,
+ stage2_channel,
+ stage2_startofpacket,
+ stage2_endofpacket,
+ stage2_dest_changed,
+ stage2_trans_changed } = stage2_payload;
+
+ generate if (PREVENT_HAZARDS == 1) begin : stage2_nonposted_block
+ assign nonposted_cmd = 1'b1;
+ end else begin
+ assign nonposted_cmd = (stage2_data[PKT_TRANS_POSTED] == 0);
+ end
+ endgenerate
+
+ assign nonposted_cmd_accepted = nonposted_cmd && internal_valid && (cmd_src_ready && cmd_src_endofpacket);
+
+ // -----------------------------------------------------------------------------
+ // Use the sink's control signals here, because write responses may be dropped
+ // when hazard prevention is on.
+ //
+ // When case REORDER, move all side to rsp_source as all packets from rsp_sink will
+ // go in the reorder memory.
+ // One special case when PREVENT_HAZARD is on, need to use reorder_memory_valid
+ // as the rsp_source will drop
+ // -----------------------------------------------------------------------------
+
+ assign response_sink_accepted = rsp_sink_valid && rsp_sink_ready && rsp_sink_endofpacket;
+ // Avoid Qis warning when incase, no REORDER, the signal reorder_mem_valid is not in used.
+ wire reorder_mem_out_valid;
+ wire reorder_mem_valid;
+ generate
+ if (REORDER) begin
+ assign reorder_mem_out_valid = reorder_mem_valid;
+ end else begin
+ assign reorder_mem_out_valid = '0;
+ end
+ endgenerate
+
+ assign response_src_accepted = reorder_mem_out_valid & rsp_src_ready & rsp_src_endofpacket;
+ assign response_accepted = (REORDER == 1) ? response_src_accepted : response_sink_accepted;
+
+ always @* begin
+ next_pending_response_count = pending_response_count;
+
+ if (nonposted_cmd_accepted)
+ next_pending_response_count = pending_response_count + 1'b1;
+ if (response_accepted)
+ next_pending_response_count = pending_response_count - 1'b1;
+ if (nonposted_cmd_accepted && response_accepted)
+ next_pending_response_count = pending_response_count;
+ end
+
+ assign count_is_1 = (pending_response_count == 1);
+ assign count_is_0 = (pending_response_count == 0);
+ // ------------------------------------------------------------------
+ // count_max_reached : count if maximum command reach to backpressure
+ // ------------------------------------------------------------------
+ reg count_max_reached;
+ always @(posedge clk, posedge reset) begin
+ if (reset) begin
+ pending_response_count <= 0;
+ has_pending_responses <= 0;
+ count_max_reached <= 0;
+ end
+ else begin
+ pending_response_count <= next_pending_response_count;
+ // synthesis translate_off
+ if (count_is_0 && response_accepted)
+ $display("%t: %m: Error: unexpected response: pending_response_count underflow", $time());
+ // synthesis translate_on
+ has_pending_responses <= has_pending_responses
+ && ~(count_is_1 && response_accepted && ~nonposted_cmd_accepted)
+ || (count_is_0 && nonposted_cmd_accepted && ~response_accepted);
+ count_max_reached <= (next_pending_response_count == MAX_OUTSTANDING_RESPONSES);
+
+ end
+ end
+
+ wire suppress_prevent_harzard_for_particular_destid;
+ wire this_destid_trans_changed;
+ genvar j;
+ generate
+ if (REORDER) begin: fifo_dest_id_write_read_control_reorder_on
+ wire [COUNTER_W - 1 : 0] current_trans_seq_of_this_destid;
+ wire [MAX_DEST_ID - 1 : 0] current_trans_seq_of_this_destid_valid;
+ wire [MAX_DEST_ID - 1 : 0] responses_arrived;
+ reg [COUNTER_W - 1:0] trans_sequence;
+ wire [MAX_DEST_ID - 1 : 0] trans_sequence_we;
+
+ wire [COUNTER_W : 0] trans_sequence_plus_trans_type;
+ wire current_trans_type_of_this_destid;
+ wire [COUNTER_W : 0] current_trans_seq_of_this_destid_plus_trans_type [MAX_DEST_ID];
+ // ------------------------------------------------------------
+ // Control write trans_sequence to fifos
+ //
+ // 1. when command accepted, read destid from command packet,
+ // write this id to the fifo (each fifo for each desitid)
+ // 2. when response acepted, read the destid from response packet,
+ // will know which sequence of this response, write it to
+ // correct segment in memory.
+ // what if two commands go to same slave, the two sequences
+ // go time same fifo, this even helps us to maintain order
+ // when two commands same thread to one slave.
+ // -----------------------------------------------------------
+ wire [DEST_ID_W - 1 : 0] rsp_sink_dest_id;
+ wire [DEST_ID_W - 1 : 0] cmd_dest_id;
+ assign rsp_sink_dest_id = rsp_sink_data[PKT_SRC_ID_H : PKT_SRC_ID_L];
+
+ // write in fifo the trans_sequence and type of transaction
+ assign trans_sequence_plus_trans_type = {stage2_data[PKT_TRANS_WRITE], trans_sequence};
+
+ // read the cmd_dest_id from output of pipeline stage so that either
+ // or not, it wont affect how we write to fifo
+ assign cmd_dest_id = stage2_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
+ // -------------------------------------
+ // Get the transaction_seq for that dest_id
+ // -------------------------------------
+ wire [COUNTER_W - 1: 0] trans_sequence_rsp;
+ wire [COUNTER_W : 0] trans_sequence_rsp_plus_trans_type;
+ wire [COUNTER_W - 1: 0] trans_sequence_rsp_this_destid_waiting;
+ wire [COUNTER_W : 0] sequence_and_trans_type_this_destid_waiting;
+ wire trans_sequence_rsp_this_destid_waiting_valid;
+ assign trans_sequence_rsp_plus_trans_type = current_trans_seq_of_this_destid_plus_trans_type[rsp_sink_dest_id];
+ assign trans_sequence_rsp = trans_sequence_rsp_plus_trans_type[COUNTER_W - 1: 0];
+
+ // do I need to check if this fifo is valid, it should be always valid, unless a command not yet sent
+ // and response comes back which means something weird happens.
+ // It is worth to do an assertion but now to avoid QIS warning, just do as normal ST handshaking
+ // check valid and ready
+
+ for (j = 0; j < MAX_DEST_ID; j = j+1)
+ begin : write_and_read_trans_sequence
+ assign trans_sequence_we[j] = (cmd_dest_id == j) && nonposted_cmd_accepted;
+ assign responses_arrived[j] = (rsp_sink_dest_id == j) && response_sink_accepted;
+ end
+
+ // --------------------------------------------------------------------
+ // This is array of fifos, which will be created base on how many slaves
+ // that this master can see (max dest_id_width)
+ // Each fifo, will store the trans_sequence, which go to that slave
+ // On the response path, based in the response from which slave
+ // the fifo of that slave will be read, to check the sequences.
+ // and this sequence is the write address to the memory
+ // -----------------------------------------------------------------------------------
+ // There are 3 sequences run around the limiter, they have a relationship
+ // And this is how the key point of reorder work:
+ //
+ // trans_sequence : command sequence, each command go thru the limiter
+ // will have a sequence to show their order. A simple
+ // counter from 0 go up and repeat.
+ // trans_sequence_rsp : response sequence, each response that go back to limiter,
+ // will be read from trans_fifos to know their sequence.
+ // expect_trans_sequence : Expected sequences for response that the master is waiting
+ // The limiter will hold this sequence and wait until exactly response
+ // for this sequence come back (trans_sequence_rsp)
+ // aka: if trans_sequence_rsp back is same as expect_trans_sequence
+ // then it is correct order, else response store in memory and
+ // send out to master later, when expect_trans_sequence match.
+ // ------------------------------------------------------------------------------------
+ for (j = 0;j < MAX_DEST_ID; j = j+1) begin : trans_sequence_per_fifo
+ altera_avalon_sc_fifo
+ #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (COUNTER_W + 1), // one bit extra to store type of transaction
+ .FIFO_DEPTH (MAX_OUTSTANDING_RESPONSES),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (0),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) dest_id_fifo
+ (
+ .clk (clk),
+ .reset (reset),
+ .in_data (trans_sequence_plus_trans_type),
+ .in_valid (trans_sequence_we[j]),
+ .in_ready (),
+ .out_data (current_trans_seq_of_this_destid_plus_trans_type[j]),
+ .out_valid (current_trans_seq_of_this_destid_valid[j]),
+ .out_ready (responses_arrived[j]),
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_startofpacket (1'b0), // (terminated)
+ .in_endofpacket (1'b0), // (terminated)
+ .out_startofpacket (), // (terminated)
+ .out_endofpacket (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+ end // block: trans_sequence_per_fifo
+
+ // -------------------------------------------------------
+ // Calculate the transaction sequence, just simple increase
+ // when each commands pass by
+ // --------------------------------------------------------
+ always @(posedge clk or posedge reset)
+ begin
+ if (reset) begin
+ trans_sequence <= '0;
+ end else begin
+ if (nonposted_cmd_accepted)
+ trans_sequence <= ( (trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : trans_sequence + 1'b1;
+ end
+ end
+
+ // -------------------------------------
+ // Control Memory for reorder responses
+ // -------------------------------------
+ wire [COUNTER_W - 1 : 0] next_rd_trans_sequence;
+ reg [COUNTER_W - 1 : 0] rd_trans_sequence;
+ reg [COUNTER_W - 1 : 0] next_expected_trans_sequence;
+ reg [COUNTER_W - 1 : 0] expect_trans_sequence;
+ wire [ST_DATA_W - 1 : 0] reorder_mem_data;
+ wire [ST_CHANNEL_W - 1 : 0] reorder_mem_channel;
+ wire reorder_mem_startofpacket;
+ wire reorder_mem_endofpacket;
+ wire reorder_mem_ready;
+ // -------------------------------------------
+ // Data to write and read from reorder memory
+ // Store everything includes channel, sop, eop
+ // -------------------------------------------
+ reg [MEM_W - 1 : 0] mem_in_rsp_sink_data;
+ reg [MEM_W - 1 : 0] reorder_mem_out_data;
+ always_comb
+ begin
+ mem_in_rsp_sink_data = {rsp_sink_data, rsp_sink_channel, rsp_sink_startofpacket, rsp_sink_endofpacket};
+ end
+
+ assign next_rd_trans_sequence = ((rd_trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : rd_trans_sequence + 1'b1;
+ assign next_expected_trans_sequence = ((expect_trans_sequence + 1'b1) == MAX_OUTSTANDING_RESPONSES) ? '0 : expect_trans_sequence + 1'b1;
+
+ always_ff @(posedge clk, posedge reset)
+ begin
+ if (reset) begin
+ rd_trans_sequence <= '0;
+ expect_trans_sequence <= '0;
+ end else begin
+ if (rsp_src_ready && reorder_mem_valid) begin
+ if (reorder_mem_endofpacket == 1) begin //endofpacket
+ expect_trans_sequence <= next_expected_trans_sequence;
+ rd_trans_sequence <= next_rd_trans_sequence;
+ end
+ end
+ end
+ end // always_ff @
+
+ // For PREVENT_HAZARD,
+ // Case: Master Write to S0, read S1, and Read S0 back but if Write for S0
+ // not yet return then we need to backpressure this, else read S0 might take over write
+ // This is more checking after the fifo destid, as read S1 is inserted in midle
+ // when see new packet, try to look at the fifo for that slave id, check if it
+ // type of transaction
+ assign sequence_and_trans_type_this_destid_waiting = current_trans_seq_of_this_destid_plus_trans_type[cmd_dest_id];
+ assign current_trans_type_of_this_destid = sequence_and_trans_type_this_destid_waiting[COUNTER_W];
+ assign trans_sequence_rsp_this_destid_waiting_valid = current_trans_seq_of_this_destid_valid[cmd_dest_id];
+ // it might waiting other sequence, check if different type of transaction as only for PREVENT HAZARD
+ // if comming comamnd to one slave and this slave is still waiting for response from previous command
+ // which has diiferent type of transaction, we back-pressure this command to avoid HAZARD
+ assign suppress_prevent_harzard_for_particular_destid = (current_trans_type_of_this_destid != is_write) & trans_sequence_rsp_this_destid_waiting_valid;
+
+ // -------------------------------------
+ // Memory for reorder buffer
+ // -------------------------------------
+ altera_merlin_reorder_memory
+ #(
+ .DATA_W (MEM_W),
+ .ADDR_H_W (COUNTER_W),
+ .ADDR_L_W (MAX_BURST_LENGTH),
+ .NUM_SEGMENT (MAX_OUTSTANDING_RESPONSES),
+ .DEPTH (MEM_DEPTH)
+ ) reorder_memory
+ (
+ .clk (clk),
+ .reset (reset),
+ .in_data (mem_in_rsp_sink_data),
+ .in_valid (rsp_sink_valid),
+ .in_ready (reorder_mem_ready),
+ .out_data (reorder_mem_out_data),
+ .out_valid (reorder_mem_valid),
+ .out_ready (rsp_src_ready),
+ .wr_segment (trans_sequence_rsp),
+ .rd_segment (expect_trans_sequence)
+ );
+ // -------------------------------------
+ // Output from reorder buffer
+ // -------------------------------------
+ assign reorder_mem_data = reorder_mem_out_data[MEM_W -1 : ST_CHANNEL_W + 2];
+ assign reorder_mem_channel = reorder_mem_out_data[ST_CHANNEL_W + 2 - 1 : 2];
+ assign reorder_mem_startofpacket = reorder_mem_out_data[1];
+ assign reorder_mem_endofpacket = reorder_mem_out_data[0];
+
+ // -------------------------------------
+ // Because use generate statment
+ // so move all rsp_src_xxx controls here
+ // -------------------------------------
+ always_comb begin
+ cmd_src_data = stage2_data;
+ rsp_src_valid = reorder_mem_valid;
+ rsp_src_data = reorder_mem_data;
+ rsp_src_channel = reorder_mem_channel;
+ rsp_src_startofpacket = reorder_mem_startofpacket;
+ rsp_src_endofpacket = reorder_mem_endofpacket;
+ // -------------------------------------
+ // Forces commands to be non-posted if hazard prevention
+ // is on, also drops write responses
+ // -------------------------------------
+ rsp_sink_ready = reorder_mem_ready; // now it takes ready signal from the memory not direct from master
+ if (PREVENT_HAZARDS == 1) begin
+ cmd_src_data[PKT_TRANS_POSTED] = 1'b0;
+
+ if (rsp_src_data[PKT_TRANS_WRITE] == 1'b1 && SUPPORTS_POSTED_WRITES == 1 && SUPPORTS_NONPOSTED_WRITES == 0) begin
+ rsp_src_valid = 1'b0;
+ rsp_sink_ready = 1'b1;
+ end
+ end
+ end // always_comb
+
+ end // block: fifo_dest_id_write_read_control_reorder_on
+ endgenerate
+
+ // -------------------------------------
+ // Pass-through command and response
+ // -------------------------------------
+
+ always_comb
+ begin
+ cmd_src_channel = stage2_channel;
+ cmd_src_startofpacket = stage2_startofpacket;
+ cmd_src_endofpacket = stage2_endofpacket;
+ end // always_comb
+
+ // -------------------------------------
+ // When there is no REORDER requirement
+ // Just pass through signals
+ // -------------------------------------
+ generate
+ if (!REORDER) begin : use_selector_or_pass_thru_rsp
+ always_comb begin
+ cmd_src_data = stage2_data;
+ // pass thru almost signals
+ rsp_src_valid = rsp_sink_valid;
+ rsp_src_data = rsp_sink_data;
+ rsp_src_channel = rsp_sink_channel;
+ rsp_src_startofpacket = rsp_sink_startofpacket;
+ rsp_src_endofpacket = rsp_sink_endofpacket;
+ // -------------------------------------
+ // Forces commands to be non-posted if hazard prevention
+ // is on, also drops write responses
+ // -------------------------------------
+ rsp_sink_ready = rsp_src_ready; // take care this, should check memory empty
+ if (PREVENT_HAZARDS == 1) begin
+ cmd_src_data[PKT_TRANS_POSTED] = 1'b0;
+
+ if (rsp_sink_data[PKT_TRANS_WRITE] == 1'b1 && SUPPORTS_POSTED_WRITES == 1 && SUPPORTS_NONPOSTED_WRITES == 0) begin
+ rsp_src_valid = 1'b0;
+ rsp_sink_ready = 1'b1;
+ end
+ end
+ end // always_comb
+ end // if (!REORDER)
+ endgenerate
+
+ // --------------------------------------------------------
+ // Backpressure & Suppression
+ // --------------------------------------------------------
+ // ENFORCE_ORDER: unused option, always is 1, remove it
+ // Now the limiter will suppress when max_outstanding reach
+ // --------------------------------------------------------
+ generate
+ if (ENFORCE_ORDER) begin : enforce_order_block
+ assign suppress_change_dest_id = (REORDER == 1) ? 1'b0 : nonposted_cmd && has_pending_responses &&
+ (stage2_dest_changed || (PREVENT_HAZARDS == 1 && stage2_trans_changed));
+ end else begin : no_order_block
+ assign suppress_change_dest_id = 1'b0;
+ end
+ endgenerate
+
+ // ------------------------------------------------------------
+ // Even we allow change slave while still have pending responses
+ // But one special case, when PREVENT_HAZARD=1, we still allow
+ // switch slave while type of transaction change (RAW, WAR) but
+ // only to different slaves.
+ // if to same slave, we still need back pressure that to make
+ // sure no racing
+ // ------------------------------------------------------------
+
+ generate
+ if (REORDER) begin : prevent_hazard_block
+ assign suppress_change_trans_but_not_dest = nonposted_cmd && has_pending_responses &&
+ !stage2_dest_changed && (PREVENT_HAZARDS == 1 && stage2_trans_changed);
+ end else begin : no_hazard_block
+ assign suppress_change_trans_but_not_dest = 1'b0; // no REORDER, the suppress_changes_destid take care of this.
+ end
+ endgenerate
+
+ generate
+ if (REORDER) begin : prevent_hazard_block_for_particular_slave
+ assign suppress_change_trans_for_one_slave = nonposted_cmd && has_pending_responses && (PREVENT_HAZARDS == 1 && suppress_prevent_harzard_for_particular_destid);
+ end else begin : no_hazard_block_for_particular_slave
+ assign suppress_change_trans_for_one_slave = 1'b0; // no REORDER, the suppress_changes_destid take care of this.
+ end
+ endgenerate
+
+ // ------------------------------------------
+ // Backpressure when max outstanding transactions are reached
+ // ------------------------------------------
+ generate
+ if (REORDER) begin : max_outstanding_block
+ assign suppress_max_outstanding = count_max_reached;
+ end else begin
+ assign suppress_max_outstanding = 1'b0;
+ end
+ endgenerate
+
+ assign suppress = suppress_change_trans_for_one_slave | suppress_change_dest_id | suppress_max_outstanding;
+ assign wide_valid = { VALID_WIDTH {stage2_valid} } & stage2_channel;
+
+ always @* begin
+ stage2_ready = cmd_src_ready;
+ internal_valid = stage2_valid;
+ // --------------------------------------------------------
+ // change suppress condidtion, in case REODER it will alllow changing slave
+ // even still have pending transactions.
+ // -------------------------------------------------------
+ if (suppress) begin
+ stage2_ready = 0;
+ internal_valid = 0;
+ end
+
+ if (VALID_WIDTH == 1) begin
+ cmd_src_valid = {VALID_WIDTH{1'b0}};
+ cmd_src_valid[0] = internal_valid;
+ end else begin
+ // -------------------------------------
+ // Use the one-hot channel to determine if the destination
+ // has changed. This results in a wide valid bus
+ // -------------------------------------
+ cmd_src_valid = wide_valid;
+ if (nonposted_cmd & has_pending_responses) begin
+ if (!REORDER) begin
+ cmd_src_valid = wide_valid & last_channel;
+ // -------------------------------------
+ // Mask the valid signals if the transaction type has changed
+ // if hazard prevention is enabled
+ // -------------------------------------
+ if (PREVENT_HAZARDS == 1)
+ cmd_src_valid = wide_valid & last_channel & { VALID_WIDTH {!stage2_trans_changed} };
+ end else begin // else: !if(!REORDER) if REORDER happen
+ if (PREVENT_HAZARDS == 1)
+ cmd_src_valid = wide_valid & { VALID_WIDTH {!suppress_change_trans_for_one_slave} };
+ if (suppress_max_outstanding) begin
+ cmd_src_valid = {VALID_WIDTH {1'b0}};
+ end
+
+ end
+ end
+ end
+ end
+
+ // --------------------------------------------------
+ // Calculates the log2ceil of the input value.
+ //
+ // This function occurs a lot... please refactor.
+ // --------------------------------------------------
+ function integer log2ceil;
+ input integer val;
+ integer i;
+
+ begin
+ i = 1;
+ log2ceil = 0;
+
+ while (i < val) begin
+ log2ceil = log2ceil + 1;
+ i = i << 1;
+ end
+ end
+ endfunction
+
+endmodule
+
+
diff --git a/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_fg5byai.v b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_fg5byai.v
new file mode 100644
index 0000000000000000000000000000000000000000..e50fee9e387a3c70151d94317cb06e11516521a8
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_fg5byai.v
@@ -0,0 +1,1076 @@
+// arria10_hps_altera_mm_interconnect_221_fg5byai.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
+// will probably be lost.
+//
+// Generated using ACDS version 22.1 922
+
+`timescale 1 ps / 1 ps
+module arria10_hps_altera_mm_interconnect_221_fg5byai (
+ input wire [3:0] a10_hps_h2f_axi_master_awid, // a10_hps_h2f_axi_master.awid
+ input wire [31:0] a10_hps_h2f_axi_master_awaddr, // .awaddr
+ input wire [3:0] a10_hps_h2f_axi_master_awlen, // .awlen
+ input wire [2:0] a10_hps_h2f_axi_master_awsize, // .awsize
+ input wire [1:0] a10_hps_h2f_axi_master_awburst, // .awburst
+ input wire [1:0] a10_hps_h2f_axi_master_awlock, // .awlock
+ input wire [3:0] a10_hps_h2f_axi_master_awcache, // .awcache
+ input wire [2:0] a10_hps_h2f_axi_master_awprot, // .awprot
+ input wire [4:0] a10_hps_h2f_axi_master_awuser, // .awuser
+ input wire a10_hps_h2f_axi_master_awvalid, // .awvalid
+ output wire a10_hps_h2f_axi_master_awready, // .awready
+ input wire [3:0] a10_hps_h2f_axi_master_wid, // .wid
+ input wire [63:0] a10_hps_h2f_axi_master_wdata, // .wdata
+ input wire [7:0] a10_hps_h2f_axi_master_wstrb, // .wstrb
+ input wire a10_hps_h2f_axi_master_wlast, // .wlast
+ input wire a10_hps_h2f_axi_master_wvalid, // .wvalid
+ output wire a10_hps_h2f_axi_master_wready, // .wready
+ output wire [3:0] a10_hps_h2f_axi_master_bid, // .bid
+ output wire [1:0] a10_hps_h2f_axi_master_bresp, // .bresp
+ output wire a10_hps_h2f_axi_master_bvalid, // .bvalid
+ input wire a10_hps_h2f_axi_master_bready, // .bready
+ input wire [3:0] a10_hps_h2f_axi_master_arid, // .arid
+ input wire [31:0] a10_hps_h2f_axi_master_araddr, // .araddr
+ input wire [3:0] a10_hps_h2f_axi_master_arlen, // .arlen
+ input wire [2:0] a10_hps_h2f_axi_master_arsize, // .arsize
+ input wire [1:0] a10_hps_h2f_axi_master_arburst, // .arburst
+ input wire [1:0] a10_hps_h2f_axi_master_arlock, // .arlock
+ input wire [3:0] a10_hps_h2f_axi_master_arcache, // .arcache
+ input wire [2:0] a10_hps_h2f_axi_master_arprot, // .arprot
+ input wire [4:0] a10_hps_h2f_axi_master_aruser, // .aruser
+ input wire a10_hps_h2f_axi_master_arvalid, // .arvalid
+ output wire a10_hps_h2f_axi_master_arready, // .arready
+ output wire [3:0] a10_hps_h2f_axi_master_rid, // .rid
+ output wire [63:0] a10_hps_h2f_axi_master_rdata, // .rdata
+ output wire [1:0] a10_hps_h2f_axi_master_rresp, // .rresp
+ output wire a10_hps_h2f_axi_master_rlast, // .rlast
+ output wire a10_hps_h2f_axi_master_rvalid, // .rvalid
+ input wire a10_hps_h2f_axi_master_rready, // .rready
+ input wire clk_0_clk_clk, // clk_0_clk.clk
+ input wire clk_50m_clk_clk, // clk_50m_clk.clk
+ input wire a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset, // a10_hps_h2f_axi_reset_reset_bridge_in_reset.reset
+ input wire eth_tse_0_reset_connection_reset_bridge_in_reset_reset, // eth_tse_0_reset_connection_reset_bridge_in_reset.reset
+ output wire [7:0] eth_tse_0_control_port_address, // eth_tse_0_control_port.address
+ output wire eth_tse_0_control_port_write, // .write
+ output wire eth_tse_0_control_port_read, // .read
+ input wire [31:0] eth_tse_0_control_port_readdata, // .readdata
+ output wire [31:0] eth_tse_0_control_port_writedata, // .writedata
+ input wire eth_tse_0_control_port_waitrequest // .waitrequest
+ );
+
+ wire rsp_mux_src_valid; // rsp_mux:src_valid -> a10_hps_h2f_axi_master_agent:write_rp_valid
+ wire [156:0] rsp_mux_src_data; // rsp_mux:src_data -> a10_hps_h2f_axi_master_agent:write_rp_data
+ wire rsp_mux_src_ready; // a10_hps_h2f_axi_master_agent:write_rp_ready -> rsp_mux:src_ready
+ wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> a10_hps_h2f_axi_master_agent:write_rp_channel
+ wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> a10_hps_h2f_axi_master_agent:write_rp_startofpacket
+ wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> a10_hps_h2f_axi_master_agent:write_rp_endofpacket
+ wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> a10_hps_h2f_axi_master_agent:read_rp_valid
+ wire [156:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> a10_hps_h2f_axi_master_agent:read_rp_data
+ wire rsp_mux_001_src_ready; // a10_hps_h2f_axi_master_agent:read_rp_ready -> rsp_mux_001:src_ready
+ wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> a10_hps_h2f_axi_master_agent:read_rp_channel
+ wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> a10_hps_h2f_axi_master_agent:read_rp_startofpacket
+ wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> a10_hps_h2f_axi_master_agent:read_rp_endofpacket
+ wire [31:0] eth_tse_0_control_port_agent_m0_readdata; // eth_tse_0_control_port_translator:uav_readdata -> eth_tse_0_control_port_agent:m0_readdata
+ wire eth_tse_0_control_port_agent_m0_waitrequest; // eth_tse_0_control_port_translator:uav_waitrequest -> eth_tse_0_control_port_agent:m0_waitrequest
+ wire eth_tse_0_control_port_agent_m0_debugaccess; // eth_tse_0_control_port_agent:m0_debugaccess -> eth_tse_0_control_port_translator:uav_debugaccess
+ wire [31:0] eth_tse_0_control_port_agent_m0_address; // eth_tse_0_control_port_agent:m0_address -> eth_tse_0_control_port_translator:uav_address
+ wire [3:0] eth_tse_0_control_port_agent_m0_byteenable; // eth_tse_0_control_port_agent:m0_byteenable -> eth_tse_0_control_port_translator:uav_byteenable
+ wire eth_tse_0_control_port_agent_m0_read; // eth_tse_0_control_port_agent:m0_read -> eth_tse_0_control_port_translator:uav_read
+ wire eth_tse_0_control_port_agent_m0_readdatavalid; // eth_tse_0_control_port_translator:uav_readdatavalid -> eth_tse_0_control_port_agent:m0_readdatavalid
+ wire eth_tse_0_control_port_agent_m0_lock; // eth_tse_0_control_port_agent:m0_lock -> eth_tse_0_control_port_translator:uav_lock
+ wire [31:0] eth_tse_0_control_port_agent_m0_writedata; // eth_tse_0_control_port_agent:m0_writedata -> eth_tse_0_control_port_translator:uav_writedata
+ wire eth_tse_0_control_port_agent_m0_write; // eth_tse_0_control_port_agent:m0_write -> eth_tse_0_control_port_translator:uav_write
+ wire [2:0] eth_tse_0_control_port_agent_m0_burstcount; // eth_tse_0_control_port_agent:m0_burstcount -> eth_tse_0_control_port_translator:uav_burstcount
+ wire eth_tse_0_control_port_agent_rf_source_valid; // eth_tse_0_control_port_agent:rf_source_valid -> eth_tse_0_control_port_agent_rsp_fifo:in_valid
+ wire [121:0] eth_tse_0_control_port_agent_rf_source_data; // eth_tse_0_control_port_agent:rf_source_data -> eth_tse_0_control_port_agent_rsp_fifo:in_data
+ wire eth_tse_0_control_port_agent_rf_source_ready; // eth_tse_0_control_port_agent_rsp_fifo:in_ready -> eth_tse_0_control_port_agent:rf_source_ready
+ wire eth_tse_0_control_port_agent_rf_source_startofpacket; // eth_tse_0_control_port_agent:rf_source_startofpacket -> eth_tse_0_control_port_agent_rsp_fifo:in_startofpacket
+ wire eth_tse_0_control_port_agent_rf_source_endofpacket; // eth_tse_0_control_port_agent:rf_source_endofpacket -> eth_tse_0_control_port_agent_rsp_fifo:in_endofpacket
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_valid; // eth_tse_0_control_port_agent_rsp_fifo:out_valid -> eth_tse_0_control_port_agent:rf_sink_valid
+ wire [121:0] eth_tse_0_control_port_agent_rsp_fifo_out_data; // eth_tse_0_control_port_agent_rsp_fifo:out_data -> eth_tse_0_control_port_agent:rf_sink_data
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_ready; // eth_tse_0_control_port_agent:rf_sink_ready -> eth_tse_0_control_port_agent_rsp_fifo:out_ready
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket; // eth_tse_0_control_port_agent_rsp_fifo:out_startofpacket -> eth_tse_0_control_port_agent:rf_sink_startofpacket
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket; // eth_tse_0_control_port_agent_rsp_fifo:out_endofpacket -> eth_tse_0_control_port_agent:rf_sink_endofpacket
+ wire eth_tse_0_control_port_agent_rdata_fifo_src_valid; // eth_tse_0_control_port_agent:rdata_fifo_src_valid -> eth_tse_0_control_port_agent_rdata_fifo:in_valid
+ wire [33:0] eth_tse_0_control_port_agent_rdata_fifo_src_data; // eth_tse_0_control_port_agent:rdata_fifo_src_data -> eth_tse_0_control_port_agent_rdata_fifo:in_data
+ wire eth_tse_0_control_port_agent_rdata_fifo_src_ready; // eth_tse_0_control_port_agent_rdata_fifo:in_ready -> eth_tse_0_control_port_agent:rdata_fifo_src_ready
+ wire a10_hps_h2f_axi_master_agent_write_cp_valid; // a10_hps_h2f_axi_master_agent:write_cp_valid -> router:sink_valid
+ wire [156:0] a10_hps_h2f_axi_master_agent_write_cp_data; // a10_hps_h2f_axi_master_agent:write_cp_data -> router:sink_data
+ wire a10_hps_h2f_axi_master_agent_write_cp_ready; // router:sink_ready -> a10_hps_h2f_axi_master_agent:write_cp_ready
+ wire a10_hps_h2f_axi_master_agent_write_cp_startofpacket; // a10_hps_h2f_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
+ wire a10_hps_h2f_axi_master_agent_write_cp_endofpacket; // a10_hps_h2f_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
+ wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
+ wire [156:0] router_src_data; // router:src_data -> cmd_demux:sink_data
+ wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
+ wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
+ wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
+ wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
+ wire a10_hps_h2f_axi_master_agent_read_cp_valid; // a10_hps_h2f_axi_master_agent:read_cp_valid -> router_001:sink_valid
+ wire [156:0] a10_hps_h2f_axi_master_agent_read_cp_data; // a10_hps_h2f_axi_master_agent:read_cp_data -> router_001:sink_data
+ wire a10_hps_h2f_axi_master_agent_read_cp_ready; // router_001:sink_ready -> a10_hps_h2f_axi_master_agent:read_cp_ready
+ wire a10_hps_h2f_axi_master_agent_read_cp_startofpacket; // a10_hps_h2f_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
+ wire a10_hps_h2f_axi_master_agent_read_cp_endofpacket; // a10_hps_h2f_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
+ wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
+ wire [156:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
+ wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
+ wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
+ wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
+ wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
+ wire eth_tse_0_control_port_agent_rp_valid; // eth_tse_0_control_port_agent:rp_valid -> router_002:sink_valid
+ wire [120:0] eth_tse_0_control_port_agent_rp_data; // eth_tse_0_control_port_agent:rp_data -> router_002:sink_data
+ wire eth_tse_0_control_port_agent_rp_ready; // router_002:sink_ready -> eth_tse_0_control_port_agent:rp_ready
+ wire eth_tse_0_control_port_agent_rp_startofpacket; // eth_tse_0_control_port_agent:rp_startofpacket -> router_002:sink_startofpacket
+ wire eth_tse_0_control_port_agent_rp_endofpacket; // eth_tse_0_control_port_agent:rp_endofpacket -> router_002:sink_endofpacket
+ wire eth_tse_0_control_port_burst_adapter_source0_valid; // eth_tse_0_control_port_burst_adapter:source0_valid -> eth_tse_0_control_port_agent:cp_valid
+ wire [120:0] eth_tse_0_control_port_burst_adapter_source0_data; // eth_tse_0_control_port_burst_adapter:source0_data -> eth_tse_0_control_port_agent:cp_data
+ wire eth_tse_0_control_port_burst_adapter_source0_ready; // eth_tse_0_control_port_agent:cp_ready -> eth_tse_0_control_port_burst_adapter:source0_ready
+ wire [1:0] eth_tse_0_control_port_burst_adapter_source0_channel; // eth_tse_0_control_port_burst_adapter:source0_channel -> eth_tse_0_control_port_agent:cp_channel
+ wire eth_tse_0_control_port_burst_adapter_source0_startofpacket; // eth_tse_0_control_port_burst_adapter:source0_startofpacket -> eth_tse_0_control_port_agent:cp_startofpacket
+ wire eth_tse_0_control_port_burst_adapter_source0_endofpacket; // eth_tse_0_control_port_burst_adapter:source0_endofpacket -> eth_tse_0_control_port_agent:cp_endofpacket
+ wire router_002_src_valid; // router_002:src_valid -> eth_tse_0_control_port_rsp_width_adapter:in_valid
+ wire [120:0] router_002_src_data; // router_002:src_data -> eth_tse_0_control_port_rsp_width_adapter:in_data
+ wire router_002_src_ready; // eth_tse_0_control_port_rsp_width_adapter:in_ready -> router_002:src_ready
+ wire [1:0] router_002_src_channel; // router_002:src_channel -> eth_tse_0_control_port_rsp_width_adapter:in_channel
+ wire router_002_src_startofpacket; // router_002:src_startofpacket -> eth_tse_0_control_port_rsp_width_adapter:in_startofpacket
+ wire router_002_src_endofpacket; // router_002:src_endofpacket -> eth_tse_0_control_port_rsp_width_adapter:in_endofpacket
+ wire eth_tse_0_control_port_rsp_width_adapter_src_valid; // eth_tse_0_control_port_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
+ wire [156:0] eth_tse_0_control_port_rsp_width_adapter_src_data; // eth_tse_0_control_port_rsp_width_adapter:out_data -> rsp_demux:sink_data
+ wire eth_tse_0_control_port_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> eth_tse_0_control_port_rsp_width_adapter:out_ready
+ wire [1:0] eth_tse_0_control_port_rsp_width_adapter_src_channel; // eth_tse_0_control_port_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
+ wire eth_tse_0_control_port_rsp_width_adapter_src_startofpacket; // eth_tse_0_control_port_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
+ wire eth_tse_0_control_port_rsp_width_adapter_src_endofpacket; // eth_tse_0_control_port_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
+ wire cmd_mux_src_valid; // cmd_mux:src_valid -> eth_tse_0_control_port_cmd_width_adapter:in_valid
+ wire [156:0] cmd_mux_src_data; // cmd_mux:src_data -> eth_tse_0_control_port_cmd_width_adapter:in_data
+ wire cmd_mux_src_ready; // eth_tse_0_control_port_cmd_width_adapter:in_ready -> cmd_mux:src_ready
+ wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> eth_tse_0_control_port_cmd_width_adapter:in_channel
+ wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> eth_tse_0_control_port_cmd_width_adapter:in_startofpacket
+ wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> eth_tse_0_control_port_cmd_width_adapter:in_endofpacket
+ wire eth_tse_0_control_port_cmd_width_adapter_src_valid; // eth_tse_0_control_port_cmd_width_adapter:out_valid -> eth_tse_0_control_port_burst_adapter:sink0_valid
+ wire [120:0] eth_tse_0_control_port_cmd_width_adapter_src_data; // eth_tse_0_control_port_cmd_width_adapter:out_data -> eth_tse_0_control_port_burst_adapter:sink0_data
+ wire eth_tse_0_control_port_cmd_width_adapter_src_ready; // eth_tse_0_control_port_burst_adapter:sink0_ready -> eth_tse_0_control_port_cmd_width_adapter:out_ready
+ wire [1:0] eth_tse_0_control_port_cmd_width_adapter_src_channel; // eth_tse_0_control_port_cmd_width_adapter:out_channel -> eth_tse_0_control_port_burst_adapter:sink0_channel
+ wire eth_tse_0_control_port_cmd_width_adapter_src_startofpacket; // eth_tse_0_control_port_cmd_width_adapter:out_startofpacket -> eth_tse_0_control_port_burst_adapter:sink0_startofpacket
+ wire eth_tse_0_control_port_cmd_width_adapter_src_endofpacket; // eth_tse_0_control_port_cmd_width_adapter:out_endofpacket -> eth_tse_0_control_port_burst_adapter:sink0_endofpacket
+ wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
+ wire [156:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
+ wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
+ wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
+ wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
+ wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
+ wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
+ wire [156:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
+ wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
+ wire [1:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
+ wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
+ wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
+ wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> crosser_001:in_valid
+ wire [156:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> crosser_001:in_data
+ wire cmd_demux_001_src0_ready; // crosser_001:in_ready -> cmd_demux_001:src0_ready
+ wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> crosser_001:in_channel
+ wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> crosser_001:in_startofpacket
+ wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> crosser_001:in_endofpacket
+ wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux:sink1_valid
+ wire [156:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux:sink1_data
+ wire crosser_001_out_ready; // cmd_mux:sink1_ready -> crosser_001:out_ready
+ wire [1:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux:sink1_channel
+ wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux:sink1_startofpacket
+ wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux:sink1_endofpacket
+ wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_002:in_valid
+ wire [156:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_002:in_data
+ wire rsp_demux_src0_ready; // crosser_002:in_ready -> rsp_demux:src0_ready
+ wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_002:in_channel
+ wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_002:in_startofpacket
+ wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_002:in_endofpacket
+ wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink0_valid
+ wire [156:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink0_data
+ wire crosser_002_out_ready; // rsp_mux:sink0_ready -> crosser_002:out_ready
+ wire [1:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink0_channel
+ wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink0_startofpacket
+ wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink0_endofpacket
+ wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> crosser_003:in_valid
+ wire [156:0] rsp_demux_src1_data; // rsp_demux:src1_data -> crosser_003:in_data
+ wire rsp_demux_src1_ready; // crosser_003:in_ready -> rsp_demux:src1_ready
+ wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> crosser_003:in_channel
+ wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> crosser_003:in_startofpacket
+ wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> crosser_003:in_endofpacket
+ wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux_001:sink0_valid
+ wire [156:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux_001:sink0_data
+ wire crosser_003_out_ready; // rsp_mux_001:sink0_ready -> crosser_003:out_ready
+ wire [1:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux_001:sink0_channel
+ wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux_001:sink0_startofpacket
+ wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux_001:sink0_endofpacket
+ wire eth_tse_0_control_port_agent_rdata_fifo_out_valid; // eth_tse_0_control_port_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
+ wire [33:0] eth_tse_0_control_port_agent_rdata_fifo_out_data; // eth_tse_0_control_port_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
+ wire eth_tse_0_control_port_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> eth_tse_0_control_port_agent_rdata_fifo:out_ready
+ wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> eth_tse_0_control_port_agent:rdata_fifo_sink_valid
+ wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> eth_tse_0_control_port_agent:rdata_fifo_sink_data
+ wire avalon_st_adapter_out_0_ready; // eth_tse_0_control_port_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
+ wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> eth_tse_0_control_port_agent:rdata_fifo_sink_error
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (8),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (32),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (0),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (1),
+ .USE_UAV_CLKEN (0),
+ .USE_READRESPONSE (0),
+ .USE_WRITERESPONSE (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (1),
+ .AV_WRITE_WAIT_CYCLES (1),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) eth_tse_0_control_port_translator (
+ .clk (clk_50m_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // reset.reset
+ .uav_address (eth_tse_0_control_port_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (eth_tse_0_control_port_agent_m0_burstcount), // .burstcount
+ .uav_read (eth_tse_0_control_port_agent_m0_read), // .read
+ .uav_write (eth_tse_0_control_port_agent_m0_write), // .write
+ .uav_waitrequest (eth_tse_0_control_port_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (eth_tse_0_control_port_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (eth_tse_0_control_port_agent_m0_byteenable), // .byteenable
+ .uav_readdata (eth_tse_0_control_port_agent_m0_readdata), // .readdata
+ .uav_writedata (eth_tse_0_control_port_agent_m0_writedata), // .writedata
+ .uav_lock (eth_tse_0_control_port_agent_m0_lock), // .lock
+ .uav_debugaccess (eth_tse_0_control_port_agent_m0_debugaccess), // .debugaccess
+ .av_address (eth_tse_0_control_port_address), // avalon_anti_slave_0.address
+ .av_write (eth_tse_0_control_port_write), // .write
+ .av_read (eth_tse_0_control_port_read), // .read
+ .av_readdata (eth_tse_0_control_port_readdata), // .readdata
+ .av_writedata (eth_tse_0_control_port_writedata), // .writedata
+ .av_waitrequest (eth_tse_0_control_port_waitrequest), // .waitrequest
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable (), // (terminated)
+ .uav_response (), // (terminated)
+ .av_response (2'b00), // (terminated)
+ .uav_writeresponsevalid (), // (terminated)
+ .av_writeresponsevalid (1'b0) // (terminated)
+ );
+
+ altera_merlin_axi_master_ni #(
+ .ID_WIDTH (4),
+ .ADDR_WIDTH (32),
+ .RDATA_WIDTH (64),
+ .WDATA_WIDTH (64),
+ .ADDR_USER_WIDTH (5),
+ .DATA_USER_WIDTH (1),
+ .AXI_BURST_LENGTH_WIDTH (4),
+ .AXI_LOCK_WIDTH (2),
+ .AXI_VERSION ("AXI3"),
+ .WRITE_ISSUING_CAPABILITY (8),
+ .READ_ISSUING_CAPABILITY (8),
+ .PKT_BEGIN_BURST (137),
+ .PKT_CACHE_H (151),
+ .PKT_CACHE_L (148),
+ .PKT_ADDR_SIDEBAND_H (135),
+ .PKT_ADDR_SIDEBAND_L (131),
+ .PKT_PROTECTION_H (147),
+ .PKT_PROTECTION_L (145),
+ .PKT_BURST_SIZE_H (128),
+ .PKT_BURST_SIZE_L (126),
+ .PKT_BURST_TYPE_H (130),
+ .PKT_BURST_TYPE_L (129),
+ .PKT_RESPONSE_STATUS_L (152),
+ .PKT_RESPONSE_STATUS_H (153),
+ .PKT_BURSTWRAP_H (125),
+ .PKT_BURSTWRAP_L (118),
+ .PKT_BYTE_CNT_H (117),
+ .PKT_BYTE_CNT_L (110),
+ .PKT_ADDR_H (103),
+ .PKT_ADDR_L (72),
+ .PKT_TRANS_EXCLUSIVE (109),
+ .PKT_TRANS_LOCK (108),
+ .PKT_TRANS_COMPRESSED_READ (104),
+ .PKT_TRANS_POSTED (105),
+ .PKT_TRANS_WRITE (106),
+ .PKT_TRANS_READ (107),
+ .PKT_DATA_H (63),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (71),
+ .PKT_BYTEEN_L (64),
+ .PKT_SRC_ID_H (139),
+ .PKT_SRC_ID_L (139),
+ .PKT_DEST_ID_H (140),
+ .PKT_DEST_ID_L (140),
+ .PKT_THREAD_ID_H (144),
+ .PKT_THREAD_ID_L (141),
+ .PKT_QOS_L (138),
+ .PKT_QOS_H (138),
+ .PKT_ORI_BURST_SIZE_L (154),
+ .PKT_ORI_BURST_SIZE_H (156),
+ .PKT_DATA_SIDEBAND_H (136),
+ .PKT_DATA_SIDEBAND_L (136),
+ .ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .ID (0)
+ ) a10_hps_h2f_axi_master_agent (
+ .aclk (clk_0_clk_clk), // clk.clk
+ .aresetn (~a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
+ .write_cp_valid (a10_hps_h2f_axi_master_agent_write_cp_valid), // write_cp.valid
+ .write_cp_data (a10_hps_h2f_axi_master_agent_write_cp_data), // .data
+ .write_cp_startofpacket (a10_hps_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
+ .write_cp_endofpacket (a10_hps_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
+ .write_cp_ready (a10_hps_h2f_axi_master_agent_write_cp_ready), // .ready
+ .write_rp_valid (rsp_mux_src_valid), // write_rp.valid
+ .write_rp_data (rsp_mux_src_data), // .data
+ .write_rp_channel (rsp_mux_src_channel), // .channel
+ .write_rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
+ .write_rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
+ .write_rp_ready (rsp_mux_src_ready), // .ready
+ .read_cp_valid (a10_hps_h2f_axi_master_agent_read_cp_valid), // read_cp.valid
+ .read_cp_data (a10_hps_h2f_axi_master_agent_read_cp_data), // .data
+ .read_cp_startofpacket (a10_hps_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
+ .read_cp_endofpacket (a10_hps_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
+ .read_cp_ready (a10_hps_h2f_axi_master_agent_read_cp_ready), // .ready
+ .read_rp_valid (rsp_mux_001_src_valid), // read_rp.valid
+ .read_rp_data (rsp_mux_001_src_data), // .data
+ .read_rp_channel (rsp_mux_001_src_channel), // .channel
+ .read_rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
+ .read_rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
+ .read_rp_ready (rsp_mux_001_src_ready), // .ready
+ .awid (a10_hps_h2f_axi_master_awid), // altera_axi_slave.awid
+ .awaddr (a10_hps_h2f_axi_master_awaddr), // .awaddr
+ .awlen (a10_hps_h2f_axi_master_awlen), // .awlen
+ .awsize (a10_hps_h2f_axi_master_awsize), // .awsize
+ .awburst (a10_hps_h2f_axi_master_awburst), // .awburst
+ .awlock (a10_hps_h2f_axi_master_awlock), // .awlock
+ .awcache (a10_hps_h2f_axi_master_awcache), // .awcache
+ .awprot (a10_hps_h2f_axi_master_awprot), // .awprot
+ .awuser (a10_hps_h2f_axi_master_awuser), // .awuser
+ .awvalid (a10_hps_h2f_axi_master_awvalid), // .awvalid
+ .awready (a10_hps_h2f_axi_master_awready), // .awready
+ .wid (a10_hps_h2f_axi_master_wid), // .wid
+ .wdata (a10_hps_h2f_axi_master_wdata), // .wdata
+ .wstrb (a10_hps_h2f_axi_master_wstrb), // .wstrb
+ .wlast (a10_hps_h2f_axi_master_wlast), // .wlast
+ .wvalid (a10_hps_h2f_axi_master_wvalid), // .wvalid
+ .wready (a10_hps_h2f_axi_master_wready), // .wready
+ .bid (a10_hps_h2f_axi_master_bid), // .bid
+ .bresp (a10_hps_h2f_axi_master_bresp), // .bresp
+ .bvalid (a10_hps_h2f_axi_master_bvalid), // .bvalid
+ .bready (a10_hps_h2f_axi_master_bready), // .bready
+ .arid (a10_hps_h2f_axi_master_arid), // .arid
+ .araddr (a10_hps_h2f_axi_master_araddr), // .araddr
+ .arlen (a10_hps_h2f_axi_master_arlen), // .arlen
+ .arsize (a10_hps_h2f_axi_master_arsize), // .arsize
+ .arburst (a10_hps_h2f_axi_master_arburst), // .arburst
+ .arlock (a10_hps_h2f_axi_master_arlock), // .arlock
+ .arcache (a10_hps_h2f_axi_master_arcache), // .arcache
+ .arprot (a10_hps_h2f_axi_master_arprot), // .arprot
+ .aruser (a10_hps_h2f_axi_master_aruser), // .aruser
+ .arvalid (a10_hps_h2f_axi_master_arvalid), // .arvalid
+ .arready (a10_hps_h2f_axi_master_arready), // .arready
+ .rid (a10_hps_h2f_axi_master_rid), // .rid
+ .rdata (a10_hps_h2f_axi_master_rdata), // .rdata
+ .rresp (a10_hps_h2f_axi_master_rresp), // .rresp
+ .rlast (a10_hps_h2f_axi_master_rlast), // .rlast
+ .rvalid (a10_hps_h2f_axi_master_rvalid), // .rvalid
+ .rready (a10_hps_h2f_axi_master_rready), // .rready
+ .awqos (4'b0000), // (terminated)
+ .arqos (4'b0000), // (terminated)
+ .awregion (4'b0000), // (terminated)
+ .arregion (4'b0000), // (terminated)
+ .wuser (1'b0), // (terminated)
+ .ruser (), // (terminated)
+ .buser () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_ORI_BURST_SIZE_H (120),
+ .PKT_ORI_BURST_SIZE_L (118),
+ .PKT_RESPONSE_STATUS_H (117),
+ .PKT_RESPONSE_STATUS_L (116),
+ .PKT_BURST_SIZE_H (92),
+ .PKT_BURST_SIZE_L (90),
+ .PKT_TRANS_LOCK (72),
+ .PKT_BEGIN_BURST (101),
+ .PKT_PROTECTION_H (111),
+ .PKT_PROTECTION_L (109),
+ .PKT_BURSTWRAP_H (89),
+ .PKT_BURSTWRAP_L (82),
+ .PKT_BYTE_CNT_H (81),
+ .PKT_BYTE_CNT_L (74),
+ .PKT_ADDR_H (67),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (68),
+ .PKT_TRANS_POSTED (69),
+ .PKT_TRANS_WRITE (70),
+ .PKT_TRANS_READ (71),
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_SRC_ID_H (103),
+ .PKT_SRC_ID_L (103),
+ .PKT_DEST_ID_H (104),
+ .PKT_DEST_ID_L (104),
+ .PKT_SYMBOL_W (8),
+ .ST_CHANNEL_W (2),
+ .ST_DATA_W (121),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (1),
+ .PREVENT_FIFO_OVERFLOW (1),
+ .USE_READRESPONSE (0),
+ .USE_WRITERESPONSE (0),
+ .ECC_ENABLE (0)
+ ) eth_tse_0_control_port_agent (
+ .clk (clk_50m_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .m0_address (eth_tse_0_control_port_agent_m0_address), // m0.address
+ .m0_burstcount (eth_tse_0_control_port_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (eth_tse_0_control_port_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (eth_tse_0_control_port_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (eth_tse_0_control_port_agent_m0_lock), // .lock
+ .m0_readdata (eth_tse_0_control_port_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (eth_tse_0_control_port_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (eth_tse_0_control_port_agent_m0_read), // .read
+ .m0_waitrequest (eth_tse_0_control_port_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (eth_tse_0_control_port_agent_m0_writedata), // .writedata
+ .m0_write (eth_tse_0_control_port_agent_m0_write), // .write
+ .rp_endofpacket (eth_tse_0_control_port_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (eth_tse_0_control_port_agent_rp_ready), // .ready
+ .rp_valid (eth_tse_0_control_port_agent_rp_valid), // .valid
+ .rp_data (eth_tse_0_control_port_agent_rp_data), // .data
+ .rp_startofpacket (eth_tse_0_control_port_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (eth_tse_0_control_port_burst_adapter_source0_ready), // cp.ready
+ .cp_valid (eth_tse_0_control_port_burst_adapter_source0_valid), // .valid
+ .cp_data (eth_tse_0_control_port_burst_adapter_source0_data), // .data
+ .cp_startofpacket (eth_tse_0_control_port_burst_adapter_source0_startofpacket), // .startofpacket
+ .cp_endofpacket (eth_tse_0_control_port_burst_adapter_source0_endofpacket), // .endofpacket
+ .cp_channel (eth_tse_0_control_port_burst_adapter_source0_channel), // .channel
+ .rf_sink_ready (eth_tse_0_control_port_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (eth_tse_0_control_port_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (eth_tse_0_control_port_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (eth_tse_0_control_port_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (eth_tse_0_control_port_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (eth_tse_0_control_port_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (eth_tse_0_control_port_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (eth_tse_0_control_port_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
+ .rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
+ .rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
+ .rdata_fifo_src_ready (eth_tse_0_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (eth_tse_0_control_port_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (eth_tse_0_control_port_agent_rdata_fifo_src_data), // .data
+ .m0_response (2'b00), // (terminated)
+ .m0_writeresponsevalid (1'b0) // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (122),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) eth_tse_0_control_port_agent_rsp_fifo (
+ .clk (clk_50m_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_data (eth_tse_0_control_port_agent_rf_source_data), // in.data
+ .in_valid (eth_tse_0_control_port_agent_rf_source_valid), // .valid
+ .in_ready (eth_tse_0_control_port_agent_rf_source_ready), // .ready
+ .in_startofpacket (eth_tse_0_control_port_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (eth_tse_0_control_port_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (eth_tse_0_control_port_agent_rsp_fifo_out_data), // out.data
+ .out_valid (eth_tse_0_control_port_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (eth_tse_0_control_port_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (34),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (0),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (0),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) eth_tse_0_control_port_agent_rdata_fifo (
+ .clk (clk_50m_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_data (eth_tse_0_control_port_agent_rdata_fifo_src_data), // in.data
+ .in_valid (eth_tse_0_control_port_agent_rdata_fifo_src_valid), // .valid
+ .in_ready (eth_tse_0_control_port_agent_rdata_fifo_src_ready), // .ready
+ .out_data (eth_tse_0_control_port_agent_rdata_fifo_out_data), // out.data
+ .out_valid (eth_tse_0_control_port_agent_rdata_fifo_out_valid), // .valid
+ .out_ready (eth_tse_0_control_port_agent_rdata_fifo_out_ready), // .ready
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_startofpacket (1'b0), // (terminated)
+ .in_endofpacket (1'b0), // (terminated)
+ .out_startofpacket (), // (terminated)
+ .out_endofpacket (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ arria10_hps_altera_merlin_router_221_qfjs35a router (
+ .sink_ready (a10_hps_h2f_axi_master_agent_write_cp_ready), // sink.ready
+ .sink_valid (a10_hps_h2f_axi_master_agent_write_cp_valid), // .valid
+ .sink_data (a10_hps_h2f_axi_master_agent_write_cp_data), // .data
+ .sink_startofpacket (a10_hps_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (a10_hps_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_src_ready), // src.ready
+ .src_valid (router_src_valid), // .valid
+ .src_data (router_src_data), // .data
+ .src_channel (router_src_channel), // .channel
+ .src_startofpacket (router_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_src_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_router_221_qfjs35a router_001 (
+ .sink_ready (a10_hps_h2f_axi_master_agent_read_cp_ready), // sink.ready
+ .sink_valid (a10_hps_h2f_axi_master_agent_read_cp_valid), // .valid
+ .sink_data (a10_hps_h2f_axi_master_agent_read_cp_data), // .data
+ .sink_startofpacket (a10_hps_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (a10_hps_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_001_src_ready), // src.ready
+ .src_valid (router_001_src_valid), // .valid
+ .src_data (router_001_src_data), // .data
+ .src_channel (router_001_src_channel), // .channel
+ .src_startofpacket (router_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_001_src_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_router_221_xe243si router_002 (
+ .sink_ready (eth_tse_0_control_port_agent_rp_ready), // sink.ready
+ .sink_valid (eth_tse_0_control_port_agent_rp_valid), // .valid
+ .sink_data (eth_tse_0_control_port_agent_rp_data), // .data
+ .sink_startofpacket (eth_tse_0_control_port_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (eth_tse_0_control_port_agent_rp_endofpacket), // .endofpacket
+ .clk (clk_50m_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_002_src_ready), // src.ready
+ .src_valid (router_002_src_valid), // .valid
+ .src_data (router_002_src_data), // .data
+ .src_channel (router_002_src_channel), // .channel
+ .src_startofpacket (router_002_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_002_src_endofpacket) // .endofpacket
+ );
+
+ altera_merlin_burst_adapter #(
+ .PKT_ADDR_H (67),
+ .PKT_ADDR_L (36),
+ .PKT_BEGIN_BURST (101),
+ .PKT_BYTE_CNT_H (81),
+ .PKT_BYTE_CNT_L (74),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_BURST_SIZE_H (92),
+ .PKT_BURST_SIZE_L (90),
+ .PKT_BURST_TYPE_H (94),
+ .PKT_BURST_TYPE_L (93),
+ .PKT_BURSTWRAP_H (89),
+ .PKT_BURSTWRAP_L (82),
+ .PKT_TRANS_COMPRESSED_READ (68),
+ .PKT_TRANS_WRITE (70),
+ .PKT_TRANS_READ (71),
+ .OUT_NARROW_SIZE (0),
+ .IN_NARROW_SIZE (1),
+ .OUT_FIXED (0),
+ .OUT_COMPLETE_WRAP (0),
+ .ST_DATA_W (121),
+ .ST_CHANNEL_W (2),
+ .OUT_BYTE_CNT_H (76),
+ .OUT_BURSTWRAP_H (89),
+ .COMPRESSED_READ_SUPPORT (1),
+ .BYTEENABLE_SYNTHESIS (1),
+ .PIPE_INPUTS (0),
+ .NO_WRAP_SUPPORT (0),
+ .INCOMPLETE_WRAP_SUPPORT (0),
+ .BURSTWRAP_CONST_MASK (0),
+ .BURSTWRAP_CONST_VALUE (0),
+ .ADAPTER_VERSION ("13.1")
+ ) eth_tse_0_control_port_burst_adapter (
+ .clk (clk_50m_clk_clk), // cr0.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // cr0_reset.reset
+ .sink0_valid (eth_tse_0_control_port_cmd_width_adapter_src_valid), // sink0.valid
+ .sink0_data (eth_tse_0_control_port_cmd_width_adapter_src_data), // .data
+ .sink0_channel (eth_tse_0_control_port_cmd_width_adapter_src_channel), // .channel
+ .sink0_startofpacket (eth_tse_0_control_port_cmd_width_adapter_src_startofpacket), // .startofpacket
+ .sink0_endofpacket (eth_tse_0_control_port_cmd_width_adapter_src_endofpacket), // .endofpacket
+ .sink0_ready (eth_tse_0_control_port_cmd_width_adapter_src_ready), // .ready
+ .source0_valid (eth_tse_0_control_port_burst_adapter_source0_valid), // source0.valid
+ .source0_data (eth_tse_0_control_port_burst_adapter_source0_data), // .data
+ .source0_channel (eth_tse_0_control_port_burst_adapter_source0_channel), // .channel
+ .source0_startofpacket (eth_tse_0_control_port_burst_adapter_source0_startofpacket), // .startofpacket
+ .source0_endofpacket (eth_tse_0_control_port_burst_adapter_source0_endofpacket), // .endofpacket
+ .source0_ready (eth_tse_0_control_port_burst_adapter_source0_ready) // .ready
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_72yhala cmd_demux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (router_src_ready), // sink.ready
+ .sink_channel (router_src_channel), // .channel
+ .sink_data (router_src_data), // .data
+ .sink_startofpacket (router_src_startofpacket), // .startofpacket
+ .sink_endofpacket (router_src_endofpacket), // .endofpacket
+ .sink_valid (router_src_valid), // .valid
+ .src0_ready (cmd_demux_src0_ready), // src0.ready
+ .src0_valid (cmd_demux_src0_valid), // .valid
+ .src0_data (cmd_demux_src0_data), // .data
+ .src0_channel (cmd_demux_src0_channel), // .channel
+ .src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_72yhala cmd_demux_001 (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (router_001_src_ready), // sink.ready
+ .sink_channel (router_001_src_channel), // .channel
+ .sink_data (router_001_src_data), // .data
+ .sink_startofpacket (router_001_src_startofpacket), // .startofpacket
+ .sink_endofpacket (router_001_src_endofpacket), // .endofpacket
+ .sink_valid (router_001_src_valid), // .valid
+ .src0_ready (cmd_demux_001_src0_ready), // src0.ready
+ .src0_valid (cmd_demux_001_src0_valid), // .valid
+ .src0_data (cmd_demux_001_src0_data), // .data
+ .src0_channel (cmd_demux_001_src0_channel), // .channel
+ .src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_vzucqyy cmd_mux (
+ .clk (clk_50m_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (cmd_mux_src_ready), // src.ready
+ .src_valid (cmd_mux_src_valid), // .valid
+ .src_data (cmd_mux_src_data), // .data
+ .src_channel (cmd_mux_src_channel), // .channel
+ .src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
+ .src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
+ .sink0_ready (crosser_out_ready), // sink0.ready
+ .sink0_valid (crosser_out_valid), // .valid
+ .sink0_channel (crosser_out_channel), // .channel
+ .sink0_data (crosser_out_data), // .data
+ .sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
+ .sink0_endofpacket (crosser_out_endofpacket), // .endofpacket
+ .sink1_ready (crosser_001_out_ready), // sink1.ready
+ .sink1_valid (crosser_001_out_valid), // .valid
+ .sink1_channel (crosser_001_out_channel), // .channel
+ .sink1_data (crosser_001_out_data), // .data
+ .sink1_startofpacket (crosser_001_out_startofpacket), // .startofpacket
+ .sink1_endofpacket (crosser_001_out_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_yx3jwsy rsp_demux (
+ .clk (clk_50m_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (eth_tse_0_control_port_rsp_width_adapter_src_ready), // sink.ready
+ .sink_channel (eth_tse_0_control_port_rsp_width_adapter_src_channel), // .channel
+ .sink_data (eth_tse_0_control_port_rsp_width_adapter_src_data), // .data
+ .sink_startofpacket (eth_tse_0_control_port_rsp_width_adapter_src_startofpacket), // .startofpacket
+ .sink_endofpacket (eth_tse_0_control_port_rsp_width_adapter_src_endofpacket), // .endofpacket
+ .sink_valid (eth_tse_0_control_port_rsp_width_adapter_src_valid), // .valid
+ .src0_ready (rsp_demux_src0_ready), // src0.ready
+ .src0_valid (rsp_demux_src0_valid), // .valid
+ .src0_data (rsp_demux_src0_data), // .data
+ .src0_channel (rsp_demux_src0_channel), // .channel
+ .src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
+ .src1_ready (rsp_demux_src1_ready), // src1.ready
+ .src1_valid (rsp_demux_src1_valid), // .valid
+ .src1_data (rsp_demux_src1_data), // .data
+ .src1_channel (rsp_demux_src1_channel), // .channel
+ .src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
+ .src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_huj2kiy rsp_mux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (rsp_mux_src_ready), // src.ready
+ .src_valid (rsp_mux_src_valid), // .valid
+ .src_data (rsp_mux_src_data), // .data
+ .src_channel (rsp_mux_src_channel), // .channel
+ .src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
+ .sink0_ready (crosser_002_out_ready), // sink0.ready
+ .sink0_valid (crosser_002_out_valid), // .valid
+ .sink0_channel (crosser_002_out_channel), // .channel
+ .sink0_data (crosser_002_out_data), // .data
+ .sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
+ .sink0_endofpacket (crosser_002_out_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_huj2kiy rsp_mux_001 (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (rsp_mux_001_src_ready), // src.ready
+ .src_valid (rsp_mux_001_src_valid), // .valid
+ .src_data (rsp_mux_001_src_data), // .data
+ .src_channel (rsp_mux_001_src_channel), // .channel
+ .src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
+ .sink0_ready (crosser_003_out_ready), // sink0.ready
+ .sink0_valid (crosser_003_out_valid), // .valid
+ .sink0_channel (crosser_003_out_channel), // .channel
+ .sink0_data (crosser_003_out_data), // .data
+ .sink0_startofpacket (crosser_003_out_startofpacket), // .startofpacket
+ .sink0_endofpacket (crosser_003_out_endofpacket) // .endofpacket
+ );
+
+ altera_merlin_width_adapter #(
+ .IN_PKT_ADDR_H (67),
+ .IN_PKT_ADDR_L (36),
+ .IN_PKT_DATA_H (31),
+ .IN_PKT_DATA_L (0),
+ .IN_PKT_BYTEEN_H (35),
+ .IN_PKT_BYTEEN_L (32),
+ .IN_PKT_BYTE_CNT_H (81),
+ .IN_PKT_BYTE_CNT_L (74),
+ .IN_PKT_TRANS_COMPRESSED_READ (68),
+ .IN_PKT_TRANS_WRITE (70),
+ .IN_PKT_BURSTWRAP_H (89),
+ .IN_PKT_BURSTWRAP_L (82),
+ .IN_PKT_BURST_SIZE_H (92),
+ .IN_PKT_BURST_SIZE_L (90),
+ .IN_PKT_RESPONSE_STATUS_H (117),
+ .IN_PKT_RESPONSE_STATUS_L (116),
+ .IN_PKT_TRANS_EXCLUSIVE (73),
+ .IN_PKT_BURST_TYPE_H (94),
+ .IN_PKT_BURST_TYPE_L (93),
+ .IN_PKT_ORI_BURST_SIZE_L (118),
+ .IN_PKT_ORI_BURST_SIZE_H (120),
+ .IN_ST_DATA_W (121),
+ .OUT_PKT_ADDR_H (103),
+ .OUT_PKT_ADDR_L (72),
+ .OUT_PKT_DATA_H (63),
+ .OUT_PKT_DATA_L (0),
+ .OUT_PKT_BYTEEN_H (71),
+ .OUT_PKT_BYTEEN_L (64),
+ .OUT_PKT_BYTE_CNT_H (117),
+ .OUT_PKT_BYTE_CNT_L (110),
+ .OUT_PKT_TRANS_COMPRESSED_READ (104),
+ .OUT_PKT_BURST_SIZE_H (128),
+ .OUT_PKT_BURST_SIZE_L (126),
+ .OUT_PKT_RESPONSE_STATUS_H (153),
+ .OUT_PKT_RESPONSE_STATUS_L (152),
+ .OUT_PKT_TRANS_EXCLUSIVE (109),
+ .OUT_PKT_BURST_TYPE_H (130),
+ .OUT_PKT_BURST_TYPE_L (129),
+ .OUT_PKT_ORI_BURST_SIZE_L (154),
+ .OUT_PKT_ORI_BURST_SIZE_H (156),
+ .OUT_ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .OPTIMIZE_FOR_RSP (0),
+ .RESPONSE_PATH (1),
+ .CONSTANT_BURST_SIZE (0),
+ .PACKING (1),
+ .ENABLE_ADDRESS_ALIGNMENT (1)
+ ) eth_tse_0_control_port_rsp_width_adapter (
+ .clk (clk_50m_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_valid (router_002_src_valid), // sink.valid
+ .in_channel (router_002_src_channel), // .channel
+ .in_startofpacket (router_002_src_startofpacket), // .startofpacket
+ .in_endofpacket (router_002_src_endofpacket), // .endofpacket
+ .in_ready (router_002_src_ready), // .ready
+ .in_data (router_002_src_data), // .data
+ .out_endofpacket (eth_tse_0_control_port_rsp_width_adapter_src_endofpacket), // src.endofpacket
+ .out_data (eth_tse_0_control_port_rsp_width_adapter_src_data), // .data
+ .out_channel (eth_tse_0_control_port_rsp_width_adapter_src_channel), // .channel
+ .out_valid (eth_tse_0_control_port_rsp_width_adapter_src_valid), // .valid
+ .out_ready (eth_tse_0_control_port_rsp_width_adapter_src_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_rsp_width_adapter_src_startofpacket), // .startofpacket
+ .in_command_size_data (3'b000) // (terminated)
+ );
+
+ altera_merlin_width_adapter #(
+ .IN_PKT_ADDR_H (103),
+ .IN_PKT_ADDR_L (72),
+ .IN_PKT_DATA_H (63),
+ .IN_PKT_DATA_L (0),
+ .IN_PKT_BYTEEN_H (71),
+ .IN_PKT_BYTEEN_L (64),
+ .IN_PKT_BYTE_CNT_H (117),
+ .IN_PKT_BYTE_CNT_L (110),
+ .IN_PKT_TRANS_COMPRESSED_READ (104),
+ .IN_PKT_TRANS_WRITE (106),
+ .IN_PKT_BURSTWRAP_H (125),
+ .IN_PKT_BURSTWRAP_L (118),
+ .IN_PKT_BURST_SIZE_H (128),
+ .IN_PKT_BURST_SIZE_L (126),
+ .IN_PKT_RESPONSE_STATUS_H (153),
+ .IN_PKT_RESPONSE_STATUS_L (152),
+ .IN_PKT_TRANS_EXCLUSIVE (109),
+ .IN_PKT_BURST_TYPE_H (130),
+ .IN_PKT_BURST_TYPE_L (129),
+ .IN_PKT_ORI_BURST_SIZE_L (154),
+ .IN_PKT_ORI_BURST_SIZE_H (156),
+ .IN_ST_DATA_W (157),
+ .OUT_PKT_ADDR_H (67),
+ .OUT_PKT_ADDR_L (36),
+ .OUT_PKT_DATA_H (31),
+ .OUT_PKT_DATA_L (0),
+ .OUT_PKT_BYTEEN_H (35),
+ .OUT_PKT_BYTEEN_L (32),
+ .OUT_PKT_BYTE_CNT_H (81),
+ .OUT_PKT_BYTE_CNT_L (74),
+ .OUT_PKT_TRANS_COMPRESSED_READ (68),
+ .OUT_PKT_BURST_SIZE_H (92),
+ .OUT_PKT_BURST_SIZE_L (90),
+ .OUT_PKT_RESPONSE_STATUS_H (117),
+ .OUT_PKT_RESPONSE_STATUS_L (116),
+ .OUT_PKT_TRANS_EXCLUSIVE (73),
+ .OUT_PKT_BURST_TYPE_H (94),
+ .OUT_PKT_BURST_TYPE_L (93),
+ .OUT_PKT_ORI_BURST_SIZE_L (118),
+ .OUT_PKT_ORI_BURST_SIZE_H (120),
+ .OUT_ST_DATA_W (121),
+ .ST_CHANNEL_W (2),
+ .OPTIMIZE_FOR_RSP (0),
+ .RESPONSE_PATH (0),
+ .CONSTANT_BURST_SIZE (0),
+ .PACKING (0),
+ .ENABLE_ADDRESS_ALIGNMENT (1)
+ ) eth_tse_0_control_port_cmd_width_adapter (
+ .clk (clk_50m_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_valid (cmd_mux_src_valid), // sink.valid
+ .in_channel (cmd_mux_src_channel), // .channel
+ .in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
+ .in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
+ .in_ready (cmd_mux_src_ready), // .ready
+ .in_data (cmd_mux_src_data), // .data
+ .out_endofpacket (eth_tse_0_control_port_cmd_width_adapter_src_endofpacket), // src.endofpacket
+ .out_data (eth_tse_0_control_port_cmd_width_adapter_src_data), // .data
+ .out_channel (eth_tse_0_control_port_cmd_width_adapter_src_channel), // .channel
+ .out_valid (eth_tse_0_control_port_cmd_width_adapter_src_valid), // .valid
+ .out_ready (eth_tse_0_control_port_cmd_width_adapter_src_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_cmd_width_adapter_src_startofpacket), // .startofpacket
+ .in_command_size_data (3'b000) // (terminated)
+ );
+
+ altera_avalon_st_handshake_clock_crosser #(
+ .DATA_WIDTH (157),
+ .BITS_PER_SYMBOL (157),
+ .USE_PACKETS (1),
+ .USE_CHANNEL (1),
+ .CHANNEL_WIDTH (2),
+ .USE_ERROR (0),
+ .ERROR_WIDTH (1),
+ .VALID_SYNC_DEPTH (2),
+ .READY_SYNC_DEPTH (2),
+ .USE_OUTPUT_PIPELINE (0)
+ ) crosser (
+ .in_clk (clk_0_clk_clk), // in_clk.clk
+ .in_reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
+ .out_clk (clk_50m_clk_clk), // out_clk.clk
+ .out_reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // out_clk_reset.reset
+ .in_ready (cmd_demux_src0_ready), // in.ready
+ .in_valid (cmd_demux_src0_valid), // .valid
+ .in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
+ .in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
+ .in_channel (cmd_demux_src0_channel), // .channel
+ .in_data (cmd_demux_src0_data), // .data
+ .out_ready (crosser_out_ready), // out.ready
+ .out_valid (crosser_out_valid), // .valid
+ .out_startofpacket (crosser_out_startofpacket), // .startofpacket
+ .out_endofpacket (crosser_out_endofpacket), // .endofpacket
+ .out_channel (crosser_out_channel), // .channel
+ .out_data (crosser_out_data), // .data
+ .in_empty (1'b0), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .out_error () // (terminated)
+ );
+
+ altera_avalon_st_handshake_clock_crosser #(
+ .DATA_WIDTH (157),
+ .BITS_PER_SYMBOL (157),
+ .USE_PACKETS (1),
+ .USE_CHANNEL (1),
+ .CHANNEL_WIDTH (2),
+ .USE_ERROR (0),
+ .ERROR_WIDTH (1),
+ .VALID_SYNC_DEPTH (2),
+ .READY_SYNC_DEPTH (2),
+ .USE_OUTPUT_PIPELINE (0)
+ ) crosser_001 (
+ .in_clk (clk_0_clk_clk), // in_clk.clk
+ .in_reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
+ .out_clk (clk_50m_clk_clk), // out_clk.clk
+ .out_reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // out_clk_reset.reset
+ .in_ready (cmd_demux_001_src0_ready), // in.ready
+ .in_valid (cmd_demux_001_src0_valid), // .valid
+ .in_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
+ .in_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
+ .in_channel (cmd_demux_001_src0_channel), // .channel
+ .in_data (cmd_demux_001_src0_data), // .data
+ .out_ready (crosser_001_out_ready), // out.ready
+ .out_valid (crosser_001_out_valid), // .valid
+ .out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
+ .out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
+ .out_channel (crosser_001_out_channel), // .channel
+ .out_data (crosser_001_out_data), // .data
+ .in_empty (1'b0), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .out_error () // (terminated)
+ );
+
+ altera_avalon_st_handshake_clock_crosser #(
+ .DATA_WIDTH (157),
+ .BITS_PER_SYMBOL (157),
+ .USE_PACKETS (1),
+ .USE_CHANNEL (1),
+ .CHANNEL_WIDTH (2),
+ .USE_ERROR (0),
+ .ERROR_WIDTH (1),
+ .VALID_SYNC_DEPTH (2),
+ .READY_SYNC_DEPTH (2),
+ .USE_OUTPUT_PIPELINE (0)
+ ) crosser_002 (
+ .in_clk (clk_50m_clk_clk), // in_clk.clk
+ .in_reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // in_clk_reset.reset
+ .out_clk (clk_0_clk_clk), // out_clk.clk
+ .out_reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
+ .in_ready (rsp_demux_src0_ready), // in.ready
+ .in_valid (rsp_demux_src0_valid), // .valid
+ .in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
+ .in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
+ .in_channel (rsp_demux_src0_channel), // .channel
+ .in_data (rsp_demux_src0_data), // .data
+ .out_ready (crosser_002_out_ready), // out.ready
+ .out_valid (crosser_002_out_valid), // .valid
+ .out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
+ .out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
+ .out_channel (crosser_002_out_channel), // .channel
+ .out_data (crosser_002_out_data), // .data
+ .in_empty (1'b0), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .out_error () // (terminated)
+ );
+
+ altera_avalon_st_handshake_clock_crosser #(
+ .DATA_WIDTH (157),
+ .BITS_PER_SYMBOL (157),
+ .USE_PACKETS (1),
+ .USE_CHANNEL (1),
+ .CHANNEL_WIDTH (2),
+ .USE_ERROR (0),
+ .ERROR_WIDTH (1),
+ .VALID_SYNC_DEPTH (2),
+ .READY_SYNC_DEPTH (2),
+ .USE_OUTPUT_PIPELINE (0)
+ ) crosser_003 (
+ .in_clk (clk_50m_clk_clk), // in_clk.clk
+ .in_reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // in_clk_reset.reset
+ .out_clk (clk_0_clk_clk), // out_clk.clk
+ .out_reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
+ .in_ready (rsp_demux_src1_ready), // in.ready
+ .in_valid (rsp_demux_src1_valid), // .valid
+ .in_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
+ .in_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
+ .in_channel (rsp_demux_src1_channel), // .channel
+ .in_data (rsp_demux_src1_data), // .data
+ .out_ready (crosser_003_out_ready), // out.ready
+ .out_valid (crosser_003_out_valid), // .valid
+ .out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
+ .out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
+ .out_channel (crosser_003_out_channel), // .channel
+ .out_data (crosser_003_out_data), // .data
+ .in_empty (1'b0), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .out_error () // (terminated)
+ );
+
+ arria10_hps_altera_avalon_st_adapter_221_36tuu3a #(
+ .inBitsPerSymbol (34),
+ .inUsePackets (0),
+ .inDataWidth (34),
+ .inChannelWidth (0),
+ .inErrorWidth (0),
+ .inUseEmptyPort (0),
+ .inUseValid (1),
+ .inUseReady (1),
+ .inReadyLatency (0),
+ .outDataWidth (34),
+ .outChannelWidth (0),
+ .outErrorWidth (1),
+ .outUseEmptyPort (0),
+ .outUseValid (1),
+ .outUseReady (1),
+ .outReadyLatency (0)
+ ) avalon_st_adapter (
+ .in_clk_0_clk (clk_50m_clk_clk), // in_clk_0.clk
+ .in_rst_0_reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // in_rst_0.reset
+ .in_0_data (eth_tse_0_control_port_agent_rdata_fifo_out_data), // in_0.data
+ .in_0_valid (eth_tse_0_control_port_agent_rdata_fifo_out_valid), // .valid
+ .in_0_ready (eth_tse_0_control_port_agent_rdata_fifo_out_ready), // .ready
+ .out_0_data (avalon_st_adapter_out_0_data), // out_0.data
+ .out_0_valid (avalon_st_adapter_out_0_valid), // .valid
+ .out_0_ready (avalon_st_adapter_out_0_ready), // .ready
+ .out_0_error (avalon_st_adapter_out_0_error) // .error
+ );
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_fg5byai_cfg.v b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_fg5byai_cfg.v
new file mode 100644
index 0000000000000000000000000000000000000000..78081771ce1f3967dd4d43749cbbec51dd2c4384
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_fg5byai_cfg.v
@@ -0,0 +1,26 @@
+config arria10_hps_altera_mm_interconnect_221_fg5byai_cfg;
+ design arria10_hps_altera_mm_interconnect_221_fg5byai;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.eth_tse_0_control_port_translator use arria10_hps_altera_merlin_slave_translator_221.altera_merlin_slave_translator;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.a10_hps_h2f_axi_master_agent use arria10_hps_altera_merlin_axi_master_ni_221.altera_merlin_axi_master_ni;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.eth_tse_0_control_port_agent use arria10_hps_altera_merlin_slave_agent_221.altera_merlin_slave_agent;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.eth_tse_0_control_port_agent_rsp_fifo use arria10_hps_altera_avalon_sc_fifo_221.altera_avalon_sc_fifo;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.eth_tse_0_control_port_agent_rdata_fifo use arria10_hps_altera_avalon_sc_fifo_221.altera_avalon_sc_fifo;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.router use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_qfjs35a;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.router_001 use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_qfjs35a;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.router_002 use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_xe243si;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.eth_tse_0_control_port_burst_adapter use arria10_hps_altera_merlin_burst_adapter_221.altera_merlin_burst_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.cmd_demux use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_72yhala;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.cmd_demux_001 use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_72yhala;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.cmd_mux use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_vzucqyy;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.rsp_demux use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_yx3jwsy;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.rsp_mux use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_huj2kiy;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.rsp_mux_001 use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_huj2kiy;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.eth_tse_0_control_port_rsp_width_adapter use arria10_hps_altera_merlin_width_adapter_221.altera_merlin_width_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.eth_tse_0_control_port_cmd_width_adapter use arria10_hps_altera_merlin_width_adapter_221.altera_merlin_width_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.crosser use arria10_hps_altera_avalon_st_handshake_clock_crosser_221.altera_avalon_st_handshake_clock_crosser;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.crosser_001 use arria10_hps_altera_avalon_st_handshake_clock_crosser_221.altera_avalon_st_handshake_clock_crosser;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.crosser_002 use arria10_hps_altera_avalon_st_handshake_clock_crosser_221.altera_avalon_st_handshake_clock_crosser;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.crosser_003 use arria10_hps_altera_avalon_st_handshake_clock_crosser_221.altera_avalon_st_handshake_clock_crosser;
+ instance arria10_hps_altera_mm_interconnect_221_fg5byai.avalon_st_adapter use arria10_hps_altera_avalon_st_adapter_221.arria10_hps_altera_avalon_st_adapter_221_36tuu3a;
+endconfig
+
diff --git a/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_jwt2njy.v b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_jwt2njy.v
new file mode 100644
index 0000000000000000000000000000000000000000..900f7fe72519a1165a0224d231e57d06486f1c62
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_jwt2njy.v
@@ -0,0 +1,1662 @@
+// arria10_hps_altera_mm_interconnect_221_jwt2njy.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
+// will probably be lost.
+//
+// Generated using ACDS version 22.1 922
+
+`timescale 1 ps / 1 ps
+module arria10_hps_altera_mm_interconnect_221_jwt2njy (
+ input wire [3:0] a10_hps_h2f_axi_master_awid, // a10_hps_h2f_axi_master.awid
+ input wire [31:0] a10_hps_h2f_axi_master_awaddr, // .awaddr
+ input wire [3:0] a10_hps_h2f_axi_master_awlen, // .awlen
+ input wire [2:0] a10_hps_h2f_axi_master_awsize, // .awsize
+ input wire [1:0] a10_hps_h2f_axi_master_awburst, // .awburst
+ input wire [1:0] a10_hps_h2f_axi_master_awlock, // .awlock
+ input wire [3:0] a10_hps_h2f_axi_master_awcache, // .awcache
+ input wire [2:0] a10_hps_h2f_axi_master_awprot, // .awprot
+ input wire [4:0] a10_hps_h2f_axi_master_awuser, // .awuser
+ input wire a10_hps_h2f_axi_master_awvalid, // .awvalid
+ output wire a10_hps_h2f_axi_master_awready, // .awready
+ input wire [3:0] a10_hps_h2f_axi_master_wid, // .wid
+ input wire [63:0] a10_hps_h2f_axi_master_wdata, // .wdata
+ input wire [7:0] a10_hps_h2f_axi_master_wstrb, // .wstrb
+ input wire a10_hps_h2f_axi_master_wlast, // .wlast
+ input wire a10_hps_h2f_axi_master_wvalid, // .wvalid
+ output wire a10_hps_h2f_axi_master_wready, // .wready
+ output wire [3:0] a10_hps_h2f_axi_master_bid, // .bid
+ output wire [1:0] a10_hps_h2f_axi_master_bresp, // .bresp
+ output wire a10_hps_h2f_axi_master_bvalid, // .bvalid
+ input wire a10_hps_h2f_axi_master_bready, // .bready
+ input wire [3:0] a10_hps_h2f_axi_master_arid, // .arid
+ input wire [31:0] a10_hps_h2f_axi_master_araddr, // .araddr
+ input wire [3:0] a10_hps_h2f_axi_master_arlen, // .arlen
+ input wire [2:0] a10_hps_h2f_axi_master_arsize, // .arsize
+ input wire [1:0] a10_hps_h2f_axi_master_arburst, // .arburst
+ input wire [1:0] a10_hps_h2f_axi_master_arlock, // .arlock
+ input wire [3:0] a10_hps_h2f_axi_master_arcache, // .arcache
+ input wire [2:0] a10_hps_h2f_axi_master_arprot, // .arprot
+ input wire [4:0] a10_hps_h2f_axi_master_aruser, // .aruser
+ input wire a10_hps_h2f_axi_master_arvalid, // .arvalid
+ output wire a10_hps_h2f_axi_master_arready, // .arready
+ output wire [3:0] a10_hps_h2f_axi_master_rid, // .rid
+ output wire [63:0] a10_hps_h2f_axi_master_rdata, // .rdata
+ output wire [1:0] a10_hps_h2f_axi_master_rresp, // .rresp
+ output wire a10_hps_h2f_axi_master_rlast, // .rlast
+ output wire a10_hps_h2f_axi_master_rvalid, // .rvalid
+ input wire a10_hps_h2f_axi_master_rready, // .rready
+ input wire clk_0_clk_clk, // clk_0_clk.clk
+ input wire a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset, // a10_hps_h2f_axi_reset_reset_bridge_in_reset.reset
+ input wire eth_tse_0_reset_connection_reset_bridge_in_reset_reset, // eth_tse_0_reset_connection_reset_bridge_in_reset.reset
+ output wire [7:0] eth_tse_0_control_port_address, // eth_tse_0_control_port.address
+ output wire eth_tse_0_control_port_write, // .write
+ output wire eth_tse_0_control_port_read, // .read
+ input wire [31:0] eth_tse_0_control_port_readdata, // .readdata
+ output wire [31:0] eth_tse_0_control_port_writedata, // .writedata
+ input wire eth_tse_0_control_port_waitrequest, // .waitrequest
+ output wire [7:0] eth_tse_1_control_port_address, // eth_tse_1_control_port.address
+ output wire eth_tse_1_control_port_write, // .write
+ output wire eth_tse_1_control_port_read, // .read
+ input wire [31:0] eth_tse_1_control_port_readdata, // .readdata
+ output wire [31:0] eth_tse_1_control_port_writedata, // .writedata
+ input wire eth_tse_1_control_port_waitrequest // .waitrequest
+ );
+
+ wire [31:0] eth_tse_0_control_port_agent_m0_readdata; // eth_tse_0_control_port_translator:uav_readdata -> eth_tse_0_control_port_agent:m0_readdata
+ wire eth_tse_0_control_port_agent_m0_waitrequest; // eth_tse_0_control_port_translator:uav_waitrequest -> eth_tse_0_control_port_agent:m0_waitrequest
+ wire eth_tse_0_control_port_agent_m0_debugaccess; // eth_tse_0_control_port_agent:m0_debugaccess -> eth_tse_0_control_port_translator:uav_debugaccess
+ wire [31:0] eth_tse_0_control_port_agent_m0_address; // eth_tse_0_control_port_agent:m0_address -> eth_tse_0_control_port_translator:uav_address
+ wire [3:0] eth_tse_0_control_port_agent_m0_byteenable; // eth_tse_0_control_port_agent:m0_byteenable -> eth_tse_0_control_port_translator:uav_byteenable
+ wire eth_tse_0_control_port_agent_m0_read; // eth_tse_0_control_port_agent:m0_read -> eth_tse_0_control_port_translator:uav_read
+ wire eth_tse_0_control_port_agent_m0_readdatavalid; // eth_tse_0_control_port_translator:uav_readdatavalid -> eth_tse_0_control_port_agent:m0_readdatavalid
+ wire eth_tse_0_control_port_agent_m0_lock; // eth_tse_0_control_port_agent:m0_lock -> eth_tse_0_control_port_translator:uav_lock
+ wire [31:0] eth_tse_0_control_port_agent_m0_writedata; // eth_tse_0_control_port_agent:m0_writedata -> eth_tse_0_control_port_translator:uav_writedata
+ wire eth_tse_0_control_port_agent_m0_write; // eth_tse_0_control_port_agent:m0_write -> eth_tse_0_control_port_translator:uav_write
+ wire [2:0] eth_tse_0_control_port_agent_m0_burstcount; // eth_tse_0_control_port_agent:m0_burstcount -> eth_tse_0_control_port_translator:uav_burstcount
+ wire eth_tse_0_control_port_agent_rf_source_valid; // eth_tse_0_control_port_agent:rf_source_valid -> eth_tse_0_control_port_agent_rsp_fifo:in_valid
+ wire [121:0] eth_tse_0_control_port_agent_rf_source_data; // eth_tse_0_control_port_agent:rf_source_data -> eth_tse_0_control_port_agent_rsp_fifo:in_data
+ wire eth_tse_0_control_port_agent_rf_source_ready; // eth_tse_0_control_port_agent_rsp_fifo:in_ready -> eth_tse_0_control_port_agent:rf_source_ready
+ wire eth_tse_0_control_port_agent_rf_source_startofpacket; // eth_tse_0_control_port_agent:rf_source_startofpacket -> eth_tse_0_control_port_agent_rsp_fifo:in_startofpacket
+ wire eth_tse_0_control_port_agent_rf_source_endofpacket; // eth_tse_0_control_port_agent:rf_source_endofpacket -> eth_tse_0_control_port_agent_rsp_fifo:in_endofpacket
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_valid; // eth_tse_0_control_port_agent_rsp_fifo:out_valid -> eth_tse_0_control_port_agent:rf_sink_valid
+ wire [121:0] eth_tse_0_control_port_agent_rsp_fifo_out_data; // eth_tse_0_control_port_agent_rsp_fifo:out_data -> eth_tse_0_control_port_agent:rf_sink_data
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_ready; // eth_tse_0_control_port_agent:rf_sink_ready -> eth_tse_0_control_port_agent_rsp_fifo:out_ready
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket; // eth_tse_0_control_port_agent_rsp_fifo:out_startofpacket -> eth_tse_0_control_port_agent:rf_sink_startofpacket
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket; // eth_tse_0_control_port_agent_rsp_fifo:out_endofpacket -> eth_tse_0_control_port_agent:rf_sink_endofpacket
+ wire eth_tse_0_control_port_agent_rdata_fifo_src_valid; // eth_tse_0_control_port_agent:rdata_fifo_src_valid -> eth_tse_0_control_port_agent_rdata_fifo:in_valid
+ wire [33:0] eth_tse_0_control_port_agent_rdata_fifo_src_data; // eth_tse_0_control_port_agent:rdata_fifo_src_data -> eth_tse_0_control_port_agent_rdata_fifo:in_data
+ wire eth_tse_0_control_port_agent_rdata_fifo_src_ready; // eth_tse_0_control_port_agent_rdata_fifo:in_ready -> eth_tse_0_control_port_agent:rdata_fifo_src_ready
+ wire [31:0] eth_tse_1_control_port_agent_m0_readdata; // eth_tse_1_control_port_translator:uav_readdata -> eth_tse_1_control_port_agent:m0_readdata
+ wire eth_tse_1_control_port_agent_m0_waitrequest; // eth_tse_1_control_port_translator:uav_waitrequest -> eth_tse_1_control_port_agent:m0_waitrequest
+ wire eth_tse_1_control_port_agent_m0_debugaccess; // eth_tse_1_control_port_agent:m0_debugaccess -> eth_tse_1_control_port_translator:uav_debugaccess
+ wire [31:0] eth_tse_1_control_port_agent_m0_address; // eth_tse_1_control_port_agent:m0_address -> eth_tse_1_control_port_translator:uav_address
+ wire [3:0] eth_tse_1_control_port_agent_m0_byteenable; // eth_tse_1_control_port_agent:m0_byteenable -> eth_tse_1_control_port_translator:uav_byteenable
+ wire eth_tse_1_control_port_agent_m0_read; // eth_tse_1_control_port_agent:m0_read -> eth_tse_1_control_port_translator:uav_read
+ wire eth_tse_1_control_port_agent_m0_readdatavalid; // eth_tse_1_control_port_translator:uav_readdatavalid -> eth_tse_1_control_port_agent:m0_readdatavalid
+ wire eth_tse_1_control_port_agent_m0_lock; // eth_tse_1_control_port_agent:m0_lock -> eth_tse_1_control_port_translator:uav_lock
+ wire [31:0] eth_tse_1_control_port_agent_m0_writedata; // eth_tse_1_control_port_agent:m0_writedata -> eth_tse_1_control_port_translator:uav_writedata
+ wire eth_tse_1_control_port_agent_m0_write; // eth_tse_1_control_port_agent:m0_write -> eth_tse_1_control_port_translator:uav_write
+ wire [2:0] eth_tse_1_control_port_agent_m0_burstcount; // eth_tse_1_control_port_agent:m0_burstcount -> eth_tse_1_control_port_translator:uav_burstcount
+ wire eth_tse_1_control_port_agent_rf_source_valid; // eth_tse_1_control_port_agent:rf_source_valid -> eth_tse_1_control_port_agent_rsp_fifo:in_valid
+ wire [121:0] eth_tse_1_control_port_agent_rf_source_data; // eth_tse_1_control_port_agent:rf_source_data -> eth_tse_1_control_port_agent_rsp_fifo:in_data
+ wire eth_tse_1_control_port_agent_rf_source_ready; // eth_tse_1_control_port_agent_rsp_fifo:in_ready -> eth_tse_1_control_port_agent:rf_source_ready
+ wire eth_tse_1_control_port_agent_rf_source_startofpacket; // eth_tse_1_control_port_agent:rf_source_startofpacket -> eth_tse_1_control_port_agent_rsp_fifo:in_startofpacket
+ wire eth_tse_1_control_port_agent_rf_source_endofpacket; // eth_tse_1_control_port_agent:rf_source_endofpacket -> eth_tse_1_control_port_agent_rsp_fifo:in_endofpacket
+ wire eth_tse_1_control_port_agent_rsp_fifo_out_valid; // eth_tse_1_control_port_agent_rsp_fifo:out_valid -> eth_tse_1_control_port_agent:rf_sink_valid
+ wire [121:0] eth_tse_1_control_port_agent_rsp_fifo_out_data; // eth_tse_1_control_port_agent_rsp_fifo:out_data -> eth_tse_1_control_port_agent:rf_sink_data
+ wire eth_tse_1_control_port_agent_rsp_fifo_out_ready; // eth_tse_1_control_port_agent:rf_sink_ready -> eth_tse_1_control_port_agent_rsp_fifo:out_ready
+ wire eth_tse_1_control_port_agent_rsp_fifo_out_startofpacket; // eth_tse_1_control_port_agent_rsp_fifo:out_startofpacket -> eth_tse_1_control_port_agent:rf_sink_startofpacket
+ wire eth_tse_1_control_port_agent_rsp_fifo_out_endofpacket; // eth_tse_1_control_port_agent_rsp_fifo:out_endofpacket -> eth_tse_1_control_port_agent:rf_sink_endofpacket
+ wire eth_tse_1_control_port_agent_rdata_fifo_src_valid; // eth_tse_1_control_port_agent:rdata_fifo_src_valid -> eth_tse_1_control_port_agent_rdata_fifo:in_valid
+ wire [33:0] eth_tse_1_control_port_agent_rdata_fifo_src_data; // eth_tse_1_control_port_agent:rdata_fifo_src_data -> eth_tse_1_control_port_agent_rdata_fifo:in_data
+ wire eth_tse_1_control_port_agent_rdata_fifo_src_ready; // eth_tse_1_control_port_agent_rdata_fifo:in_ready -> eth_tse_1_control_port_agent:rdata_fifo_src_ready
+ wire a10_hps_h2f_axi_master_agent_write_cp_valid; // a10_hps_h2f_axi_master_agent:write_cp_valid -> router:sink_valid
+ wire [156:0] a10_hps_h2f_axi_master_agent_write_cp_data; // a10_hps_h2f_axi_master_agent:write_cp_data -> router:sink_data
+ wire a10_hps_h2f_axi_master_agent_write_cp_ready; // router:sink_ready -> a10_hps_h2f_axi_master_agent:write_cp_ready
+ wire a10_hps_h2f_axi_master_agent_write_cp_startofpacket; // a10_hps_h2f_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
+ wire a10_hps_h2f_axi_master_agent_write_cp_endofpacket; // a10_hps_h2f_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
+ wire a10_hps_h2f_axi_master_agent_read_cp_valid; // a10_hps_h2f_axi_master_agent:read_cp_valid -> router_001:sink_valid
+ wire [156:0] a10_hps_h2f_axi_master_agent_read_cp_data; // a10_hps_h2f_axi_master_agent:read_cp_data -> router_001:sink_data
+ wire a10_hps_h2f_axi_master_agent_read_cp_ready; // router_001:sink_ready -> a10_hps_h2f_axi_master_agent:read_cp_ready
+ wire a10_hps_h2f_axi_master_agent_read_cp_startofpacket; // a10_hps_h2f_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
+ wire a10_hps_h2f_axi_master_agent_read_cp_endofpacket; // a10_hps_h2f_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
+ wire eth_tse_0_control_port_agent_rp_valid; // eth_tse_0_control_port_agent:rp_valid -> router_002:sink_valid
+ wire [120:0] eth_tse_0_control_port_agent_rp_data; // eth_tse_0_control_port_agent:rp_data -> router_002:sink_data
+ wire eth_tse_0_control_port_agent_rp_ready; // router_002:sink_ready -> eth_tse_0_control_port_agent:rp_ready
+ wire eth_tse_0_control_port_agent_rp_startofpacket; // eth_tse_0_control_port_agent:rp_startofpacket -> router_002:sink_startofpacket
+ wire eth_tse_0_control_port_agent_rp_endofpacket; // eth_tse_0_control_port_agent:rp_endofpacket -> router_002:sink_endofpacket
+ wire eth_tse_1_control_port_agent_rp_valid; // eth_tse_1_control_port_agent:rp_valid -> router_003:sink_valid
+ wire [120:0] eth_tse_1_control_port_agent_rp_data; // eth_tse_1_control_port_agent:rp_data -> router_003:sink_data
+ wire eth_tse_1_control_port_agent_rp_ready; // router_003:sink_ready -> eth_tse_1_control_port_agent:rp_ready
+ wire eth_tse_1_control_port_agent_rp_startofpacket; // eth_tse_1_control_port_agent:rp_startofpacket -> router_003:sink_startofpacket
+ wire eth_tse_1_control_port_agent_rp_endofpacket; // eth_tse_1_control_port_agent:rp_endofpacket -> router_003:sink_endofpacket
+ wire router_src_valid; // router:src_valid -> a10_hps_h2f_axi_master_wr_limiter:cmd_sink_valid
+ wire [156:0] router_src_data; // router:src_data -> a10_hps_h2f_axi_master_wr_limiter:cmd_sink_data
+ wire router_src_ready; // a10_hps_h2f_axi_master_wr_limiter:cmd_sink_ready -> router:src_ready
+ wire [1:0] router_src_channel; // router:src_channel -> a10_hps_h2f_axi_master_wr_limiter:cmd_sink_channel
+ wire router_src_startofpacket; // router:src_startofpacket -> a10_hps_h2f_axi_master_wr_limiter:cmd_sink_startofpacket
+ wire router_src_endofpacket; // router:src_endofpacket -> a10_hps_h2f_axi_master_wr_limiter:cmd_sink_endofpacket
+ wire [156:0] a10_hps_h2f_axi_master_wr_limiter_cmd_src_data; // a10_hps_h2f_axi_master_wr_limiter:cmd_src_data -> cmd_demux:sink_data
+ wire a10_hps_h2f_axi_master_wr_limiter_cmd_src_ready; // cmd_demux:sink_ready -> a10_hps_h2f_axi_master_wr_limiter:cmd_src_ready
+ wire [1:0] a10_hps_h2f_axi_master_wr_limiter_cmd_src_channel; // a10_hps_h2f_axi_master_wr_limiter:cmd_src_channel -> cmd_demux:sink_channel
+ wire a10_hps_h2f_axi_master_wr_limiter_cmd_src_startofpacket; // a10_hps_h2f_axi_master_wr_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
+ wire a10_hps_h2f_axi_master_wr_limiter_cmd_src_endofpacket; // a10_hps_h2f_axi_master_wr_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
+ wire rsp_mux_src_valid; // rsp_mux:src_valid -> a10_hps_h2f_axi_master_wr_limiter:rsp_sink_valid
+ wire [156:0] rsp_mux_src_data; // rsp_mux:src_data -> a10_hps_h2f_axi_master_wr_limiter:rsp_sink_data
+ wire rsp_mux_src_ready; // a10_hps_h2f_axi_master_wr_limiter:rsp_sink_ready -> rsp_mux:src_ready
+ wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> a10_hps_h2f_axi_master_wr_limiter:rsp_sink_channel
+ wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> a10_hps_h2f_axi_master_wr_limiter:rsp_sink_startofpacket
+ wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> a10_hps_h2f_axi_master_wr_limiter:rsp_sink_endofpacket
+ wire a10_hps_h2f_axi_master_wr_limiter_rsp_src_valid; // a10_hps_h2f_axi_master_wr_limiter:rsp_src_valid -> a10_hps_h2f_axi_master_agent:write_rp_valid
+ wire [156:0] a10_hps_h2f_axi_master_wr_limiter_rsp_src_data; // a10_hps_h2f_axi_master_wr_limiter:rsp_src_data -> a10_hps_h2f_axi_master_agent:write_rp_data
+ wire a10_hps_h2f_axi_master_wr_limiter_rsp_src_ready; // a10_hps_h2f_axi_master_agent:write_rp_ready -> a10_hps_h2f_axi_master_wr_limiter:rsp_src_ready
+ wire [1:0] a10_hps_h2f_axi_master_wr_limiter_rsp_src_channel; // a10_hps_h2f_axi_master_wr_limiter:rsp_src_channel -> a10_hps_h2f_axi_master_agent:write_rp_channel
+ wire a10_hps_h2f_axi_master_wr_limiter_rsp_src_startofpacket; // a10_hps_h2f_axi_master_wr_limiter:rsp_src_startofpacket -> a10_hps_h2f_axi_master_agent:write_rp_startofpacket
+ wire a10_hps_h2f_axi_master_wr_limiter_rsp_src_endofpacket; // a10_hps_h2f_axi_master_wr_limiter:rsp_src_endofpacket -> a10_hps_h2f_axi_master_agent:write_rp_endofpacket
+ wire router_001_src_valid; // router_001:src_valid -> a10_hps_h2f_axi_master_rd_limiter:cmd_sink_valid
+ wire [156:0] router_001_src_data; // router_001:src_data -> a10_hps_h2f_axi_master_rd_limiter:cmd_sink_data
+ wire router_001_src_ready; // a10_hps_h2f_axi_master_rd_limiter:cmd_sink_ready -> router_001:src_ready
+ wire [1:0] router_001_src_channel; // router_001:src_channel -> a10_hps_h2f_axi_master_rd_limiter:cmd_sink_channel
+ wire router_001_src_startofpacket; // router_001:src_startofpacket -> a10_hps_h2f_axi_master_rd_limiter:cmd_sink_startofpacket
+ wire router_001_src_endofpacket; // router_001:src_endofpacket -> a10_hps_h2f_axi_master_rd_limiter:cmd_sink_endofpacket
+ wire [156:0] a10_hps_h2f_axi_master_rd_limiter_cmd_src_data; // a10_hps_h2f_axi_master_rd_limiter:cmd_src_data -> cmd_demux_001:sink_data
+ wire a10_hps_h2f_axi_master_rd_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> a10_hps_h2f_axi_master_rd_limiter:cmd_src_ready
+ wire [1:0] a10_hps_h2f_axi_master_rd_limiter_cmd_src_channel; // a10_hps_h2f_axi_master_rd_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
+ wire a10_hps_h2f_axi_master_rd_limiter_cmd_src_startofpacket; // a10_hps_h2f_axi_master_rd_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
+ wire a10_hps_h2f_axi_master_rd_limiter_cmd_src_endofpacket; // a10_hps_h2f_axi_master_rd_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
+ wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> a10_hps_h2f_axi_master_rd_limiter:rsp_sink_valid
+ wire [156:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> a10_hps_h2f_axi_master_rd_limiter:rsp_sink_data
+ wire rsp_mux_001_src_ready; // a10_hps_h2f_axi_master_rd_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
+ wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> a10_hps_h2f_axi_master_rd_limiter:rsp_sink_channel
+ wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> a10_hps_h2f_axi_master_rd_limiter:rsp_sink_startofpacket
+ wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> a10_hps_h2f_axi_master_rd_limiter:rsp_sink_endofpacket
+ wire a10_hps_h2f_axi_master_rd_limiter_rsp_src_valid; // a10_hps_h2f_axi_master_rd_limiter:rsp_src_valid -> a10_hps_h2f_axi_master_agent:read_rp_valid
+ wire [156:0] a10_hps_h2f_axi_master_rd_limiter_rsp_src_data; // a10_hps_h2f_axi_master_rd_limiter:rsp_src_data -> a10_hps_h2f_axi_master_agent:read_rp_data
+ wire a10_hps_h2f_axi_master_rd_limiter_rsp_src_ready; // a10_hps_h2f_axi_master_agent:read_rp_ready -> a10_hps_h2f_axi_master_rd_limiter:rsp_src_ready
+ wire [1:0] a10_hps_h2f_axi_master_rd_limiter_rsp_src_channel; // a10_hps_h2f_axi_master_rd_limiter:rsp_src_channel -> a10_hps_h2f_axi_master_agent:read_rp_channel
+ wire a10_hps_h2f_axi_master_rd_limiter_rsp_src_startofpacket; // a10_hps_h2f_axi_master_rd_limiter:rsp_src_startofpacket -> a10_hps_h2f_axi_master_agent:read_rp_startofpacket
+ wire a10_hps_h2f_axi_master_rd_limiter_rsp_src_endofpacket; // a10_hps_h2f_axi_master_rd_limiter:rsp_src_endofpacket -> a10_hps_h2f_axi_master_agent:read_rp_endofpacket
+ wire eth_tse_0_control_port_burst_adapter_source0_valid; // eth_tse_0_control_port_burst_adapter:source0_valid -> eth_tse_0_control_port_agent:cp_valid
+ wire [120:0] eth_tse_0_control_port_burst_adapter_source0_data; // eth_tse_0_control_port_burst_adapter:source0_data -> eth_tse_0_control_port_agent:cp_data
+ wire eth_tse_0_control_port_burst_adapter_source0_ready; // eth_tse_0_control_port_agent:cp_ready -> eth_tse_0_control_port_burst_adapter:source0_ready
+ wire [1:0] eth_tse_0_control_port_burst_adapter_source0_channel; // eth_tse_0_control_port_burst_adapter:source0_channel -> eth_tse_0_control_port_agent:cp_channel
+ wire eth_tse_0_control_port_burst_adapter_source0_startofpacket; // eth_tse_0_control_port_burst_adapter:source0_startofpacket -> eth_tse_0_control_port_agent:cp_startofpacket
+ wire eth_tse_0_control_port_burst_adapter_source0_endofpacket; // eth_tse_0_control_port_burst_adapter:source0_endofpacket -> eth_tse_0_control_port_agent:cp_endofpacket
+ wire eth_tse_1_control_port_burst_adapter_source0_valid; // eth_tse_1_control_port_burst_adapter:source0_valid -> eth_tse_1_control_port_agent:cp_valid
+ wire [120:0] eth_tse_1_control_port_burst_adapter_source0_data; // eth_tse_1_control_port_burst_adapter:source0_data -> eth_tse_1_control_port_agent:cp_data
+ wire eth_tse_1_control_port_burst_adapter_source0_ready; // eth_tse_1_control_port_agent:cp_ready -> eth_tse_1_control_port_burst_adapter:source0_ready
+ wire [1:0] eth_tse_1_control_port_burst_adapter_source0_channel; // eth_tse_1_control_port_burst_adapter:source0_channel -> eth_tse_1_control_port_agent:cp_channel
+ wire eth_tse_1_control_port_burst_adapter_source0_startofpacket; // eth_tse_1_control_port_burst_adapter:source0_startofpacket -> eth_tse_1_control_port_agent:cp_startofpacket
+ wire eth_tse_1_control_port_burst_adapter_source0_endofpacket; // eth_tse_1_control_port_burst_adapter:source0_endofpacket -> eth_tse_1_control_port_agent:cp_endofpacket
+ wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
+ wire [156:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
+ wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
+ wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
+ wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
+ wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
+ wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
+ wire [156:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
+ wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
+ wire [1:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
+ wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
+ wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
+ wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
+ wire [156:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
+ wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
+ wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
+ wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
+ wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
+ wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
+ wire [156:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
+ wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
+ wire [1:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
+ wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
+ wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
+ wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
+ wire [156:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
+ wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
+ wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
+ wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
+ wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
+ wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
+ wire [156:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
+ wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
+ wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
+ wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
+ wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
+ wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
+ wire [156:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
+ wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
+ wire [1:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
+ wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
+ wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
+ wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
+ wire [156:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
+ wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
+ wire [1:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
+ wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
+ wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
+ wire router_002_src_valid; // router_002:src_valid -> eth_tse_0_control_port_rsp_width_adapter:in_valid
+ wire [120:0] router_002_src_data; // router_002:src_data -> eth_tse_0_control_port_rsp_width_adapter:in_data
+ wire router_002_src_ready; // eth_tse_0_control_port_rsp_width_adapter:in_ready -> router_002:src_ready
+ wire [1:0] router_002_src_channel; // router_002:src_channel -> eth_tse_0_control_port_rsp_width_adapter:in_channel
+ wire router_002_src_startofpacket; // router_002:src_startofpacket -> eth_tse_0_control_port_rsp_width_adapter:in_startofpacket
+ wire router_002_src_endofpacket; // router_002:src_endofpacket -> eth_tse_0_control_port_rsp_width_adapter:in_endofpacket
+ wire eth_tse_0_control_port_rsp_width_adapter_src_valid; // eth_tse_0_control_port_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
+ wire [156:0] eth_tse_0_control_port_rsp_width_adapter_src_data; // eth_tse_0_control_port_rsp_width_adapter:out_data -> rsp_demux:sink_data
+ wire eth_tse_0_control_port_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> eth_tse_0_control_port_rsp_width_adapter:out_ready
+ wire [1:0] eth_tse_0_control_port_rsp_width_adapter_src_channel; // eth_tse_0_control_port_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
+ wire eth_tse_0_control_port_rsp_width_adapter_src_startofpacket; // eth_tse_0_control_port_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
+ wire eth_tse_0_control_port_rsp_width_adapter_src_endofpacket; // eth_tse_0_control_port_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
+ wire router_003_src_valid; // router_003:src_valid -> eth_tse_1_control_port_rsp_width_adapter:in_valid
+ wire [120:0] router_003_src_data; // router_003:src_data -> eth_tse_1_control_port_rsp_width_adapter:in_data
+ wire router_003_src_ready; // eth_tse_1_control_port_rsp_width_adapter:in_ready -> router_003:src_ready
+ wire [1:0] router_003_src_channel; // router_003:src_channel -> eth_tse_1_control_port_rsp_width_adapter:in_channel
+ wire router_003_src_startofpacket; // router_003:src_startofpacket -> eth_tse_1_control_port_rsp_width_adapter:in_startofpacket
+ wire router_003_src_endofpacket; // router_003:src_endofpacket -> eth_tse_1_control_port_rsp_width_adapter:in_endofpacket
+ wire eth_tse_1_control_port_rsp_width_adapter_src_valid; // eth_tse_1_control_port_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
+ wire [156:0] eth_tse_1_control_port_rsp_width_adapter_src_data; // eth_tse_1_control_port_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
+ wire eth_tse_1_control_port_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> eth_tse_1_control_port_rsp_width_adapter:out_ready
+ wire [1:0] eth_tse_1_control_port_rsp_width_adapter_src_channel; // eth_tse_1_control_port_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
+ wire eth_tse_1_control_port_rsp_width_adapter_src_startofpacket; // eth_tse_1_control_port_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
+ wire eth_tse_1_control_port_rsp_width_adapter_src_endofpacket; // eth_tse_1_control_port_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
+ wire cmd_mux_src_valid; // cmd_mux:src_valid -> eth_tse_0_control_port_cmd_width_adapter:in_valid
+ wire [156:0] cmd_mux_src_data; // cmd_mux:src_data -> eth_tse_0_control_port_cmd_width_adapter:in_data
+ wire cmd_mux_src_ready; // eth_tse_0_control_port_cmd_width_adapter:in_ready -> cmd_mux:src_ready
+ wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> eth_tse_0_control_port_cmd_width_adapter:in_channel
+ wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> eth_tse_0_control_port_cmd_width_adapter:in_startofpacket
+ wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> eth_tse_0_control_port_cmd_width_adapter:in_endofpacket
+ wire eth_tse_0_control_port_cmd_width_adapter_src_valid; // eth_tse_0_control_port_cmd_width_adapter:out_valid -> eth_tse_0_control_port_burst_adapter:sink0_valid
+ wire [120:0] eth_tse_0_control_port_cmd_width_adapter_src_data; // eth_tse_0_control_port_cmd_width_adapter:out_data -> eth_tse_0_control_port_burst_adapter:sink0_data
+ wire eth_tse_0_control_port_cmd_width_adapter_src_ready; // eth_tse_0_control_port_burst_adapter:sink0_ready -> eth_tse_0_control_port_cmd_width_adapter:out_ready
+ wire [1:0] eth_tse_0_control_port_cmd_width_adapter_src_channel; // eth_tse_0_control_port_cmd_width_adapter:out_channel -> eth_tse_0_control_port_burst_adapter:sink0_channel
+ wire eth_tse_0_control_port_cmd_width_adapter_src_startofpacket; // eth_tse_0_control_port_cmd_width_adapter:out_startofpacket -> eth_tse_0_control_port_burst_adapter:sink0_startofpacket
+ wire eth_tse_0_control_port_cmd_width_adapter_src_endofpacket; // eth_tse_0_control_port_cmd_width_adapter:out_endofpacket -> eth_tse_0_control_port_burst_adapter:sink0_endofpacket
+ wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> eth_tse_1_control_port_cmd_width_adapter:in_valid
+ wire [156:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> eth_tse_1_control_port_cmd_width_adapter:in_data
+ wire cmd_mux_001_src_ready; // eth_tse_1_control_port_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
+ wire [1:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> eth_tse_1_control_port_cmd_width_adapter:in_channel
+ wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> eth_tse_1_control_port_cmd_width_adapter:in_startofpacket
+ wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> eth_tse_1_control_port_cmd_width_adapter:in_endofpacket
+ wire eth_tse_1_control_port_cmd_width_adapter_src_valid; // eth_tse_1_control_port_cmd_width_adapter:out_valid -> eth_tse_1_control_port_burst_adapter:sink0_valid
+ wire [120:0] eth_tse_1_control_port_cmd_width_adapter_src_data; // eth_tse_1_control_port_cmd_width_adapter:out_data -> eth_tse_1_control_port_burst_adapter:sink0_data
+ wire eth_tse_1_control_port_cmd_width_adapter_src_ready; // eth_tse_1_control_port_burst_adapter:sink0_ready -> eth_tse_1_control_port_cmd_width_adapter:out_ready
+ wire [1:0] eth_tse_1_control_port_cmd_width_adapter_src_channel; // eth_tse_1_control_port_cmd_width_adapter:out_channel -> eth_tse_1_control_port_burst_adapter:sink0_channel
+ wire eth_tse_1_control_port_cmd_width_adapter_src_startofpacket; // eth_tse_1_control_port_cmd_width_adapter:out_startofpacket -> eth_tse_1_control_port_burst_adapter:sink0_startofpacket
+ wire eth_tse_1_control_port_cmd_width_adapter_src_endofpacket; // eth_tse_1_control_port_cmd_width_adapter:out_endofpacket -> eth_tse_1_control_port_burst_adapter:sink0_endofpacket
+ wire [1:0] a10_hps_h2f_axi_master_wr_limiter_cmd_valid_data; // a10_hps_h2f_axi_master_wr_limiter:cmd_src_valid -> cmd_demux:sink_valid
+ wire [1:0] a10_hps_h2f_axi_master_rd_limiter_cmd_valid_data; // a10_hps_h2f_axi_master_rd_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
+ wire eth_tse_0_control_port_agent_rdata_fifo_out_valid; // eth_tse_0_control_port_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
+ wire [33:0] eth_tse_0_control_port_agent_rdata_fifo_out_data; // eth_tse_0_control_port_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
+ wire eth_tse_0_control_port_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> eth_tse_0_control_port_agent_rdata_fifo:out_ready
+ wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> eth_tse_0_control_port_agent:rdata_fifo_sink_valid
+ wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> eth_tse_0_control_port_agent:rdata_fifo_sink_data
+ wire avalon_st_adapter_out_0_ready; // eth_tse_0_control_port_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
+ wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> eth_tse_0_control_port_agent:rdata_fifo_sink_error
+ wire eth_tse_1_control_port_agent_rdata_fifo_out_valid; // eth_tse_1_control_port_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
+ wire [33:0] eth_tse_1_control_port_agent_rdata_fifo_out_data; // eth_tse_1_control_port_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
+ wire eth_tse_1_control_port_agent_rdata_fifo_out_ready; // avalon_st_adapter_001:in_0_ready -> eth_tse_1_control_port_agent_rdata_fifo:out_ready
+ wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> eth_tse_1_control_port_agent:rdata_fifo_sink_valid
+ wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> eth_tse_1_control_port_agent:rdata_fifo_sink_data
+ wire avalon_st_adapter_001_out_0_ready; // eth_tse_1_control_port_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
+ wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> eth_tse_1_control_port_agent:rdata_fifo_sink_error
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (8),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (32),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (0),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (1),
+ .USE_UAV_CLKEN (0),
+ .USE_READRESPONSE (0),
+ .USE_WRITERESPONSE (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (1),
+ .AV_WRITE_WAIT_CYCLES (1),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) eth_tse_0_control_port_translator (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // reset.reset
+ .uav_address (eth_tse_0_control_port_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (eth_tse_0_control_port_agent_m0_burstcount), // .burstcount
+ .uav_read (eth_tse_0_control_port_agent_m0_read), // .read
+ .uav_write (eth_tse_0_control_port_agent_m0_write), // .write
+ .uav_waitrequest (eth_tse_0_control_port_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (eth_tse_0_control_port_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (eth_tse_0_control_port_agent_m0_byteenable), // .byteenable
+ .uav_readdata (eth_tse_0_control_port_agent_m0_readdata), // .readdata
+ .uav_writedata (eth_tse_0_control_port_agent_m0_writedata), // .writedata
+ .uav_lock (eth_tse_0_control_port_agent_m0_lock), // .lock
+ .uav_debugaccess (eth_tse_0_control_port_agent_m0_debugaccess), // .debugaccess
+ .av_address (eth_tse_0_control_port_address), // avalon_anti_slave_0.address
+ .av_write (eth_tse_0_control_port_write), // .write
+ .av_read (eth_tse_0_control_port_read), // .read
+ .av_readdata (eth_tse_0_control_port_readdata), // .readdata
+ .av_writedata (eth_tse_0_control_port_writedata), // .writedata
+ .av_waitrequest (eth_tse_0_control_port_waitrequest), // .waitrequest
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable (), // (terminated)
+ .uav_response (), // (terminated)
+ .av_response (2'b00), // (terminated)
+ .uav_writeresponsevalid (), // (terminated)
+ .av_writeresponsevalid (1'b0) // (terminated)
+ );
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (8),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (32),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (0),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (1),
+ .USE_UAV_CLKEN (0),
+ .USE_READRESPONSE (0),
+ .USE_WRITERESPONSE (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (1),
+ .AV_WRITE_WAIT_CYCLES (1),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) eth_tse_1_control_port_translator (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // reset.reset
+ .uav_address (eth_tse_1_control_port_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (eth_tse_1_control_port_agent_m0_burstcount), // .burstcount
+ .uav_read (eth_tse_1_control_port_agent_m0_read), // .read
+ .uav_write (eth_tse_1_control_port_agent_m0_write), // .write
+ .uav_waitrequest (eth_tse_1_control_port_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (eth_tse_1_control_port_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (eth_tse_1_control_port_agent_m0_byteenable), // .byteenable
+ .uav_readdata (eth_tse_1_control_port_agent_m0_readdata), // .readdata
+ .uav_writedata (eth_tse_1_control_port_agent_m0_writedata), // .writedata
+ .uav_lock (eth_tse_1_control_port_agent_m0_lock), // .lock
+ .uav_debugaccess (eth_tse_1_control_port_agent_m0_debugaccess), // .debugaccess
+ .av_address (eth_tse_1_control_port_address), // avalon_anti_slave_0.address
+ .av_write (eth_tse_1_control_port_write), // .write
+ .av_read (eth_tse_1_control_port_read), // .read
+ .av_readdata (eth_tse_1_control_port_readdata), // .readdata
+ .av_writedata (eth_tse_1_control_port_writedata), // .writedata
+ .av_waitrequest (eth_tse_1_control_port_waitrequest), // .waitrequest
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable (), // (terminated)
+ .uav_response (), // (terminated)
+ .av_response (2'b00), // (terminated)
+ .uav_writeresponsevalid (), // (terminated)
+ .av_writeresponsevalid (1'b0) // (terminated)
+ );
+
+ altera_merlin_axi_master_ni #(
+ .ID_WIDTH (4),
+ .ADDR_WIDTH (32),
+ .RDATA_WIDTH (64),
+ .WDATA_WIDTH (64),
+ .ADDR_USER_WIDTH (5),
+ .DATA_USER_WIDTH (1),
+ .AXI_BURST_LENGTH_WIDTH (4),
+ .AXI_LOCK_WIDTH (2),
+ .AXI_VERSION ("AXI3"),
+ .WRITE_ISSUING_CAPABILITY (8),
+ .READ_ISSUING_CAPABILITY (8),
+ .PKT_BEGIN_BURST (137),
+ .PKT_CACHE_H (151),
+ .PKT_CACHE_L (148),
+ .PKT_ADDR_SIDEBAND_H (135),
+ .PKT_ADDR_SIDEBAND_L (131),
+ .PKT_PROTECTION_H (147),
+ .PKT_PROTECTION_L (145),
+ .PKT_BURST_SIZE_H (128),
+ .PKT_BURST_SIZE_L (126),
+ .PKT_BURST_TYPE_H (130),
+ .PKT_BURST_TYPE_L (129),
+ .PKT_RESPONSE_STATUS_L (152),
+ .PKT_RESPONSE_STATUS_H (153),
+ .PKT_BURSTWRAP_H (125),
+ .PKT_BURSTWRAP_L (118),
+ .PKT_BYTE_CNT_H (117),
+ .PKT_BYTE_CNT_L (110),
+ .PKT_ADDR_H (103),
+ .PKT_ADDR_L (72),
+ .PKT_TRANS_EXCLUSIVE (109),
+ .PKT_TRANS_LOCK (108),
+ .PKT_TRANS_COMPRESSED_READ (104),
+ .PKT_TRANS_POSTED (105),
+ .PKT_TRANS_WRITE (106),
+ .PKT_TRANS_READ (107),
+ .PKT_DATA_H (63),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (71),
+ .PKT_BYTEEN_L (64),
+ .PKT_SRC_ID_H (139),
+ .PKT_SRC_ID_L (139),
+ .PKT_DEST_ID_H (140),
+ .PKT_DEST_ID_L (140),
+ .PKT_THREAD_ID_H (144),
+ .PKT_THREAD_ID_L (141),
+ .PKT_QOS_L (138),
+ .PKT_QOS_H (138),
+ .PKT_ORI_BURST_SIZE_L (154),
+ .PKT_ORI_BURST_SIZE_H (156),
+ .PKT_DATA_SIDEBAND_H (136),
+ .PKT_DATA_SIDEBAND_L (136),
+ .ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .ID (0)
+ ) a10_hps_h2f_axi_master_agent (
+ .aclk (clk_0_clk_clk), // clk.clk
+ .aresetn (~a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
+ .write_cp_valid (a10_hps_h2f_axi_master_agent_write_cp_valid), // write_cp.valid
+ .write_cp_data (a10_hps_h2f_axi_master_agent_write_cp_data), // .data
+ .write_cp_startofpacket (a10_hps_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
+ .write_cp_endofpacket (a10_hps_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
+ .write_cp_ready (a10_hps_h2f_axi_master_agent_write_cp_ready), // .ready
+ .write_rp_valid (a10_hps_h2f_axi_master_wr_limiter_rsp_src_valid), // write_rp.valid
+ .write_rp_data (a10_hps_h2f_axi_master_wr_limiter_rsp_src_data), // .data
+ .write_rp_channel (a10_hps_h2f_axi_master_wr_limiter_rsp_src_channel), // .channel
+ .write_rp_startofpacket (a10_hps_h2f_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
+ .write_rp_endofpacket (a10_hps_h2f_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
+ .write_rp_ready (a10_hps_h2f_axi_master_wr_limiter_rsp_src_ready), // .ready
+ .read_cp_valid (a10_hps_h2f_axi_master_agent_read_cp_valid), // read_cp.valid
+ .read_cp_data (a10_hps_h2f_axi_master_agent_read_cp_data), // .data
+ .read_cp_startofpacket (a10_hps_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
+ .read_cp_endofpacket (a10_hps_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
+ .read_cp_ready (a10_hps_h2f_axi_master_agent_read_cp_ready), // .ready
+ .read_rp_valid (a10_hps_h2f_axi_master_rd_limiter_rsp_src_valid), // read_rp.valid
+ .read_rp_data (a10_hps_h2f_axi_master_rd_limiter_rsp_src_data), // .data
+ .read_rp_channel (a10_hps_h2f_axi_master_rd_limiter_rsp_src_channel), // .channel
+ .read_rp_startofpacket (a10_hps_h2f_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
+ .read_rp_endofpacket (a10_hps_h2f_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
+ .read_rp_ready (a10_hps_h2f_axi_master_rd_limiter_rsp_src_ready), // .ready
+ .awid (a10_hps_h2f_axi_master_awid), // altera_axi_slave.awid
+ .awaddr (a10_hps_h2f_axi_master_awaddr), // .awaddr
+ .awlen (a10_hps_h2f_axi_master_awlen), // .awlen
+ .awsize (a10_hps_h2f_axi_master_awsize), // .awsize
+ .awburst (a10_hps_h2f_axi_master_awburst), // .awburst
+ .awlock (a10_hps_h2f_axi_master_awlock), // .awlock
+ .awcache (a10_hps_h2f_axi_master_awcache), // .awcache
+ .awprot (a10_hps_h2f_axi_master_awprot), // .awprot
+ .awuser (a10_hps_h2f_axi_master_awuser), // .awuser
+ .awvalid (a10_hps_h2f_axi_master_awvalid), // .awvalid
+ .awready (a10_hps_h2f_axi_master_awready), // .awready
+ .wid (a10_hps_h2f_axi_master_wid), // .wid
+ .wdata (a10_hps_h2f_axi_master_wdata), // .wdata
+ .wstrb (a10_hps_h2f_axi_master_wstrb), // .wstrb
+ .wlast (a10_hps_h2f_axi_master_wlast), // .wlast
+ .wvalid (a10_hps_h2f_axi_master_wvalid), // .wvalid
+ .wready (a10_hps_h2f_axi_master_wready), // .wready
+ .bid (a10_hps_h2f_axi_master_bid), // .bid
+ .bresp (a10_hps_h2f_axi_master_bresp), // .bresp
+ .bvalid (a10_hps_h2f_axi_master_bvalid), // .bvalid
+ .bready (a10_hps_h2f_axi_master_bready), // .bready
+ .arid (a10_hps_h2f_axi_master_arid), // .arid
+ .araddr (a10_hps_h2f_axi_master_araddr), // .araddr
+ .arlen (a10_hps_h2f_axi_master_arlen), // .arlen
+ .arsize (a10_hps_h2f_axi_master_arsize), // .arsize
+ .arburst (a10_hps_h2f_axi_master_arburst), // .arburst
+ .arlock (a10_hps_h2f_axi_master_arlock), // .arlock
+ .arcache (a10_hps_h2f_axi_master_arcache), // .arcache
+ .arprot (a10_hps_h2f_axi_master_arprot), // .arprot
+ .aruser (a10_hps_h2f_axi_master_aruser), // .aruser
+ .arvalid (a10_hps_h2f_axi_master_arvalid), // .arvalid
+ .arready (a10_hps_h2f_axi_master_arready), // .arready
+ .rid (a10_hps_h2f_axi_master_rid), // .rid
+ .rdata (a10_hps_h2f_axi_master_rdata), // .rdata
+ .rresp (a10_hps_h2f_axi_master_rresp), // .rresp
+ .rlast (a10_hps_h2f_axi_master_rlast), // .rlast
+ .rvalid (a10_hps_h2f_axi_master_rvalid), // .rvalid
+ .rready (a10_hps_h2f_axi_master_rready), // .rready
+ .awqos (4'b0000), // (terminated)
+ .arqos (4'b0000), // (terminated)
+ .awregion (4'b0000), // (terminated)
+ .arregion (4'b0000), // (terminated)
+ .wuser (1'b0), // (terminated)
+ .ruser (), // (terminated)
+ .buser () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_ORI_BURST_SIZE_H (120),
+ .PKT_ORI_BURST_SIZE_L (118),
+ .PKT_RESPONSE_STATUS_H (117),
+ .PKT_RESPONSE_STATUS_L (116),
+ .PKT_BURST_SIZE_H (92),
+ .PKT_BURST_SIZE_L (90),
+ .PKT_TRANS_LOCK (72),
+ .PKT_BEGIN_BURST (101),
+ .PKT_PROTECTION_H (111),
+ .PKT_PROTECTION_L (109),
+ .PKT_BURSTWRAP_H (89),
+ .PKT_BURSTWRAP_L (82),
+ .PKT_BYTE_CNT_H (81),
+ .PKT_BYTE_CNT_L (74),
+ .PKT_ADDR_H (67),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (68),
+ .PKT_TRANS_POSTED (69),
+ .PKT_TRANS_WRITE (70),
+ .PKT_TRANS_READ (71),
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_SRC_ID_H (103),
+ .PKT_SRC_ID_L (103),
+ .PKT_DEST_ID_H (104),
+ .PKT_DEST_ID_L (104),
+ .PKT_SYMBOL_W (8),
+ .ST_CHANNEL_W (2),
+ .ST_DATA_W (121),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (1),
+ .PREVENT_FIFO_OVERFLOW (1),
+ .USE_READRESPONSE (0),
+ .USE_WRITERESPONSE (0),
+ .ECC_ENABLE (0)
+ ) eth_tse_0_control_port_agent (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .m0_address (eth_tse_0_control_port_agent_m0_address), // m0.address
+ .m0_burstcount (eth_tse_0_control_port_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (eth_tse_0_control_port_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (eth_tse_0_control_port_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (eth_tse_0_control_port_agent_m0_lock), // .lock
+ .m0_readdata (eth_tse_0_control_port_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (eth_tse_0_control_port_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (eth_tse_0_control_port_agent_m0_read), // .read
+ .m0_waitrequest (eth_tse_0_control_port_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (eth_tse_0_control_port_agent_m0_writedata), // .writedata
+ .m0_write (eth_tse_0_control_port_agent_m0_write), // .write
+ .rp_endofpacket (eth_tse_0_control_port_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (eth_tse_0_control_port_agent_rp_ready), // .ready
+ .rp_valid (eth_tse_0_control_port_agent_rp_valid), // .valid
+ .rp_data (eth_tse_0_control_port_agent_rp_data), // .data
+ .rp_startofpacket (eth_tse_0_control_port_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (eth_tse_0_control_port_burst_adapter_source0_ready), // cp.ready
+ .cp_valid (eth_tse_0_control_port_burst_adapter_source0_valid), // .valid
+ .cp_data (eth_tse_0_control_port_burst_adapter_source0_data), // .data
+ .cp_startofpacket (eth_tse_0_control_port_burst_adapter_source0_startofpacket), // .startofpacket
+ .cp_endofpacket (eth_tse_0_control_port_burst_adapter_source0_endofpacket), // .endofpacket
+ .cp_channel (eth_tse_0_control_port_burst_adapter_source0_channel), // .channel
+ .rf_sink_ready (eth_tse_0_control_port_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (eth_tse_0_control_port_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (eth_tse_0_control_port_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (eth_tse_0_control_port_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (eth_tse_0_control_port_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (eth_tse_0_control_port_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (eth_tse_0_control_port_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (eth_tse_0_control_port_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
+ .rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
+ .rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
+ .rdata_fifo_src_ready (eth_tse_0_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (eth_tse_0_control_port_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (eth_tse_0_control_port_agent_rdata_fifo_src_data), // .data
+ .m0_response (2'b00), // (terminated)
+ .m0_writeresponsevalid (1'b0) // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (122),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) eth_tse_0_control_port_agent_rsp_fifo (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_data (eth_tse_0_control_port_agent_rf_source_data), // in.data
+ .in_valid (eth_tse_0_control_port_agent_rf_source_valid), // .valid
+ .in_ready (eth_tse_0_control_port_agent_rf_source_ready), // .ready
+ .in_startofpacket (eth_tse_0_control_port_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (eth_tse_0_control_port_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (eth_tse_0_control_port_agent_rsp_fifo_out_data), // out.data
+ .out_valid (eth_tse_0_control_port_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (eth_tse_0_control_port_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (34),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (0),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (0),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) eth_tse_0_control_port_agent_rdata_fifo (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_data (eth_tse_0_control_port_agent_rdata_fifo_src_data), // in.data
+ .in_valid (eth_tse_0_control_port_agent_rdata_fifo_src_valid), // .valid
+ .in_ready (eth_tse_0_control_port_agent_rdata_fifo_src_ready), // .ready
+ .out_data (eth_tse_0_control_port_agent_rdata_fifo_out_data), // out.data
+ .out_valid (eth_tse_0_control_port_agent_rdata_fifo_out_valid), // .valid
+ .out_ready (eth_tse_0_control_port_agent_rdata_fifo_out_ready), // .ready
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_startofpacket (1'b0), // (terminated)
+ .in_endofpacket (1'b0), // (terminated)
+ .out_startofpacket (), // (terminated)
+ .out_endofpacket (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_ORI_BURST_SIZE_H (120),
+ .PKT_ORI_BURST_SIZE_L (118),
+ .PKT_RESPONSE_STATUS_H (117),
+ .PKT_RESPONSE_STATUS_L (116),
+ .PKT_BURST_SIZE_H (92),
+ .PKT_BURST_SIZE_L (90),
+ .PKT_TRANS_LOCK (72),
+ .PKT_BEGIN_BURST (101),
+ .PKT_PROTECTION_H (111),
+ .PKT_PROTECTION_L (109),
+ .PKT_BURSTWRAP_H (89),
+ .PKT_BURSTWRAP_L (82),
+ .PKT_BYTE_CNT_H (81),
+ .PKT_BYTE_CNT_L (74),
+ .PKT_ADDR_H (67),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (68),
+ .PKT_TRANS_POSTED (69),
+ .PKT_TRANS_WRITE (70),
+ .PKT_TRANS_READ (71),
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_SRC_ID_H (103),
+ .PKT_SRC_ID_L (103),
+ .PKT_DEST_ID_H (104),
+ .PKT_DEST_ID_L (104),
+ .PKT_SYMBOL_W (8),
+ .ST_CHANNEL_W (2),
+ .ST_DATA_W (121),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (1),
+ .PREVENT_FIFO_OVERFLOW (1),
+ .USE_READRESPONSE (0),
+ .USE_WRITERESPONSE (0),
+ .ECC_ENABLE (0)
+ ) eth_tse_1_control_port_agent (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .m0_address (eth_tse_1_control_port_agent_m0_address), // m0.address
+ .m0_burstcount (eth_tse_1_control_port_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (eth_tse_1_control_port_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (eth_tse_1_control_port_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (eth_tse_1_control_port_agent_m0_lock), // .lock
+ .m0_readdata (eth_tse_1_control_port_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (eth_tse_1_control_port_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (eth_tse_1_control_port_agent_m0_read), // .read
+ .m0_waitrequest (eth_tse_1_control_port_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (eth_tse_1_control_port_agent_m0_writedata), // .writedata
+ .m0_write (eth_tse_1_control_port_agent_m0_write), // .write
+ .rp_endofpacket (eth_tse_1_control_port_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (eth_tse_1_control_port_agent_rp_ready), // .ready
+ .rp_valid (eth_tse_1_control_port_agent_rp_valid), // .valid
+ .rp_data (eth_tse_1_control_port_agent_rp_data), // .data
+ .rp_startofpacket (eth_tse_1_control_port_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (eth_tse_1_control_port_burst_adapter_source0_ready), // cp.ready
+ .cp_valid (eth_tse_1_control_port_burst_adapter_source0_valid), // .valid
+ .cp_data (eth_tse_1_control_port_burst_adapter_source0_data), // .data
+ .cp_startofpacket (eth_tse_1_control_port_burst_adapter_source0_startofpacket), // .startofpacket
+ .cp_endofpacket (eth_tse_1_control_port_burst_adapter_source0_endofpacket), // .endofpacket
+ .cp_channel (eth_tse_1_control_port_burst_adapter_source0_channel), // .channel
+ .rf_sink_ready (eth_tse_1_control_port_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (eth_tse_1_control_port_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (eth_tse_1_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (eth_tse_1_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (eth_tse_1_control_port_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (eth_tse_1_control_port_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (eth_tse_1_control_port_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (eth_tse_1_control_port_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (eth_tse_1_control_port_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (eth_tse_1_control_port_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
+ .rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
+ .rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
+ .rdata_fifo_src_ready (eth_tse_1_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (eth_tse_1_control_port_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (eth_tse_1_control_port_agent_rdata_fifo_src_data), // .data
+ .m0_response (2'b00), // (terminated)
+ .m0_writeresponsevalid (1'b0) // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (122),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) eth_tse_1_control_port_agent_rsp_fifo (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_data (eth_tse_1_control_port_agent_rf_source_data), // in.data
+ .in_valid (eth_tse_1_control_port_agent_rf_source_valid), // .valid
+ .in_ready (eth_tse_1_control_port_agent_rf_source_ready), // .ready
+ .in_startofpacket (eth_tse_1_control_port_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (eth_tse_1_control_port_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (eth_tse_1_control_port_agent_rsp_fifo_out_data), // out.data
+ .out_valid (eth_tse_1_control_port_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (eth_tse_1_control_port_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (eth_tse_1_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (eth_tse_1_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (34),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (0),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (0),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) eth_tse_1_control_port_agent_rdata_fifo (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_data (eth_tse_1_control_port_agent_rdata_fifo_src_data), // in.data
+ .in_valid (eth_tse_1_control_port_agent_rdata_fifo_src_valid), // .valid
+ .in_ready (eth_tse_1_control_port_agent_rdata_fifo_src_ready), // .ready
+ .out_data (eth_tse_1_control_port_agent_rdata_fifo_out_data), // out.data
+ .out_valid (eth_tse_1_control_port_agent_rdata_fifo_out_valid), // .valid
+ .out_ready (eth_tse_1_control_port_agent_rdata_fifo_out_ready), // .ready
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_startofpacket (1'b0), // (terminated)
+ .in_endofpacket (1'b0), // (terminated)
+ .out_startofpacket (), // (terminated)
+ .out_endofpacket (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ arria10_hps_altera_merlin_router_221_qdda7ra router (
+ .sink_ready (a10_hps_h2f_axi_master_agent_write_cp_ready), // sink.ready
+ .sink_valid (a10_hps_h2f_axi_master_agent_write_cp_valid), // .valid
+ .sink_data (a10_hps_h2f_axi_master_agent_write_cp_data), // .data
+ .sink_startofpacket (a10_hps_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (a10_hps_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_src_ready), // src.ready
+ .src_valid (router_src_valid), // .valid
+ .src_data (router_src_data), // .data
+ .src_channel (router_src_channel), // .channel
+ .src_startofpacket (router_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_src_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_router_221_qdda7ra router_001 (
+ .sink_ready (a10_hps_h2f_axi_master_agent_read_cp_ready), // sink.ready
+ .sink_valid (a10_hps_h2f_axi_master_agent_read_cp_valid), // .valid
+ .sink_data (a10_hps_h2f_axi_master_agent_read_cp_data), // .data
+ .sink_startofpacket (a10_hps_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (a10_hps_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_001_src_ready), // src.ready
+ .src_valid (router_001_src_valid), // .valid
+ .src_data (router_001_src_data), // .data
+ .src_channel (router_001_src_channel), // .channel
+ .src_startofpacket (router_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_001_src_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_router_221_xe243si router_002 (
+ .sink_ready (eth_tse_0_control_port_agent_rp_ready), // sink.ready
+ .sink_valid (eth_tse_0_control_port_agent_rp_valid), // .valid
+ .sink_data (eth_tse_0_control_port_agent_rp_data), // .data
+ .sink_startofpacket (eth_tse_0_control_port_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (eth_tse_0_control_port_agent_rp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_002_src_ready), // src.ready
+ .src_valid (router_002_src_valid), // .valid
+ .src_data (router_002_src_data), // .data
+ .src_channel (router_002_src_channel), // .channel
+ .src_startofpacket (router_002_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_002_src_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_router_221_xe243si router_003 (
+ .sink_ready (eth_tse_1_control_port_agent_rp_ready), // sink.ready
+ .sink_valid (eth_tse_1_control_port_agent_rp_valid), // .valid
+ .sink_data (eth_tse_1_control_port_agent_rp_data), // .data
+ .sink_startofpacket (eth_tse_1_control_port_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (eth_tse_1_control_port_agent_rp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_003_src_ready), // src.ready
+ .src_valid (router_003_src_valid), // .valid
+ .src_data (router_003_src_data), // .data
+ .src_channel (router_003_src_channel), // .channel
+ .src_startofpacket (router_003_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_003_src_endofpacket) // .endofpacket
+ );
+
+ altera_merlin_traffic_limiter #(
+ .PKT_DEST_ID_H (140),
+ .PKT_DEST_ID_L (140),
+ .PKT_SRC_ID_H (139),
+ .PKT_SRC_ID_L (139),
+ .PKT_BYTE_CNT_H (117),
+ .PKT_BYTE_CNT_L (110),
+ .PKT_BYTEEN_H (71),
+ .PKT_BYTEEN_L (64),
+ .PKT_TRANS_POSTED (105),
+ .PKT_TRANS_WRITE (106),
+ .MAX_OUTSTANDING_RESPONSES (3),
+ .PIPELINED (0),
+ .ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .VALID_WIDTH (2),
+ .ENFORCE_ORDER (1),
+ .PREVENT_HAZARDS (0),
+ .SUPPORTS_POSTED_WRITES (1),
+ .SUPPORTS_NONPOSTED_WRITES (0),
+ .REORDER (0)
+ ) a10_hps_h2f_axi_master_wr_limiter (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .cmd_sink_ready (router_src_ready), // cmd_sink.ready
+ .cmd_sink_valid (router_src_valid), // .valid
+ .cmd_sink_data (router_src_data), // .data
+ .cmd_sink_channel (router_src_channel), // .channel
+ .cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
+ .cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
+ .cmd_src_ready (a10_hps_h2f_axi_master_wr_limiter_cmd_src_ready), // cmd_src.ready
+ .cmd_src_data (a10_hps_h2f_axi_master_wr_limiter_cmd_src_data), // .data
+ .cmd_src_channel (a10_hps_h2f_axi_master_wr_limiter_cmd_src_channel), // .channel
+ .cmd_src_startofpacket (a10_hps_h2f_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
+ .cmd_src_endofpacket (a10_hps_h2f_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
+ .rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
+ .rsp_sink_valid (rsp_mux_src_valid), // .valid
+ .rsp_sink_channel (rsp_mux_src_channel), // .channel
+ .rsp_sink_data (rsp_mux_src_data), // .data
+ .rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
+ .rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
+ .rsp_src_ready (a10_hps_h2f_axi_master_wr_limiter_rsp_src_ready), // rsp_src.ready
+ .rsp_src_valid (a10_hps_h2f_axi_master_wr_limiter_rsp_src_valid), // .valid
+ .rsp_src_data (a10_hps_h2f_axi_master_wr_limiter_rsp_src_data), // .data
+ .rsp_src_channel (a10_hps_h2f_axi_master_wr_limiter_rsp_src_channel), // .channel
+ .rsp_src_startofpacket (a10_hps_h2f_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
+ .rsp_src_endofpacket (a10_hps_h2f_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
+ .cmd_src_valid (a10_hps_h2f_axi_master_wr_limiter_cmd_valid_data) // cmd_valid.data
+ );
+
+ altera_merlin_traffic_limiter #(
+ .PKT_DEST_ID_H (140),
+ .PKT_DEST_ID_L (140),
+ .PKT_SRC_ID_H (139),
+ .PKT_SRC_ID_L (139),
+ .PKT_BYTE_CNT_H (117),
+ .PKT_BYTE_CNT_L (110),
+ .PKT_BYTEEN_H (71),
+ .PKT_BYTEEN_L (64),
+ .PKT_TRANS_POSTED (105),
+ .PKT_TRANS_WRITE (106),
+ .MAX_OUTSTANDING_RESPONSES (3),
+ .PIPELINED (0),
+ .ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .VALID_WIDTH (2),
+ .ENFORCE_ORDER (1),
+ .PREVENT_HAZARDS (0),
+ .SUPPORTS_POSTED_WRITES (1),
+ .SUPPORTS_NONPOSTED_WRITES (0),
+ .REORDER (0)
+ ) a10_hps_h2f_axi_master_rd_limiter (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
+ .cmd_sink_valid (router_001_src_valid), // .valid
+ .cmd_sink_data (router_001_src_data), // .data
+ .cmd_sink_channel (router_001_src_channel), // .channel
+ .cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
+ .cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
+ .cmd_src_ready (a10_hps_h2f_axi_master_rd_limiter_cmd_src_ready), // cmd_src.ready
+ .cmd_src_data (a10_hps_h2f_axi_master_rd_limiter_cmd_src_data), // .data
+ .cmd_src_channel (a10_hps_h2f_axi_master_rd_limiter_cmd_src_channel), // .channel
+ .cmd_src_startofpacket (a10_hps_h2f_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
+ .cmd_src_endofpacket (a10_hps_h2f_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
+ .rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
+ .rsp_sink_valid (rsp_mux_001_src_valid), // .valid
+ .rsp_sink_channel (rsp_mux_001_src_channel), // .channel
+ .rsp_sink_data (rsp_mux_001_src_data), // .data
+ .rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
+ .rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
+ .rsp_src_ready (a10_hps_h2f_axi_master_rd_limiter_rsp_src_ready), // rsp_src.ready
+ .rsp_src_valid (a10_hps_h2f_axi_master_rd_limiter_rsp_src_valid), // .valid
+ .rsp_src_data (a10_hps_h2f_axi_master_rd_limiter_rsp_src_data), // .data
+ .rsp_src_channel (a10_hps_h2f_axi_master_rd_limiter_rsp_src_channel), // .channel
+ .rsp_src_startofpacket (a10_hps_h2f_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
+ .rsp_src_endofpacket (a10_hps_h2f_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
+ .cmd_src_valid (a10_hps_h2f_axi_master_rd_limiter_cmd_valid_data) // cmd_valid.data
+ );
+
+ altera_merlin_burst_adapter #(
+ .PKT_ADDR_H (67),
+ .PKT_ADDR_L (36),
+ .PKT_BEGIN_BURST (101),
+ .PKT_BYTE_CNT_H (81),
+ .PKT_BYTE_CNT_L (74),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_BURST_SIZE_H (92),
+ .PKT_BURST_SIZE_L (90),
+ .PKT_BURST_TYPE_H (94),
+ .PKT_BURST_TYPE_L (93),
+ .PKT_BURSTWRAP_H (89),
+ .PKT_BURSTWRAP_L (82),
+ .PKT_TRANS_COMPRESSED_READ (68),
+ .PKT_TRANS_WRITE (70),
+ .PKT_TRANS_READ (71),
+ .OUT_NARROW_SIZE (0),
+ .IN_NARROW_SIZE (1),
+ .OUT_FIXED (0),
+ .OUT_COMPLETE_WRAP (0),
+ .ST_DATA_W (121),
+ .ST_CHANNEL_W (2),
+ .OUT_BYTE_CNT_H (76),
+ .OUT_BURSTWRAP_H (89),
+ .COMPRESSED_READ_SUPPORT (1),
+ .BYTEENABLE_SYNTHESIS (1),
+ .PIPE_INPUTS (0),
+ .NO_WRAP_SUPPORT (0),
+ .INCOMPLETE_WRAP_SUPPORT (0),
+ .BURSTWRAP_CONST_MASK (0),
+ .BURSTWRAP_CONST_VALUE (0),
+ .ADAPTER_VERSION ("13.1")
+ ) eth_tse_0_control_port_burst_adapter (
+ .clk (clk_0_clk_clk), // cr0.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // cr0_reset.reset
+ .sink0_valid (eth_tse_0_control_port_cmd_width_adapter_src_valid), // sink0.valid
+ .sink0_data (eth_tse_0_control_port_cmd_width_adapter_src_data), // .data
+ .sink0_channel (eth_tse_0_control_port_cmd_width_adapter_src_channel), // .channel
+ .sink0_startofpacket (eth_tse_0_control_port_cmd_width_adapter_src_startofpacket), // .startofpacket
+ .sink0_endofpacket (eth_tse_0_control_port_cmd_width_adapter_src_endofpacket), // .endofpacket
+ .sink0_ready (eth_tse_0_control_port_cmd_width_adapter_src_ready), // .ready
+ .source0_valid (eth_tse_0_control_port_burst_adapter_source0_valid), // source0.valid
+ .source0_data (eth_tse_0_control_port_burst_adapter_source0_data), // .data
+ .source0_channel (eth_tse_0_control_port_burst_adapter_source0_channel), // .channel
+ .source0_startofpacket (eth_tse_0_control_port_burst_adapter_source0_startofpacket), // .startofpacket
+ .source0_endofpacket (eth_tse_0_control_port_burst_adapter_source0_endofpacket), // .endofpacket
+ .source0_ready (eth_tse_0_control_port_burst_adapter_source0_ready) // .ready
+ );
+
+ altera_merlin_burst_adapter #(
+ .PKT_ADDR_H (67),
+ .PKT_ADDR_L (36),
+ .PKT_BEGIN_BURST (101),
+ .PKT_BYTE_CNT_H (81),
+ .PKT_BYTE_CNT_L (74),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_BURST_SIZE_H (92),
+ .PKT_BURST_SIZE_L (90),
+ .PKT_BURST_TYPE_H (94),
+ .PKT_BURST_TYPE_L (93),
+ .PKT_BURSTWRAP_H (89),
+ .PKT_BURSTWRAP_L (82),
+ .PKT_TRANS_COMPRESSED_READ (68),
+ .PKT_TRANS_WRITE (70),
+ .PKT_TRANS_READ (71),
+ .OUT_NARROW_SIZE (0),
+ .IN_NARROW_SIZE (1),
+ .OUT_FIXED (0),
+ .OUT_COMPLETE_WRAP (0),
+ .ST_DATA_W (121),
+ .ST_CHANNEL_W (2),
+ .OUT_BYTE_CNT_H (76),
+ .OUT_BURSTWRAP_H (89),
+ .COMPRESSED_READ_SUPPORT (1),
+ .BYTEENABLE_SYNTHESIS (1),
+ .PIPE_INPUTS (0),
+ .NO_WRAP_SUPPORT (0),
+ .INCOMPLETE_WRAP_SUPPORT (0),
+ .BURSTWRAP_CONST_MASK (0),
+ .BURSTWRAP_CONST_VALUE (0),
+ .ADAPTER_VERSION ("13.1")
+ ) eth_tse_1_control_port_burst_adapter (
+ .clk (clk_0_clk_clk), // cr0.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // cr0_reset.reset
+ .sink0_valid (eth_tse_1_control_port_cmd_width_adapter_src_valid), // sink0.valid
+ .sink0_data (eth_tse_1_control_port_cmd_width_adapter_src_data), // .data
+ .sink0_channel (eth_tse_1_control_port_cmd_width_adapter_src_channel), // .channel
+ .sink0_startofpacket (eth_tse_1_control_port_cmd_width_adapter_src_startofpacket), // .startofpacket
+ .sink0_endofpacket (eth_tse_1_control_port_cmd_width_adapter_src_endofpacket), // .endofpacket
+ .sink0_ready (eth_tse_1_control_port_cmd_width_adapter_src_ready), // .ready
+ .source0_valid (eth_tse_1_control_port_burst_adapter_source0_valid), // source0.valid
+ .source0_data (eth_tse_1_control_port_burst_adapter_source0_data), // .data
+ .source0_channel (eth_tse_1_control_port_burst_adapter_source0_channel), // .channel
+ .source0_startofpacket (eth_tse_1_control_port_burst_adapter_source0_startofpacket), // .startofpacket
+ .source0_endofpacket (eth_tse_1_control_port_burst_adapter_source0_endofpacket), // .endofpacket
+ .source0_ready (eth_tse_1_control_port_burst_adapter_source0_ready) // .ready
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_d6tse3y cmd_demux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (a10_hps_h2f_axi_master_wr_limiter_cmd_src_ready), // sink.ready
+ .sink_channel (a10_hps_h2f_axi_master_wr_limiter_cmd_src_channel), // .channel
+ .sink_data (a10_hps_h2f_axi_master_wr_limiter_cmd_src_data), // .data
+ .sink_startofpacket (a10_hps_h2f_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
+ .sink_endofpacket (a10_hps_h2f_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
+ .sink_valid (a10_hps_h2f_axi_master_wr_limiter_cmd_valid_data), // sink_valid.data
+ .src0_ready (cmd_demux_src0_ready), // src0.ready
+ .src0_valid (cmd_demux_src0_valid), // .valid
+ .src0_data (cmd_demux_src0_data), // .data
+ .src0_channel (cmd_demux_src0_channel), // .channel
+ .src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
+ .src1_ready (cmd_demux_src1_ready), // src1.ready
+ .src1_valid (cmd_demux_src1_valid), // .valid
+ .src1_data (cmd_demux_src1_data), // .data
+ .src1_channel (cmd_demux_src1_channel), // .channel
+ .src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
+ .src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_d6tse3y cmd_demux_001 (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (a10_hps_h2f_axi_master_rd_limiter_cmd_src_ready), // sink.ready
+ .sink_channel (a10_hps_h2f_axi_master_rd_limiter_cmd_src_channel), // .channel
+ .sink_data (a10_hps_h2f_axi_master_rd_limiter_cmd_src_data), // .data
+ .sink_startofpacket (a10_hps_h2f_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
+ .sink_endofpacket (a10_hps_h2f_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
+ .sink_valid (a10_hps_h2f_axi_master_rd_limiter_cmd_valid_data), // sink_valid.data
+ .src0_ready (cmd_demux_001_src0_ready), // src0.ready
+ .src0_valid (cmd_demux_001_src0_valid), // .valid
+ .src0_data (cmd_demux_001_src0_data), // .data
+ .src0_channel (cmd_demux_001_src0_channel), // .channel
+ .src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
+ .src1_ready (cmd_demux_001_src1_ready), // src1.ready
+ .src1_valid (cmd_demux_001_src1_valid), // .valid
+ .src1_data (cmd_demux_001_src1_data), // .data
+ .src1_channel (cmd_demux_001_src1_channel), // .channel
+ .src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
+ .src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_vzucqyy cmd_mux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (cmd_mux_src_ready), // src.ready
+ .src_valid (cmd_mux_src_valid), // .valid
+ .src_data (cmd_mux_src_data), // .data
+ .src_channel (cmd_mux_src_channel), // .channel
+ .src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
+ .src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
+ .sink0_ready (cmd_demux_src0_ready), // sink0.ready
+ .sink0_valid (cmd_demux_src0_valid), // .valid
+ .sink0_channel (cmd_demux_src0_channel), // .channel
+ .sink0_data (cmd_demux_src0_data), // .data
+ .sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
+ .sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
+ .sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
+ .sink1_valid (cmd_demux_001_src0_valid), // .valid
+ .sink1_channel (cmd_demux_001_src0_channel), // .channel
+ .sink1_data (cmd_demux_001_src0_data), // .data
+ .sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
+ .sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_vzucqyy cmd_mux_001 (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (cmd_mux_001_src_ready), // src.ready
+ .src_valid (cmd_mux_001_src_valid), // .valid
+ .src_data (cmd_mux_001_src_data), // .data
+ .src_channel (cmd_mux_001_src_channel), // .channel
+ .src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
+ .sink0_ready (cmd_demux_src1_ready), // sink0.ready
+ .sink0_valid (cmd_demux_src1_valid), // .valid
+ .sink0_channel (cmd_demux_src1_channel), // .channel
+ .sink0_data (cmd_demux_src1_data), // .data
+ .sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
+ .sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
+ .sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
+ .sink1_valid (cmd_demux_001_src1_valid), // .valid
+ .sink1_channel (cmd_demux_001_src1_channel), // .channel
+ .sink1_data (cmd_demux_001_src1_data), // .data
+ .sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
+ .sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_e3m23ka rsp_demux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (eth_tse_0_control_port_rsp_width_adapter_src_ready), // sink.ready
+ .sink_channel (eth_tse_0_control_port_rsp_width_adapter_src_channel), // .channel
+ .sink_data (eth_tse_0_control_port_rsp_width_adapter_src_data), // .data
+ .sink_startofpacket (eth_tse_0_control_port_rsp_width_adapter_src_startofpacket), // .startofpacket
+ .sink_endofpacket (eth_tse_0_control_port_rsp_width_adapter_src_endofpacket), // .endofpacket
+ .sink_valid (eth_tse_0_control_port_rsp_width_adapter_src_valid), // .valid
+ .src0_ready (rsp_demux_src0_ready), // src0.ready
+ .src0_valid (rsp_demux_src0_valid), // .valid
+ .src0_data (rsp_demux_src0_data), // .data
+ .src0_channel (rsp_demux_src0_channel), // .channel
+ .src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
+ .src1_ready (rsp_demux_src1_ready), // src1.ready
+ .src1_valid (rsp_demux_src1_valid), // .valid
+ .src1_data (rsp_demux_src1_data), // .data
+ .src1_channel (rsp_demux_src1_channel), // .channel
+ .src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
+ .src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_e3m23ka rsp_demux_001 (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (eth_tse_1_control_port_rsp_width_adapter_src_ready), // sink.ready
+ .sink_channel (eth_tse_1_control_port_rsp_width_adapter_src_channel), // .channel
+ .sink_data (eth_tse_1_control_port_rsp_width_adapter_src_data), // .data
+ .sink_startofpacket (eth_tse_1_control_port_rsp_width_adapter_src_startofpacket), // .startofpacket
+ .sink_endofpacket (eth_tse_1_control_port_rsp_width_adapter_src_endofpacket), // .endofpacket
+ .sink_valid (eth_tse_1_control_port_rsp_width_adapter_src_valid), // .valid
+ .src0_ready (rsp_demux_001_src0_ready), // src0.ready
+ .src0_valid (rsp_demux_001_src0_valid), // .valid
+ .src0_data (rsp_demux_001_src0_data), // .data
+ .src0_channel (rsp_demux_001_src0_channel), // .channel
+ .src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
+ .src1_ready (rsp_demux_001_src1_ready), // src1.ready
+ .src1_valid (rsp_demux_001_src1_valid), // .valid
+ .src1_data (rsp_demux_001_src1_data), // .data
+ .src1_channel (rsp_demux_001_src1_channel), // .channel
+ .src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
+ .src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_h6k2nza rsp_mux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (rsp_mux_src_ready), // src.ready
+ .src_valid (rsp_mux_src_valid), // .valid
+ .src_data (rsp_mux_src_data), // .data
+ .src_channel (rsp_mux_src_channel), // .channel
+ .src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
+ .sink0_ready (rsp_demux_src0_ready), // sink0.ready
+ .sink0_valid (rsp_demux_src0_valid), // .valid
+ .sink0_channel (rsp_demux_src0_channel), // .channel
+ .sink0_data (rsp_demux_src0_data), // .data
+ .sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
+ .sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
+ .sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
+ .sink1_valid (rsp_demux_001_src0_valid), // .valid
+ .sink1_channel (rsp_demux_001_src0_channel), // .channel
+ .sink1_data (rsp_demux_001_src0_data), // .data
+ .sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
+ .sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_h6k2nza rsp_mux_001 (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (rsp_mux_001_src_ready), // src.ready
+ .src_valid (rsp_mux_001_src_valid), // .valid
+ .src_data (rsp_mux_001_src_data), // .data
+ .src_channel (rsp_mux_001_src_channel), // .channel
+ .src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
+ .sink0_ready (rsp_demux_src1_ready), // sink0.ready
+ .sink0_valid (rsp_demux_src1_valid), // .valid
+ .sink0_channel (rsp_demux_src1_channel), // .channel
+ .sink0_data (rsp_demux_src1_data), // .data
+ .sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
+ .sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
+ .sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
+ .sink1_valid (rsp_demux_001_src1_valid), // .valid
+ .sink1_channel (rsp_demux_001_src1_channel), // .channel
+ .sink1_data (rsp_demux_001_src1_data), // .data
+ .sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
+ .sink1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
+ );
+
+ altera_merlin_width_adapter #(
+ .IN_PKT_ADDR_H (67),
+ .IN_PKT_ADDR_L (36),
+ .IN_PKT_DATA_H (31),
+ .IN_PKT_DATA_L (0),
+ .IN_PKT_BYTEEN_H (35),
+ .IN_PKT_BYTEEN_L (32),
+ .IN_PKT_BYTE_CNT_H (81),
+ .IN_PKT_BYTE_CNT_L (74),
+ .IN_PKT_TRANS_COMPRESSED_READ (68),
+ .IN_PKT_TRANS_WRITE (70),
+ .IN_PKT_BURSTWRAP_H (89),
+ .IN_PKT_BURSTWRAP_L (82),
+ .IN_PKT_BURST_SIZE_H (92),
+ .IN_PKT_BURST_SIZE_L (90),
+ .IN_PKT_RESPONSE_STATUS_H (117),
+ .IN_PKT_RESPONSE_STATUS_L (116),
+ .IN_PKT_TRANS_EXCLUSIVE (73),
+ .IN_PKT_BURST_TYPE_H (94),
+ .IN_PKT_BURST_TYPE_L (93),
+ .IN_PKT_ORI_BURST_SIZE_L (118),
+ .IN_PKT_ORI_BURST_SIZE_H (120),
+ .IN_ST_DATA_W (121),
+ .OUT_PKT_ADDR_H (103),
+ .OUT_PKT_ADDR_L (72),
+ .OUT_PKT_DATA_H (63),
+ .OUT_PKT_DATA_L (0),
+ .OUT_PKT_BYTEEN_H (71),
+ .OUT_PKT_BYTEEN_L (64),
+ .OUT_PKT_BYTE_CNT_H (117),
+ .OUT_PKT_BYTE_CNT_L (110),
+ .OUT_PKT_TRANS_COMPRESSED_READ (104),
+ .OUT_PKT_BURST_SIZE_H (128),
+ .OUT_PKT_BURST_SIZE_L (126),
+ .OUT_PKT_RESPONSE_STATUS_H (153),
+ .OUT_PKT_RESPONSE_STATUS_L (152),
+ .OUT_PKT_TRANS_EXCLUSIVE (109),
+ .OUT_PKT_BURST_TYPE_H (130),
+ .OUT_PKT_BURST_TYPE_L (129),
+ .OUT_PKT_ORI_BURST_SIZE_L (154),
+ .OUT_PKT_ORI_BURST_SIZE_H (156),
+ .OUT_ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .OPTIMIZE_FOR_RSP (0),
+ .RESPONSE_PATH (1),
+ .CONSTANT_BURST_SIZE (0),
+ .PACKING (1),
+ .ENABLE_ADDRESS_ALIGNMENT (1)
+ ) eth_tse_0_control_port_rsp_width_adapter (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_valid (router_002_src_valid), // sink.valid
+ .in_channel (router_002_src_channel), // .channel
+ .in_startofpacket (router_002_src_startofpacket), // .startofpacket
+ .in_endofpacket (router_002_src_endofpacket), // .endofpacket
+ .in_ready (router_002_src_ready), // .ready
+ .in_data (router_002_src_data), // .data
+ .out_endofpacket (eth_tse_0_control_port_rsp_width_adapter_src_endofpacket), // src.endofpacket
+ .out_data (eth_tse_0_control_port_rsp_width_adapter_src_data), // .data
+ .out_channel (eth_tse_0_control_port_rsp_width_adapter_src_channel), // .channel
+ .out_valid (eth_tse_0_control_port_rsp_width_adapter_src_valid), // .valid
+ .out_ready (eth_tse_0_control_port_rsp_width_adapter_src_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_rsp_width_adapter_src_startofpacket), // .startofpacket
+ .in_command_size_data (3'b000) // (terminated)
+ );
+
+ altera_merlin_width_adapter #(
+ .IN_PKT_ADDR_H (67),
+ .IN_PKT_ADDR_L (36),
+ .IN_PKT_DATA_H (31),
+ .IN_PKT_DATA_L (0),
+ .IN_PKT_BYTEEN_H (35),
+ .IN_PKT_BYTEEN_L (32),
+ .IN_PKT_BYTE_CNT_H (81),
+ .IN_PKT_BYTE_CNT_L (74),
+ .IN_PKT_TRANS_COMPRESSED_READ (68),
+ .IN_PKT_TRANS_WRITE (70),
+ .IN_PKT_BURSTWRAP_H (89),
+ .IN_PKT_BURSTWRAP_L (82),
+ .IN_PKT_BURST_SIZE_H (92),
+ .IN_PKT_BURST_SIZE_L (90),
+ .IN_PKT_RESPONSE_STATUS_H (117),
+ .IN_PKT_RESPONSE_STATUS_L (116),
+ .IN_PKT_TRANS_EXCLUSIVE (73),
+ .IN_PKT_BURST_TYPE_H (94),
+ .IN_PKT_BURST_TYPE_L (93),
+ .IN_PKT_ORI_BURST_SIZE_L (118),
+ .IN_PKT_ORI_BURST_SIZE_H (120),
+ .IN_ST_DATA_W (121),
+ .OUT_PKT_ADDR_H (103),
+ .OUT_PKT_ADDR_L (72),
+ .OUT_PKT_DATA_H (63),
+ .OUT_PKT_DATA_L (0),
+ .OUT_PKT_BYTEEN_H (71),
+ .OUT_PKT_BYTEEN_L (64),
+ .OUT_PKT_BYTE_CNT_H (117),
+ .OUT_PKT_BYTE_CNT_L (110),
+ .OUT_PKT_TRANS_COMPRESSED_READ (104),
+ .OUT_PKT_BURST_SIZE_H (128),
+ .OUT_PKT_BURST_SIZE_L (126),
+ .OUT_PKT_RESPONSE_STATUS_H (153),
+ .OUT_PKT_RESPONSE_STATUS_L (152),
+ .OUT_PKT_TRANS_EXCLUSIVE (109),
+ .OUT_PKT_BURST_TYPE_H (130),
+ .OUT_PKT_BURST_TYPE_L (129),
+ .OUT_PKT_ORI_BURST_SIZE_L (154),
+ .OUT_PKT_ORI_BURST_SIZE_H (156),
+ .OUT_ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .OPTIMIZE_FOR_RSP (0),
+ .RESPONSE_PATH (1),
+ .CONSTANT_BURST_SIZE (0),
+ .PACKING (1),
+ .ENABLE_ADDRESS_ALIGNMENT (1)
+ ) eth_tse_1_control_port_rsp_width_adapter (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_valid (router_003_src_valid), // sink.valid
+ .in_channel (router_003_src_channel), // .channel
+ .in_startofpacket (router_003_src_startofpacket), // .startofpacket
+ .in_endofpacket (router_003_src_endofpacket), // .endofpacket
+ .in_ready (router_003_src_ready), // .ready
+ .in_data (router_003_src_data), // .data
+ .out_endofpacket (eth_tse_1_control_port_rsp_width_adapter_src_endofpacket), // src.endofpacket
+ .out_data (eth_tse_1_control_port_rsp_width_adapter_src_data), // .data
+ .out_channel (eth_tse_1_control_port_rsp_width_adapter_src_channel), // .channel
+ .out_valid (eth_tse_1_control_port_rsp_width_adapter_src_valid), // .valid
+ .out_ready (eth_tse_1_control_port_rsp_width_adapter_src_ready), // .ready
+ .out_startofpacket (eth_tse_1_control_port_rsp_width_adapter_src_startofpacket), // .startofpacket
+ .in_command_size_data (3'b000) // (terminated)
+ );
+
+ altera_merlin_width_adapter #(
+ .IN_PKT_ADDR_H (103),
+ .IN_PKT_ADDR_L (72),
+ .IN_PKT_DATA_H (63),
+ .IN_PKT_DATA_L (0),
+ .IN_PKT_BYTEEN_H (71),
+ .IN_PKT_BYTEEN_L (64),
+ .IN_PKT_BYTE_CNT_H (117),
+ .IN_PKT_BYTE_CNT_L (110),
+ .IN_PKT_TRANS_COMPRESSED_READ (104),
+ .IN_PKT_TRANS_WRITE (106),
+ .IN_PKT_BURSTWRAP_H (125),
+ .IN_PKT_BURSTWRAP_L (118),
+ .IN_PKT_BURST_SIZE_H (128),
+ .IN_PKT_BURST_SIZE_L (126),
+ .IN_PKT_RESPONSE_STATUS_H (153),
+ .IN_PKT_RESPONSE_STATUS_L (152),
+ .IN_PKT_TRANS_EXCLUSIVE (109),
+ .IN_PKT_BURST_TYPE_H (130),
+ .IN_PKT_BURST_TYPE_L (129),
+ .IN_PKT_ORI_BURST_SIZE_L (154),
+ .IN_PKT_ORI_BURST_SIZE_H (156),
+ .IN_ST_DATA_W (157),
+ .OUT_PKT_ADDR_H (67),
+ .OUT_PKT_ADDR_L (36),
+ .OUT_PKT_DATA_H (31),
+ .OUT_PKT_DATA_L (0),
+ .OUT_PKT_BYTEEN_H (35),
+ .OUT_PKT_BYTEEN_L (32),
+ .OUT_PKT_BYTE_CNT_H (81),
+ .OUT_PKT_BYTE_CNT_L (74),
+ .OUT_PKT_TRANS_COMPRESSED_READ (68),
+ .OUT_PKT_BURST_SIZE_H (92),
+ .OUT_PKT_BURST_SIZE_L (90),
+ .OUT_PKT_RESPONSE_STATUS_H (117),
+ .OUT_PKT_RESPONSE_STATUS_L (116),
+ .OUT_PKT_TRANS_EXCLUSIVE (73),
+ .OUT_PKT_BURST_TYPE_H (94),
+ .OUT_PKT_BURST_TYPE_L (93),
+ .OUT_PKT_ORI_BURST_SIZE_L (118),
+ .OUT_PKT_ORI_BURST_SIZE_H (120),
+ .OUT_ST_DATA_W (121),
+ .ST_CHANNEL_W (2),
+ .OPTIMIZE_FOR_RSP (0),
+ .RESPONSE_PATH (0),
+ .CONSTANT_BURST_SIZE (0),
+ .PACKING (0),
+ .ENABLE_ADDRESS_ALIGNMENT (1)
+ ) eth_tse_0_control_port_cmd_width_adapter (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_valid (cmd_mux_src_valid), // sink.valid
+ .in_channel (cmd_mux_src_channel), // .channel
+ .in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
+ .in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
+ .in_ready (cmd_mux_src_ready), // .ready
+ .in_data (cmd_mux_src_data), // .data
+ .out_endofpacket (eth_tse_0_control_port_cmd_width_adapter_src_endofpacket), // src.endofpacket
+ .out_data (eth_tse_0_control_port_cmd_width_adapter_src_data), // .data
+ .out_channel (eth_tse_0_control_port_cmd_width_adapter_src_channel), // .channel
+ .out_valid (eth_tse_0_control_port_cmd_width_adapter_src_valid), // .valid
+ .out_ready (eth_tse_0_control_port_cmd_width_adapter_src_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_cmd_width_adapter_src_startofpacket), // .startofpacket
+ .in_command_size_data (3'b000) // (terminated)
+ );
+
+ altera_merlin_width_adapter #(
+ .IN_PKT_ADDR_H (103),
+ .IN_PKT_ADDR_L (72),
+ .IN_PKT_DATA_H (63),
+ .IN_PKT_DATA_L (0),
+ .IN_PKT_BYTEEN_H (71),
+ .IN_PKT_BYTEEN_L (64),
+ .IN_PKT_BYTE_CNT_H (117),
+ .IN_PKT_BYTE_CNT_L (110),
+ .IN_PKT_TRANS_COMPRESSED_READ (104),
+ .IN_PKT_TRANS_WRITE (106),
+ .IN_PKT_BURSTWRAP_H (125),
+ .IN_PKT_BURSTWRAP_L (118),
+ .IN_PKT_BURST_SIZE_H (128),
+ .IN_PKT_BURST_SIZE_L (126),
+ .IN_PKT_RESPONSE_STATUS_H (153),
+ .IN_PKT_RESPONSE_STATUS_L (152),
+ .IN_PKT_TRANS_EXCLUSIVE (109),
+ .IN_PKT_BURST_TYPE_H (130),
+ .IN_PKT_BURST_TYPE_L (129),
+ .IN_PKT_ORI_BURST_SIZE_L (154),
+ .IN_PKT_ORI_BURST_SIZE_H (156),
+ .IN_ST_DATA_W (157),
+ .OUT_PKT_ADDR_H (67),
+ .OUT_PKT_ADDR_L (36),
+ .OUT_PKT_DATA_H (31),
+ .OUT_PKT_DATA_L (0),
+ .OUT_PKT_BYTEEN_H (35),
+ .OUT_PKT_BYTEEN_L (32),
+ .OUT_PKT_BYTE_CNT_H (81),
+ .OUT_PKT_BYTE_CNT_L (74),
+ .OUT_PKT_TRANS_COMPRESSED_READ (68),
+ .OUT_PKT_BURST_SIZE_H (92),
+ .OUT_PKT_BURST_SIZE_L (90),
+ .OUT_PKT_RESPONSE_STATUS_H (117),
+ .OUT_PKT_RESPONSE_STATUS_L (116),
+ .OUT_PKT_TRANS_EXCLUSIVE (73),
+ .OUT_PKT_BURST_TYPE_H (94),
+ .OUT_PKT_BURST_TYPE_L (93),
+ .OUT_PKT_ORI_BURST_SIZE_L (118),
+ .OUT_PKT_ORI_BURST_SIZE_H (120),
+ .OUT_ST_DATA_W (121),
+ .ST_CHANNEL_W (2),
+ .OPTIMIZE_FOR_RSP (0),
+ .RESPONSE_PATH (0),
+ .CONSTANT_BURST_SIZE (0),
+ .PACKING (0),
+ .ENABLE_ADDRESS_ALIGNMENT (1)
+ ) eth_tse_1_control_port_cmd_width_adapter (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_valid (cmd_mux_001_src_valid), // sink.valid
+ .in_channel (cmd_mux_001_src_channel), // .channel
+ .in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
+ .in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
+ .in_ready (cmd_mux_001_src_ready), // .ready
+ .in_data (cmd_mux_001_src_data), // .data
+ .out_endofpacket (eth_tse_1_control_port_cmd_width_adapter_src_endofpacket), // src.endofpacket
+ .out_data (eth_tse_1_control_port_cmd_width_adapter_src_data), // .data
+ .out_channel (eth_tse_1_control_port_cmd_width_adapter_src_channel), // .channel
+ .out_valid (eth_tse_1_control_port_cmd_width_adapter_src_valid), // .valid
+ .out_ready (eth_tse_1_control_port_cmd_width_adapter_src_ready), // .ready
+ .out_startofpacket (eth_tse_1_control_port_cmd_width_adapter_src_startofpacket), // .startofpacket
+ .in_command_size_data (3'b000) // (terminated)
+ );
+
+ arria10_hps_altera_avalon_st_adapter_221_36tuu3a #(
+ .inBitsPerSymbol (34),
+ .inUsePackets (0),
+ .inDataWidth (34),
+ .inChannelWidth (0),
+ .inErrorWidth (0),
+ .inUseEmptyPort (0),
+ .inUseValid (1),
+ .inUseReady (1),
+ .inReadyLatency (0),
+ .outDataWidth (34),
+ .outChannelWidth (0),
+ .outErrorWidth (1),
+ .outUseEmptyPort (0),
+ .outUseValid (1),
+ .outUseReady (1),
+ .outReadyLatency (0)
+ ) avalon_st_adapter (
+ .in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
+ .in_rst_0_reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // in_rst_0.reset
+ .in_0_data (eth_tse_0_control_port_agent_rdata_fifo_out_data), // in_0.data
+ .in_0_valid (eth_tse_0_control_port_agent_rdata_fifo_out_valid), // .valid
+ .in_0_ready (eth_tse_0_control_port_agent_rdata_fifo_out_ready), // .ready
+ .out_0_data (avalon_st_adapter_out_0_data), // out_0.data
+ .out_0_valid (avalon_st_adapter_out_0_valid), // .valid
+ .out_0_ready (avalon_st_adapter_out_0_ready), // .ready
+ .out_0_error (avalon_st_adapter_out_0_error) // .error
+ );
+
+ arria10_hps_altera_avalon_st_adapter_221_36tuu3a #(
+ .inBitsPerSymbol (34),
+ .inUsePackets (0),
+ .inDataWidth (34),
+ .inChannelWidth (0),
+ .inErrorWidth (0),
+ .inUseEmptyPort (0),
+ .inUseValid (1),
+ .inUseReady (1),
+ .inReadyLatency (0),
+ .outDataWidth (34),
+ .outChannelWidth (0),
+ .outErrorWidth (1),
+ .outUseEmptyPort (0),
+ .outUseValid (1),
+ .outUseReady (1),
+ .outReadyLatency (0)
+ ) avalon_st_adapter_001 (
+ .in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
+ .in_rst_0_reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // in_rst_0.reset
+ .in_0_data (eth_tse_1_control_port_agent_rdata_fifo_out_data), // in_0.data
+ .in_0_valid (eth_tse_1_control_port_agent_rdata_fifo_out_valid), // .valid
+ .in_0_ready (eth_tse_1_control_port_agent_rdata_fifo_out_ready), // .ready
+ .out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
+ .out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
+ .out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
+ .out_0_error (avalon_st_adapter_001_out_0_error) // .error
+ );
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_jwt2njy_cfg.v b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_jwt2njy_cfg.v
new file mode 100644
index 0000000000000000000000000000000000000000..7af125c16e6ca4bf1df3e426e0cea36060975f82
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_jwt2njy_cfg.v
@@ -0,0 +1,35 @@
+config arria10_hps_altera_mm_interconnect_221_jwt2njy_cfg;
+ design arria10_hps_altera_mm_interconnect_221_jwt2njy;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_0_control_port_translator use arria10_hps_altera_merlin_slave_translator_221.altera_merlin_slave_translator;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_1_control_port_translator use arria10_hps_altera_merlin_slave_translator_221.altera_merlin_slave_translator;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.a10_hps_h2f_axi_master_agent use arria10_hps_altera_merlin_axi_master_ni_221.altera_merlin_axi_master_ni;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_0_control_port_agent use arria10_hps_altera_merlin_slave_agent_221.altera_merlin_slave_agent;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_0_control_port_agent_rsp_fifo use arria10_hps_altera_avalon_sc_fifo_221.altera_avalon_sc_fifo;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_0_control_port_agent_rdata_fifo use arria10_hps_altera_avalon_sc_fifo_221.altera_avalon_sc_fifo;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_1_control_port_agent use arria10_hps_altera_merlin_slave_agent_221.altera_merlin_slave_agent;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_1_control_port_agent_rsp_fifo use arria10_hps_altera_avalon_sc_fifo_221.altera_avalon_sc_fifo;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_1_control_port_agent_rdata_fifo use arria10_hps_altera_avalon_sc_fifo_221.altera_avalon_sc_fifo;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.router use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_qdda7ra;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.router_001 use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_qdda7ra;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.router_002 use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_xe243si;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.router_003 use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_xe243si;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.a10_hps_h2f_axi_master_wr_limiter use arria10_hps_altera_merlin_traffic_limiter_221.altera_merlin_traffic_limiter;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.a10_hps_h2f_axi_master_rd_limiter use arria10_hps_altera_merlin_traffic_limiter_221.altera_merlin_traffic_limiter;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_0_control_port_burst_adapter use arria10_hps_altera_merlin_burst_adapter_221.altera_merlin_burst_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_1_control_port_burst_adapter use arria10_hps_altera_merlin_burst_adapter_221.altera_merlin_burst_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.cmd_demux use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_d6tse3y;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.cmd_demux_001 use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_d6tse3y;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.cmd_mux use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_vzucqyy;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.cmd_mux_001 use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_vzucqyy;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.rsp_demux use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_e3m23ka;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.rsp_demux_001 use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_e3m23ka;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.rsp_mux use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_h6k2nza;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.rsp_mux_001 use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_h6k2nza;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_0_control_port_rsp_width_adapter use arria10_hps_altera_merlin_width_adapter_221.altera_merlin_width_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_1_control_port_rsp_width_adapter use arria10_hps_altera_merlin_width_adapter_221.altera_merlin_width_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_0_control_port_cmd_width_adapter use arria10_hps_altera_merlin_width_adapter_221.altera_merlin_width_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.eth_tse_1_control_port_cmd_width_adapter use arria10_hps_altera_merlin_width_adapter_221.altera_merlin_width_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.avalon_st_adapter use arria10_hps_altera_avalon_st_adapter_221.arria10_hps_altera_avalon_st_adapter_221_36tuu3a;
+ instance arria10_hps_altera_mm_interconnect_221_jwt2njy.avalon_st_adapter_001 use arria10_hps_altera_avalon_st_adapter_221.arria10_hps_altera_avalon_st_adapter_221_36tuu3a;
+endconfig
+
diff --git a/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_qogprma.v b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_qogprma.v
new file mode 100644
index 0000000000000000000000000000000000000000..456dca1bec240cdf9aa526b83f7815fa4f85e1e9
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_qogprma.v
@@ -0,0 +1,915 @@
+// arria10_hps_altera_mm_interconnect_221_qogprma.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
+// will probably be lost.
+//
+// Generated using ACDS version 22.1 922
+
+`timescale 1 ps / 1 ps
+module arria10_hps_altera_mm_interconnect_221_qogprma (
+ input wire [3:0] a10_hps_h2f_axi_master_awid, // a10_hps_h2f_axi_master.awid
+ input wire [31:0] a10_hps_h2f_axi_master_awaddr, // .awaddr
+ input wire [3:0] a10_hps_h2f_axi_master_awlen, // .awlen
+ input wire [2:0] a10_hps_h2f_axi_master_awsize, // .awsize
+ input wire [1:0] a10_hps_h2f_axi_master_awburst, // .awburst
+ input wire [1:0] a10_hps_h2f_axi_master_awlock, // .awlock
+ input wire [3:0] a10_hps_h2f_axi_master_awcache, // .awcache
+ input wire [2:0] a10_hps_h2f_axi_master_awprot, // .awprot
+ input wire [4:0] a10_hps_h2f_axi_master_awuser, // .awuser
+ input wire a10_hps_h2f_axi_master_awvalid, // .awvalid
+ output wire a10_hps_h2f_axi_master_awready, // .awready
+ input wire [3:0] a10_hps_h2f_axi_master_wid, // .wid
+ input wire [63:0] a10_hps_h2f_axi_master_wdata, // .wdata
+ input wire [7:0] a10_hps_h2f_axi_master_wstrb, // .wstrb
+ input wire a10_hps_h2f_axi_master_wlast, // .wlast
+ input wire a10_hps_h2f_axi_master_wvalid, // .wvalid
+ output wire a10_hps_h2f_axi_master_wready, // .wready
+ output wire [3:0] a10_hps_h2f_axi_master_bid, // .bid
+ output wire [1:0] a10_hps_h2f_axi_master_bresp, // .bresp
+ output wire a10_hps_h2f_axi_master_bvalid, // .bvalid
+ input wire a10_hps_h2f_axi_master_bready, // .bready
+ input wire [3:0] a10_hps_h2f_axi_master_arid, // .arid
+ input wire [31:0] a10_hps_h2f_axi_master_araddr, // .araddr
+ input wire [3:0] a10_hps_h2f_axi_master_arlen, // .arlen
+ input wire [2:0] a10_hps_h2f_axi_master_arsize, // .arsize
+ input wire [1:0] a10_hps_h2f_axi_master_arburst, // .arburst
+ input wire [1:0] a10_hps_h2f_axi_master_arlock, // .arlock
+ input wire [3:0] a10_hps_h2f_axi_master_arcache, // .arcache
+ input wire [2:0] a10_hps_h2f_axi_master_arprot, // .arprot
+ input wire [4:0] a10_hps_h2f_axi_master_aruser, // .aruser
+ input wire a10_hps_h2f_axi_master_arvalid, // .arvalid
+ output wire a10_hps_h2f_axi_master_arready, // .arready
+ output wire [3:0] a10_hps_h2f_axi_master_rid, // .rid
+ output wire [63:0] a10_hps_h2f_axi_master_rdata, // .rdata
+ output wire [1:0] a10_hps_h2f_axi_master_rresp, // .rresp
+ output wire a10_hps_h2f_axi_master_rlast, // .rlast
+ output wire a10_hps_h2f_axi_master_rvalid, // .rvalid
+ input wire a10_hps_h2f_axi_master_rready, // .rready
+ input wire clk_0_clk_clk, // clk_0_clk.clk
+ input wire a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset, // a10_hps_h2f_axi_reset_reset_bridge_in_reset.reset
+ input wire eth_tse_0_reset_connection_reset_bridge_in_reset_reset, // eth_tse_0_reset_connection_reset_bridge_in_reset.reset
+ output wire [7:0] eth_tse_0_control_port_address, // eth_tse_0_control_port.address
+ output wire eth_tse_0_control_port_write, // .write
+ output wire eth_tse_0_control_port_read, // .read
+ input wire [31:0] eth_tse_0_control_port_readdata, // .readdata
+ output wire [31:0] eth_tse_0_control_port_writedata, // .writedata
+ input wire eth_tse_0_control_port_waitrequest // .waitrequest
+ );
+
+ wire rsp_mux_src_valid; // rsp_mux:src_valid -> a10_hps_h2f_axi_master_agent:write_rp_valid
+ wire [156:0] rsp_mux_src_data; // rsp_mux:src_data -> a10_hps_h2f_axi_master_agent:write_rp_data
+ wire rsp_mux_src_ready; // a10_hps_h2f_axi_master_agent:write_rp_ready -> rsp_mux:src_ready
+ wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> a10_hps_h2f_axi_master_agent:write_rp_channel
+ wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> a10_hps_h2f_axi_master_agent:write_rp_startofpacket
+ wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> a10_hps_h2f_axi_master_agent:write_rp_endofpacket
+ wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> a10_hps_h2f_axi_master_agent:read_rp_valid
+ wire [156:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> a10_hps_h2f_axi_master_agent:read_rp_data
+ wire rsp_mux_001_src_ready; // a10_hps_h2f_axi_master_agent:read_rp_ready -> rsp_mux_001:src_ready
+ wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> a10_hps_h2f_axi_master_agent:read_rp_channel
+ wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> a10_hps_h2f_axi_master_agent:read_rp_startofpacket
+ wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> a10_hps_h2f_axi_master_agent:read_rp_endofpacket
+ wire [31:0] eth_tse_0_control_port_agent_m0_readdata; // eth_tse_0_control_port_translator:uav_readdata -> eth_tse_0_control_port_agent:m0_readdata
+ wire eth_tse_0_control_port_agent_m0_waitrequest; // eth_tse_0_control_port_translator:uav_waitrequest -> eth_tse_0_control_port_agent:m0_waitrequest
+ wire eth_tse_0_control_port_agent_m0_debugaccess; // eth_tse_0_control_port_agent:m0_debugaccess -> eth_tse_0_control_port_translator:uav_debugaccess
+ wire [31:0] eth_tse_0_control_port_agent_m0_address; // eth_tse_0_control_port_agent:m0_address -> eth_tse_0_control_port_translator:uav_address
+ wire [3:0] eth_tse_0_control_port_agent_m0_byteenable; // eth_tse_0_control_port_agent:m0_byteenable -> eth_tse_0_control_port_translator:uav_byteenable
+ wire eth_tse_0_control_port_agent_m0_read; // eth_tse_0_control_port_agent:m0_read -> eth_tse_0_control_port_translator:uav_read
+ wire eth_tse_0_control_port_agent_m0_readdatavalid; // eth_tse_0_control_port_translator:uav_readdatavalid -> eth_tse_0_control_port_agent:m0_readdatavalid
+ wire eth_tse_0_control_port_agent_m0_lock; // eth_tse_0_control_port_agent:m0_lock -> eth_tse_0_control_port_translator:uav_lock
+ wire [31:0] eth_tse_0_control_port_agent_m0_writedata; // eth_tse_0_control_port_agent:m0_writedata -> eth_tse_0_control_port_translator:uav_writedata
+ wire eth_tse_0_control_port_agent_m0_write; // eth_tse_0_control_port_agent:m0_write -> eth_tse_0_control_port_translator:uav_write
+ wire [2:0] eth_tse_0_control_port_agent_m0_burstcount; // eth_tse_0_control_port_agent:m0_burstcount -> eth_tse_0_control_port_translator:uav_burstcount
+ wire eth_tse_0_control_port_agent_rf_source_valid; // eth_tse_0_control_port_agent:rf_source_valid -> eth_tse_0_control_port_agent_rsp_fifo:in_valid
+ wire [121:0] eth_tse_0_control_port_agent_rf_source_data; // eth_tse_0_control_port_agent:rf_source_data -> eth_tse_0_control_port_agent_rsp_fifo:in_data
+ wire eth_tse_0_control_port_agent_rf_source_ready; // eth_tse_0_control_port_agent_rsp_fifo:in_ready -> eth_tse_0_control_port_agent:rf_source_ready
+ wire eth_tse_0_control_port_agent_rf_source_startofpacket; // eth_tse_0_control_port_agent:rf_source_startofpacket -> eth_tse_0_control_port_agent_rsp_fifo:in_startofpacket
+ wire eth_tse_0_control_port_agent_rf_source_endofpacket; // eth_tse_0_control_port_agent:rf_source_endofpacket -> eth_tse_0_control_port_agent_rsp_fifo:in_endofpacket
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_valid; // eth_tse_0_control_port_agent_rsp_fifo:out_valid -> eth_tse_0_control_port_agent:rf_sink_valid
+ wire [121:0] eth_tse_0_control_port_agent_rsp_fifo_out_data; // eth_tse_0_control_port_agent_rsp_fifo:out_data -> eth_tse_0_control_port_agent:rf_sink_data
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_ready; // eth_tse_0_control_port_agent:rf_sink_ready -> eth_tse_0_control_port_agent_rsp_fifo:out_ready
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket; // eth_tse_0_control_port_agent_rsp_fifo:out_startofpacket -> eth_tse_0_control_port_agent:rf_sink_startofpacket
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket; // eth_tse_0_control_port_agent_rsp_fifo:out_endofpacket -> eth_tse_0_control_port_agent:rf_sink_endofpacket
+ wire eth_tse_0_control_port_agent_rdata_fifo_src_valid; // eth_tse_0_control_port_agent:rdata_fifo_src_valid -> eth_tse_0_control_port_agent_rdata_fifo:in_valid
+ wire [33:0] eth_tse_0_control_port_agent_rdata_fifo_src_data; // eth_tse_0_control_port_agent:rdata_fifo_src_data -> eth_tse_0_control_port_agent_rdata_fifo:in_data
+ wire eth_tse_0_control_port_agent_rdata_fifo_src_ready; // eth_tse_0_control_port_agent_rdata_fifo:in_ready -> eth_tse_0_control_port_agent:rdata_fifo_src_ready
+ wire a10_hps_h2f_axi_master_agent_write_cp_valid; // a10_hps_h2f_axi_master_agent:write_cp_valid -> router:sink_valid
+ wire [156:0] a10_hps_h2f_axi_master_agent_write_cp_data; // a10_hps_h2f_axi_master_agent:write_cp_data -> router:sink_data
+ wire a10_hps_h2f_axi_master_agent_write_cp_ready; // router:sink_ready -> a10_hps_h2f_axi_master_agent:write_cp_ready
+ wire a10_hps_h2f_axi_master_agent_write_cp_startofpacket; // a10_hps_h2f_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
+ wire a10_hps_h2f_axi_master_agent_write_cp_endofpacket; // a10_hps_h2f_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
+ wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
+ wire [156:0] router_src_data; // router:src_data -> cmd_demux:sink_data
+ wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
+ wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
+ wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
+ wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
+ wire a10_hps_h2f_axi_master_agent_read_cp_valid; // a10_hps_h2f_axi_master_agent:read_cp_valid -> router_001:sink_valid
+ wire [156:0] a10_hps_h2f_axi_master_agent_read_cp_data; // a10_hps_h2f_axi_master_agent:read_cp_data -> router_001:sink_data
+ wire a10_hps_h2f_axi_master_agent_read_cp_ready; // router_001:sink_ready -> a10_hps_h2f_axi_master_agent:read_cp_ready
+ wire a10_hps_h2f_axi_master_agent_read_cp_startofpacket; // a10_hps_h2f_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
+ wire a10_hps_h2f_axi_master_agent_read_cp_endofpacket; // a10_hps_h2f_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
+ wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
+ wire [156:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
+ wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
+ wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
+ wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
+ wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
+ wire eth_tse_0_control_port_agent_rp_valid; // eth_tse_0_control_port_agent:rp_valid -> router_002:sink_valid
+ wire [120:0] eth_tse_0_control_port_agent_rp_data; // eth_tse_0_control_port_agent:rp_data -> router_002:sink_data
+ wire eth_tse_0_control_port_agent_rp_ready; // router_002:sink_ready -> eth_tse_0_control_port_agent:rp_ready
+ wire eth_tse_0_control_port_agent_rp_startofpacket; // eth_tse_0_control_port_agent:rp_startofpacket -> router_002:sink_startofpacket
+ wire eth_tse_0_control_port_agent_rp_endofpacket; // eth_tse_0_control_port_agent:rp_endofpacket -> router_002:sink_endofpacket
+ wire eth_tse_0_control_port_burst_adapter_source0_valid; // eth_tse_0_control_port_burst_adapter:source0_valid -> eth_tse_0_control_port_agent:cp_valid
+ wire [120:0] eth_tse_0_control_port_burst_adapter_source0_data; // eth_tse_0_control_port_burst_adapter:source0_data -> eth_tse_0_control_port_agent:cp_data
+ wire eth_tse_0_control_port_burst_adapter_source0_ready; // eth_tse_0_control_port_agent:cp_ready -> eth_tse_0_control_port_burst_adapter:source0_ready
+ wire [1:0] eth_tse_0_control_port_burst_adapter_source0_channel; // eth_tse_0_control_port_burst_adapter:source0_channel -> eth_tse_0_control_port_agent:cp_channel
+ wire eth_tse_0_control_port_burst_adapter_source0_startofpacket; // eth_tse_0_control_port_burst_adapter:source0_startofpacket -> eth_tse_0_control_port_agent:cp_startofpacket
+ wire eth_tse_0_control_port_burst_adapter_source0_endofpacket; // eth_tse_0_control_port_burst_adapter:source0_endofpacket -> eth_tse_0_control_port_agent:cp_endofpacket
+ wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
+ wire [156:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
+ wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
+ wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
+ wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
+ wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
+ wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
+ wire [156:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
+ wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
+ wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
+ wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
+ wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
+ wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
+ wire [156:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
+ wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
+ wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
+ wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
+ wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
+ wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
+ wire [156:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
+ wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
+ wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
+ wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
+ wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
+ wire router_002_src_valid; // router_002:src_valid -> eth_tse_0_control_port_rsp_width_adapter:in_valid
+ wire [120:0] router_002_src_data; // router_002:src_data -> eth_tse_0_control_port_rsp_width_adapter:in_data
+ wire router_002_src_ready; // eth_tse_0_control_port_rsp_width_adapter:in_ready -> router_002:src_ready
+ wire [1:0] router_002_src_channel; // router_002:src_channel -> eth_tse_0_control_port_rsp_width_adapter:in_channel
+ wire router_002_src_startofpacket; // router_002:src_startofpacket -> eth_tse_0_control_port_rsp_width_adapter:in_startofpacket
+ wire router_002_src_endofpacket; // router_002:src_endofpacket -> eth_tse_0_control_port_rsp_width_adapter:in_endofpacket
+ wire eth_tse_0_control_port_rsp_width_adapter_src_valid; // eth_tse_0_control_port_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
+ wire [156:0] eth_tse_0_control_port_rsp_width_adapter_src_data; // eth_tse_0_control_port_rsp_width_adapter:out_data -> rsp_demux:sink_data
+ wire eth_tse_0_control_port_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> eth_tse_0_control_port_rsp_width_adapter:out_ready
+ wire [1:0] eth_tse_0_control_port_rsp_width_adapter_src_channel; // eth_tse_0_control_port_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
+ wire eth_tse_0_control_port_rsp_width_adapter_src_startofpacket; // eth_tse_0_control_port_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
+ wire eth_tse_0_control_port_rsp_width_adapter_src_endofpacket; // eth_tse_0_control_port_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
+ wire cmd_mux_src_valid; // cmd_mux:src_valid -> eth_tse_0_control_port_cmd_width_adapter:in_valid
+ wire [156:0] cmd_mux_src_data; // cmd_mux:src_data -> eth_tse_0_control_port_cmd_width_adapter:in_data
+ wire cmd_mux_src_ready; // eth_tse_0_control_port_cmd_width_adapter:in_ready -> cmd_mux:src_ready
+ wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> eth_tse_0_control_port_cmd_width_adapter:in_channel
+ wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> eth_tse_0_control_port_cmd_width_adapter:in_startofpacket
+ wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> eth_tse_0_control_port_cmd_width_adapter:in_endofpacket
+ wire eth_tse_0_control_port_cmd_width_adapter_src_valid; // eth_tse_0_control_port_cmd_width_adapter:out_valid -> eth_tse_0_control_port_burst_adapter:sink0_valid
+ wire [120:0] eth_tse_0_control_port_cmd_width_adapter_src_data; // eth_tse_0_control_port_cmd_width_adapter:out_data -> eth_tse_0_control_port_burst_adapter:sink0_data
+ wire eth_tse_0_control_port_cmd_width_adapter_src_ready; // eth_tse_0_control_port_burst_adapter:sink0_ready -> eth_tse_0_control_port_cmd_width_adapter:out_ready
+ wire [1:0] eth_tse_0_control_port_cmd_width_adapter_src_channel; // eth_tse_0_control_port_cmd_width_adapter:out_channel -> eth_tse_0_control_port_burst_adapter:sink0_channel
+ wire eth_tse_0_control_port_cmd_width_adapter_src_startofpacket; // eth_tse_0_control_port_cmd_width_adapter:out_startofpacket -> eth_tse_0_control_port_burst_adapter:sink0_startofpacket
+ wire eth_tse_0_control_port_cmd_width_adapter_src_endofpacket; // eth_tse_0_control_port_cmd_width_adapter:out_endofpacket -> eth_tse_0_control_port_burst_adapter:sink0_endofpacket
+ wire eth_tse_0_control_port_agent_rdata_fifo_out_valid; // eth_tse_0_control_port_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
+ wire [33:0] eth_tse_0_control_port_agent_rdata_fifo_out_data; // eth_tse_0_control_port_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
+ wire eth_tse_0_control_port_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> eth_tse_0_control_port_agent_rdata_fifo:out_ready
+ wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> eth_tse_0_control_port_agent:rdata_fifo_sink_valid
+ wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> eth_tse_0_control_port_agent:rdata_fifo_sink_data
+ wire avalon_st_adapter_out_0_ready; // eth_tse_0_control_port_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
+ wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> eth_tse_0_control_port_agent:rdata_fifo_sink_error
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (8),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (32),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (0),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (1),
+ .USE_UAV_CLKEN (0),
+ .USE_READRESPONSE (0),
+ .USE_WRITERESPONSE (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (1),
+ .AV_WRITE_WAIT_CYCLES (1),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) eth_tse_0_control_port_translator (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // reset.reset
+ .uav_address (eth_tse_0_control_port_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (eth_tse_0_control_port_agent_m0_burstcount), // .burstcount
+ .uav_read (eth_tse_0_control_port_agent_m0_read), // .read
+ .uav_write (eth_tse_0_control_port_agent_m0_write), // .write
+ .uav_waitrequest (eth_tse_0_control_port_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (eth_tse_0_control_port_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (eth_tse_0_control_port_agent_m0_byteenable), // .byteenable
+ .uav_readdata (eth_tse_0_control_port_agent_m0_readdata), // .readdata
+ .uav_writedata (eth_tse_0_control_port_agent_m0_writedata), // .writedata
+ .uav_lock (eth_tse_0_control_port_agent_m0_lock), // .lock
+ .uav_debugaccess (eth_tse_0_control_port_agent_m0_debugaccess), // .debugaccess
+ .av_address (eth_tse_0_control_port_address), // avalon_anti_slave_0.address
+ .av_write (eth_tse_0_control_port_write), // .write
+ .av_read (eth_tse_0_control_port_read), // .read
+ .av_readdata (eth_tse_0_control_port_readdata), // .readdata
+ .av_writedata (eth_tse_0_control_port_writedata), // .writedata
+ .av_waitrequest (eth_tse_0_control_port_waitrequest), // .waitrequest
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable (), // (terminated)
+ .uav_response (), // (terminated)
+ .av_response (2'b00), // (terminated)
+ .uav_writeresponsevalid (), // (terminated)
+ .av_writeresponsevalid (1'b0) // (terminated)
+ );
+
+ altera_merlin_axi_master_ni #(
+ .ID_WIDTH (4),
+ .ADDR_WIDTH (32),
+ .RDATA_WIDTH (64),
+ .WDATA_WIDTH (64),
+ .ADDR_USER_WIDTH (5),
+ .DATA_USER_WIDTH (1),
+ .AXI_BURST_LENGTH_WIDTH (4),
+ .AXI_LOCK_WIDTH (2),
+ .AXI_VERSION ("AXI3"),
+ .WRITE_ISSUING_CAPABILITY (8),
+ .READ_ISSUING_CAPABILITY (8),
+ .PKT_BEGIN_BURST (137),
+ .PKT_CACHE_H (151),
+ .PKT_CACHE_L (148),
+ .PKT_ADDR_SIDEBAND_H (135),
+ .PKT_ADDR_SIDEBAND_L (131),
+ .PKT_PROTECTION_H (147),
+ .PKT_PROTECTION_L (145),
+ .PKT_BURST_SIZE_H (128),
+ .PKT_BURST_SIZE_L (126),
+ .PKT_BURST_TYPE_H (130),
+ .PKT_BURST_TYPE_L (129),
+ .PKT_RESPONSE_STATUS_L (152),
+ .PKT_RESPONSE_STATUS_H (153),
+ .PKT_BURSTWRAP_H (125),
+ .PKT_BURSTWRAP_L (118),
+ .PKT_BYTE_CNT_H (117),
+ .PKT_BYTE_CNT_L (110),
+ .PKT_ADDR_H (103),
+ .PKT_ADDR_L (72),
+ .PKT_TRANS_EXCLUSIVE (109),
+ .PKT_TRANS_LOCK (108),
+ .PKT_TRANS_COMPRESSED_READ (104),
+ .PKT_TRANS_POSTED (105),
+ .PKT_TRANS_WRITE (106),
+ .PKT_TRANS_READ (107),
+ .PKT_DATA_H (63),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (71),
+ .PKT_BYTEEN_L (64),
+ .PKT_SRC_ID_H (139),
+ .PKT_SRC_ID_L (139),
+ .PKT_DEST_ID_H (140),
+ .PKT_DEST_ID_L (140),
+ .PKT_THREAD_ID_H (144),
+ .PKT_THREAD_ID_L (141),
+ .PKT_QOS_L (138),
+ .PKT_QOS_H (138),
+ .PKT_ORI_BURST_SIZE_L (154),
+ .PKT_ORI_BURST_SIZE_H (156),
+ .PKT_DATA_SIDEBAND_H (136),
+ .PKT_DATA_SIDEBAND_L (136),
+ .ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .ID (0)
+ ) a10_hps_h2f_axi_master_agent (
+ .aclk (clk_0_clk_clk), // clk.clk
+ .aresetn (~a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
+ .write_cp_valid (a10_hps_h2f_axi_master_agent_write_cp_valid), // write_cp.valid
+ .write_cp_data (a10_hps_h2f_axi_master_agent_write_cp_data), // .data
+ .write_cp_startofpacket (a10_hps_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
+ .write_cp_endofpacket (a10_hps_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
+ .write_cp_ready (a10_hps_h2f_axi_master_agent_write_cp_ready), // .ready
+ .write_rp_valid (rsp_mux_src_valid), // write_rp.valid
+ .write_rp_data (rsp_mux_src_data), // .data
+ .write_rp_channel (rsp_mux_src_channel), // .channel
+ .write_rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
+ .write_rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
+ .write_rp_ready (rsp_mux_src_ready), // .ready
+ .read_cp_valid (a10_hps_h2f_axi_master_agent_read_cp_valid), // read_cp.valid
+ .read_cp_data (a10_hps_h2f_axi_master_agent_read_cp_data), // .data
+ .read_cp_startofpacket (a10_hps_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
+ .read_cp_endofpacket (a10_hps_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
+ .read_cp_ready (a10_hps_h2f_axi_master_agent_read_cp_ready), // .ready
+ .read_rp_valid (rsp_mux_001_src_valid), // read_rp.valid
+ .read_rp_data (rsp_mux_001_src_data), // .data
+ .read_rp_channel (rsp_mux_001_src_channel), // .channel
+ .read_rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
+ .read_rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
+ .read_rp_ready (rsp_mux_001_src_ready), // .ready
+ .awid (a10_hps_h2f_axi_master_awid), // altera_axi_slave.awid
+ .awaddr (a10_hps_h2f_axi_master_awaddr), // .awaddr
+ .awlen (a10_hps_h2f_axi_master_awlen), // .awlen
+ .awsize (a10_hps_h2f_axi_master_awsize), // .awsize
+ .awburst (a10_hps_h2f_axi_master_awburst), // .awburst
+ .awlock (a10_hps_h2f_axi_master_awlock), // .awlock
+ .awcache (a10_hps_h2f_axi_master_awcache), // .awcache
+ .awprot (a10_hps_h2f_axi_master_awprot), // .awprot
+ .awuser (a10_hps_h2f_axi_master_awuser), // .awuser
+ .awvalid (a10_hps_h2f_axi_master_awvalid), // .awvalid
+ .awready (a10_hps_h2f_axi_master_awready), // .awready
+ .wid (a10_hps_h2f_axi_master_wid), // .wid
+ .wdata (a10_hps_h2f_axi_master_wdata), // .wdata
+ .wstrb (a10_hps_h2f_axi_master_wstrb), // .wstrb
+ .wlast (a10_hps_h2f_axi_master_wlast), // .wlast
+ .wvalid (a10_hps_h2f_axi_master_wvalid), // .wvalid
+ .wready (a10_hps_h2f_axi_master_wready), // .wready
+ .bid (a10_hps_h2f_axi_master_bid), // .bid
+ .bresp (a10_hps_h2f_axi_master_bresp), // .bresp
+ .bvalid (a10_hps_h2f_axi_master_bvalid), // .bvalid
+ .bready (a10_hps_h2f_axi_master_bready), // .bready
+ .arid (a10_hps_h2f_axi_master_arid), // .arid
+ .araddr (a10_hps_h2f_axi_master_araddr), // .araddr
+ .arlen (a10_hps_h2f_axi_master_arlen), // .arlen
+ .arsize (a10_hps_h2f_axi_master_arsize), // .arsize
+ .arburst (a10_hps_h2f_axi_master_arburst), // .arburst
+ .arlock (a10_hps_h2f_axi_master_arlock), // .arlock
+ .arcache (a10_hps_h2f_axi_master_arcache), // .arcache
+ .arprot (a10_hps_h2f_axi_master_arprot), // .arprot
+ .aruser (a10_hps_h2f_axi_master_aruser), // .aruser
+ .arvalid (a10_hps_h2f_axi_master_arvalid), // .arvalid
+ .arready (a10_hps_h2f_axi_master_arready), // .arready
+ .rid (a10_hps_h2f_axi_master_rid), // .rid
+ .rdata (a10_hps_h2f_axi_master_rdata), // .rdata
+ .rresp (a10_hps_h2f_axi_master_rresp), // .rresp
+ .rlast (a10_hps_h2f_axi_master_rlast), // .rlast
+ .rvalid (a10_hps_h2f_axi_master_rvalid), // .rvalid
+ .rready (a10_hps_h2f_axi_master_rready), // .rready
+ .awqos (4'b0000), // (terminated)
+ .arqos (4'b0000), // (terminated)
+ .awregion (4'b0000), // (terminated)
+ .arregion (4'b0000), // (terminated)
+ .wuser (1'b0), // (terminated)
+ .ruser (), // (terminated)
+ .buser () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_ORI_BURST_SIZE_H (120),
+ .PKT_ORI_BURST_SIZE_L (118),
+ .PKT_RESPONSE_STATUS_H (117),
+ .PKT_RESPONSE_STATUS_L (116),
+ .PKT_BURST_SIZE_H (92),
+ .PKT_BURST_SIZE_L (90),
+ .PKT_TRANS_LOCK (72),
+ .PKT_BEGIN_BURST (101),
+ .PKT_PROTECTION_H (111),
+ .PKT_PROTECTION_L (109),
+ .PKT_BURSTWRAP_H (89),
+ .PKT_BURSTWRAP_L (82),
+ .PKT_BYTE_CNT_H (81),
+ .PKT_BYTE_CNT_L (74),
+ .PKT_ADDR_H (67),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (68),
+ .PKT_TRANS_POSTED (69),
+ .PKT_TRANS_WRITE (70),
+ .PKT_TRANS_READ (71),
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_SRC_ID_H (103),
+ .PKT_SRC_ID_L (103),
+ .PKT_DEST_ID_H (104),
+ .PKT_DEST_ID_L (104),
+ .PKT_SYMBOL_W (8),
+ .ST_CHANNEL_W (2),
+ .ST_DATA_W (121),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (1),
+ .PREVENT_FIFO_OVERFLOW (1),
+ .USE_READRESPONSE (0),
+ .USE_WRITERESPONSE (0),
+ .ECC_ENABLE (0)
+ ) eth_tse_0_control_port_agent (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .m0_address (eth_tse_0_control_port_agent_m0_address), // m0.address
+ .m0_burstcount (eth_tse_0_control_port_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (eth_tse_0_control_port_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (eth_tse_0_control_port_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (eth_tse_0_control_port_agent_m0_lock), // .lock
+ .m0_readdata (eth_tse_0_control_port_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (eth_tse_0_control_port_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (eth_tse_0_control_port_agent_m0_read), // .read
+ .m0_waitrequest (eth_tse_0_control_port_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (eth_tse_0_control_port_agent_m0_writedata), // .writedata
+ .m0_write (eth_tse_0_control_port_agent_m0_write), // .write
+ .rp_endofpacket (eth_tse_0_control_port_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (eth_tse_0_control_port_agent_rp_ready), // .ready
+ .rp_valid (eth_tse_0_control_port_agent_rp_valid), // .valid
+ .rp_data (eth_tse_0_control_port_agent_rp_data), // .data
+ .rp_startofpacket (eth_tse_0_control_port_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (eth_tse_0_control_port_burst_adapter_source0_ready), // cp.ready
+ .cp_valid (eth_tse_0_control_port_burst_adapter_source0_valid), // .valid
+ .cp_data (eth_tse_0_control_port_burst_adapter_source0_data), // .data
+ .cp_startofpacket (eth_tse_0_control_port_burst_adapter_source0_startofpacket), // .startofpacket
+ .cp_endofpacket (eth_tse_0_control_port_burst_adapter_source0_endofpacket), // .endofpacket
+ .cp_channel (eth_tse_0_control_port_burst_adapter_source0_channel), // .channel
+ .rf_sink_ready (eth_tse_0_control_port_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (eth_tse_0_control_port_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (eth_tse_0_control_port_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (eth_tse_0_control_port_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (eth_tse_0_control_port_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (eth_tse_0_control_port_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (eth_tse_0_control_port_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (eth_tse_0_control_port_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
+ .rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
+ .rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
+ .rdata_fifo_src_ready (eth_tse_0_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (eth_tse_0_control_port_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (eth_tse_0_control_port_agent_rdata_fifo_src_data), // .data
+ .m0_response (2'b00), // (terminated)
+ .m0_writeresponsevalid (1'b0) // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (122),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) eth_tse_0_control_port_agent_rsp_fifo (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_data (eth_tse_0_control_port_agent_rf_source_data), // in.data
+ .in_valid (eth_tse_0_control_port_agent_rf_source_valid), // .valid
+ .in_ready (eth_tse_0_control_port_agent_rf_source_ready), // .ready
+ .in_startofpacket (eth_tse_0_control_port_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (eth_tse_0_control_port_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (eth_tse_0_control_port_agent_rsp_fifo_out_data), // out.data
+ .out_valid (eth_tse_0_control_port_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (eth_tse_0_control_port_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (34),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (0),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (0),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) eth_tse_0_control_port_agent_rdata_fifo (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_data (eth_tse_0_control_port_agent_rdata_fifo_src_data), // in.data
+ .in_valid (eth_tse_0_control_port_agent_rdata_fifo_src_valid), // .valid
+ .in_ready (eth_tse_0_control_port_agent_rdata_fifo_src_ready), // .ready
+ .out_data (eth_tse_0_control_port_agent_rdata_fifo_out_data), // out.data
+ .out_valid (eth_tse_0_control_port_agent_rdata_fifo_out_valid), // .valid
+ .out_ready (eth_tse_0_control_port_agent_rdata_fifo_out_ready), // .ready
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_startofpacket (1'b0), // (terminated)
+ .in_endofpacket (1'b0), // (terminated)
+ .out_startofpacket (), // (terminated)
+ .out_endofpacket (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ arria10_hps_altera_merlin_router_221_qfjs35a router (
+ .sink_ready (a10_hps_h2f_axi_master_agent_write_cp_ready), // sink.ready
+ .sink_valid (a10_hps_h2f_axi_master_agent_write_cp_valid), // .valid
+ .sink_data (a10_hps_h2f_axi_master_agent_write_cp_data), // .data
+ .sink_startofpacket (a10_hps_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (a10_hps_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_src_ready), // src.ready
+ .src_valid (router_src_valid), // .valid
+ .src_data (router_src_data), // .data
+ .src_channel (router_src_channel), // .channel
+ .src_startofpacket (router_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_src_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_router_221_qfjs35a router_001 (
+ .sink_ready (a10_hps_h2f_axi_master_agent_read_cp_ready), // sink.ready
+ .sink_valid (a10_hps_h2f_axi_master_agent_read_cp_valid), // .valid
+ .sink_data (a10_hps_h2f_axi_master_agent_read_cp_data), // .data
+ .sink_startofpacket (a10_hps_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (a10_hps_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_001_src_ready), // src.ready
+ .src_valid (router_001_src_valid), // .valid
+ .src_data (router_001_src_data), // .data
+ .src_channel (router_001_src_channel), // .channel
+ .src_startofpacket (router_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_001_src_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_router_221_xe243si router_002 (
+ .sink_ready (eth_tse_0_control_port_agent_rp_ready), // sink.ready
+ .sink_valid (eth_tse_0_control_port_agent_rp_valid), // .valid
+ .sink_data (eth_tse_0_control_port_agent_rp_data), // .data
+ .sink_startofpacket (eth_tse_0_control_port_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (eth_tse_0_control_port_agent_rp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_002_src_ready), // src.ready
+ .src_valid (router_002_src_valid), // .valid
+ .src_data (router_002_src_data), // .data
+ .src_channel (router_002_src_channel), // .channel
+ .src_startofpacket (router_002_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_002_src_endofpacket) // .endofpacket
+ );
+
+ altera_merlin_burst_adapter #(
+ .PKT_ADDR_H (67),
+ .PKT_ADDR_L (36),
+ .PKT_BEGIN_BURST (101),
+ .PKT_BYTE_CNT_H (81),
+ .PKT_BYTE_CNT_L (74),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_BURST_SIZE_H (92),
+ .PKT_BURST_SIZE_L (90),
+ .PKT_BURST_TYPE_H (94),
+ .PKT_BURST_TYPE_L (93),
+ .PKT_BURSTWRAP_H (89),
+ .PKT_BURSTWRAP_L (82),
+ .PKT_TRANS_COMPRESSED_READ (68),
+ .PKT_TRANS_WRITE (70),
+ .PKT_TRANS_READ (71),
+ .OUT_NARROW_SIZE (0),
+ .IN_NARROW_SIZE (1),
+ .OUT_FIXED (0),
+ .OUT_COMPLETE_WRAP (0),
+ .ST_DATA_W (121),
+ .ST_CHANNEL_W (2),
+ .OUT_BYTE_CNT_H (76),
+ .OUT_BURSTWRAP_H (89),
+ .COMPRESSED_READ_SUPPORT (1),
+ .BYTEENABLE_SYNTHESIS (1),
+ .PIPE_INPUTS (0),
+ .NO_WRAP_SUPPORT (0),
+ .INCOMPLETE_WRAP_SUPPORT (0),
+ .BURSTWRAP_CONST_MASK (0),
+ .BURSTWRAP_CONST_VALUE (0),
+ .ADAPTER_VERSION ("13.1")
+ ) eth_tse_0_control_port_burst_adapter (
+ .clk (clk_0_clk_clk), // cr0.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // cr0_reset.reset
+ .sink0_valid (eth_tse_0_control_port_cmd_width_adapter_src_valid), // sink0.valid
+ .sink0_data (eth_tse_0_control_port_cmd_width_adapter_src_data), // .data
+ .sink0_channel (eth_tse_0_control_port_cmd_width_adapter_src_channel), // .channel
+ .sink0_startofpacket (eth_tse_0_control_port_cmd_width_adapter_src_startofpacket), // .startofpacket
+ .sink0_endofpacket (eth_tse_0_control_port_cmd_width_adapter_src_endofpacket), // .endofpacket
+ .sink0_ready (eth_tse_0_control_port_cmd_width_adapter_src_ready), // .ready
+ .source0_valid (eth_tse_0_control_port_burst_adapter_source0_valid), // source0.valid
+ .source0_data (eth_tse_0_control_port_burst_adapter_source0_data), // .data
+ .source0_channel (eth_tse_0_control_port_burst_adapter_source0_channel), // .channel
+ .source0_startofpacket (eth_tse_0_control_port_burst_adapter_source0_startofpacket), // .startofpacket
+ .source0_endofpacket (eth_tse_0_control_port_burst_adapter_source0_endofpacket), // .endofpacket
+ .source0_ready (eth_tse_0_control_port_burst_adapter_source0_ready) // .ready
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_72yhala cmd_demux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (router_src_ready), // sink.ready
+ .sink_channel (router_src_channel), // .channel
+ .sink_data (router_src_data), // .data
+ .sink_startofpacket (router_src_startofpacket), // .startofpacket
+ .sink_endofpacket (router_src_endofpacket), // .endofpacket
+ .sink_valid (router_src_valid), // .valid
+ .src0_ready (cmd_demux_src0_ready), // src0.ready
+ .src0_valid (cmd_demux_src0_valid), // .valid
+ .src0_data (cmd_demux_src0_data), // .data
+ .src0_channel (cmd_demux_src0_channel), // .channel
+ .src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_72yhala cmd_demux_001 (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (router_001_src_ready), // sink.ready
+ .sink_channel (router_001_src_channel), // .channel
+ .sink_data (router_001_src_data), // .data
+ .sink_startofpacket (router_001_src_startofpacket), // .startofpacket
+ .sink_endofpacket (router_001_src_endofpacket), // .endofpacket
+ .sink_valid (router_001_src_valid), // .valid
+ .src0_ready (cmd_demux_001_src0_ready), // src0.ready
+ .src0_valid (cmd_demux_001_src0_valid), // .valid
+ .src0_data (cmd_demux_001_src0_data), // .data
+ .src0_channel (cmd_demux_001_src0_channel), // .channel
+ .src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_vzucqyy cmd_mux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (cmd_mux_src_ready), // src.ready
+ .src_valid (cmd_mux_src_valid), // .valid
+ .src_data (cmd_mux_src_data), // .data
+ .src_channel (cmd_mux_src_channel), // .channel
+ .src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
+ .src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
+ .sink0_ready (cmd_demux_src0_ready), // sink0.ready
+ .sink0_valid (cmd_demux_src0_valid), // .valid
+ .sink0_channel (cmd_demux_src0_channel), // .channel
+ .sink0_data (cmd_demux_src0_data), // .data
+ .sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
+ .sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
+ .sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
+ .sink1_valid (cmd_demux_001_src0_valid), // .valid
+ .sink1_channel (cmd_demux_001_src0_channel), // .channel
+ .sink1_data (cmd_demux_001_src0_data), // .data
+ .sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
+ .sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_e3m23ka rsp_demux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (eth_tse_0_control_port_rsp_width_adapter_src_ready), // sink.ready
+ .sink_channel (eth_tse_0_control_port_rsp_width_adapter_src_channel), // .channel
+ .sink_data (eth_tse_0_control_port_rsp_width_adapter_src_data), // .data
+ .sink_startofpacket (eth_tse_0_control_port_rsp_width_adapter_src_startofpacket), // .startofpacket
+ .sink_endofpacket (eth_tse_0_control_port_rsp_width_adapter_src_endofpacket), // .endofpacket
+ .sink_valid (eth_tse_0_control_port_rsp_width_adapter_src_valid), // .valid
+ .src0_ready (rsp_demux_src0_ready), // src0.ready
+ .src0_valid (rsp_demux_src0_valid), // .valid
+ .src0_data (rsp_demux_src0_data), // .data
+ .src0_channel (rsp_demux_src0_channel), // .channel
+ .src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
+ .src1_ready (rsp_demux_src1_ready), // src1.ready
+ .src1_valid (rsp_demux_src1_valid), // .valid
+ .src1_data (rsp_demux_src1_data), // .data
+ .src1_channel (rsp_demux_src1_channel), // .channel
+ .src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
+ .src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_huj2kiy rsp_mux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (rsp_mux_src_ready), // src.ready
+ .src_valid (rsp_mux_src_valid), // .valid
+ .src_data (rsp_mux_src_data), // .data
+ .src_channel (rsp_mux_src_channel), // .channel
+ .src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
+ .sink0_ready (rsp_demux_src0_ready), // sink0.ready
+ .sink0_valid (rsp_demux_src0_valid), // .valid
+ .sink0_channel (rsp_demux_src0_channel), // .channel
+ .sink0_data (rsp_demux_src0_data), // .data
+ .sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
+ .sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_huj2kiy rsp_mux_001 (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (rsp_mux_001_src_ready), // src.ready
+ .src_valid (rsp_mux_001_src_valid), // .valid
+ .src_data (rsp_mux_001_src_data), // .data
+ .src_channel (rsp_mux_001_src_channel), // .channel
+ .src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
+ .sink0_ready (rsp_demux_src1_ready), // sink0.ready
+ .sink0_valid (rsp_demux_src1_valid), // .valid
+ .sink0_channel (rsp_demux_src1_channel), // .channel
+ .sink0_data (rsp_demux_src1_data), // .data
+ .sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
+ .sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
+ );
+
+ altera_merlin_width_adapter #(
+ .IN_PKT_ADDR_H (67),
+ .IN_PKT_ADDR_L (36),
+ .IN_PKT_DATA_H (31),
+ .IN_PKT_DATA_L (0),
+ .IN_PKT_BYTEEN_H (35),
+ .IN_PKT_BYTEEN_L (32),
+ .IN_PKT_BYTE_CNT_H (81),
+ .IN_PKT_BYTE_CNT_L (74),
+ .IN_PKT_TRANS_COMPRESSED_READ (68),
+ .IN_PKT_TRANS_WRITE (70),
+ .IN_PKT_BURSTWRAP_H (89),
+ .IN_PKT_BURSTWRAP_L (82),
+ .IN_PKT_BURST_SIZE_H (92),
+ .IN_PKT_BURST_SIZE_L (90),
+ .IN_PKT_RESPONSE_STATUS_H (117),
+ .IN_PKT_RESPONSE_STATUS_L (116),
+ .IN_PKT_TRANS_EXCLUSIVE (73),
+ .IN_PKT_BURST_TYPE_H (94),
+ .IN_PKT_BURST_TYPE_L (93),
+ .IN_PKT_ORI_BURST_SIZE_L (118),
+ .IN_PKT_ORI_BURST_SIZE_H (120),
+ .IN_ST_DATA_W (121),
+ .OUT_PKT_ADDR_H (103),
+ .OUT_PKT_ADDR_L (72),
+ .OUT_PKT_DATA_H (63),
+ .OUT_PKT_DATA_L (0),
+ .OUT_PKT_BYTEEN_H (71),
+ .OUT_PKT_BYTEEN_L (64),
+ .OUT_PKT_BYTE_CNT_H (117),
+ .OUT_PKT_BYTE_CNT_L (110),
+ .OUT_PKT_TRANS_COMPRESSED_READ (104),
+ .OUT_PKT_BURST_SIZE_H (128),
+ .OUT_PKT_BURST_SIZE_L (126),
+ .OUT_PKT_RESPONSE_STATUS_H (153),
+ .OUT_PKT_RESPONSE_STATUS_L (152),
+ .OUT_PKT_TRANS_EXCLUSIVE (109),
+ .OUT_PKT_BURST_TYPE_H (130),
+ .OUT_PKT_BURST_TYPE_L (129),
+ .OUT_PKT_ORI_BURST_SIZE_L (154),
+ .OUT_PKT_ORI_BURST_SIZE_H (156),
+ .OUT_ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .OPTIMIZE_FOR_RSP (0),
+ .RESPONSE_PATH (1),
+ .CONSTANT_BURST_SIZE (0),
+ .PACKING (1),
+ .ENABLE_ADDRESS_ALIGNMENT (1)
+ ) eth_tse_0_control_port_rsp_width_adapter (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_valid (router_002_src_valid), // sink.valid
+ .in_channel (router_002_src_channel), // .channel
+ .in_startofpacket (router_002_src_startofpacket), // .startofpacket
+ .in_endofpacket (router_002_src_endofpacket), // .endofpacket
+ .in_ready (router_002_src_ready), // .ready
+ .in_data (router_002_src_data), // .data
+ .out_endofpacket (eth_tse_0_control_port_rsp_width_adapter_src_endofpacket), // src.endofpacket
+ .out_data (eth_tse_0_control_port_rsp_width_adapter_src_data), // .data
+ .out_channel (eth_tse_0_control_port_rsp_width_adapter_src_channel), // .channel
+ .out_valid (eth_tse_0_control_port_rsp_width_adapter_src_valid), // .valid
+ .out_ready (eth_tse_0_control_port_rsp_width_adapter_src_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_rsp_width_adapter_src_startofpacket), // .startofpacket
+ .in_command_size_data (3'b000) // (terminated)
+ );
+
+ altera_merlin_width_adapter #(
+ .IN_PKT_ADDR_H (103),
+ .IN_PKT_ADDR_L (72),
+ .IN_PKT_DATA_H (63),
+ .IN_PKT_DATA_L (0),
+ .IN_PKT_BYTEEN_H (71),
+ .IN_PKT_BYTEEN_L (64),
+ .IN_PKT_BYTE_CNT_H (117),
+ .IN_PKT_BYTE_CNT_L (110),
+ .IN_PKT_TRANS_COMPRESSED_READ (104),
+ .IN_PKT_TRANS_WRITE (106),
+ .IN_PKT_BURSTWRAP_H (125),
+ .IN_PKT_BURSTWRAP_L (118),
+ .IN_PKT_BURST_SIZE_H (128),
+ .IN_PKT_BURST_SIZE_L (126),
+ .IN_PKT_RESPONSE_STATUS_H (153),
+ .IN_PKT_RESPONSE_STATUS_L (152),
+ .IN_PKT_TRANS_EXCLUSIVE (109),
+ .IN_PKT_BURST_TYPE_H (130),
+ .IN_PKT_BURST_TYPE_L (129),
+ .IN_PKT_ORI_BURST_SIZE_L (154),
+ .IN_PKT_ORI_BURST_SIZE_H (156),
+ .IN_ST_DATA_W (157),
+ .OUT_PKT_ADDR_H (67),
+ .OUT_PKT_ADDR_L (36),
+ .OUT_PKT_DATA_H (31),
+ .OUT_PKT_DATA_L (0),
+ .OUT_PKT_BYTEEN_H (35),
+ .OUT_PKT_BYTEEN_L (32),
+ .OUT_PKT_BYTE_CNT_H (81),
+ .OUT_PKT_BYTE_CNT_L (74),
+ .OUT_PKT_TRANS_COMPRESSED_READ (68),
+ .OUT_PKT_BURST_SIZE_H (92),
+ .OUT_PKT_BURST_SIZE_L (90),
+ .OUT_PKT_RESPONSE_STATUS_H (117),
+ .OUT_PKT_RESPONSE_STATUS_L (116),
+ .OUT_PKT_TRANS_EXCLUSIVE (73),
+ .OUT_PKT_BURST_TYPE_H (94),
+ .OUT_PKT_BURST_TYPE_L (93),
+ .OUT_PKT_ORI_BURST_SIZE_L (118),
+ .OUT_PKT_ORI_BURST_SIZE_H (120),
+ .OUT_ST_DATA_W (121),
+ .ST_CHANNEL_W (2),
+ .OPTIMIZE_FOR_RSP (0),
+ .RESPONSE_PATH (0),
+ .CONSTANT_BURST_SIZE (0),
+ .PACKING (0),
+ .ENABLE_ADDRESS_ALIGNMENT (1)
+ ) eth_tse_0_control_port_cmd_width_adapter (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_valid (cmd_mux_src_valid), // sink.valid
+ .in_channel (cmd_mux_src_channel), // .channel
+ .in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
+ .in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
+ .in_ready (cmd_mux_src_ready), // .ready
+ .in_data (cmd_mux_src_data), // .data
+ .out_endofpacket (eth_tse_0_control_port_cmd_width_adapter_src_endofpacket), // src.endofpacket
+ .out_data (eth_tse_0_control_port_cmd_width_adapter_src_data), // .data
+ .out_channel (eth_tse_0_control_port_cmd_width_adapter_src_channel), // .channel
+ .out_valid (eth_tse_0_control_port_cmd_width_adapter_src_valid), // .valid
+ .out_ready (eth_tse_0_control_port_cmd_width_adapter_src_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_cmd_width_adapter_src_startofpacket), // .startofpacket
+ .in_command_size_data (3'b000) // (terminated)
+ );
+
+ arria10_hps_altera_avalon_st_adapter_221_36tuu3a #(
+ .inBitsPerSymbol (34),
+ .inUsePackets (0),
+ .inDataWidth (34),
+ .inChannelWidth (0),
+ .inErrorWidth (0),
+ .inUseEmptyPort (0),
+ .inUseValid (1),
+ .inUseReady (1),
+ .inReadyLatency (0),
+ .outDataWidth (34),
+ .outChannelWidth (0),
+ .outErrorWidth (1),
+ .outUseEmptyPort (0),
+ .outUseValid (1),
+ .outUseReady (1),
+ .outReadyLatency (0)
+ ) avalon_st_adapter (
+ .in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
+ .in_rst_0_reset (eth_tse_0_reset_connection_reset_bridge_in_reset_reset), // in_rst_0.reset
+ .in_0_data (eth_tse_0_control_port_agent_rdata_fifo_out_data), // in_0.data
+ .in_0_valid (eth_tse_0_control_port_agent_rdata_fifo_out_valid), // .valid
+ .in_0_ready (eth_tse_0_control_port_agent_rdata_fifo_out_ready), // .ready
+ .out_0_data (avalon_st_adapter_out_0_data), // out_0.data
+ .out_0_valid (avalon_st_adapter_out_0_valid), // .valid
+ .out_0_ready (avalon_st_adapter_out_0_ready), // .ready
+ .out_0_error (avalon_st_adapter_out_0_error) // .error
+ );
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_qogprma_cfg.v b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_qogprma_cfg.v
new file mode 100644
index 0000000000000000000000000000000000000000..9d97a1e92b46003edf4d3f03d095271098aad417
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_qogprma_cfg.v
@@ -0,0 +1,22 @@
+config arria10_hps_altera_mm_interconnect_221_qogprma_cfg;
+ design arria10_hps_altera_mm_interconnect_221_qogprma;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.eth_tse_0_control_port_translator use arria10_hps_altera_merlin_slave_translator_221.altera_merlin_slave_translator;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.a10_hps_h2f_axi_master_agent use arria10_hps_altera_merlin_axi_master_ni_221.altera_merlin_axi_master_ni;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.eth_tse_0_control_port_agent use arria10_hps_altera_merlin_slave_agent_221.altera_merlin_slave_agent;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.eth_tse_0_control_port_agent_rsp_fifo use arria10_hps_altera_avalon_sc_fifo_221.altera_avalon_sc_fifo;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.eth_tse_0_control_port_agent_rdata_fifo use arria10_hps_altera_avalon_sc_fifo_221.altera_avalon_sc_fifo;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.router use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_qfjs35a;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.router_001 use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_qfjs35a;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.router_002 use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_xe243si;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.eth_tse_0_control_port_burst_adapter use arria10_hps_altera_merlin_burst_adapter_221.altera_merlin_burst_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.cmd_demux use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_72yhala;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.cmd_demux_001 use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_72yhala;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.cmd_mux use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_vzucqyy;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.rsp_demux use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_e3m23ka;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.rsp_mux use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_huj2kiy;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.rsp_mux_001 use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_huj2kiy;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.eth_tse_0_control_port_rsp_width_adapter use arria10_hps_altera_merlin_width_adapter_221.altera_merlin_width_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.eth_tse_0_control_port_cmd_width_adapter use arria10_hps_altera_merlin_width_adapter_221.altera_merlin_width_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_qogprma.avalon_st_adapter use arria10_hps_altera_avalon_st_adapter_221.arria10_hps_altera_avalon_st_adapter_221_36tuu3a;
+endconfig
+
diff --git a/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_yw4vjdi.v b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_yw4vjdi.v
new file mode 100644
index 0000000000000000000000000000000000000000..f56c4c4d6f9490a0debf600f50ed4d6f5a01a09d
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_yw4vjdi.v
@@ -0,0 +1,914 @@
+// arria10_hps_altera_mm_interconnect_221_yw4vjdi.v
+
+// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
+// will probably be lost.
+//
+// Generated using ACDS version 22.1 922
+
+`timescale 1 ps / 1 ps
+module arria10_hps_altera_mm_interconnect_221_yw4vjdi (
+ input wire [3:0] a10_hps_h2f_axi_master_awid, // a10_hps_h2f_axi_master.awid
+ input wire [31:0] a10_hps_h2f_axi_master_awaddr, // .awaddr
+ input wire [3:0] a10_hps_h2f_axi_master_awlen, // .awlen
+ input wire [2:0] a10_hps_h2f_axi_master_awsize, // .awsize
+ input wire [1:0] a10_hps_h2f_axi_master_awburst, // .awburst
+ input wire [1:0] a10_hps_h2f_axi_master_awlock, // .awlock
+ input wire [3:0] a10_hps_h2f_axi_master_awcache, // .awcache
+ input wire [2:0] a10_hps_h2f_axi_master_awprot, // .awprot
+ input wire [4:0] a10_hps_h2f_axi_master_awuser, // .awuser
+ input wire a10_hps_h2f_axi_master_awvalid, // .awvalid
+ output wire a10_hps_h2f_axi_master_awready, // .awready
+ input wire [3:0] a10_hps_h2f_axi_master_wid, // .wid
+ input wire [63:0] a10_hps_h2f_axi_master_wdata, // .wdata
+ input wire [7:0] a10_hps_h2f_axi_master_wstrb, // .wstrb
+ input wire a10_hps_h2f_axi_master_wlast, // .wlast
+ input wire a10_hps_h2f_axi_master_wvalid, // .wvalid
+ output wire a10_hps_h2f_axi_master_wready, // .wready
+ output wire [3:0] a10_hps_h2f_axi_master_bid, // .bid
+ output wire [1:0] a10_hps_h2f_axi_master_bresp, // .bresp
+ output wire a10_hps_h2f_axi_master_bvalid, // .bvalid
+ input wire a10_hps_h2f_axi_master_bready, // .bready
+ input wire [3:0] a10_hps_h2f_axi_master_arid, // .arid
+ input wire [31:0] a10_hps_h2f_axi_master_araddr, // .araddr
+ input wire [3:0] a10_hps_h2f_axi_master_arlen, // .arlen
+ input wire [2:0] a10_hps_h2f_axi_master_arsize, // .arsize
+ input wire [1:0] a10_hps_h2f_axi_master_arburst, // .arburst
+ input wire [1:0] a10_hps_h2f_axi_master_arlock, // .arlock
+ input wire [3:0] a10_hps_h2f_axi_master_arcache, // .arcache
+ input wire [2:0] a10_hps_h2f_axi_master_arprot, // .arprot
+ input wire [4:0] a10_hps_h2f_axi_master_aruser, // .aruser
+ input wire a10_hps_h2f_axi_master_arvalid, // .arvalid
+ output wire a10_hps_h2f_axi_master_arready, // .arready
+ output wire [3:0] a10_hps_h2f_axi_master_rid, // .rid
+ output wire [63:0] a10_hps_h2f_axi_master_rdata, // .rdata
+ output wire [1:0] a10_hps_h2f_axi_master_rresp, // .rresp
+ output wire a10_hps_h2f_axi_master_rlast, // .rlast
+ output wire a10_hps_h2f_axi_master_rvalid, // .rvalid
+ input wire a10_hps_h2f_axi_master_rready, // .rready
+ input wire clk_0_clk_clk, // clk_0_clk.clk
+ input wire a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset, // a10_hps_h2f_axi_reset_reset_bridge_in_reset.reset
+ output wire [7:0] eth_tse_0_control_port_address, // eth_tse_0_control_port.address
+ output wire eth_tse_0_control_port_write, // .write
+ output wire eth_tse_0_control_port_read, // .read
+ input wire [31:0] eth_tse_0_control_port_readdata, // .readdata
+ output wire [31:0] eth_tse_0_control_port_writedata, // .writedata
+ input wire eth_tse_0_control_port_waitrequest // .waitrequest
+ );
+
+ wire rsp_mux_src_valid; // rsp_mux:src_valid -> a10_hps_h2f_axi_master_agent:write_rp_valid
+ wire [156:0] rsp_mux_src_data; // rsp_mux:src_data -> a10_hps_h2f_axi_master_agent:write_rp_data
+ wire rsp_mux_src_ready; // a10_hps_h2f_axi_master_agent:write_rp_ready -> rsp_mux:src_ready
+ wire [1:0] rsp_mux_src_channel; // rsp_mux:src_channel -> a10_hps_h2f_axi_master_agent:write_rp_channel
+ wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> a10_hps_h2f_axi_master_agent:write_rp_startofpacket
+ wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> a10_hps_h2f_axi_master_agent:write_rp_endofpacket
+ wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> a10_hps_h2f_axi_master_agent:read_rp_valid
+ wire [156:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> a10_hps_h2f_axi_master_agent:read_rp_data
+ wire rsp_mux_001_src_ready; // a10_hps_h2f_axi_master_agent:read_rp_ready -> rsp_mux_001:src_ready
+ wire [1:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> a10_hps_h2f_axi_master_agent:read_rp_channel
+ wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> a10_hps_h2f_axi_master_agent:read_rp_startofpacket
+ wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> a10_hps_h2f_axi_master_agent:read_rp_endofpacket
+ wire [31:0] eth_tse_0_control_port_agent_m0_readdata; // eth_tse_0_control_port_translator:uav_readdata -> eth_tse_0_control_port_agent:m0_readdata
+ wire eth_tse_0_control_port_agent_m0_waitrequest; // eth_tse_0_control_port_translator:uav_waitrequest -> eth_tse_0_control_port_agent:m0_waitrequest
+ wire eth_tse_0_control_port_agent_m0_debugaccess; // eth_tse_0_control_port_agent:m0_debugaccess -> eth_tse_0_control_port_translator:uav_debugaccess
+ wire [31:0] eth_tse_0_control_port_agent_m0_address; // eth_tse_0_control_port_agent:m0_address -> eth_tse_0_control_port_translator:uav_address
+ wire [3:0] eth_tse_0_control_port_agent_m0_byteenable; // eth_tse_0_control_port_agent:m0_byteenable -> eth_tse_0_control_port_translator:uav_byteenable
+ wire eth_tse_0_control_port_agent_m0_read; // eth_tse_0_control_port_agent:m0_read -> eth_tse_0_control_port_translator:uav_read
+ wire eth_tse_0_control_port_agent_m0_readdatavalid; // eth_tse_0_control_port_translator:uav_readdatavalid -> eth_tse_0_control_port_agent:m0_readdatavalid
+ wire eth_tse_0_control_port_agent_m0_lock; // eth_tse_0_control_port_agent:m0_lock -> eth_tse_0_control_port_translator:uav_lock
+ wire [31:0] eth_tse_0_control_port_agent_m0_writedata; // eth_tse_0_control_port_agent:m0_writedata -> eth_tse_0_control_port_translator:uav_writedata
+ wire eth_tse_0_control_port_agent_m0_write; // eth_tse_0_control_port_agent:m0_write -> eth_tse_0_control_port_translator:uav_write
+ wire [2:0] eth_tse_0_control_port_agent_m0_burstcount; // eth_tse_0_control_port_agent:m0_burstcount -> eth_tse_0_control_port_translator:uav_burstcount
+ wire eth_tse_0_control_port_agent_rf_source_valid; // eth_tse_0_control_port_agent:rf_source_valid -> eth_tse_0_control_port_agent_rsp_fifo:in_valid
+ wire [121:0] eth_tse_0_control_port_agent_rf_source_data; // eth_tse_0_control_port_agent:rf_source_data -> eth_tse_0_control_port_agent_rsp_fifo:in_data
+ wire eth_tse_0_control_port_agent_rf_source_ready; // eth_tse_0_control_port_agent_rsp_fifo:in_ready -> eth_tse_0_control_port_agent:rf_source_ready
+ wire eth_tse_0_control_port_agent_rf_source_startofpacket; // eth_tse_0_control_port_agent:rf_source_startofpacket -> eth_tse_0_control_port_agent_rsp_fifo:in_startofpacket
+ wire eth_tse_0_control_port_agent_rf_source_endofpacket; // eth_tse_0_control_port_agent:rf_source_endofpacket -> eth_tse_0_control_port_agent_rsp_fifo:in_endofpacket
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_valid; // eth_tse_0_control_port_agent_rsp_fifo:out_valid -> eth_tse_0_control_port_agent:rf_sink_valid
+ wire [121:0] eth_tse_0_control_port_agent_rsp_fifo_out_data; // eth_tse_0_control_port_agent_rsp_fifo:out_data -> eth_tse_0_control_port_agent:rf_sink_data
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_ready; // eth_tse_0_control_port_agent:rf_sink_ready -> eth_tse_0_control_port_agent_rsp_fifo:out_ready
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket; // eth_tse_0_control_port_agent_rsp_fifo:out_startofpacket -> eth_tse_0_control_port_agent:rf_sink_startofpacket
+ wire eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket; // eth_tse_0_control_port_agent_rsp_fifo:out_endofpacket -> eth_tse_0_control_port_agent:rf_sink_endofpacket
+ wire eth_tse_0_control_port_agent_rdata_fifo_src_valid; // eth_tse_0_control_port_agent:rdata_fifo_src_valid -> eth_tse_0_control_port_agent_rdata_fifo:in_valid
+ wire [33:0] eth_tse_0_control_port_agent_rdata_fifo_src_data; // eth_tse_0_control_port_agent:rdata_fifo_src_data -> eth_tse_0_control_port_agent_rdata_fifo:in_data
+ wire eth_tse_0_control_port_agent_rdata_fifo_src_ready; // eth_tse_0_control_port_agent_rdata_fifo:in_ready -> eth_tse_0_control_port_agent:rdata_fifo_src_ready
+ wire a10_hps_h2f_axi_master_agent_write_cp_valid; // a10_hps_h2f_axi_master_agent:write_cp_valid -> router:sink_valid
+ wire [156:0] a10_hps_h2f_axi_master_agent_write_cp_data; // a10_hps_h2f_axi_master_agent:write_cp_data -> router:sink_data
+ wire a10_hps_h2f_axi_master_agent_write_cp_ready; // router:sink_ready -> a10_hps_h2f_axi_master_agent:write_cp_ready
+ wire a10_hps_h2f_axi_master_agent_write_cp_startofpacket; // a10_hps_h2f_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
+ wire a10_hps_h2f_axi_master_agent_write_cp_endofpacket; // a10_hps_h2f_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
+ wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
+ wire [156:0] router_src_data; // router:src_data -> cmd_demux:sink_data
+ wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
+ wire [1:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
+ wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
+ wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
+ wire a10_hps_h2f_axi_master_agent_read_cp_valid; // a10_hps_h2f_axi_master_agent:read_cp_valid -> router_001:sink_valid
+ wire [156:0] a10_hps_h2f_axi_master_agent_read_cp_data; // a10_hps_h2f_axi_master_agent:read_cp_data -> router_001:sink_data
+ wire a10_hps_h2f_axi_master_agent_read_cp_ready; // router_001:sink_ready -> a10_hps_h2f_axi_master_agent:read_cp_ready
+ wire a10_hps_h2f_axi_master_agent_read_cp_startofpacket; // a10_hps_h2f_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
+ wire a10_hps_h2f_axi_master_agent_read_cp_endofpacket; // a10_hps_h2f_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
+ wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
+ wire [156:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
+ wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
+ wire [1:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
+ wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
+ wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
+ wire eth_tse_0_control_port_agent_rp_valid; // eth_tse_0_control_port_agent:rp_valid -> router_002:sink_valid
+ wire [120:0] eth_tse_0_control_port_agent_rp_data; // eth_tse_0_control_port_agent:rp_data -> router_002:sink_data
+ wire eth_tse_0_control_port_agent_rp_ready; // router_002:sink_ready -> eth_tse_0_control_port_agent:rp_ready
+ wire eth_tse_0_control_port_agent_rp_startofpacket; // eth_tse_0_control_port_agent:rp_startofpacket -> router_002:sink_startofpacket
+ wire eth_tse_0_control_port_agent_rp_endofpacket; // eth_tse_0_control_port_agent:rp_endofpacket -> router_002:sink_endofpacket
+ wire eth_tse_0_control_port_burst_adapter_source0_valid; // eth_tse_0_control_port_burst_adapter:source0_valid -> eth_tse_0_control_port_agent:cp_valid
+ wire [120:0] eth_tse_0_control_port_burst_adapter_source0_data; // eth_tse_0_control_port_burst_adapter:source0_data -> eth_tse_0_control_port_agent:cp_data
+ wire eth_tse_0_control_port_burst_adapter_source0_ready; // eth_tse_0_control_port_agent:cp_ready -> eth_tse_0_control_port_burst_adapter:source0_ready
+ wire [1:0] eth_tse_0_control_port_burst_adapter_source0_channel; // eth_tse_0_control_port_burst_adapter:source0_channel -> eth_tse_0_control_port_agent:cp_channel
+ wire eth_tse_0_control_port_burst_adapter_source0_startofpacket; // eth_tse_0_control_port_burst_adapter:source0_startofpacket -> eth_tse_0_control_port_agent:cp_startofpacket
+ wire eth_tse_0_control_port_burst_adapter_source0_endofpacket; // eth_tse_0_control_port_burst_adapter:source0_endofpacket -> eth_tse_0_control_port_agent:cp_endofpacket
+ wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
+ wire [156:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
+ wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
+ wire [1:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
+ wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
+ wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
+ wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
+ wire [156:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
+ wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
+ wire [1:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
+ wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
+ wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
+ wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
+ wire [156:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
+ wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
+ wire [1:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
+ wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
+ wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
+ wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
+ wire [156:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
+ wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
+ wire [1:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
+ wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
+ wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
+ wire router_002_src_valid; // router_002:src_valid -> eth_tse_0_control_port_rsp_width_adapter:in_valid
+ wire [120:0] router_002_src_data; // router_002:src_data -> eth_tse_0_control_port_rsp_width_adapter:in_data
+ wire router_002_src_ready; // eth_tse_0_control_port_rsp_width_adapter:in_ready -> router_002:src_ready
+ wire [1:0] router_002_src_channel; // router_002:src_channel -> eth_tse_0_control_port_rsp_width_adapter:in_channel
+ wire router_002_src_startofpacket; // router_002:src_startofpacket -> eth_tse_0_control_port_rsp_width_adapter:in_startofpacket
+ wire router_002_src_endofpacket; // router_002:src_endofpacket -> eth_tse_0_control_port_rsp_width_adapter:in_endofpacket
+ wire eth_tse_0_control_port_rsp_width_adapter_src_valid; // eth_tse_0_control_port_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
+ wire [156:0] eth_tse_0_control_port_rsp_width_adapter_src_data; // eth_tse_0_control_port_rsp_width_adapter:out_data -> rsp_demux:sink_data
+ wire eth_tse_0_control_port_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> eth_tse_0_control_port_rsp_width_adapter:out_ready
+ wire [1:0] eth_tse_0_control_port_rsp_width_adapter_src_channel; // eth_tse_0_control_port_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
+ wire eth_tse_0_control_port_rsp_width_adapter_src_startofpacket; // eth_tse_0_control_port_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
+ wire eth_tse_0_control_port_rsp_width_adapter_src_endofpacket; // eth_tse_0_control_port_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
+ wire cmd_mux_src_valid; // cmd_mux:src_valid -> eth_tse_0_control_port_cmd_width_adapter:in_valid
+ wire [156:0] cmd_mux_src_data; // cmd_mux:src_data -> eth_tse_0_control_port_cmd_width_adapter:in_data
+ wire cmd_mux_src_ready; // eth_tse_0_control_port_cmd_width_adapter:in_ready -> cmd_mux:src_ready
+ wire [1:0] cmd_mux_src_channel; // cmd_mux:src_channel -> eth_tse_0_control_port_cmd_width_adapter:in_channel
+ wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> eth_tse_0_control_port_cmd_width_adapter:in_startofpacket
+ wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> eth_tse_0_control_port_cmd_width_adapter:in_endofpacket
+ wire eth_tse_0_control_port_cmd_width_adapter_src_valid; // eth_tse_0_control_port_cmd_width_adapter:out_valid -> eth_tse_0_control_port_burst_adapter:sink0_valid
+ wire [120:0] eth_tse_0_control_port_cmd_width_adapter_src_data; // eth_tse_0_control_port_cmd_width_adapter:out_data -> eth_tse_0_control_port_burst_adapter:sink0_data
+ wire eth_tse_0_control_port_cmd_width_adapter_src_ready; // eth_tse_0_control_port_burst_adapter:sink0_ready -> eth_tse_0_control_port_cmd_width_adapter:out_ready
+ wire [1:0] eth_tse_0_control_port_cmd_width_adapter_src_channel; // eth_tse_0_control_port_cmd_width_adapter:out_channel -> eth_tse_0_control_port_burst_adapter:sink0_channel
+ wire eth_tse_0_control_port_cmd_width_adapter_src_startofpacket; // eth_tse_0_control_port_cmd_width_adapter:out_startofpacket -> eth_tse_0_control_port_burst_adapter:sink0_startofpacket
+ wire eth_tse_0_control_port_cmd_width_adapter_src_endofpacket; // eth_tse_0_control_port_cmd_width_adapter:out_endofpacket -> eth_tse_0_control_port_burst_adapter:sink0_endofpacket
+ wire eth_tse_0_control_port_agent_rdata_fifo_out_valid; // eth_tse_0_control_port_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
+ wire [33:0] eth_tse_0_control_port_agent_rdata_fifo_out_data; // eth_tse_0_control_port_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
+ wire eth_tse_0_control_port_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> eth_tse_0_control_port_agent_rdata_fifo:out_ready
+ wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> eth_tse_0_control_port_agent:rdata_fifo_sink_valid
+ wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> eth_tse_0_control_port_agent:rdata_fifo_sink_data
+ wire avalon_st_adapter_out_0_ready; // eth_tse_0_control_port_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
+ wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> eth_tse_0_control_port_agent:rdata_fifo_sink_error
+
+ altera_merlin_slave_translator #(
+ .AV_ADDRESS_W (8),
+ .AV_DATA_W (32),
+ .UAV_DATA_W (32),
+ .AV_BURSTCOUNT_W (1),
+ .AV_BYTEENABLE_W (4),
+ .UAV_BYTEENABLE_W (4),
+ .UAV_ADDRESS_W (32),
+ .UAV_BURSTCOUNT_W (3),
+ .AV_READLATENCY (0),
+ .USE_READDATAVALID (0),
+ .USE_WAITREQUEST (1),
+ .USE_UAV_CLKEN (0),
+ .USE_READRESPONSE (0),
+ .USE_WRITERESPONSE (0),
+ .AV_SYMBOLS_PER_WORD (4),
+ .AV_ADDRESS_SYMBOLS (0),
+ .AV_BURSTCOUNT_SYMBOLS (0),
+ .AV_CONSTANT_BURST_BEHAVIOR (0),
+ .UAV_CONSTANT_BURST_BEHAVIOR (0),
+ .AV_REQUIRE_UNALIGNED_ADDRESSES (0),
+ .CHIPSELECT_THROUGH_READLATENCY (0),
+ .AV_READ_WAIT_CYCLES (1),
+ .AV_WRITE_WAIT_CYCLES (1),
+ .AV_SETUP_WAIT_CYCLES (0),
+ .AV_DATA_HOLD_CYCLES (0)
+ ) eth_tse_0_control_port_translator (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // reset.reset
+ .uav_address (eth_tse_0_control_port_agent_m0_address), // avalon_universal_slave_0.address
+ .uav_burstcount (eth_tse_0_control_port_agent_m0_burstcount), // .burstcount
+ .uav_read (eth_tse_0_control_port_agent_m0_read), // .read
+ .uav_write (eth_tse_0_control_port_agent_m0_write), // .write
+ .uav_waitrequest (eth_tse_0_control_port_agent_m0_waitrequest), // .waitrequest
+ .uav_readdatavalid (eth_tse_0_control_port_agent_m0_readdatavalid), // .readdatavalid
+ .uav_byteenable (eth_tse_0_control_port_agent_m0_byteenable), // .byteenable
+ .uav_readdata (eth_tse_0_control_port_agent_m0_readdata), // .readdata
+ .uav_writedata (eth_tse_0_control_port_agent_m0_writedata), // .writedata
+ .uav_lock (eth_tse_0_control_port_agent_m0_lock), // .lock
+ .uav_debugaccess (eth_tse_0_control_port_agent_m0_debugaccess), // .debugaccess
+ .av_address (eth_tse_0_control_port_address), // avalon_anti_slave_0.address
+ .av_write (eth_tse_0_control_port_write), // .write
+ .av_read (eth_tse_0_control_port_read), // .read
+ .av_readdata (eth_tse_0_control_port_readdata), // .readdata
+ .av_writedata (eth_tse_0_control_port_writedata), // .writedata
+ .av_waitrequest (eth_tse_0_control_port_waitrequest), // .waitrequest
+ .av_begintransfer (), // (terminated)
+ .av_beginbursttransfer (), // (terminated)
+ .av_burstcount (), // (terminated)
+ .av_byteenable (), // (terminated)
+ .av_readdatavalid (1'b0), // (terminated)
+ .av_writebyteenable (), // (terminated)
+ .av_lock (), // (terminated)
+ .av_chipselect (), // (terminated)
+ .av_clken (), // (terminated)
+ .uav_clken (1'b0), // (terminated)
+ .av_debugaccess (), // (terminated)
+ .av_outputenable (), // (terminated)
+ .uav_response (), // (terminated)
+ .av_response (2'b00), // (terminated)
+ .uav_writeresponsevalid (), // (terminated)
+ .av_writeresponsevalid (1'b0) // (terminated)
+ );
+
+ altera_merlin_axi_master_ni #(
+ .ID_WIDTH (4),
+ .ADDR_WIDTH (32),
+ .RDATA_WIDTH (64),
+ .WDATA_WIDTH (64),
+ .ADDR_USER_WIDTH (5),
+ .DATA_USER_WIDTH (1),
+ .AXI_BURST_LENGTH_WIDTH (4),
+ .AXI_LOCK_WIDTH (2),
+ .AXI_VERSION ("AXI3"),
+ .WRITE_ISSUING_CAPABILITY (8),
+ .READ_ISSUING_CAPABILITY (8),
+ .PKT_BEGIN_BURST (137),
+ .PKT_CACHE_H (151),
+ .PKT_CACHE_L (148),
+ .PKT_ADDR_SIDEBAND_H (135),
+ .PKT_ADDR_SIDEBAND_L (131),
+ .PKT_PROTECTION_H (147),
+ .PKT_PROTECTION_L (145),
+ .PKT_BURST_SIZE_H (128),
+ .PKT_BURST_SIZE_L (126),
+ .PKT_BURST_TYPE_H (130),
+ .PKT_BURST_TYPE_L (129),
+ .PKT_RESPONSE_STATUS_L (152),
+ .PKT_RESPONSE_STATUS_H (153),
+ .PKT_BURSTWRAP_H (125),
+ .PKT_BURSTWRAP_L (118),
+ .PKT_BYTE_CNT_H (117),
+ .PKT_BYTE_CNT_L (110),
+ .PKT_ADDR_H (103),
+ .PKT_ADDR_L (72),
+ .PKT_TRANS_EXCLUSIVE (109),
+ .PKT_TRANS_LOCK (108),
+ .PKT_TRANS_COMPRESSED_READ (104),
+ .PKT_TRANS_POSTED (105),
+ .PKT_TRANS_WRITE (106),
+ .PKT_TRANS_READ (107),
+ .PKT_DATA_H (63),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (71),
+ .PKT_BYTEEN_L (64),
+ .PKT_SRC_ID_H (139),
+ .PKT_SRC_ID_L (139),
+ .PKT_DEST_ID_H (140),
+ .PKT_DEST_ID_L (140),
+ .PKT_THREAD_ID_H (144),
+ .PKT_THREAD_ID_L (141),
+ .PKT_QOS_L (138),
+ .PKT_QOS_H (138),
+ .PKT_ORI_BURST_SIZE_L (154),
+ .PKT_ORI_BURST_SIZE_H (156),
+ .PKT_DATA_SIDEBAND_H (136),
+ .PKT_DATA_SIDEBAND_L (136),
+ .ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .ID (0)
+ ) a10_hps_h2f_axi_master_agent (
+ .aclk (clk_0_clk_clk), // clk.clk
+ .aresetn (~a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
+ .write_cp_valid (a10_hps_h2f_axi_master_agent_write_cp_valid), // write_cp.valid
+ .write_cp_data (a10_hps_h2f_axi_master_agent_write_cp_data), // .data
+ .write_cp_startofpacket (a10_hps_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
+ .write_cp_endofpacket (a10_hps_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
+ .write_cp_ready (a10_hps_h2f_axi_master_agent_write_cp_ready), // .ready
+ .write_rp_valid (rsp_mux_src_valid), // write_rp.valid
+ .write_rp_data (rsp_mux_src_data), // .data
+ .write_rp_channel (rsp_mux_src_channel), // .channel
+ .write_rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
+ .write_rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
+ .write_rp_ready (rsp_mux_src_ready), // .ready
+ .read_cp_valid (a10_hps_h2f_axi_master_agent_read_cp_valid), // read_cp.valid
+ .read_cp_data (a10_hps_h2f_axi_master_agent_read_cp_data), // .data
+ .read_cp_startofpacket (a10_hps_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
+ .read_cp_endofpacket (a10_hps_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
+ .read_cp_ready (a10_hps_h2f_axi_master_agent_read_cp_ready), // .ready
+ .read_rp_valid (rsp_mux_001_src_valid), // read_rp.valid
+ .read_rp_data (rsp_mux_001_src_data), // .data
+ .read_rp_channel (rsp_mux_001_src_channel), // .channel
+ .read_rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
+ .read_rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
+ .read_rp_ready (rsp_mux_001_src_ready), // .ready
+ .awid (a10_hps_h2f_axi_master_awid), // altera_axi_slave.awid
+ .awaddr (a10_hps_h2f_axi_master_awaddr), // .awaddr
+ .awlen (a10_hps_h2f_axi_master_awlen), // .awlen
+ .awsize (a10_hps_h2f_axi_master_awsize), // .awsize
+ .awburst (a10_hps_h2f_axi_master_awburst), // .awburst
+ .awlock (a10_hps_h2f_axi_master_awlock), // .awlock
+ .awcache (a10_hps_h2f_axi_master_awcache), // .awcache
+ .awprot (a10_hps_h2f_axi_master_awprot), // .awprot
+ .awuser (a10_hps_h2f_axi_master_awuser), // .awuser
+ .awvalid (a10_hps_h2f_axi_master_awvalid), // .awvalid
+ .awready (a10_hps_h2f_axi_master_awready), // .awready
+ .wid (a10_hps_h2f_axi_master_wid), // .wid
+ .wdata (a10_hps_h2f_axi_master_wdata), // .wdata
+ .wstrb (a10_hps_h2f_axi_master_wstrb), // .wstrb
+ .wlast (a10_hps_h2f_axi_master_wlast), // .wlast
+ .wvalid (a10_hps_h2f_axi_master_wvalid), // .wvalid
+ .wready (a10_hps_h2f_axi_master_wready), // .wready
+ .bid (a10_hps_h2f_axi_master_bid), // .bid
+ .bresp (a10_hps_h2f_axi_master_bresp), // .bresp
+ .bvalid (a10_hps_h2f_axi_master_bvalid), // .bvalid
+ .bready (a10_hps_h2f_axi_master_bready), // .bready
+ .arid (a10_hps_h2f_axi_master_arid), // .arid
+ .araddr (a10_hps_h2f_axi_master_araddr), // .araddr
+ .arlen (a10_hps_h2f_axi_master_arlen), // .arlen
+ .arsize (a10_hps_h2f_axi_master_arsize), // .arsize
+ .arburst (a10_hps_h2f_axi_master_arburst), // .arburst
+ .arlock (a10_hps_h2f_axi_master_arlock), // .arlock
+ .arcache (a10_hps_h2f_axi_master_arcache), // .arcache
+ .arprot (a10_hps_h2f_axi_master_arprot), // .arprot
+ .aruser (a10_hps_h2f_axi_master_aruser), // .aruser
+ .arvalid (a10_hps_h2f_axi_master_arvalid), // .arvalid
+ .arready (a10_hps_h2f_axi_master_arready), // .arready
+ .rid (a10_hps_h2f_axi_master_rid), // .rid
+ .rdata (a10_hps_h2f_axi_master_rdata), // .rdata
+ .rresp (a10_hps_h2f_axi_master_rresp), // .rresp
+ .rlast (a10_hps_h2f_axi_master_rlast), // .rlast
+ .rvalid (a10_hps_h2f_axi_master_rvalid), // .rvalid
+ .rready (a10_hps_h2f_axi_master_rready), // .rready
+ .awqos (4'b0000), // (terminated)
+ .arqos (4'b0000), // (terminated)
+ .awregion (4'b0000), // (terminated)
+ .arregion (4'b0000), // (terminated)
+ .wuser (1'b0), // (terminated)
+ .ruser (), // (terminated)
+ .buser () // (terminated)
+ );
+
+ altera_merlin_slave_agent #(
+ .PKT_ORI_BURST_SIZE_H (120),
+ .PKT_ORI_BURST_SIZE_L (118),
+ .PKT_RESPONSE_STATUS_H (117),
+ .PKT_RESPONSE_STATUS_L (116),
+ .PKT_BURST_SIZE_H (92),
+ .PKT_BURST_SIZE_L (90),
+ .PKT_TRANS_LOCK (72),
+ .PKT_BEGIN_BURST (101),
+ .PKT_PROTECTION_H (111),
+ .PKT_PROTECTION_L (109),
+ .PKT_BURSTWRAP_H (89),
+ .PKT_BURSTWRAP_L (82),
+ .PKT_BYTE_CNT_H (81),
+ .PKT_BYTE_CNT_L (74),
+ .PKT_ADDR_H (67),
+ .PKT_ADDR_L (36),
+ .PKT_TRANS_COMPRESSED_READ (68),
+ .PKT_TRANS_POSTED (69),
+ .PKT_TRANS_WRITE (70),
+ .PKT_TRANS_READ (71),
+ .PKT_DATA_H (31),
+ .PKT_DATA_L (0),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_SRC_ID_H (103),
+ .PKT_SRC_ID_L (103),
+ .PKT_DEST_ID_H (104),
+ .PKT_DEST_ID_L (104),
+ .PKT_SYMBOL_W (8),
+ .ST_CHANNEL_W (2),
+ .ST_DATA_W (121),
+ .AVS_BURSTCOUNT_W (3),
+ .SUPPRESS_0_BYTEEN_CMD (1),
+ .PREVENT_FIFO_OVERFLOW (1),
+ .USE_READRESPONSE (0),
+ .USE_WRITERESPONSE (0),
+ .ECC_ENABLE (0)
+ ) eth_tse_0_control_port_agent (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .m0_address (eth_tse_0_control_port_agent_m0_address), // m0.address
+ .m0_burstcount (eth_tse_0_control_port_agent_m0_burstcount), // .burstcount
+ .m0_byteenable (eth_tse_0_control_port_agent_m0_byteenable), // .byteenable
+ .m0_debugaccess (eth_tse_0_control_port_agent_m0_debugaccess), // .debugaccess
+ .m0_lock (eth_tse_0_control_port_agent_m0_lock), // .lock
+ .m0_readdata (eth_tse_0_control_port_agent_m0_readdata), // .readdata
+ .m0_readdatavalid (eth_tse_0_control_port_agent_m0_readdatavalid), // .readdatavalid
+ .m0_read (eth_tse_0_control_port_agent_m0_read), // .read
+ .m0_waitrequest (eth_tse_0_control_port_agent_m0_waitrequest), // .waitrequest
+ .m0_writedata (eth_tse_0_control_port_agent_m0_writedata), // .writedata
+ .m0_write (eth_tse_0_control_port_agent_m0_write), // .write
+ .rp_endofpacket (eth_tse_0_control_port_agent_rp_endofpacket), // rp.endofpacket
+ .rp_ready (eth_tse_0_control_port_agent_rp_ready), // .ready
+ .rp_valid (eth_tse_0_control_port_agent_rp_valid), // .valid
+ .rp_data (eth_tse_0_control_port_agent_rp_data), // .data
+ .rp_startofpacket (eth_tse_0_control_port_agent_rp_startofpacket), // .startofpacket
+ .cp_ready (eth_tse_0_control_port_burst_adapter_source0_ready), // cp.ready
+ .cp_valid (eth_tse_0_control_port_burst_adapter_source0_valid), // .valid
+ .cp_data (eth_tse_0_control_port_burst_adapter_source0_data), // .data
+ .cp_startofpacket (eth_tse_0_control_port_burst_adapter_source0_startofpacket), // .startofpacket
+ .cp_endofpacket (eth_tse_0_control_port_burst_adapter_source0_endofpacket), // .endofpacket
+ .cp_channel (eth_tse_0_control_port_burst_adapter_source0_channel), // .channel
+ .rf_sink_ready (eth_tse_0_control_port_agent_rsp_fifo_out_ready), // rf_sink.ready
+ .rf_sink_valid (eth_tse_0_control_port_agent_rsp_fifo_out_valid), // .valid
+ .rf_sink_startofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .rf_sink_endofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .rf_sink_data (eth_tse_0_control_port_agent_rsp_fifo_out_data), // .data
+ .rf_source_ready (eth_tse_0_control_port_agent_rf_source_ready), // rf_source.ready
+ .rf_source_valid (eth_tse_0_control_port_agent_rf_source_valid), // .valid
+ .rf_source_startofpacket (eth_tse_0_control_port_agent_rf_source_startofpacket), // .startofpacket
+ .rf_source_endofpacket (eth_tse_0_control_port_agent_rf_source_endofpacket), // .endofpacket
+ .rf_source_data (eth_tse_0_control_port_agent_rf_source_data), // .data
+ .rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
+ .rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
+ .rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
+ .rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
+ .rdata_fifo_src_ready (eth_tse_0_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
+ .rdata_fifo_src_valid (eth_tse_0_control_port_agent_rdata_fifo_src_valid), // .valid
+ .rdata_fifo_src_data (eth_tse_0_control_port_agent_rdata_fifo_src_data), // .data
+ .m0_response (2'b00), // (terminated)
+ .m0_writeresponsevalid (1'b0) // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (122),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (1),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (1),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) eth_tse_0_control_port_agent_rsp_fifo (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_data (eth_tse_0_control_port_agent_rf_source_data), // in.data
+ .in_valid (eth_tse_0_control_port_agent_rf_source_valid), // .valid
+ .in_ready (eth_tse_0_control_port_agent_rf_source_ready), // .ready
+ .in_startofpacket (eth_tse_0_control_port_agent_rf_source_startofpacket), // .startofpacket
+ .in_endofpacket (eth_tse_0_control_port_agent_rf_source_endofpacket), // .endofpacket
+ .out_data (eth_tse_0_control_port_agent_rsp_fifo_out_data), // out.data
+ .out_valid (eth_tse_0_control_port_agent_rsp_fifo_out_valid), // .valid
+ .out_ready (eth_tse_0_control_port_agent_rsp_fifo_out_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
+ .out_endofpacket (eth_tse_0_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ altera_avalon_sc_fifo #(
+ .SYMBOLS_PER_BEAT (1),
+ .BITS_PER_SYMBOL (34),
+ .FIFO_DEPTH (2),
+ .CHANNEL_WIDTH (0),
+ .ERROR_WIDTH (0),
+ .USE_PACKETS (0),
+ .USE_FILL_LEVEL (0),
+ .EMPTY_LATENCY (0),
+ .USE_MEMORY_BLOCKS (0),
+ .USE_STORE_FORWARD (0),
+ .USE_ALMOST_FULL_IF (0),
+ .USE_ALMOST_EMPTY_IF (0)
+ ) eth_tse_0_control_port_agent_rdata_fifo (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_data (eth_tse_0_control_port_agent_rdata_fifo_src_data), // in.data
+ .in_valid (eth_tse_0_control_port_agent_rdata_fifo_src_valid), // .valid
+ .in_ready (eth_tse_0_control_port_agent_rdata_fifo_src_ready), // .ready
+ .out_data (eth_tse_0_control_port_agent_rdata_fifo_out_data), // out.data
+ .out_valid (eth_tse_0_control_port_agent_rdata_fifo_out_valid), // .valid
+ .out_ready (eth_tse_0_control_port_agent_rdata_fifo_out_ready), // .ready
+ .csr_address (2'b00), // (terminated)
+ .csr_read (1'b0), // (terminated)
+ .csr_write (1'b0), // (terminated)
+ .csr_readdata (), // (terminated)
+ .csr_writedata (32'b00000000000000000000000000000000), // (terminated)
+ .almost_full_data (), // (terminated)
+ .almost_empty_data (), // (terminated)
+ .in_startofpacket (1'b0), // (terminated)
+ .in_endofpacket (1'b0), // (terminated)
+ .out_startofpacket (), // (terminated)
+ .out_endofpacket (), // (terminated)
+ .in_empty (1'b0), // (terminated)
+ .out_empty (), // (terminated)
+ .in_error (1'b0), // (terminated)
+ .out_error (), // (terminated)
+ .in_channel (1'b0), // (terminated)
+ .out_channel () // (terminated)
+ );
+
+ arria10_hps_altera_merlin_router_221_qfjs35a router (
+ .sink_ready (a10_hps_h2f_axi_master_agent_write_cp_ready), // sink.ready
+ .sink_valid (a10_hps_h2f_axi_master_agent_write_cp_valid), // .valid
+ .sink_data (a10_hps_h2f_axi_master_agent_write_cp_data), // .data
+ .sink_startofpacket (a10_hps_h2f_axi_master_agent_write_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (a10_hps_h2f_axi_master_agent_write_cp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_src_ready), // src.ready
+ .src_valid (router_src_valid), // .valid
+ .src_data (router_src_data), // .data
+ .src_channel (router_src_channel), // .channel
+ .src_startofpacket (router_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_src_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_router_221_qfjs35a router_001 (
+ .sink_ready (a10_hps_h2f_axi_master_agent_read_cp_ready), // sink.ready
+ .sink_valid (a10_hps_h2f_axi_master_agent_read_cp_valid), // .valid
+ .sink_data (a10_hps_h2f_axi_master_agent_read_cp_data), // .data
+ .sink_startofpacket (a10_hps_h2f_axi_master_agent_read_cp_startofpacket), // .startofpacket
+ .sink_endofpacket (a10_hps_h2f_axi_master_agent_read_cp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_001_src_ready), // src.ready
+ .src_valid (router_001_src_valid), // .valid
+ .src_data (router_001_src_data), // .data
+ .src_channel (router_001_src_channel), // .channel
+ .src_startofpacket (router_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_001_src_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_router_221_xe243si router_002 (
+ .sink_ready (eth_tse_0_control_port_agent_rp_ready), // sink.ready
+ .sink_valid (eth_tse_0_control_port_agent_rp_valid), // .valid
+ .sink_data (eth_tse_0_control_port_agent_rp_data), // .data
+ .sink_startofpacket (eth_tse_0_control_port_agent_rp_startofpacket), // .startofpacket
+ .sink_endofpacket (eth_tse_0_control_port_agent_rp_endofpacket), // .endofpacket
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (router_002_src_ready), // src.ready
+ .src_valid (router_002_src_valid), // .valid
+ .src_data (router_002_src_data), // .data
+ .src_channel (router_002_src_channel), // .channel
+ .src_startofpacket (router_002_src_startofpacket), // .startofpacket
+ .src_endofpacket (router_002_src_endofpacket) // .endofpacket
+ );
+
+ altera_merlin_burst_adapter #(
+ .PKT_ADDR_H (67),
+ .PKT_ADDR_L (36),
+ .PKT_BEGIN_BURST (101),
+ .PKT_BYTE_CNT_H (81),
+ .PKT_BYTE_CNT_L (74),
+ .PKT_BYTEEN_H (35),
+ .PKT_BYTEEN_L (32),
+ .PKT_BURST_SIZE_H (92),
+ .PKT_BURST_SIZE_L (90),
+ .PKT_BURST_TYPE_H (94),
+ .PKT_BURST_TYPE_L (93),
+ .PKT_BURSTWRAP_H (89),
+ .PKT_BURSTWRAP_L (82),
+ .PKT_TRANS_COMPRESSED_READ (68),
+ .PKT_TRANS_WRITE (70),
+ .PKT_TRANS_READ (71),
+ .OUT_NARROW_SIZE (0),
+ .IN_NARROW_SIZE (1),
+ .OUT_FIXED (0),
+ .OUT_COMPLETE_WRAP (0),
+ .ST_DATA_W (121),
+ .ST_CHANNEL_W (2),
+ .OUT_BYTE_CNT_H (76),
+ .OUT_BURSTWRAP_H (89),
+ .COMPRESSED_READ_SUPPORT (1),
+ .BYTEENABLE_SYNTHESIS (1),
+ .PIPE_INPUTS (0),
+ .NO_WRAP_SUPPORT (0),
+ .INCOMPLETE_WRAP_SUPPORT (0),
+ .BURSTWRAP_CONST_MASK (0),
+ .BURSTWRAP_CONST_VALUE (0),
+ .ADAPTER_VERSION ("13.1")
+ ) eth_tse_0_control_port_burst_adapter (
+ .clk (clk_0_clk_clk), // cr0.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
+ .sink0_valid (eth_tse_0_control_port_cmd_width_adapter_src_valid), // sink0.valid
+ .sink0_data (eth_tse_0_control_port_cmd_width_adapter_src_data), // .data
+ .sink0_channel (eth_tse_0_control_port_cmd_width_adapter_src_channel), // .channel
+ .sink0_startofpacket (eth_tse_0_control_port_cmd_width_adapter_src_startofpacket), // .startofpacket
+ .sink0_endofpacket (eth_tse_0_control_port_cmd_width_adapter_src_endofpacket), // .endofpacket
+ .sink0_ready (eth_tse_0_control_port_cmd_width_adapter_src_ready), // .ready
+ .source0_valid (eth_tse_0_control_port_burst_adapter_source0_valid), // source0.valid
+ .source0_data (eth_tse_0_control_port_burst_adapter_source0_data), // .data
+ .source0_channel (eth_tse_0_control_port_burst_adapter_source0_channel), // .channel
+ .source0_startofpacket (eth_tse_0_control_port_burst_adapter_source0_startofpacket), // .startofpacket
+ .source0_endofpacket (eth_tse_0_control_port_burst_adapter_source0_endofpacket), // .endofpacket
+ .source0_ready (eth_tse_0_control_port_burst_adapter_source0_ready) // .ready
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_72yhala cmd_demux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (router_src_ready), // sink.ready
+ .sink_channel (router_src_channel), // .channel
+ .sink_data (router_src_data), // .data
+ .sink_startofpacket (router_src_startofpacket), // .startofpacket
+ .sink_endofpacket (router_src_endofpacket), // .endofpacket
+ .sink_valid (router_src_valid), // .valid
+ .src0_ready (cmd_demux_src0_ready), // src0.ready
+ .src0_valid (cmd_demux_src0_valid), // .valid
+ .src0_data (cmd_demux_src0_data), // .data
+ .src0_channel (cmd_demux_src0_channel), // .channel
+ .src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_72yhala cmd_demux_001 (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (router_001_src_ready), // sink.ready
+ .sink_channel (router_001_src_channel), // .channel
+ .sink_data (router_001_src_data), // .data
+ .sink_startofpacket (router_001_src_startofpacket), // .startofpacket
+ .sink_endofpacket (router_001_src_endofpacket), // .endofpacket
+ .sink_valid (router_001_src_valid), // .valid
+ .src0_ready (cmd_demux_001_src0_ready), // src0.ready
+ .src0_valid (cmd_demux_001_src0_valid), // .valid
+ .src0_data (cmd_demux_001_src0_data), // .data
+ .src0_channel (cmd_demux_001_src0_channel), // .channel
+ .src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_vzucqyy cmd_mux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (cmd_mux_src_ready), // src.ready
+ .src_valid (cmd_mux_src_valid), // .valid
+ .src_data (cmd_mux_src_data), // .data
+ .src_channel (cmd_mux_src_channel), // .channel
+ .src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
+ .src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
+ .sink0_ready (cmd_demux_src0_ready), // sink0.ready
+ .sink0_valid (cmd_demux_src0_valid), // .valid
+ .sink0_channel (cmd_demux_src0_channel), // .channel
+ .sink0_data (cmd_demux_src0_data), // .data
+ .sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
+ .sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
+ .sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
+ .sink1_valid (cmd_demux_001_src0_valid), // .valid
+ .sink1_channel (cmd_demux_001_src0_channel), // .channel
+ .sink1_data (cmd_demux_001_src0_data), // .data
+ .sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
+ .sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_demultiplexer_221_e3m23ka rsp_demux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .sink_ready (eth_tse_0_control_port_rsp_width_adapter_src_ready), // sink.ready
+ .sink_channel (eth_tse_0_control_port_rsp_width_adapter_src_channel), // .channel
+ .sink_data (eth_tse_0_control_port_rsp_width_adapter_src_data), // .data
+ .sink_startofpacket (eth_tse_0_control_port_rsp_width_adapter_src_startofpacket), // .startofpacket
+ .sink_endofpacket (eth_tse_0_control_port_rsp_width_adapter_src_endofpacket), // .endofpacket
+ .sink_valid (eth_tse_0_control_port_rsp_width_adapter_src_valid), // .valid
+ .src0_ready (rsp_demux_src0_ready), // src0.ready
+ .src0_valid (rsp_demux_src0_valid), // .valid
+ .src0_data (rsp_demux_src0_data), // .data
+ .src0_channel (rsp_demux_src0_channel), // .channel
+ .src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
+ .src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
+ .src1_ready (rsp_demux_src1_ready), // src1.ready
+ .src1_valid (rsp_demux_src1_valid), // .valid
+ .src1_data (rsp_demux_src1_data), // .data
+ .src1_channel (rsp_demux_src1_channel), // .channel
+ .src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
+ .src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_huj2kiy rsp_mux (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (rsp_mux_src_ready), // src.ready
+ .src_valid (rsp_mux_src_valid), // .valid
+ .src_data (rsp_mux_src_data), // .data
+ .src_channel (rsp_mux_src_channel), // .channel
+ .src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
+ .sink0_ready (rsp_demux_src0_ready), // sink0.ready
+ .sink0_valid (rsp_demux_src0_valid), // .valid
+ .sink0_channel (rsp_demux_src0_channel), // .channel
+ .sink0_data (rsp_demux_src0_data), // .data
+ .sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
+ .sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
+ );
+
+ arria10_hps_altera_merlin_multiplexer_221_huj2kiy rsp_mux_001 (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .src_ready (rsp_mux_001_src_ready), // src.ready
+ .src_valid (rsp_mux_001_src_valid), // .valid
+ .src_data (rsp_mux_001_src_data), // .data
+ .src_channel (rsp_mux_001_src_channel), // .channel
+ .src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
+ .src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
+ .sink0_ready (rsp_demux_src1_ready), // sink0.ready
+ .sink0_valid (rsp_demux_src1_valid), // .valid
+ .sink0_channel (rsp_demux_src1_channel), // .channel
+ .sink0_data (rsp_demux_src1_data), // .data
+ .sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
+ .sink0_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
+ );
+
+ altera_merlin_width_adapter #(
+ .IN_PKT_ADDR_H (67),
+ .IN_PKT_ADDR_L (36),
+ .IN_PKT_DATA_H (31),
+ .IN_PKT_DATA_L (0),
+ .IN_PKT_BYTEEN_H (35),
+ .IN_PKT_BYTEEN_L (32),
+ .IN_PKT_BYTE_CNT_H (81),
+ .IN_PKT_BYTE_CNT_L (74),
+ .IN_PKT_TRANS_COMPRESSED_READ (68),
+ .IN_PKT_TRANS_WRITE (70),
+ .IN_PKT_BURSTWRAP_H (89),
+ .IN_PKT_BURSTWRAP_L (82),
+ .IN_PKT_BURST_SIZE_H (92),
+ .IN_PKT_BURST_SIZE_L (90),
+ .IN_PKT_RESPONSE_STATUS_H (117),
+ .IN_PKT_RESPONSE_STATUS_L (116),
+ .IN_PKT_TRANS_EXCLUSIVE (73),
+ .IN_PKT_BURST_TYPE_H (94),
+ .IN_PKT_BURST_TYPE_L (93),
+ .IN_PKT_ORI_BURST_SIZE_L (118),
+ .IN_PKT_ORI_BURST_SIZE_H (120),
+ .IN_ST_DATA_W (121),
+ .OUT_PKT_ADDR_H (103),
+ .OUT_PKT_ADDR_L (72),
+ .OUT_PKT_DATA_H (63),
+ .OUT_PKT_DATA_L (0),
+ .OUT_PKT_BYTEEN_H (71),
+ .OUT_PKT_BYTEEN_L (64),
+ .OUT_PKT_BYTE_CNT_H (117),
+ .OUT_PKT_BYTE_CNT_L (110),
+ .OUT_PKT_TRANS_COMPRESSED_READ (104),
+ .OUT_PKT_BURST_SIZE_H (128),
+ .OUT_PKT_BURST_SIZE_L (126),
+ .OUT_PKT_RESPONSE_STATUS_H (153),
+ .OUT_PKT_RESPONSE_STATUS_L (152),
+ .OUT_PKT_TRANS_EXCLUSIVE (109),
+ .OUT_PKT_BURST_TYPE_H (130),
+ .OUT_PKT_BURST_TYPE_L (129),
+ .OUT_PKT_ORI_BURST_SIZE_L (154),
+ .OUT_PKT_ORI_BURST_SIZE_H (156),
+ .OUT_ST_DATA_W (157),
+ .ST_CHANNEL_W (2),
+ .OPTIMIZE_FOR_RSP (0),
+ .RESPONSE_PATH (1),
+ .CONSTANT_BURST_SIZE (0),
+ .PACKING (1),
+ .ENABLE_ADDRESS_ALIGNMENT (1)
+ ) eth_tse_0_control_port_rsp_width_adapter (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_valid (router_002_src_valid), // sink.valid
+ .in_channel (router_002_src_channel), // .channel
+ .in_startofpacket (router_002_src_startofpacket), // .startofpacket
+ .in_endofpacket (router_002_src_endofpacket), // .endofpacket
+ .in_ready (router_002_src_ready), // .ready
+ .in_data (router_002_src_data), // .data
+ .out_endofpacket (eth_tse_0_control_port_rsp_width_adapter_src_endofpacket), // src.endofpacket
+ .out_data (eth_tse_0_control_port_rsp_width_adapter_src_data), // .data
+ .out_channel (eth_tse_0_control_port_rsp_width_adapter_src_channel), // .channel
+ .out_valid (eth_tse_0_control_port_rsp_width_adapter_src_valid), // .valid
+ .out_ready (eth_tse_0_control_port_rsp_width_adapter_src_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_rsp_width_adapter_src_startofpacket), // .startofpacket
+ .in_command_size_data (3'b000) // (terminated)
+ );
+
+ altera_merlin_width_adapter #(
+ .IN_PKT_ADDR_H (103),
+ .IN_PKT_ADDR_L (72),
+ .IN_PKT_DATA_H (63),
+ .IN_PKT_DATA_L (0),
+ .IN_PKT_BYTEEN_H (71),
+ .IN_PKT_BYTEEN_L (64),
+ .IN_PKT_BYTE_CNT_H (117),
+ .IN_PKT_BYTE_CNT_L (110),
+ .IN_PKT_TRANS_COMPRESSED_READ (104),
+ .IN_PKT_TRANS_WRITE (106),
+ .IN_PKT_BURSTWRAP_H (125),
+ .IN_PKT_BURSTWRAP_L (118),
+ .IN_PKT_BURST_SIZE_H (128),
+ .IN_PKT_BURST_SIZE_L (126),
+ .IN_PKT_RESPONSE_STATUS_H (153),
+ .IN_PKT_RESPONSE_STATUS_L (152),
+ .IN_PKT_TRANS_EXCLUSIVE (109),
+ .IN_PKT_BURST_TYPE_H (130),
+ .IN_PKT_BURST_TYPE_L (129),
+ .IN_PKT_ORI_BURST_SIZE_L (154),
+ .IN_PKT_ORI_BURST_SIZE_H (156),
+ .IN_ST_DATA_W (157),
+ .OUT_PKT_ADDR_H (67),
+ .OUT_PKT_ADDR_L (36),
+ .OUT_PKT_DATA_H (31),
+ .OUT_PKT_DATA_L (0),
+ .OUT_PKT_BYTEEN_H (35),
+ .OUT_PKT_BYTEEN_L (32),
+ .OUT_PKT_BYTE_CNT_H (81),
+ .OUT_PKT_BYTE_CNT_L (74),
+ .OUT_PKT_TRANS_COMPRESSED_READ (68),
+ .OUT_PKT_BURST_SIZE_H (92),
+ .OUT_PKT_BURST_SIZE_L (90),
+ .OUT_PKT_RESPONSE_STATUS_H (117),
+ .OUT_PKT_RESPONSE_STATUS_L (116),
+ .OUT_PKT_TRANS_EXCLUSIVE (73),
+ .OUT_PKT_BURST_TYPE_H (94),
+ .OUT_PKT_BURST_TYPE_L (93),
+ .OUT_PKT_ORI_BURST_SIZE_L (118),
+ .OUT_PKT_ORI_BURST_SIZE_H (120),
+ .OUT_ST_DATA_W (121),
+ .ST_CHANNEL_W (2),
+ .OPTIMIZE_FOR_RSP (0),
+ .RESPONSE_PATH (0),
+ .CONSTANT_BURST_SIZE (0),
+ .PACKING (0),
+ .ENABLE_ADDRESS_ALIGNMENT (1)
+ ) eth_tse_0_control_port_cmd_width_adapter (
+ .clk (clk_0_clk_clk), // clk.clk
+ .reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // clk_reset.reset
+ .in_valid (cmd_mux_src_valid), // sink.valid
+ .in_channel (cmd_mux_src_channel), // .channel
+ .in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
+ .in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
+ .in_ready (cmd_mux_src_ready), // .ready
+ .in_data (cmd_mux_src_data), // .data
+ .out_endofpacket (eth_tse_0_control_port_cmd_width_adapter_src_endofpacket), // src.endofpacket
+ .out_data (eth_tse_0_control_port_cmd_width_adapter_src_data), // .data
+ .out_channel (eth_tse_0_control_port_cmd_width_adapter_src_channel), // .channel
+ .out_valid (eth_tse_0_control_port_cmd_width_adapter_src_valid), // .valid
+ .out_ready (eth_tse_0_control_port_cmd_width_adapter_src_ready), // .ready
+ .out_startofpacket (eth_tse_0_control_port_cmd_width_adapter_src_startofpacket), // .startofpacket
+ .in_command_size_data (3'b000) // (terminated)
+ );
+
+ arria10_hps_altera_avalon_st_adapter_221_36tuu3a #(
+ .inBitsPerSymbol (34),
+ .inUsePackets (0),
+ .inDataWidth (34),
+ .inChannelWidth (0),
+ .inErrorWidth (0),
+ .inUseEmptyPort (0),
+ .inUseValid (1),
+ .inUseReady (1),
+ .inReadyLatency (0),
+ .outDataWidth (34),
+ .outChannelWidth (0),
+ .outErrorWidth (1),
+ .outUseEmptyPort (0),
+ .outUseValid (1),
+ .outUseReady (1),
+ .outReadyLatency (0)
+ ) avalon_st_adapter (
+ .in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
+ .in_rst_0_reset (a10_hps_h2f_axi_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
+ .in_0_data (eth_tse_0_control_port_agent_rdata_fifo_out_data), // in_0.data
+ .in_0_valid (eth_tse_0_control_port_agent_rdata_fifo_out_valid), // .valid
+ .in_0_ready (eth_tse_0_control_port_agent_rdata_fifo_out_ready), // .ready
+ .out_0_data (avalon_st_adapter_out_0_data), // out_0.data
+ .out_0_valid (avalon_st_adapter_out_0_valid), // .valid
+ .out_0_ready (avalon_st_adapter_out_0_ready), // .ready
+ .out_0_error (avalon_st_adapter_out_0_error) // .error
+ );
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_yw4vjdi_cfg.v b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_yw4vjdi_cfg.v
new file mode 100644
index 0000000000000000000000000000000000000000..2f79f1f4938795d0140427fe228ec25e925071f5
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_mm_interconnect_221/synth/arria10_hps_altera_mm_interconnect_221_yw4vjdi_cfg.v
@@ -0,0 +1,22 @@
+config arria10_hps_altera_mm_interconnect_221_yw4vjdi_cfg;
+ design arria10_hps_altera_mm_interconnect_221_yw4vjdi;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.eth_tse_0_control_port_translator use arria10_hps_altera_merlin_slave_translator_221.altera_merlin_slave_translator;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.a10_hps_h2f_axi_master_agent use arria10_hps_altera_merlin_axi_master_ni_221.altera_merlin_axi_master_ni;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.eth_tse_0_control_port_agent use arria10_hps_altera_merlin_slave_agent_221.altera_merlin_slave_agent;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.eth_tse_0_control_port_agent_rsp_fifo use arria10_hps_altera_avalon_sc_fifo_221.altera_avalon_sc_fifo;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.eth_tse_0_control_port_agent_rdata_fifo use arria10_hps_altera_avalon_sc_fifo_221.altera_avalon_sc_fifo;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.router use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_qfjs35a;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.router_001 use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_qfjs35a;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.router_002 use arria10_hps_altera_merlin_router_221.arria10_hps_altera_merlin_router_221_xe243si;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.eth_tse_0_control_port_burst_adapter use arria10_hps_altera_merlin_burst_adapter_221.altera_merlin_burst_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.cmd_demux use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_72yhala;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.cmd_demux_001 use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_72yhala;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.cmd_mux use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_vzucqyy;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.rsp_demux use arria10_hps_altera_merlin_demultiplexer_221.arria10_hps_altera_merlin_demultiplexer_221_e3m23ka;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.rsp_mux use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_huj2kiy;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.rsp_mux_001 use arria10_hps_altera_merlin_multiplexer_221.arria10_hps_altera_merlin_multiplexer_221_huj2kiy;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.eth_tse_0_control_port_rsp_width_adapter use arria10_hps_altera_merlin_width_adapter_221.altera_merlin_width_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.eth_tse_0_control_port_cmd_width_adapter use arria10_hps_altera_merlin_width_adapter_221.altera_merlin_width_adapter;
+ instance arria10_hps_altera_mm_interconnect_221_yw4vjdi.avalon_st_adapter use arria10_hps_altera_avalon_st_adapter_221.arria10_hps_altera_avalon_st_adapter_221_36tuu3a;
+endconfig
+
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/a10_avmm_h.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/a10_avmm_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..73f6f7157e844104fe84b5f88f316dcca727e848
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/a10_avmm_h.sv
@@ -0,0 +1,163 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+package a10_avmm_h;
+
+ // localparam to define unused bus
+ localparam RD_UNUSED = 8'h0;
+
+ // localparams for common capability registers
+ localparam A10_XR_ADDR_ID_0 = 9'h0;
+ localparam A10_XR_ADDR_ID_1 = 9'h1;
+ localparam A10_XR_ADDR_ID_2 = 9'h2;
+ localparam A10_XR_ADDR_ID_3 = 9'h3;
+ localparam A10_XR_ADDR_STATUS_EN = 9'h4;
+ localparam A10_XR_ADDR_CONTROL_EN = 9'h5;
+ // Reserve Address 9'h6 to 9'hF for common capablities
+
+ // native phy capability
+ localparam A10_XR_ADDR_NAT_CHNLS = 9'h10;
+ localparam A10_XR_ADDR_NAT_CHNL_NUM = 9'h11;
+ localparam A10_XR_ADDR_NAT_DUPLEX = 9'h12;
+ localparam A10_XR_ADDR_NAT_PRBS_EN = 9'h13;
+ localparam A10_XR_ADDR_NAT_ODI_EN = 9'h14;
+
+ // pll ip capability
+ localparam A10_XR_ADDR_PLL_MCGB_EN = 9'h10;
+
+ // localparams for csr for pll locked and cal busy
+ localparam A10_XR_ADDR_GP_PLL_LOCK = 9'h80;
+ localparam A10_XR_OFFSET_GP_LOCK = 0;
+ localparam A10_XR_OFFSET_GP_CAL_BUSY = 1;
+ localparam A10_XR_OFFSET_GP_AVMM_BUSY = 2;
+ localparam A10_XR_OFFSET_LOCK_UNUSED = 3;
+ localparam A10_XR_LOCK_UNUSED_LEN = 5;
+
+ // localparams for pll powerdown
+ localparam A10_XR_ADDR_GP_PLL_RST = 9'hE0;
+ localparam A10_XR_OFFSET_PLL_RST = 0;
+ localparam A10_XR_OFFSET_PLL_RST_OVR = 1;
+ localparam A10_XR_OFFSET_PLL_RST_UNUSED = 2;
+ localparam A10_XR_PLL_RST_UNUSED_LEN = 6;
+
+ // localparams for csr for lock to ref and lock to data
+ localparam A10_XR_ADDR_GP_RD_LTR = 9'h80;
+ localparam A10_XR_OFFSET_RD_LTD = 0;
+ localparam A10_XR_OFFSET_RD_LTR = 1;
+ localparam A10_XR_OFFSET_LTR_UNUSED = 2;
+ localparam A10_XR_LTR_UNUSED_LEN = 6;
+
+ // localparams for csr for cal busy
+ localparam A10_XR_ADDR_GP_CAL_BUSY = 9'h81;
+ localparam A10_XR_OFFSET_TX_CAL_BUSY = 0;
+ localparam A10_XR_OFFSET_RX_CAL_BUSY = 1;
+ localparam A10_XR_OFFSET_AVMM_BUSY = 2;
+ localparam A10_XR_OFFSET_CAL_DUMMY = 3;
+ localparam A10_XR_OFFSET_TX_CAL_MASK = 4;
+ localparam A10_XR_OFFSET_RX_CAL_MASK = 5;
+ localparam A10_XR_OFFSET_CAL_UNUSED = 6;
+ localparam A10_XR_CAL_UNUSED_LEN = 2;
+
+ // localparams for setting lock to ref and lock to data
+ localparam A10_XR_ADDR_GP_SET_LTR = 9'hE0;
+ localparam A10_XR_OFFSET_SET_LTD = 0;
+ localparam A10_XR_OFFSET_SET_LTR = 1;
+ localparam A10_XR_OFFSET_SET_LTD_OVR = 2;
+ localparam A10_XR_OFFSET_SET_LTR_OVR = 3;
+ localparam A10_XR_OFFSET_SET_LTR_UNUSED = 4;
+ localparam A10_XR_SET_LTR_UNUSED_LEN = 4;
+
+ // localparams for setting loopback
+ localparam A10_XR_ADDR_GP_LPBK = 9'hE1;
+ localparam A10_XR_OFFSET_LPBK = 0;
+ localparam A10_XR_OFFSET_LPBK_UNUSED = 1;
+ localparam A10_XR_LPBK_UNUSED_LEN = 7;
+
+ // localparams for setting channel resets
+ localparam A10_XR_ADDR_CHNL_RESET = 9'hE2;
+ localparam A10_XR_OFFSET_RX_ANA = 0;
+ localparam A10_XR_OFFSET_RX_DIG = 1;
+ localparam A10_XR_OFFSET_TX_ANA = 2;
+ localparam A10_XR_OFFSET_TX_DIG = 3;
+ localparam A10_XR_OFFSET_RX_ANA_OVR = 4;
+ localparam A10_XR_OFFSET_RX_DIG_OVR = 5;
+ localparam A10_XR_OFFSET_TX_ANA_OVR = 6;
+ localparam A10_XR_OFFSET_TX_DIG_OVR = 7;
+
+ // localparams for prbs addresses
+ localparam A10_XR_ADDR_PRBS_CTRL = 9'h100;
+ localparam A10_XR_ADDR_PRBS_ERR_0 = 9'h101;
+ localparam A10_XR_ADDR_PRBS_ERR_1 = 9'h102;
+ localparam A10_XR_ADDR_PRBS_ERR_2 = 9'h103;
+ localparam A10_XR_ADDR_PRBS_ERR_3 = 9'h104;
+ localparam A10_XR_ADDR_PRBS_ERR_4 = 9'h105;
+ localparam A10_XR_ADDR_PRBS_ERR_5 = 9'h106;
+ localparam A10_XR_ADDR_PRBS_ERR_6 = 9'h107;
+ localparam A10_XR_ADDR_PRBS_BIT_0 = 9'h10D;
+ localparam A10_XR_ADDR_PRBS_BIT_1 = 9'h10E;
+ localparam A10_XR_ADDR_PRBS_BIT_2 = 9'h10F;
+ localparam A10_XR_ADDR_PRBS_BIT_3 = 9'h110;
+ localparam A10_XR_ADDR_PRBS_BIT_4 = 9'h111;
+ localparam A10_XR_ADDR_PRBS_BIT_5 = 9'h112;
+ localparam A10_XR_ADDR_PRBS_BIT_6 = 9'h113;
+
+ // localparams for prbs bit offsets
+ localparam A10_XR_OFFSET_PRBS_EN = 0;
+ localparam A10_XR_OFFSET_PRBS_RESET = 1;
+ localparam A10_XR_OFFSET_PRBS_SNAP = 2;
+ localparam A10_XR_OFFSET_PRBS_DONE = 3;
+ localparam A10_XR_OFFSET_PRBS_UNUSED = 4;
+ localparam A10_XR_PRBS_UNUSED_LEN = 4;
+
+ // localparams for odi addresses
+ localparam A10_XR_ADDR_ODI_CTRL = 9'h120;
+ localparam A10_XR_ADDR_ODI_ERR_0 = 9'h121;
+ localparam A10_XR_ADDR_ODI_ERR_1 = 9'h122;
+ localparam A10_XR_ADDR_ODI_ERR_2 = 9'h123;
+ localparam A10_XR_ADDR_ODI_ERR_3 = 9'h124;
+ localparam A10_XR_ADDR_ODI_ERR_4 = 9'h125;
+ localparam A10_XR_ADDR_ODI_ERR_5 = 9'h126;
+ localparam A10_XR_ADDR_ODI_ERR_6 = 9'h127;
+ localparam A10_XR_ADDR_ODI_BIT_0 = 9'h12D;
+ localparam A10_XR_ADDR_ODI_BIT_1 = 9'h12E;
+ localparam A10_XR_ADDR_ODI_BIT_2 = 9'h12F;
+ localparam A10_XR_ADDR_ODI_BIT_3 = 9'h130;
+ localparam A10_XR_ADDR_ODI_BIT_4 = 9'h131;
+ localparam A10_XR_ADDR_ODI_BIT_5 = 9'h132;
+ localparam A10_XR_ADDR_ODI_BIT_6 = 9'h133;
+
+ // localparams for odi bit offsets
+ localparam A10_XR_OFFSET_ODI_EN = 0;
+ localparam A10_XR_OFFSET_ODI_RESET = 1;
+ localparam A10_XR_OFFSET_ODI_SNAP = 2;
+ localparam A10_XR_OFFSET_ODI_DONE = 3;
+ localparam A10_XR_OFFSET_ODI_UNUSED = 4;
+ localparam A10_XR_ODI_UNUSED_LEN = 4;
+
+ // localparams for embedded reconfig addresses
+ // Control reg and offsets
+ localparam A10_XR_ADDR_EMBED_RCFG_CTRL = 9'h140;
+ localparam A10_XR_OFFSET_EMBED_RCFG_CFG_SEL = 0;
+ localparam A10_XR_EMBED_RCFG_CFG_SEL_LEN = 6; //bits [5:0] are alloted for cfg_sel even though GUI currently only supports upto 8 profiles.
+
+ localparam A10_XR_OFFSET_EMBED_RCFG_BCAST_EN = 6;
+ localparam A10_XR_OFFSET_EMBED_RCFG_CFG_LOAD = 7;
+
+ // Status reg and offsets
+ localparam A10_XR_ADDR_EMBED_RCFG_STATUS = 9'h141;
+ localparam A10_XR_OFFSET_EMBED_RCFG_STRM_BUSY = 0;
+
+
+endpackage
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/a10_xcvr_atx_pll.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/a10_xcvr_atx_pll.sv
new file mode 100644
index 0000000000000000000000000000000000000000..297b0674fa6af13cfd15f77436aaa6a2a77cadc3
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/a10_xcvr_atx_pll.sv
@@ -0,0 +1,527 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+//------------------------------------------------------------------
+// filename: a10_xcvr_atx_pll.sv
+//
+// Description : instantiates lc-pll atoms
+//
+// Limitation : Intended for NightFury
+//
+// Copyright (c) Altera Corporation 1997-2012
+// All rights reserved
+//-------------------------------------------------------------------
+//
+// NOTEs
+// - comments marked with \OPEN means there is an issue that needs to be resolved but cannot be done due to lack of information.
+// - comments marked with \TODO means there is an issue that needs to be resolved and there is enough information already for the issue to be resolved.
+//
+//-------------------------------------------------------------------
+
+
+// \OPEN should we remove timescale?
+`timescale 1 ns / 1 ns
+
+module a10_xcvr_atx_pll
+#(
+ // \OPEN previous atx atom had hclk_buffer_enable [CM: will find out]
+
+ parameter enable_debug_info = "true", // \RANGE false|true \NOTE this is simulation-only parameter, for debug purpose only
+ parameter atx_pll_regulator_bypass = "reg_enable",
+ parameter atx_pll_pfd_delay_compensation = "normal_delay",
+ parameter atx_pll_xcpvco_xchgpmplf_cp_current_boost = "normal_setting",
+ parameter atx_pll_pfd_pulse_width = "pulse_width_setting0",
+
+ parameter atx_pll_l_counter_enable = "true", // \RANGE true (false)
+ parameter atx_pll_fb_select = "direct_fb", // \RANGE "direct_fb" "iqtxrxclk_fb"
+ parameter atx_pll_bonding_mode = "cpri_bonding", // \RANGE (cpri_bonding) pll_bonding \NOTE CPRI is for external feedback mode without feedback compensation bonding and PLL is for external feedback with feedback compensation bonding
+ parameter atx_pll_prot_mode = "basic_tx", // \RANGE "unused" (basic_tx) "basic_kr_tx" "pcie_gen1_tx" "pcie_gen2_tx" "pcie_gen3_tx" "pcie_gen4_tx" "cei_tx" "qpi_tx" "cpri_tx" "fc_tx" "srio_tx" "gpon_tx" "sdi_tx" "sata_tx" "xaui_tx" "obsai_tx" "gige_tx" "higig_tx" "sonet_tx" "sfp_tx" "xfp_tx" "sfi_tx"
+ parameter atx_pll_silicon_rev = "20nm5es", // \RANGE (20nm5es) "20nm5es2" "20nm4" "20nm3" "20nm4qor" "20nm2" "20nm1"
+ parameter atx_pll_bw_sel = "low", // \RANGE (low) medium high
+ parameter atx_pll_dsm_mode = "dsm_mode_integer", // \RANGE (dsm_mode_integer) dsm_mode_phase
+ parameter atx_pll_reference_clock_frequency = "0 ps",
+ parameter atx_pll_output_clock_frequency = "0 ps",
+ parameter atx_pll_m_counter = 1, // \RANGE (1) 2 3 4 5 6 8 9 10 12 15 16 18 20 24 25 30 32 36 40 48 50 60 64 80 100
+ parameter atx_pll_ref_clk_div = 1, // \RANGE (1) 2 4 8
+ parameter atx_pll_l_counter = 1, // \RANGE (1) 2 4 8 16
+ parameter atx_pll_dsm_fractional_division = 32'b1, // (32'b1) bitvec
+ parameter atx_pll_tank_band = "lc_band0", // \RANGE (lc_band0) lc_band1 lc_band2 lc_band3 lc_band4 lc_band5 lc_band6 lc_band7
+ parameter atx_pll_tank_sel = "lctank0", // \RANGE (lctank0) lctank1 lctank2
+ parameter atx_pll_hclk_divide = 1, // \RANGE (1) 40 50
+ parameter atx_pll_cgb_div = 1, // \RANGE (1) 2 4 8
+ parameter atx_pll_pma_width = 8, // \RANGE (8) 10 16 20 32 40 64
+
+ parameter atx_pll_primary_use = "hssi_x1",
+ parameter atx_pll_lc_mode = "lccmu_normal", // \RANGE (lccmu_pd) lccmu_normal lccmu_reset
+ parameter atx_pll_lc_atb = "atb_selectdisable", // \RANGE (atb_selectdisable) atb_select0 atb_select1 atb_select2 atb_select3 atb_select4 atb_select5 atb_select6 atb_select7 atb_select8 atb_select9 atb_select10 atb_select11 atb_select12 atb_select13 atb_select14 atb_select15 atb_select16 atb_select17 atb_select18 atb_select19 atb_select20 atb_select21 atb_select22 atb_select23 atb_select24 atb_select25 atb_select26 atb_select27 atb_select28 atb_select29 atb_select30
+ parameter atx_pll_cp_compensation_enable = "true", // \RANGE false (true)
+ parameter atx_pll_cp_current_setting = "cp_current_setting0", // \RANGE (cp_current_setting0) cp_current_setting1 cp_current_setting2 cp_current_setting3 cp_current_setting4 cp_current_setting5 cp_current_setting6 cp_current_setting7 cp_current_setting8 cp_current_setting9 cp_current_setting10 cp_current_setting11
+ parameter atx_pll_cp_testmode = "cp_normal", // \RANGE (cp_normal) cp_test_up cp_test_dn cp_tristate
+ parameter atx_pll_cp_lf_3rd_pole_freq = "lf_3rd_pole_setting0", // \RANGE (lf_3rd_pole_setting0) lf_3rd_pole_setting1 lf_3rd_pole_setting2 lf_3rd_pole_setting3
+ parameter atx_pll_cp_lf_order = "lf_2nd_order", // \RANGE (lf_2nd_order) lf_3rd_order lf_4th_order
+ parameter atx_pll_lf_resistance = "lf_setting0", // \RANGE (lf_setting0) lf_setting1 lf_setting2 lf_setting3
+ parameter atx_pll_lf_ripplecap = "lf_ripple_cap_0", // \RANGE lf_no_ripple (lf_ripple_cap_0) lf_ripplecap_1
+ parameter atx_pll_d2a_voltage = "d2a_disable", // \RANGE d2a_setting_0 d2a_setting_1 d2a_setting_2 d2a_setting_3 d2a_setting_4 d2a_setting_5 d2a_setting_6 d2a_setting_7 (d2a_disable)
+ parameter atx_pll_dsm_out_sel = "pll_dsm_disable", // \RANGE (pll_dsm_disable) pll_dsm_1st_order pll_dsm_2nd_order pll_dsm_3rd_order
+ parameter atx_pll_dsm_ecn_bypass = "false", // \RANGE (false) true
+ parameter atx_pll_dsm_ecn_test_en = "false", // \RANGE (false) true
+ parameter atx_pll_dsm_fractional_value_ready = "pll_k_ready", // \RANGE pll_k_not_ready (pll_k_ready)
+ parameter atx_pll_vco_bypass_enable = "false", // \RANGE (false) true
+ parameter atx_pll_cascadeclk_test = "cascadetest_off", // \RANGE (cascadetest_off) cascadetest_on
+ parameter atx_pll_tank_voltage_coarse = "vreg_setting_coarse1", // \RANGE vreg_setting_coarse0 (vreg_setting_coarse1) vreg_setting_coarse2 vreg_setting_coarse3
+ parameter atx_pll_tank_voltage_fine = "vreg_setting3", // \RANGE vreg_setting0 vreg_setting1 vreg_setting2 (vreg_setting3) vreg_setting4 vreg_setting5 vreg_setting6 vreg_setting7
+ parameter atx_pll_output_regulator_supply = "vreg1v_setting1", // \RANGE vreg1v_setting0 (vreg1v_setting1) vreg1v_setting2 vreg1v_setting3
+ parameter atx_pll_overrange_voltage = "over_setting3", // \RANGE over_setting0 over_setting1 over_setting2 (over_setting3) over_setting4 over_setting5 over_setting6 over_setting7
+ parameter atx_pll_underrange_voltage = "under_setting3", // \RANGE under_setting0 under_setting1 under_setting2 (under_setting3) under_setting4 under_setting5 under_setting6 under_setting7
+ parameter atx_pll_is_cascaded_pll = "false", // \RANGE (false) true
+ parameter atx_pll_is_otn = "false", // \RANGE (false) true
+ parameter atx_pll_is_sdi = "false", // \RANGE (false) true
+ parameter atx_pll_side = "side_unknown", // \RANGE (side_unknown) left right
+
+ parameter atx_pll_lf_cbig_size = "lf_cbig_setting0" , // \RANGE (lf_cbig_setting0) , lf_cbig_setting1 , lf_cbig_setting2 , lf_cbig_setting3 , lf_cbig_setting4
+ parameter atx_pll_iqclk_mux_sel = "power_down" , // \RANGE iqtxrxclk0 , iqtxrxclk1 , iqtxrxclk2 , iqtxrxclk3 , iqtxrxclk4 , iqtxrxclk5 , (power_down)
+ parameter atx_pll_enable_hclk = "hclk_disabled" , // \RANGE (hclk_disabled), hclk_enable
+ parameter atx_pll_calibration_mode = "cal_off" , // \RANGE (cal_off), uc_rst_pll , uc_rst_lf , uc_not_rst
+ parameter atx_pll_datarate = "0 bps" , // \RANGE
+ parameter atx_pll_device_variant = "device1" , // \RANGE (device1), device2 , device3 , device4 , device5
+ parameter atx_pll_initial_settings = "false" , // \RANGE (false), true
+ parameter [4:0] atx_pll_l_counter_scratch = 5'b00001 , // \RANGE (5)
+ parameter [2:0] atx_pll_n_counter_scratch = 3'b001 , // \RANGE (3)
+ parameter atx_pll_powerdown_mode = "powerup" , // \RANGE (powerup) , powerdown
+ parameter atx_pll_sup_mode = "user_mode" , // \RANGE (user_mode) , engineering_mode
+ parameter atx_pll_vco_freq = "0 hz", // \RANGE
+ parameter atx_pll_fpll_refclk_selection = "select_div_by_2", // \RANGE (select_div_by_2), select_vco_output
+ parameter lc_to_fpll_l_counter = "lcounter_setting0", // \RANGE (lcounter_setting0) .. lcounter_setting31
+ parameter lc_to_fpll_l_counter_scratch = 5'b00000, // \RANGE (5)
+
+ parameter hssi_pma_lc_refclk_select_mux_powerdown_mode = "powerup", // \RANGE (powerup) powerdown
+ parameter hssi_pma_lc_refclk_select_mux_refclk_select = "ref_iqclk0", // \RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+ parameter hssi_pma_lc_refclk_select_mux_silicon_rev = "20nm5es", // \RANGE (20nm5es) "20nm5es2" "20nm4" "20nm3" "20nm4qor" "20nm2" "20nm1"
+
+ parameter hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping = "ref_iqclk0", // \RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+ parameter hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping = "ref_iqclk1", // \RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+ parameter hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping = "ref_iqclk2", // \RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+ parameter hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping = "ref_iqclk3", // \RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+ parameter hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping = "ref_iqclk4", // \RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+
+ parameter hssi_refclk_divider_silicon_rev = "20nm5es", // \RANGE (20nm5es) "20nm5es2" "20nm4" "20nm3" "20nm4qor" "20nm2" "20nm1"
+ parameter enable_mcgb = 0, // \RANGE (0) 1
+ parameter enable_mcgb_debug_ports_parameters = 0, // \RANGE (0) 1
+ parameter avmm_interfaces = ((enable_mcgb==1) && (enable_mcgb_debug_ports_parameters==1)) ? 2 : 1,
+
+ parameter hssi_pma_cgb_master_silicon_rev = "20nm5es", // \RANGE (20nm5es) "20nm5es2" "20nm4" "20nm3" "20nm4qor" "20nm2" "20nm1"
+ parameter hssi_pma_cgb_master_prot_mode = "basic_tx", // \RANGE "unused" (basic_tx) "basic_kr_tx" "pcie_gen1_tx" "pcie_gen2_tx" "pcie_gen3_tx" "pcie_gen4_tx" "cei_tx" "qpi_tx" "cpri_tx" "fc_tx" "srio_tx" "gpon_tx" "sdi_tx" "sata_tx" "xaui_tx" "obsai_tx" "gige_tx" "higig_tx" "sonet_tx" "sfp_tx" "xfp_tx" "sfi_tx"
+ parameter hssi_pma_cgb_master_cgb_enable_iqtxrxclk = "disable_iqtxrxclk", // \OPEN in atom default is enable in _hw.tcl default is disable // \RANGE disable_iqtxrxclk (enable_iqtxrxclk)
+ parameter hssi_pma_cgb_master_x1_div_m_sel = "divbypass", // \RANGE (divbypass) divby2 divby4 divby8
+ parameter hssi_pma_cgb_master_ser_mode = "eight_bit", // \RANGE (eight_bit) ten_bit sixteen_bit twenty_bit thirty_two_bit forty_bit sixty_four_bit
+ parameter hssi_pma_cgb_master_datarate = "0 Mbps",
+
+ parameter hssi_pma_cgb_master_cgb_power_down = "normal_cgb", // \RANGE normal_cgb (power_down_cgb)
+ parameter hssi_pma_cgb_master_bonding_reset_enable = "allow_bonding_reset", // \RANGE disallow_bonding_reset (allow_bonding_reset)
+ parameter hssi_pma_cgb_master_observe_cgb_clocks = "observe_nothing", // \RANGE (observe_nothing) observe_x1mux_out
+ parameter hssi_pma_cgb_master_optimal = "true", // \RANGE (true) false
+ parameter hssi_pma_cgb_master_op_mode = "enabled", // \RANGE (enabled) pwr_down
+ parameter hssi_pma_cgb_master_tx_ucontrol_reset_pcie = "pcscorehip_controls_mcgb", // \RANGE (pcscorehip_controls_mcgb) cgb_reset tx_pcie_gen1 tx_pcie_gen2 tx_pcie_gen3 tx_pcie_gen4
+ parameter hssi_pma_cgb_master_vccdreg_output = "vccdreg_nominal", // \RANGE (vccdreg_nominal) vccdreg_pos_setting0 vccdreg_pos_setting1 vccdreg_pos_setting2 vccdreg_pos_setting3 vccdreg_pos_setting4 vccdreg_pos_setting5 vccdreg_pos_setting6 vccdreg_pos_setting7 vccdreg_pos_setting8 vccdreg_pos_setting9 vccdreg_pos_setting10 vccdreg_pos_setting11 vccdreg_pos_setting12 vccdreg_pos_setting13 vccdreg_pos_setting14 vccdreg_pos_setting15 reserved1 reserved2 vccdreg_neg_setting0 vccdreg_neg_setting1 vccdreg_neg_setting2 vccdreg_neg_setting3 reserved3 reserved4 reserved5 reserved6 reserved7 reserved8 reserved9 reserved10 reserved11
+ parameter hssi_pma_cgb_master_input_select = "lcpll_top", // \RANGE lcpll_bot lcpll_top fpll_bot fpll_top (unused)
+ parameter hssi_pma_cgb_master_input_select_gen3 = "unused" , // \RANGE lcpll_bot lcpll_top fpll_bot fpll_top (unused)
+ parameter hssi_pma_cgb_master_pcie_gen3_bitwidth = "pciegen3_wide" , // \RANGE (pciegen3_wide) pciegen3_narrow parameter powerdown_mode = "powerup" , //Valid values: powerup , powerdown
+ parameter hssi_pma_cgb_master_powerdown_mode = "powerup" , // \RANGE (powerup) powerdown
+ parameter hssi_pma_cgb_master_sup_mode = "user_mode" , // \RANGE (user_mode) engineering_mode
+ parameter hssi_pma_cgb_master_initial_settings = "false" // \RANGE (false) true
+) (
+ input pll_powerdown, // \OPEN verify connection to atoms(lc and cgb)
+ input pll_refclk0, // \OPEN verify connection to atom(mux) (currently LSB of ref_iqclk(rest is all-0s))
+ input pll_refclk1, // \OPEN verify connection to atom(mux) (currently LSB of ref_iqclk(rest is all-0s))
+ input pll_refclk2, // \OPEN verify connection to atom(mux) (currently LSB of ref_iqclk(rest is all-0s))
+ input pll_refclk3, // \OPEN verify connection to atom(mux) (currently LSB of ref_iqclk(rest is all-0s))
+ input pll_refclk4, // \OPEN verify connection to atom(mux) (currently LSB of ref_iqclk(rest is all-0s))
+ input mcgb_aux_clk0, // \OPEN verify connection to atom(cgb) ()
+ input mcgb_aux_clk1, // \OPEN verify connection to atom(cgb) ()
+ input mcgb_aux_clk2, // \OPEN verify connection to atom(cgb) ()
+
+ input [1:0] mcgb_pcie_sw,
+
+ output pll_serial_clk_8g,
+ output pll_serial_clk_16g,
+ output pll_locked,
+ output pll_pcie_clk,
+ output pll_cascade_clk,
+ output lc_to_fpll_refclk,
+
+ input mcgb_rst,
+ output [5:0] tx_bonding_clocks, // \OPEN should hardcoded width come from a definition?
+ output mcgb_serial_clk,
+ output [1:0] mcgb_pcie_sw_done,
+
+ // \NOTE reconfig for lc-pll and refclk_select atoms
+ input [avmm_interfaces-1:0] pll_avmm_clk,
+ input [avmm_interfaces-1:0] pll_avmm_rstn,
+ input [8*avmm_interfaces-1:0] pll_avmm_writedata,
+ input [9*avmm_interfaces-1:0] pll_avmm_address,
+ input [avmm_interfaces-1:0] pll_avmm_write,
+ input [avmm_interfaces-1:0] pll_avmm_read,
+ output [8*avmm_interfaces-1:0] pll_avmmreaddata_lc, // \OPEN [8:0] is bus size defined somewhere
+ output [avmm_interfaces-1:0] pll_blockselect_lc,
+ output [8*avmm_interfaces-1:0] pll_avmmreaddata_refclk, // \OPEN [8:0] is bus size defined somewhere
+ output [avmm_interfaces-1:0] pll_blockselect_refclk,
+ output [8*avmm_interfaces-1:0] pll_avmmreaddata_mcgb, // \OPEN [8:0] is bus size defined somewhere
+ output [avmm_interfaces-1:0] pll_blockselect_mcgb,
+
+
+ // \NOTE Debug related not in hw.tcl
+ output clklow,
+ output fref,
+ output overrange,
+ output underrange
+ /// \TODO include anyother ports for debugging?
+);
+ wire feedback_path_for_fb_comp_bonding_to_lc;
+ wire feedback_path_for_fb_comp_bonding_from_cgb;
+
+ generate
+ if (enable_mcgb == 1 && hssi_pma_cgb_master_cgb_enable_iqtxrxclk == "enable_iqtxrxclk") begin
+ assign feedback_path_for_fb_comp_bonding_to_lc = feedback_path_for_fb_comp_bonding_from_cgb;
+ end
+ else begin
+ assign feedback_path_for_fb_comp_bonding_to_lc = 0;
+ end
+ endgenerate
+
+ wire avmm_clk_refclk, avmm_clk_lc, avmm_clk_mcgb;
+ wire avmm_rstn_refclk, avmm_rstn_lc, avmm_rstn_mcgb;
+ wire [7:0] avmm_writedata_refclk, avmm_writedata_lc, avmm_writedata_mcgb;
+ wire [8:0] avmm_address_refclk, avmm_address_lc, avmm_address_mcgb;
+ wire avmm_write_refclk, avmm_write_lc, avmm_write_mcgb;
+ wire avmm_read_refclk, avmm_read_lc, avmm_read_mcgb;
+ wire [7:0] avmmreaddata_refclk, avmmreaddata_lc, avmmreaddata_mcgb;
+ wire blockselect_refclk, blockselect_lc, blockselect_mcgb;
+
+ assign pll_avmmreaddata_mcgb[7:0] = { 8 {1'b0} }; // \NOTE only [15:8] is used, hence [7:0] is tied-off to '0'
+ assign pll_blockselect_mcgb[0:0] = {1'b0}; // \NOTE only [1:1] is used, hence [0:0] is tied-off to '0'
+
+ generate
+ if (avmm_interfaces==2) begin
+ assign pll_avmmreaddata_lc[avmm_interfaces*8-1:8] = { 8 {1'b0} }; // \NOTE only [7:0] is used, hence [15:8] is tied-off to '0'
+ assign pll_avmmreaddata_refclk[avmm_interfaces*8-1:8] = { 8 {1'b0} }; // \NOTE only [7:0] is used, hence [15:8] is tied-off to '0'
+
+ assign pll_blockselect_lc[avmm_interfaces-1:1] = {1'b0}; // \NOTE only [0:0] is used, hence [1:1] is tied-off to '0'
+ assign pll_blockselect_refclk[avmm_interfaces-1:1] = {1'b0}; // \NOTE only [0:0] is used, hence [1:1] is tied-off to '0'
+
+ assign avmm_clk_mcgb = pll_avmm_clk[1];
+ assign avmm_rstn_mcgb = pll_avmm_rstn[1];
+ assign avmm_writedata_mcgb = pll_avmm_writedata[15:8];
+ assign avmm_address_mcgb = pll_avmm_address[17:9];
+ assign avmm_write_mcgb = pll_avmm_write[1];
+ assign avmm_read_mcgb = pll_avmm_read[1];
+ assign pll_avmmreaddata_mcgb[15:8] = avmmreaddata_mcgb;
+ assign pll_blockselect_mcgb[1] = blockselect_mcgb;
+ end
+ endgenerate
+
+ assign avmm_clk_refclk = pll_avmm_clk[0];
+ assign avmm_rstn_refclk = pll_avmm_rstn[0];
+ assign avmm_writedata_refclk = pll_avmm_writedata[7:0];
+ assign avmm_address_refclk = pll_avmm_address[8:0];
+ assign avmm_write_refclk = pll_avmm_write[0];
+ assign avmm_read_refclk = pll_avmm_read[0];
+ assign pll_avmmreaddata_refclk[7:0] = avmmreaddata_refclk;
+ assign pll_blockselect_refclk[0] = blockselect_refclk;
+
+ assign avmm_clk_lc = pll_avmm_clk[0];
+ assign avmm_rstn_lc = pll_avmm_rstn[0];
+ assign avmm_writedata_lc = pll_avmm_writedata[7:0];
+ assign avmm_address_lc = pll_avmm_address[8:0];
+ assign avmm_write_lc = pll_avmm_write[0];
+ assign avmm_read_lc = pll_avmm_read[0];
+ assign pll_avmmreaddata_lc[7:0] = avmmreaddata_lc;
+ assign pll_blockselect_lc[0] = blockselect_lc;
+
+ wire refclk_mux_out;
+
+ // \OPEN find a better way for the following parameters
+ localparam SIZE_CGB_BONDING_CLK = 6;
+ localparam SIZE_REFIQCLK = 12;
+ localparam REFCLK_CNT = 5;
+
+ assign mcgb_serial_clk = tx_bonding_clocks[SIZE_CGB_BONDING_CLK-1];
+
+
+ //-----------------------------------
+ // MUX STARTS
+ twentynm_hssi_pma_lc_refclk_select_mux
+ #(
+ //-----------------------------------
+ //-----------------------------------
+ .enable_debug_info(enable_debug_info), // \OPEN verify if still exists
+ .powerdown_mode(hssi_pma_lc_refclk_select_mux_powerdown_mode),
+ .refclk_select(hssi_pma_lc_refclk_select_mux_refclk_select),
+ .silicon_rev(hssi_pma_lc_refclk_select_mux_silicon_rev),
+ //-----------------------------------
+ //-----------------------------------
+ //.xmux_refclk_src // \NOTE: Second mux, handled by fitter
+ //.xpm_iqref_mux_iqclk_sel // \NOTE: First mux, handled by fitter
+ //.xpm_iqref_mux_scratch0_src // \NOTE: Handled by fitter
+ //.xpm_iqref_mux_scratch1_src // \NOTE: Handled by fitter
+ //.xpm_iqref_mux_scratch2_src // \NOTE: Handled by fitter
+ //.xpm_iqref_mux_scratch3_src // \NOTE: Handled by fitter
+ //.xpm_iqref_mux_scratch4_src // \NOTE: Handled by fitter
+
+ .inclk0_logical_to_physical_mapping (hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping),
+ .inclk1_logical_to_physical_mapping (hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping),
+ .inclk2_logical_to_physical_mapping (hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping),
+ .inclk3_logical_to_physical_mapping (hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping),
+ .inclk4_logical_to_physical_mapping (hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping)
+ //-----------------------------------
+ //-----------------------------------
+ )
+ twentynm_hssi_pma_lc_refclk_select_mux_inst (
+
+ .ref_iqclk({{(SIZE_REFIQCLK-REFCLK_CNT){1'b0}}, {pll_refclk4, pll_refclk3, pll_refclk2, pll_refclk1, pll_refclk0}}), /// \OPEN verify this connection?
+ .refclk(refclk_mux_out),
+
+ //----------------------------------- // \OPEN what to do with the following input ports [CM: ?talk to Enoch]
+ .core_refclk(1'b0),
+ .cr_pdb(1'b1),
+ .iqtxrxclk(6'b0), // \SIZE: [5:0]
+ .lvpecl_in(1'b0),
+ //-----------------------------------
+
+ //-----------------------------------
+ .avmmaddress(avmm_address_refclk),
+ .avmmclk(avmm_clk_refclk),
+ .avmmread(avmm_read_refclk),
+ .avmmrstn(avmm_rstn_refclk),
+ .avmmwrite(avmm_write_refclk),
+ .avmmwritedata(avmm_writedata_refclk),
+ .avmmreaddata(avmmreaddata_refclk),
+ .blockselect(blockselect_refclk)
+ //-----------------------------------
+ );
+ // MUX ENDS
+ //-----------------------------------
+
+
+ //-----------------------------------
+ // LC STARTS
+ twentynm_atx_pll
+ #(
+ //-----------------------------------
+ //-----------------------------------
+ .enable_debug_info(enable_debug_info), // \OPEN verify if still exists
+ .fb_select(atx_pll_fb_select),
+ .bonding(atx_pll_bonding_mode),
+ .prot_mode(atx_pll_prot_mode),
+ .silicon_rev(atx_pll_silicon_rev),
+ .bw_sel(atx_pll_bw_sel),
+ .output_clock_frequency(atx_pll_output_clock_frequency),
+ .reference_clock_frequency(atx_pll_reference_clock_frequency),
+ .m_counter(atx_pll_m_counter),
+ .ref_clk_div(atx_pll_ref_clk_div),
+ .l_counter(atx_pll_l_counter),
+ .dsm_fractional_division(atx_pll_dsm_fractional_division), // \OPEN is this assignment correct [CM: ]
+ .cgb_div(atx_pll_cgb_div), // \OPEN is not this supposed to be in cgb_master only [CM: ]
+ .pma_width(atx_pll_pma_width),
+ .hclk_divide(atx_pll_hclk_divide),
+ .dsm_mode(atx_pll_dsm_mode),
+ .l_counter_enable(atx_pll_l_counter_enable),
+ .tank_band(atx_pll_tank_band),
+ .tank_sel(atx_pll_tank_sel),
+ .regulator_bypass (atx_pll_regulator_bypass),
+ .pfd_delay_compensation (atx_pll_pfd_delay_compensation),
+ .xcpvco_xchgpmplf_cp_current_boost (atx_pll_xcpvco_xchgpmplf_cp_current_boost),
+ .pfd_pulse_width (atx_pll_pfd_pulse_width),
+ //-----------------------------------
+ //-----------------------------------
+ .primary_use (atx_pll_primary_use ),
+ .lc_mode (atx_pll_lc_mode ),
+ .lc_atb (atx_pll_lc_atb ),
+ .cp_compensation_enable (atx_pll_cp_compensation_enable ),
+ .cp_current_setting (atx_pll_cp_current_setting ),
+ .cp_testmode (atx_pll_cp_testmode ),
+ .cp_lf_3rd_pole_freq (atx_pll_cp_lf_3rd_pole_freq ),
+ .cp_lf_order (atx_pll_cp_lf_order ),
+ .lf_resistance (atx_pll_lf_resistance ),
+ .lf_ripplecap (atx_pll_lf_ripplecap ),
+ .d2a_voltage (atx_pll_d2a_voltage ),
+ .dsm_out_sel (atx_pll_dsm_out_sel ),
+ .dsm_ecn_bypass (atx_pll_dsm_ecn_bypass ),
+ .dsm_ecn_test_en (atx_pll_dsm_ecn_test_en ),
+ .dsm_fractional_value_ready (atx_pll_dsm_fractional_value_ready),
+ // iqclk_mux_sel: \NOTE should be handled by fitter, but required to set fb-comp sims to pass
+ // iqclk_mux_sel: \RANGE iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 (power_down)
+ .iqclk_mux_sel ("iqtxrxclk0" ),
+ .vco_bypass_enable (atx_pll_vco_bypass_enable ),
+ .cascadeclk_test (atx_pll_cascadeclk_test ),
+ .tank_voltage_coarse (atx_pll_tank_voltage_coarse ),
+ .tank_voltage_fine (atx_pll_tank_voltage_fine ),
+ .output_regulator_supply (atx_pll_output_regulator_supply ),
+ .overrange_voltage (atx_pll_overrange_voltage ),
+ .underrange_voltage (atx_pll_underrange_voltage ),
+ .is_cascaded_pll (atx_pll_is_cascaded_pll ),
+ .is_otn (atx_pll_is_otn ),
+ .is_sdi (atx_pll_is_sdi ),
+ .side (atx_pll_side ),
+ .lf_cbig_size (atx_pll_lf_cbig_size ),
+ .enable_hclk (atx_pll_enable_hclk ),
+ .calibration_mode (atx_pll_calibration_mode ),
+ .datarate (atx_pll_datarate ),
+ .device_variant (atx_pll_device_variant ),
+ .initial_settings (atx_pll_initial_settings ),
+ .l_counter_scratch (atx_pll_l_counter_scratch ),
+ .n_counter_scratch (atx_pll_n_counter_scratch ),
+ .powerdown_mode (atx_pll_powerdown_mode ),
+ .sup_mode (atx_pll_sup_mode ),
+ .vco_freq (atx_pll_vco_freq ),
+ .fpll_refclk_selection (atx_pll_fpll_refclk_selection ),
+ .lc_to_fpll_l_counter (lc_to_fpll_l_counter )
+
+ //-----------------------------------
+ //-----------------------------------
+ // \OPEN .sel_buf8g(ENABLE_BUF8G), does not exist anymore [CM: ]
+ // \OPEN .sel_buf14g(ENABLE_BUF14G), does not exist anymore
+ // \OPEN .lcpll_hclk_driver_enable(HCLK_ENABLE_ATX), does not exist anymore
+ // \OPEN .lc_cmu_pdb("true"), does not exist anymore
+ //-----------------------------------
+ //-----------------------------------
+ )
+ twentynm_atx_pll_inst (
+
+ .clk0_16g(pll_serial_clk_16g),
+ .clk0_8g(pll_serial_clk_8g),
+
+ .clk180_16g( /*unused*/ ),
+ .clk180_8g( /*unused*/ ),
+
+ .lf_rst_n(1'b1),
+ .rst_n(pll_powerdown),
+ .refclk(refclk_mux_out),
+ .lock(pll_locked),
+
+ .iqtxrxclk({5'b0, feedback_path_for_fb_comp_bonding_to_lc}),
+
+ .hclk_out(pll_pcie_clk),
+ .iqtxrxclk_out(pll_cascade_clk),
+ .lc_to_fpll_refclk (lc_to_fpll_refclk),
+
+ //-----------------------------------
+ .clklow_buf(clklow),
+ .fref_buf(fref),
+ .overrange(overrange),
+ .underrange(underrange),
+ //-----------------------------------
+
+ //-----------------------------------
+ .avmmaddress(avmm_address_lc),
+ .avmmclk(avmm_clk_lc),
+ .avmmread(avmm_read_lc),
+ .avmmrstn(avmm_rstn_lc),
+ .avmmwrite(avmm_write_lc),
+ .avmmwritedata(avmm_writedata_lc),
+ .avmmreaddata(avmmreaddata_lc),
+ .blockselect(blockselect_lc)
+ //-----------------------------------
+ );
+ // LC ENDS
+ //-----------------------------------
+
+
+generate
+if (enable_mcgb == 1) begin
+ //-----------------------------------
+ // CGB STARTS
+ twentynm_hssi_pma_cgb_master
+ #(
+ //-----------------------------------
+ //-----------------------------------
+ .enable_debug_info(enable_debug_info), // \OPEN verify if still exists
+ .silicon_rev(hssi_pma_cgb_master_silicon_rev),
+ .datarate(hssi_pma_cgb_master_datarate),
+ .x1_div_m_sel(hssi_pma_cgb_master_x1_div_m_sel),
+ .prot_mode(hssi_pma_cgb_master_prot_mode),
+ .ser_mode(hssi_pma_cgb_master_ser_mode),
+ .cgb_enable_iqtxrxclk(hssi_pma_cgb_master_cgb_enable_iqtxrxclk), // \OPEN 1) needs to be reviewed 2) in atom default is enable in _hw.tcl default is disable
+ //-----------------------------------
+ //-----------------------------------
+ .cgb_power_down (hssi_pma_cgb_master_cgb_power_down ),
+ .observe_cgb_clocks (hssi_pma_cgb_master_observe_cgb_clocks ),
+ //.op_mode (hssi_pma_cgb_master_op_mode ),
+
+ //.tx_ucontrol_reset_pcie (hssi_pma_cgb_master_tx_ucontrol_reset_pcie ),
+ .vccdreg_output (hssi_pma_cgb_master_vccdreg_output ),
+ .input_select (hssi_pma_cgb_master_input_select ),
+ .input_select_gen3 (hssi_pma_cgb_master_input_select_gen3 ),
+ //-----------------------------------
+ //-----------------------------------
+ .bonding_reset_enable (hssi_pma_cgb_master_bonding_reset_enable ), // \NOTE applies to slave cgb // \RANGE disallow_bonding_reset (allow_bonding_reset)
+ .optimal (hssi_pma_cgb_master_optimal),
+ .pcie_gen3_bitwidth (hssi_pma_cgb_master_pcie_gen3_bitwidth),
+ .powerdown_mode (hssi_pma_cgb_master_powerdown_mode),
+ .sup_mode (hssi_pma_cgb_master_sup_mode),
+ .initial_settings (hssi_pma_cgb_master_initial_settings)
+ //.scratch0_x1_clock_src() // \NOTE set by fitter // \RANGE (unused) lcpll_bot lcpll_top fpll_bot fpll_top
+ //.scratch1_x1_clock_src() // \NOTE set by fitter // \RANGE (unused) lcpll_bot lcpll_top fpll_bot fpll_top
+ //.scratch2_x1_clock_src() // \NOTE set by fitter // \RANGE (unused) lcpll_bot lcpll_top fpll_bot fpll_top
+ //.scratch3_x1_clock_src() // \NOTE set by fitter // \RANGE (unused) lcpll_bot lcpll_top fpll_bot fpll_top
+ //.x1_clock_source_sel() // \NOTE set by fitter // \RANGE lcpll_bot lcpll_top fpll_bot (fpll_top) lcpll_bot_g1_g2 lcpll_top_g1_g2 fpll_bot_g1_g2 fpll_top_g1_g2 fpll_bot_g2_lcpll_bot_g3 fpll_bot_g2_lcpll_top_g3 fpll_top_g2_lcpll_bot_g3 fpll_top_g2_lcpll_top_g3
+ //-----------------------------------
+ //-----------------------------------
+ )
+ twentynm_hssi_pma_cgb_master_inst (
+
+ .cgb_rstb(mcgb_rst), // \OPEN active high or low?
+
+ .clk_fpll_t(mcgb_aux_clk0),
+ .clk_lc_t (pll_serial_clk_8g),
+
+ .clk_fpll_b (mcgb_aux_clk2),
+ .clk_lc_b (mcgb_aux_clk1),
+
+ .clkb_fpll_b( /*unused*/ ),
+ .clkb_fpll_t( /*unused*/ ),
+ .clkb_lc_b ( /*unused*/ ),
+ .clkb_lc_t ( /*unused*/ ),
+ //-----------------------------------
+
+ .cpulse_out_bus(tx_bonding_clocks), // \OPEN is bus ok?
+
+ .tx_iqtxrxclk_out(feedback_path_for_fb_comp_bonding_from_cgb),
+
+ .pcie_sw_done(mcgb_pcie_sw_done),
+ .pcie_sw(mcgb_pcie_sw),
+
+ //-----------------------------------
+ .tx_bonding_rstb(1'b1), // \NOTE carried over from slave cgb
+ //-----------------------------------
+
+ //-----------------------------------
+ .avmmaddress(avmm_address_mcgb),
+ .avmmclk(avmm_clk_mcgb),
+ .avmmread(avmm_read_mcgb),
+ .avmmrstn(avmm_rstn_mcgb),
+ .avmmwrite(avmm_write_mcgb),
+ .avmmwritedata(avmm_writedata_mcgb),
+ .avmmreaddata(avmmreaddata_mcgb),
+ .blockselect(blockselect_mcgb)
+ //-----------------------------------
+ );
+ // CGB ENDS
+ //-----------------------------------
+end else begin
+ assign mcgb_pcie_sw_done = 2'b0;
+ assign tx_bonding_clocks = 6'b0;
+end
+endgenerate
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_arbiter.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_arbiter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..7eb77632c6d21f14d681d129b191eacd0de6339b
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_arbiter.sv
@@ -0,0 +1,68 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Clocked priority encoder with state
+//
+// On each clock cycle, updates state to show which request is granted.
+// Most recent grant holder is always the highest priority.
+// If current grant holder is not making a request, while others are,
+// then new grant holder is always the requester with lowest bit number.
+// If no requests, current grant holder retains grant state
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_arbiter #(
+ parameter width = 2
+) (
+ input wire clock,
+ input wire [width-1:0] req, // req[n] requests for this cycle
+ output reg [width-1:0] grant // grant[n] means requester n is grantee in this cycle
+);
+
+ wire idle; // idle when no requests
+ wire [width-1:0] keep; // keep[n] means requester n is requesting, and already has the grant
+ // Note: current grantee is always highest priority for next grant
+ wire [width-1:0] take; // take[n] means requester n is requesting, and there are no higher-priority requests
+
+ assign keep = req & grant; // current grantee is always highest priority for next grant
+ assign idle = ~| req; // idle when no requests
+
+ initial begin
+ grant = 0;
+ end
+
+ // grant next state depends on current grant and take priority
+ always @(posedge clock) begin
+ grant <=
+// synthesis translate_off
+ (grant === {width{1'bx}})? {width{1'b0}} :
+// synthesis translate_on
+ keep // if current grantee is requesting, gets to keep grant
+ | ({width{idle}} & grant) // if no requests, grant state remains unchanged
+ | take; // take applies only if current grantee is not requesting
+ end
+
+ // 'take' bus encodes priority. Request with lowest bit number wins when current grantee not requesting
+ assign take[0] = req[0]
+ & (~| (keep & ({width{1'b1}} << 1))); // no 'keep' from lower-priority inputs
+ genvar i;
+ generate
+ for (i=1; i < width; i = i + 1) begin : arb
+ assign take[i] = req[i]
+ & (~| (keep & ({width{1'b1}} << (i+1)))) // no 'keep' from lower-priority inputs
+ & (~| (req & {i{1'b1}})); // no 'req' from higher-priority inputs
+ end
+ endgenerate
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_atx_pll_rcfg_arb.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_atx_pll_rcfg_arb.sv
new file mode 100644
index 0000000000000000000000000000000000000000..e579939863f558f8a5478890db1e10c836367fdd
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_atx_pll_rcfg_arb.sv
@@ -0,0 +1,121 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+module alt_xcvr_atx_pll_rcfg_arb #(
+ parameter total_masters = 3,
+ parameter interfaces = 1,
+ parameter address_width = 10,
+ parameter data_width = 32
+) (
+ // Basic AVMM inputs
+ input [interfaces-1:0] reconfig_clk,
+ input [interfaces-1:0] reconfig_reset,
+
+ // User AVMM input
+ input [interfaces-1:0] user_read,
+ input [interfaces-1:0] user_write,
+ input [interfaces*address_width-1:0] user_address,
+ input [interfaces*data_width-1:0] user_writedata,
+ input [interfaces-1:0] user_read_write,
+ output [interfaces-1:0] user_waitrequest,
+
+ // Reconfig Steamer AVMM input
+ input [interfaces-1:0] strm_read,
+ input [interfaces-1:0] strm_write,
+ input [interfaces*address_width-1:0] strm_address,
+ input [interfaces*data_width-1:0] strm_writedata,
+ input [interfaces-1:0] strm_read_write,
+ output [interfaces-1:0] strm_waitrequest,
+
+ // ADME AVMM input
+ input [interfaces-1:0] jtag_read,
+ input [interfaces-1:0] jtag_write,
+ input [interfaces*address_width-1:0] jtag_address,
+ input [interfaces*data_width-1:0] jtag_writedata,
+ input [interfaces-1:0] jtag_read_write,
+ output [interfaces-1:0] jtag_waitrequest,
+
+ // AVMM output the interface and the CSR
+ input [interfaces-1:0] avmm_waitrequest,
+ output [interfaces-1:0] avmm_read,
+ output [interfaces-1:0] avmm_write,
+ output [interfaces*address_width-1:0] avmm_address,
+ output [interfaces*data_width-1:0] avmm_writedata
+);
+
+// General wires
+wire [interfaces*total_masters-1:0] grant;
+wire [interfaces-1:0] strm_grants;
+wire [interfaces-1:0] user_read_write_lcl;
+
+// Variables for the generate loops
+genvar ig; // For bus widths
+genvar jg; // For interfaces
+generate for(jg=0;jg<interfaces;jg=jg+1) begin: g_arb
+
+ /*********************************************************************/
+ // case: 309705
+ // Simulation fix. When the user inputs drive x at the beginning of simulation,
+ // then even after a reset, the grant will have been assigned a value of x.
+ // since there is a loopback in the RTL, the value will continue to be x,
+ // and gets reflected on avmm_readdata and avmm_waitrequest. once an avmm master
+ // requests a read or write, the x value for grant will correct itself.
+ /**********************************************************************/
+ assign user_read_write_lcl[jg] =
+ // synthesis translate_off
+ (user_read_write[jg] === 1'bx) ? 1'b0 :
+ // synthesis translate_on
+ user_read_write[jg];
+
+
+
+ /**********************************************************************/
+ // Per Instance instantiations and assignments
+ // Priority in decreasing order is embedded reconfig -> user AVMM -> JTAG
+ /**********************************************************************/
+ alt_xcvr_arbiter #(
+ .width (total_masters)
+ ) arbiter_inst (
+ .clock (reconfig_clk[jg]),
+ .req ({jtag_read_write[jg], user_read_write_lcl[jg], strm_read_write[jg]}),
+ .grant (grant[jg*total_masters+:total_masters])
+ );
+
+ // Assign the grant signal
+ assign strm_grants[jg] = grant[jg*total_masters];
+
+ // Use the grant as a mask for the various read and writes signals
+ // if you OR them all together, it will generate the read/write request if any are high
+ // For streamer write/read condition - if broadcasting, wait for all interfaces to receive grant before asserting write/read
+ assign avmm_write[jg] = |(grant[jg*total_masters+:total_masters] & {jtag_write[jg], user_write[jg], ((~&strm_write | &strm_grants) & strm_write[jg])});
+ assign avmm_read[jg] = |(grant[jg*total_masters+:total_masters] & {jtag_read[jg], user_read[jg], ((~&strm_read | &strm_grants) & strm_read[jg])});
+
+ // Split the wait request, and if the grant is asserted to any one master, assert wait request to all others
+ assign {jtag_waitrequest[jg], user_waitrequest[jg], strm_waitrequest[jg]} = (~grant[jg*total_masters+:total_masters] | {total_masters{avmm_waitrequest[jg]}});
+
+ // Since these are buses, the logic must be done in a bit-wise fashion; hence the for loop
+ // Generate the address for the bus width
+ for(ig=0; ig<address_width;ig=ig+1) begin: g_avmm_address
+ assign avmm_address[jg*address_width + ig] = |(grant[jg*total_masters+:total_masters] & {jtag_address[jg*address_width + ig], user_address[jg*address_width + ig], strm_address[jg*address_width + ig]});
+ end // End g_avmm_address
+
+ // Generate the write data for the bus width
+ for(ig=0; ig<data_width;ig=ig+1) begin: g_avmm_writdata
+ assign avmm_writedata[jg*data_width+ ig] = |(grant[jg*total_masters+:total_masters] & {jtag_writedata[jg*data_width + ig], user_writedata[jg*data_width + ig], strm_writedata[jg*data_width + ig]});
+ end // End g_avmm_writedata
+
+ end //End for interface-wise for loop
+endgenerate // End generate
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_atx_pll_rcfg_opt_logic_syj5sga.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_atx_pll_rcfg_opt_logic_syj5sga.sv
new file mode 100644
index 0000000000000000000000000000000000000000..99fbbfe698660005eda7545d723eb4387007cc0f
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_atx_pll_rcfg_opt_logic_syj5sga.sv
@@ -0,0 +1,451 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+module alt_xcvr_atx_pll_rcfg_opt_logic_syj5sga #(
+ // Parameters for the embedded reconfiguration logic
+ parameter dbg_user_identifier = 0,
+ parameter dbg_embedded_debug_enable = 0,
+ parameter dbg_capability_reg_enable = 0,
+ parameter dbg_stat_soft_logic_enable = 0,
+ parameter dbg_ctrl_soft_logic_enable = 0,
+ parameter en_master_cgb = 0,
+
+ // Parameters for the AVMM masters and split interface
+ parameter INTERFACES = 1,
+ parameter RECONFIG_SHARED = 0,
+ parameter JTAG_ENABLED = 0, // Can only be enabled when using a shared reconfig interface
+ parameter ADME_SLAVE_MAP = "altera_xcvr_atx_pll_a10",
+ parameter ADME_ASSGN_MAP = " ",
+ parameter RCFG_EMB_STRM_ENABLED = 0, // Enable the embedded reconfiguration streamer logic
+ parameter RCFG_PROFILE_CNT = 2, // Number of configuration profiles for embedded streamer
+
+ // The following are not intended to be directly set
+ parameter IFACES = RECONFIG_SHARED ? 1 : INTERFACES,
+ parameter ADDR_BITS = 10,
+ parameter SEL_BITS = (RECONFIG_SHARED ? altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(INTERFACES-1) : 0),
+ parameter DATA_WIDTH = 32
+
+) (
+ // User reconfig interface ports
+ input [IFACES-1:0] reconfig_clk,
+ input [IFACES-1:0] reconfig_reset,
+ input [IFACES-1:0] reconfig_write,
+ input [IFACES-1:0] reconfig_read,
+ input [IFACES*(ADDR_BITS+SEL_BITS)-1:0] reconfig_address,
+ input [IFACES*DATA_WIDTH-1:0] reconfig_writedata,
+ output [IFACES*DATA_WIDTH-1:0] reconfig_readdata,
+ output [IFACES-1:0] reconfig_waitrequest,
+
+ // AVMM ports to transceiver Split by interface
+ output [INTERFACES-1:0] avmm_clk,
+ output [INTERFACES-1:0] avmm_reset,
+ output [INTERFACES-1:0] avmm_write,
+ output [INTERFACES-1:0] avmm_read,
+ output [INTERFACES*ADDR_BITS-1:0] avmm_address,
+ output [INTERFACES*8-1:0] avmm_writedata,
+ input [INTERFACES*8-1:0] avmm_readdata,
+ input [INTERFACES-1:0] avmm_waitrequest,
+
+ // input signals from the core
+ input in_pll_powerdown,
+ input in_pll_locked,
+ input in_pll_cal_busy,
+ input in_avmm_busy,
+
+ // output signals to the ip
+ output out_pll_powerdown
+
+);
+
+/**********************************************************************/
+// Per Instance instantiations and assignments
+/**********************************************************************/
+localparam INTERFACE_SEL_WIDTH = altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(INTERFACES-1);
+localparam ENABLED_JTAG_MASTERS = 1 + JTAG_ENABLED + RCFG_EMB_STRM_ENABLED;
+localparam RCFG_EMB_STRM_CFG_SEL_WIDTH = altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(RCFG_PROFILE_CNT-1);
+
+
+// Raw rmbedded reconfig signals (always independent)
+wire [INTERFACES-1:0] rcfg_emb_strm_write;
+wire [INTERFACES-1:0] rcfg_emb_strm_read;
+wire [INTERFACES*ADDR_BITS-1:0] rcfg_emb_strm_address;
+wire [INTERFACES*DATA_WIDTH-1:0] rcfg_emb_strm_writedata;
+wire [INTERFACES-1:0] rcfg_emb_strm_waitrequest;
+
+// User AVMM signals expanded to independent interfaces
+wire [INTERFACES-1:0] split_user_write;
+wire [INTERFACES-1:0] split_user_read;
+wire [INTERFACES*ADDR_BITS-1:0] split_user_address;
+wire [INTERFACES*DATA_WIDTH-1:0] split_user_writedata;
+wire [INTERFACES-1:0] split_user_waitrequest;
+
+// JTAG signals expanded to independent interfaces
+wire [INTERFACES-1:0] split_jtag_write;
+wire [INTERFACES-1:0] split_jtag_read;
+wire [INTERFACES*ADDR_BITS-1:0] split_jtag_address;
+wire [INTERFACES*DATA_WIDTH-1:0] split_jtag_writedata;
+wire [INTERFACES-1:0] split_jtag_waitrequest;
+
+// Additional arbitration signals for soft CSR
+wire [INTERFACES-1:0] chnl_write;
+wire [INTERFACES-1:0] chnl_read;
+wire [INTERFACES-1:0] chnl_busy;
+wire [INTERFACES-1:0] chnl_waitrequest;
+wire [INTERFACES*8-1:0] chnl_readdata;
+
+// embedded reconfig signals
+wire [INTERFACES-1:0] rcfg_emb_strm_busy;
+wire [INTERFACES-1:0] rcfg_emb_strm_chan_sel;
+wire [INTERFACES*RCFG_EMB_STRM_CFG_SEL_WIDTH-1:0] rcfg_emb_strm_cfg_sel;
+wire [INTERFACES-1:0] rcfg_emb_strm_bcast_en;
+wire [INTERFACES-1:0] rcfg_emb_strm_cfg_load;
+
+// Read_write signals to assist with prioritizing arbitrarion
+wire [INTERFACES-1:0] user_read_write;
+wire [INTERFACES-1:0] jtag_read_write;
+wire [INTERFACES-1:0] rcfg_emb_strm_read_write;
+
+// Wires for converting between data widths
+wire [INTERFACES*DATA_WIDTH-1:0] expanded_avmm_readdata;
+wire [INTERFACES*DATA_WIDTH-1:0] expanded_avmm_writedata;
+
+
+// Wires for qmap cleanup
+wire lcl_g_arbiter_dis;
+wire lcl_g_avmm_csr_dis;
+wire lcl_ground;
+
+// Warning Removal
+assign lcl_g_avmm_csr_dis = &{1'b0,
+ rcfg_emb_strm_busy};
+assign lcl_g_arbiter_dis = &{1'b0,
+ rcfg_emb_strm_address,
+ rcfg_emb_strm_writedata,
+ split_jtag_address,
+ split_jtag_writedata,
+ user_read_write,
+ jtag_read_write,
+ rcfg_emb_strm_read_write};
+assign lcl_ground = &{1'b0,
+ lcl_g_avmm_csr_dis,
+ lcl_g_arbiter_dis};
+
+// Generate variable for interface numbers
+genvar ig;
+
+
+/**********************************************************************/
+// Generate Statement for the Shared vs Split user interface
+/**********************************************************************/
+generate
+ // Expand the AVMM signals from the interface to the 32-bit interface of the user
+ for(ig=0;ig<INTERFACES;ig=ig+1) begin: g_expanded_avmm_signals
+ assign expanded_avmm_readdata [ig*DATA_WIDTH +: DATA_WIDTH] = {24'd0,chnl_readdata [ig*8 +: 8]};
+ assign avmm_writedata [ig*8 +: 8] = expanded_avmm_writedata [ig*DATA_WIDTH +: 8];
+ end
+
+
+ /**********************************************************************/
+ // Split the reconfig interface to the independent interface when using shared reconfig
+ /**********************************************************************/
+ if(!RECONFIG_SHARED) begin : g_not_shared
+ // Signals are already split, so wire straight through
+ assign avmm_clk = reconfig_clk;
+ assign avmm_reset = reconfig_reset;
+
+ assign split_user_write = reconfig_write;
+ assign split_user_read = reconfig_read;
+ assign split_user_address = reconfig_address;
+ assign split_user_writedata = reconfig_writedata;
+ assign reconfig_readdata = expanded_avmm_readdata;
+ assign reconfig_waitrequest = ({INTERFACES{lcl_ground}} | split_user_waitrequest);
+
+ // If we are using a shared interface
+ end else begin : g_shared
+ wire [INTERFACE_SEL_WIDTH-1:0] rcfg_if_sel;
+
+ // Generate interface select based on upper address bits
+ assign rcfg_if_sel = reconfig_address[ADDR_BITS+:INTERFACE_SEL_WIDTH];
+ assign reconfig_readdata = expanded_avmm_readdata[rcfg_if_sel*DATA_WIDTH +: DATA_WIDTH];
+ assign reconfig_waitrequest = split_user_waitrequest[rcfg_if_sel];
+
+ for(ig=0;ig<INTERFACES;ig=ig+1) begin : g_shared
+ // Split shared signals to independent interfaces
+ assign avmm_clk [ig] = reconfig_clk;
+ assign avmm_reset [ig] = reconfig_reset;
+
+ assign split_user_write [ig] = reconfig_write & (rcfg_if_sel == ig) | lcl_ground;
+ assign split_user_read [ig] = reconfig_read & (rcfg_if_sel == ig);
+ assign split_user_address [ig*ADDR_BITS +: ADDR_BITS] = reconfig_address[0+:ADDR_BITS];
+ assign split_user_writedata [ig*DATA_WIDTH +: DATA_WIDTH] = reconfig_writedata;
+ end
+ end //End g_not_shared
+endgenerate
+
+
+/**********************************************************************/
+// Embedded JTAG Debug Master (ADME)
+/**********************************************************************/
+generate if(JTAG_ENABLED) begin : g_jtag
+
+ // Set the slave type for the ADME. Since the span needs to be a string, 2^(total addr_bits) will
+ // give the max value, however since the adme uses byte alignment, shift the span by two bits.
+ localparam set_slave_span = altera_xcvr_native_a10_functions_h::int2str_alt_xcvr_native_a10(2**(ADDR_BITS+INTERFACE_SEL_WIDTH+2));
+ localparam set_slave_map = {"{typeName ",ADME_SLAVE_MAP," address 0x0 span ",set_slave_span," hpath {}",ADME_ASSGN_MAP,"}"};
+
+ // Raw JTAG signals
+ wire jtag_write;
+ wire jtag_read;
+ wire [(ADDR_BITS+INTERFACE_SEL_WIDTH)-1:0] jtag_address;
+ wire [DATA_WIDTH-1:0] jtag_writedata;
+ wire [DATA_WIDTH-1:0] jtag_readdata;
+ wire jtag_waitrequest;
+ wire jtag_readdatavalid;
+ wire [INTERFACE_SEL_WIDTH-1:0] jtag_if_sel;
+
+ // Generate interface select based on upper address bits
+ assign jtag_if_sel = jtag_address[ADDR_BITS+:INTERFACE_SEL_WIDTH];
+ assign jtag_readdata = expanded_avmm_readdata[jtag_if_sel*DATA_WIDTH +: DATA_WIDTH];
+ assign jtag_waitrequest = split_jtag_waitrequest[jtag_if_sel];
+
+ // Split shared signals to independent interface
+ for(ig=0;ig<INTERFACES;ig=ig+1) begin: g_expanded_avmm_signals
+ assign split_jtag_write [ig] = jtag_write & (jtag_if_sel == ig);
+ assign split_jtag_read [ig] = jtag_read & (jtag_if_sel == ig);
+ assign split_jtag_address [ig*ADDR_BITS +: ADDR_BITS] = jtag_address[0+:ADDR_BITS];
+ assign split_jtag_writedata [ig*DATA_WIDTH +: DATA_WIDTH] = jtag_writedata[DATA_WIDTH-1:0];
+ end
+
+ // When doing RTL sims, remove the altera_debug_master_endpoint, as
+ // there is no RTL simulation model. Pre and Post Fit sims are ok.
+ `ifdef ALTERA_RESERVED_QIS
+ altera_debug_master_endpoint
+ #(
+ .ADDR_WIDTH ( (ADDR_BITS+INTERFACE_SEL_WIDTH) ),
+ .DATA_WIDTH ( DATA_WIDTH ),
+ .HAS_RDV ( 0 ),
+ .SLAVE_MAP ( set_slave_map ),
+ .PREFER_HOST ( " " ),
+ .CLOCK_RATE_CLK ( 0 )
+ ) adme (
+ .clk ( reconfig_clk ),
+ .reset ( reconfig_reset ),
+ .master_write ( jtag_write ),
+ .master_read ( jtag_read ),
+ .master_address ( jtag_address ),
+ .master_writedata ( jtag_writedata ),
+ .master_waitrequest ( jtag_waitrequest ),
+ .master_readdatavalid ( jtag_readdatavalid ),
+ .master_readdata ( jtag_readdata )
+ );
+ `else
+ assign jtag_write = 1'b0;
+ assign jtag_read = 1'b0;
+ assign jtag_address = {(ADDR_BITS+INTERFACE_SEL_WIDTH){1'b0}};
+ assign jtag_writedata = {DATA_WIDTH{1'b0}};
+ `endif
+
+ // If we have not enabled the ADME
+ end else begin : g_jtag_disable
+ assign split_jtag_write = {INTERFACES{1'b0}};
+ assign split_jtag_read = {INTERFACES{1'b0}};
+ assign split_jtag_address = {(INTERFACES*ADDR_BITS){1'b0}};
+ assign split_jtag_writedata = {(INTERFACES*DATA_WIDTH){1'b0}};
+ end
+endgenerate // End g_jtag
+
+
+/**********************************************************************/
+// Embedded Reconfig Streamer
+/**********************************************************************/
+generate if(RCFG_EMB_STRM_ENABLED) begin : g_rcfg_strm_enable //TODO check to see if there is parameter redundancy
+
+ alt_xcvr_native_rcfg_strm_top_syj5sga #(
+ .xcvr_rcfg_interfaces ( INTERFACES ),
+ .xcvr_rcfg_addr_width ( ADDR_BITS ),
+ .xcvr_rcfg_data_width ( DATA_WIDTH ),
+ .rcfg_profile_cnt ( RCFG_PROFILE_CNT )
+ )rcfg_strm_top_inst(
+ .clk ( reconfig_clk[0] ), // All clock bits should be driven by the same source if using independent interface
+ .reset ( |reconfig_reset ), // Any reset bit will reset the reconfig streamer
+ .cfg_sel ( rcfg_emb_strm_cfg_sel ),
+ .bcast_en ( rcfg_emb_strm_bcast_en ),
+ .cfg_load ( rcfg_emb_strm_cfg_load ),
+ .chan_sel ( rcfg_emb_strm_chan_sel ),
+ .stream_busy ( rcfg_emb_strm_busy ),
+ .xcvr_reconfig_write ( rcfg_emb_strm_write ),
+ .xcvr_reconfig_read ( rcfg_emb_strm_read ),
+ .xcvr_reconfig_address ( rcfg_emb_strm_address ),
+ .xcvr_reconfig_writedata ( rcfg_emb_strm_writedata ),
+ .xcvr_reconfig_readdata ( expanded_avmm_readdata ),
+ .xcvr_reconfig_waitrequest ( rcfg_emb_strm_waitrequest )
+ );
+
+ // If we disable the reconfig streamer
+ end else begin: g_rcfg_strm_disable
+ assign rcfg_emb_strm_write = {INTERFACES{1'b0}};
+ assign rcfg_emb_strm_read = {INTERFACES{1'b0}};
+ assign rcfg_emb_strm_address = {(INTERFACES*ADDR_BITS){1'b0}};
+ assign rcfg_emb_strm_writedata = {INTERFACES{32'b0}};
+ assign rcfg_emb_strm_busy = {INTERFACES{1'b0}};
+ end
+endgenerate // End g_rcfg_strm_enable
+
+
+/**********************************************************************/
+// AVMM Master read/write signals.
+/**********************************************************************/
+assign user_read_write = split_user_read | split_user_write; // Bits asserted for corresponding interfaces from/to which user avmm is currently reading/writing
+assign jtag_read_write = split_jtag_read | split_jtag_write; // Bits asserted for corresponding interfaces from/to which jtag is currently reading/writing
+assign rcfg_emb_strm_read_write = rcfg_emb_strm_read | rcfg_emb_strm_write; // Bits asserted for corresponding interfaces from/to which embedded streamer is currently reading/writing
+
+
+/**********************************************************************/
+// AVMM Arbiter. Instantiated once per interface, however to handle streaming
+// broadcast, the interface-wise instantiation is handled within the arbiter.
+/**********************************************************************/
+generate if (ENABLED_JTAG_MASTERS > 1) begin: g_arbiter_enable
+ alt_xcvr_atx_pll_rcfg_arb #(
+ .total_masters ( 3 ),
+ .interfaces ( INTERFACES ),
+ .address_width ( ADDR_BITS ),
+ .data_width ( DATA_WIDTH )
+ ) alt_xcvr_rcfg_arb (
+ // Basic AVMM inputs
+ .reconfig_clk ( avmm_clk ),
+ .reconfig_reset ( avmm_reset ),
+
+ // User AVMM input
+ .user_read ( split_user_read ),
+ .user_write ( split_user_write ),
+ .user_address ( split_user_address ),
+ .user_writedata ( split_user_writedata ),
+ .user_read_write ( user_read_write ),
+ .user_waitrequest ( split_user_waitrequest ),
+
+ // Reconfig Steamer AVMM input
+ .strm_read ( rcfg_emb_strm_read ),
+ .strm_write ( rcfg_emb_strm_write ),
+ .strm_address ( rcfg_emb_strm_address ),
+ .strm_writedata ( rcfg_emb_strm_writedata ),
+ .strm_read_write ( rcfg_emb_strm_read_write ),
+ .strm_waitrequest ( rcfg_emb_strm_waitrequest ),
+
+ // ADME AVMM input
+ .jtag_read ( split_jtag_read ),
+ .jtag_write ( split_jtag_write ),
+ .jtag_address ( split_jtag_address ),
+ .jtag_writedata ( split_jtag_writedata ),
+ .jtag_read_write ( jtag_read_write ),
+ .jtag_waitrequest ( split_jtag_waitrequest ),
+
+ // AVMM output the interface and the CSR
+ .avmm_waitrequest ( chnl_waitrequest ),
+ .avmm_read ( chnl_read ),
+ .avmm_write ( chnl_write ),
+ .avmm_address ( avmm_address ),
+ .avmm_writedata ( expanded_avmm_writedata )
+ );
+ end else begin: g_arbiter_disable
+ // Pass through signals
+ assign split_user_waitrequest = chnl_waitrequest;
+ assign chnl_read = split_user_read;
+ assign chnl_write = split_user_write;
+ assign expanded_avmm_writedata = split_user_writedata;
+ assign avmm_address = split_user_address;
+
+ end
+endgenerate // End g_arbiter
+
+
+/**********************************************************************/
+// Per interface instantiations and assignments
+/**********************************************************************/
+generate for(ig=0;ig<INTERFACES;ig=ig+1) begin: g_optional_chnl_reconfig_logic
+
+ /**********************************************************************/
+ // Instantiate the Soft CSR
+ /**********************************************************************/
+ if(dbg_embedded_debug_enable) begin: g_avmm_csr_enabled
+
+ // Instantiate wires as part of generate to avoid warnings about unused wires.
+ // AVMM reconfiguration signals for embedded debug
+ wire [INTERFACES-1:0] debug_write;
+ wire [INTERFACES-1:0] debug_read;
+ wire [INTERFACES-1:0] debug_waitrequest;
+ wire [INTERFACES*8-1:0] debug_readdata;
+
+ // avmm arbitration for soft csr and interface
+ assign debug_read [ig] = (avmm_address[ig*ADDR_BITS+9]) ? chnl_read [ig] : 1'b0;
+ assign debug_write [ig] = (avmm_address[ig*ADDR_BITS+9]) ? chnl_write [ig] : 1'b0;
+ assign avmm_read [ig] = (avmm_address[ig*ADDR_BITS+9]) ? 1'b0 : chnl_read [ig];
+ assign avmm_write [ig] = (avmm_address[ig*ADDR_BITS+9]) ? 1'b0 : chnl_write [ig];
+ assign chnl_waitrequest [ig] = (avmm_address[ig*ADDR_BITS+9]) ? debug_waitrequest [ig] : avmm_waitrequest [ig];
+ assign chnl_readdata [ig*8+:8] = (avmm_address[ig*ADDR_BITS+9]) ? debug_readdata [ig*8+:8] : avmm_readdata [ig*8+:8];
+
+
+ alt_xcvr_pll_avmm_csr #(
+ .dbg_capability_reg_enable ( dbg_capability_reg_enable ),
+ .dbg_user_identifier ( dbg_user_identifier ),
+ .dbg_stat_soft_logic_enable ( dbg_stat_soft_logic_enable ),
+ .dbg_ctrl_soft_logic_enable ( dbg_ctrl_soft_logic_enable ),
+ .en_master_cgb ( en_master_cgb ),
+ .rcfg_emb_strm_enable ( RCFG_EMB_STRM_ENABLED ),
+ .rcfg_emb_strm_cfg_sel_width ( RCFG_EMB_STRM_CFG_SEL_WIDTH )
+ ) embedded_debug_soft_csr (
+ // avmm signals
+ .avmm_clk ( avmm_clk [ig] ),
+ .avmm_reset ( avmm_reset [ig] ),
+ .avmm_address ( avmm_address [ig*ADDR_BITS+:9] ),
+ .avmm_writedata ( avmm_writedata [ig*8+:8] ),
+ .avmm_write ( debug_write [ig] ),
+ .avmm_read ( debug_read [ig] ),
+ .avmm_readdata ( debug_readdata [ig*8+:8] ),
+ .avmm_waitrequest ( debug_waitrequest [ig] ),
+
+ // input status signals from the interface
+ .pll_powerdown (in_pll_powerdown),
+ .pll_locked (in_pll_locked),
+ .pll_cal_busy (in_pll_cal_busy),
+ .avmm_busy (in_avmm_busy),
+
+ // embedded reconfig signals
+ .rcfg_emb_strm_busy ( rcfg_emb_strm_busy [ig] ),
+ .rcfg_emb_strm_chan_sel ( rcfg_emb_strm_chan_sel [ig] ),
+ .rcfg_emb_strm_cfg_sel ( rcfg_emb_strm_cfg_sel [ig*RCFG_EMB_STRM_CFG_SEL_WIDTH+:RCFG_EMB_STRM_CFG_SEL_WIDTH]),
+ .rcfg_emb_strm_bcast_en ( rcfg_emb_strm_bcast_en [ig] ),
+ .rcfg_emb_strm_cfg_load ( rcfg_emb_strm_cfg_load [ig] ),
+
+
+ // output control signals
+ .csr_pll_powerdown (out_pll_powerdown)
+ );
+
+ end else begin: g_avmm_csr_disable
+ // do a pass though for control signals when no embedded debug
+ assign out_pll_powerdown = in_pll_powerdown;
+
+ // assign these signals to ground when no embedded debug
+ assign avmm_read [ig] = chnl_read [ig];
+ assign avmm_write [ig] = chnl_write [ig];
+ assign chnl_waitrequest [ig] = avmm_waitrequest [ig];
+ assign chnl_readdata [ig*8+:8] = avmm_readdata [ig*8+:8];
+ end
+
+ end // End for Loop for interfaces
+endgenerate
+
+endmodule
+
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_pll_avmm_csr.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_pll_avmm_csr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..49410f534936769ff4cb9eab76d5a9338816cd94
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_pll_avmm_csr.sv
@@ -0,0 +1,244 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+module alt_xcvr_pll_avmm_csr #(
+ parameter dbg_capability_reg_enable = 0,
+ parameter dbg_user_identifier = 0,
+ parameter dbg_stat_soft_logic_enable = 0,
+ parameter dbg_ctrl_soft_logic_enable = 0,
+ parameter en_master_cgb = 0,
+ parameter rcfg_emb_strm_enable = 0,
+ parameter rcfg_emb_strm_cfg_sel_width = 2
+) (
+ // avmm signals
+ input avmm_clk,
+ input avmm_reset,
+ input [8:0] avmm_address,
+ input [7:0] avmm_writedata,
+ input avmm_write,
+ input avmm_read,
+ output reg [7:0] avmm_readdata,
+ output avmm_waitrequest,
+
+ // PLL Status signal
+ input pll_powerdown,
+ input pll_locked,
+ input pll_cal_busy,
+ input avmm_busy,
+
+ // embedded reconfig signals
+ input rcfg_emb_strm_busy,
+ input rcfg_emb_strm_chan_sel,
+ output [rcfg_emb_strm_cfg_sel_width-1:0] rcfg_emb_strm_cfg_sel,
+ output rcfg_emb_strm_bcast_en,
+ output rcfg_emb_strm_cfg_load,
+
+ // PLL Control Signals
+ output csr_pll_powerdown
+);
+
+// Import package with parameters for the soft addresses and offsets
+import a10_avmm_h::*;
+
+// Reg for generating waitrequest and data valid
+reg avmm_valid;
+
+/**********************************************************************/
+// wires and bus declaration
+/**********************************************************************/
+wire [7:0] rd_system_id;
+wire [7:0] rd_status_en;
+wire [7:0] rd_control_en;
+wire [7:0] rd_mcgb_en;
+wire [7:0] rd_ctrl_pll_lock;
+wire [7:0] rd_pll_reset;
+wire [7:0] rd_rcfg_emb_ctrl;
+wire [7:0] rd_rcfg_emb_status;
+
+/**********************************************************************/
+//generate waitrequest
+/**********************************************************************/
+assign avmm_waitrequest = (~avmm_valid & avmm_read);
+
+/**********************************************************************/
+// soft CSRs for embedded debug
+/**********************************************************************/
+always@(posedge avmm_clk) begin
+ if(~avmm_read) begin
+ avmm_valid <= 1'b0;
+ avmm_readdata <= RD_UNUSED;
+ end else begin
+ avmm_valid <= avmm_waitrequest;
+ case(avmm_address)
+ A10_XR_ADDR_ID_0: avmm_readdata <= rd_system_id;
+ A10_XR_ADDR_STATUS_EN: avmm_readdata <= rd_status_en;
+ A10_XR_ADDR_CONTROL_EN: avmm_readdata <= rd_control_en;
+ A10_XR_ADDR_PLL_MCGB_EN:avmm_readdata <= rd_mcgb_en;
+
+ A10_XR_ADDR_GP_PLL_LOCK:avmm_readdata <= rd_ctrl_pll_lock;
+
+ A10_XR_ADDR_GP_PLL_RST: avmm_readdata <= rd_pll_reset;
+
+ //Embedded reconfig
+ A10_XR_ADDR_EMBED_RCFG_CTRL: avmm_readdata <= rd_rcfg_emb_ctrl;
+ A10_XR_ADDR_EMBED_RCFG_STATUS: avmm_readdata <= rd_rcfg_emb_status;
+
+ default: avmm_readdata <= RD_UNUSED;
+ endcase
+ end
+end
+
+
+/**********************************************************************/
+// Capability Registers
+/**********************************************************************/
+generate if(dbg_capability_reg_enable == 1) begin: enable_pll_capability_reg
+ assign rd_system_id = dbg_user_identifier[7:0];
+ assign rd_status_en = dbg_stat_soft_logic_enable[7:0];
+ assign rd_control_en = dbg_ctrl_soft_logic_enable[7:0];
+ assign rd_mcgb_en = en_master_cgb[7:0];
+end else begin
+ assign rd_system_id = RD_UNUSED;
+ assign rd_status_en = RD_UNUSED;
+ assign rd_control_en = RD_UNUSED;
+ assign rd_mcgb_en = RD_UNUSED;
+end
+endgenerate
+
+
+/**********************************************************************/
+// Generate registers for status signals
+/**********************************************************************/
+generate if(dbg_stat_soft_logic_enable == 1) begin: en_stat_reg
+
+ /**********************************************************************/
+ // wires for synchronizers
+ /**********************************************************************/
+ wire pll_cal_busy_sync;
+ wire pll_locked_sync;
+ reg r_avmm_busy;
+
+
+ /**********************************************************************/
+ // readback data at OFFSET synchronize the incoming signals
+ /**********************************************************************/
+ alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 2 ) // two bits, one for locktodata and one for locktoref
+ ) rx_is_locked_sync (
+ .clk (avmm_clk),
+ .reset (avmm_reset),
+ .d ({pll_cal_busy, pll_locked}),
+ .q ({pll_cal_busy_sync, pll_locked_sync})
+ );
+
+
+ assign rd_ctrl_pll_lock[A10_XR_OFFSET_GP_LOCK] = pll_locked_sync;
+ assign rd_ctrl_pll_lock[A10_XR_OFFSET_GP_CAL_BUSY] = pll_cal_busy_sync;
+ assign rd_ctrl_pll_lock[A10_XR_OFFSET_GP_AVMM_BUSY] = r_avmm_busy;
+ assign rd_ctrl_pll_lock[A10_XR_OFFSET_LOCK_UNUSED+:A10_XR_LOCK_UNUSED_LEN] = {A10_XR_LOCK_UNUSED_LEN{1'b0}};
+
+ always@(posedge avmm_clk) begin
+ r_avmm_busy <= avmm_busy;
+ end
+
+ end else begin
+ assign rd_ctrl_pll_lock = RD_UNUSED;
+ end
+endgenerate
+
+
+/**********************************************************************/
+// Generate registers for control signals
+/**********************************************************************/
+generate if(dbg_ctrl_soft_logic_enable == 1) begin: en_ctrl_reg
+
+ // register for embedded debug-driven powerdown
+ reg r_pll_reset;
+ reg r_pll_reset_override;
+
+ // readback control signals for the pll powerdown
+ assign rd_pll_reset[A10_XR_OFFSET_PLL_RST] = r_pll_reset;
+ assign rd_pll_reset[A10_XR_OFFSET_PLL_RST_OVR] = r_pll_reset_override;
+ assign rd_pll_reset[A10_XR_OFFSET_PLL_RST_UNUSED+:A10_XR_PLL_RST_UNUSED_LEN] = {A10_XR_PLL_RST_UNUSED_LEN{1'b0}};
+
+ // assign the output control signal to the pll
+ assign csr_pll_powerdown = (rd_pll_reset[A10_XR_OFFSET_PLL_RST_OVR]) ? rd_pll_reset[A10_XR_OFFSET_PLL_RST] : pll_powerdown;
+
+ // write control registers for pll_powerodwn
+ always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ r_pll_reset <= 1'b0;
+ r_pll_reset_override <= 1'b0;
+ end else if(avmm_write && avmm_address == A10_XR_ADDR_GP_PLL_RST) begin
+ r_pll_reset <= avmm_writedata[A10_XR_OFFSET_PLL_RST];
+ r_pll_reset_override <= avmm_writedata[A10_XR_OFFSET_PLL_RST_OVR];
+ end
+ end
+ end else begin
+ // assign pll powerdown when the ctrl registers arn't used
+ assign rd_pll_reset = RD_UNUSED;
+ assign csr_pll_powerdown = (pll_powerdown);
+ end
+endgenerate
+
+/**********************************************************************/
+// Embedded reconfig registers
+/**********************************************************************/
+generate if(rcfg_emb_strm_enable) begin: en_rcfg_reg
+
+ /**********************************************************************/
+ // Generate registers and wires for the reconfig soft logic
+ /**********************************************************************/
+ reg [rcfg_emb_strm_cfg_sel_width-1:0] r_rcfg_emb_strm_cfg_sel;
+ reg r_rcfg_emb_strm_cfg_load;
+ reg r_rcfg_emb_strm_bcast_en;
+ reg rcfg_emb_strm_cfg_load_lock = 1'b0;
+
+ // readback the embedded reconfig control
+ assign rd_rcfg_emb_ctrl = {r_rcfg_emb_strm_cfg_load, r_rcfg_emb_strm_bcast_en, {(A10_XR_EMBED_RCFG_CFG_SEL_LEN-rcfg_emb_strm_cfg_sel_width){1'b0}}, r_rcfg_emb_strm_cfg_sel};
+ assign rd_rcfg_emb_status = {7'b0, rcfg_emb_strm_busy};
+
+ // assign the output signals to the channel
+ assign rcfg_emb_strm_cfg_sel = r_rcfg_emb_strm_cfg_sel;
+ assign rcfg_emb_strm_cfg_load = r_rcfg_emb_strm_cfg_load;
+ assign rcfg_emb_strm_bcast_en = r_rcfg_emb_strm_bcast_en;
+
+ always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ r_rcfg_emb_strm_cfg_sel <= {rcfg_emb_strm_cfg_sel_width{1'b0}};
+ r_rcfg_emb_strm_cfg_load <= 1'b0;
+ r_rcfg_emb_strm_bcast_en <= 1'b0;
+ rcfg_emb_strm_cfg_load_lock <= 1'b0;
+ end else if(avmm_write && avmm_address == A10_XR_ADDR_EMBED_RCFG_CTRL) begin
+ // Write to this register
+ r_rcfg_emb_strm_cfg_sel <= avmm_writedata[A10_XR_OFFSET_EMBED_RCFG_CFG_SEL +: rcfg_emb_strm_cfg_sel_width ];
+ r_rcfg_emb_strm_cfg_load <= avmm_writedata[A10_XR_OFFSET_EMBED_RCFG_CFG_LOAD];
+ r_rcfg_emb_strm_bcast_en <= avmm_writedata[A10_XR_OFFSET_EMBED_RCFG_BCAST_EN];
+ end else if(rcfg_emb_strm_chan_sel & rcfg_emb_strm_busy & ~rcfg_emb_strm_cfg_load_lock) begin
+ // Reset the cfg_load bit when the streaming has started
+ r_rcfg_emb_strm_cfg_load <= 1'b0;
+ rcfg_emb_strm_cfg_load_lock <= 1'b1;
+ end else if(~rcfg_emb_strm_busy & rcfg_emb_strm_cfg_load_lock)
+ rcfg_emb_strm_cfg_load_lock <= 1'b0;
+ end
+ end else begin: g_rcfg_reg_dis
+ assign rd_rcfg_emb_ctrl = RD_UNUSED;
+ assign rd_rcfg_emb_status = RD_UNUSED;
+ assign rcfg_emb_strm_cfg_sel = 1'b0;
+ assign rcfg_emb_strm_bcast_en = 1'b0;
+ assign rcfg_emb_strm_cfg_load = 1'b0;
+ end
+endgenerate //End generate g_rcfg_reg
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_pll_embedded_debug.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_pll_embedded_debug.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2283b1af4f23ca3079bd1411e72e829208c14b19
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_pll_embedded_debug.sv
@@ -0,0 +1,75 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+module alt_xcvr_pll_embedded_debug #(
+ parameter dbg_capability_reg_enable = 0,
+ parameter dbg_user_identifier = 0,
+ parameter dbg_stat_soft_logic_enable = 0,
+ parameter dbg_ctrl_soft_logic_enable = 0,
+ parameter en_master_cgb = 0
+) (
+ // avmm signals
+ input avmm_clk,
+ input avmm_reset,
+ input [8:0] avmm_address,
+ input [7:0] avmm_writedata,
+ input avmm_write,
+ input avmm_read,
+ output [7:0] avmm_readdata,
+ output avmm_waitrequest,
+
+ // input signals from the core
+ input in_pll_powerdown,
+ input in_pll_locked,
+ input in_pll_cal_busy,
+ input in_avmm_busy,
+
+ // output signals to the ip
+ output out_pll_powerdown
+);
+
+wire prbs_done_sync;
+wire csr_prbs_snapshot;
+wire csr_prbs_count_en;
+wire csr_prbs_reset;
+wire [47:0] prbs_err_count;
+wire [47:0] prbs_bit_count;
+
+alt_xcvr_pll_avmm_csr #(
+ .dbg_capability_reg_enable ( dbg_capability_reg_enable ),
+ .dbg_user_identifier ( dbg_user_identifier ),
+ .dbg_stat_soft_logic_enable ( dbg_stat_soft_logic_enable ),
+ .dbg_ctrl_soft_logic_enable ( dbg_ctrl_soft_logic_enable ),
+ .en_master_cgb ( en_master_cgb)
+) embedded_debug_soft_csr (
+ // avmm signals
+ .avmm_clk (avmm_clk),
+ .avmm_reset (avmm_reset),
+ .avmm_address (avmm_address),
+ .avmm_writedata (avmm_writedata),
+ .avmm_write (avmm_write),
+ .avmm_read (avmm_read),
+ .avmm_readdata (avmm_readdata),
+ .avmm_waitrequest (avmm_waitrequest),
+
+ // input status signals from the channel
+ .pll_powerdown (in_pll_powerdown),
+ .pll_locked (in_pll_locked),
+ .pll_cal_busy (in_pll_cal_busy),
+ .avmm_busy (in_avmm_busy),
+
+ // output control signals
+ .csr_pll_powerdown (out_pll_powerdown)
+);
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_resync.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_resync.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2f0f3fe0b7b8c3b0f584954c44bc70c1ddd88480
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/alt_xcvr_resync.sv
@@ -0,0 +1,97 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Module: alt_xcvr_resync
+//
+// Description:
+// A general purpose resynchronization module.
+//
+// Parameters:
+// SYNC_CHAIN_LENGTH
+// - Specifies the length of the synchronizer chain for metastability
+// retiming.
+// WIDTH
+// - Specifies the number of bits you want to synchronize. Controls the width of the
+// d and q ports.
+// SLOW_CLOCK - USE WITH CAUTION.
+// - Leaving this setting at its default will create a standard resynch circuit that
+// merely passes the input data through a chain of flip-flops. This setting assumes
+// that the input data has a pulse width longer than one clock cycle sufficient to
+// satisfy setup and hold requirements on at least one clock edge.
+// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
+// circuit that will capture the input data regardless of the pulse width and
+// its relationship to the clock. However it is more difficult to apply static
+// timing constraints as it ties the data input to the clock input of the flop.
+// This implementation assumes the data rate is slow enough
+// INIT_VALUE
+// - Specifies the initial values of the synchronization registers.
+//
+// Apply embedded false path timing constraint
+(* altera_attribute = "-name SDC_STATEMENT \"set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}\"" *)
+
+`timescale 1ps/1ps
+
+module alt_xcvr_resync #(
+ parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming. Must be >1
+ parameter WIDTH = 1, // Number of bits to resync
+ parameter SLOW_CLOCK = 0, // See description above
+ parameter INIT_VALUE = 0
+ ) (
+ input wire clk,
+ input wire reset,
+ input wire [WIDTH-1:0] d,
+ output wire [WIDTH-1:0] q
+ );
+
+localparam INT_LEN = (SYNC_CHAIN_LENGTH > 1) ? SYNC_CHAIN_LENGTH : 2;
+localparam [INT_LEN-1:0] L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};
+
+genvar ig;
+
+// Generate a synchronizer chain for each bit
+generate begin
+ for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
+ wire d_in; // Input to sychronization chain.
+ (* altera_attribute = "disable_da_rule=D103" *)
+ reg [INT_LEN-1:0] sync_r = L_INIT_VALUE;
+
+ assign q[ig] = sync_r[INT_LEN-1]; // Output signal
+
+ always @(posedge clk or posedge reset)
+ if(reset)
+ sync_r <= L_INIT_VALUE;
+ else
+ sync_r <= {sync_r[INT_LEN-2:0],d_in};
+
+ // Generate asynchronous capture circuit if specified.
+ if(SLOW_CLOCK == 0) begin
+ assign d_in = d[ig];
+ end else begin
+ wire d_clk;
+ reg d_r = L_INIT_VALUE[0];
+ wire clr_n;
+
+ assign d_clk = d[ig];
+ assign d_in = d_r;
+ assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
+
+ // Asynchronously latch the input signal.
+ always @(posedge d_clk or negedge clr_n)
+ if(!clr_n) d_r <= 1'b0;
+ else if(d_clk) d_r <= 1'b1;
+ end // SLOW_CLOCK
+ end // for loop
+end // generate
+endgenerate
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/altera_xcvr_native_a10_functions_h.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/altera_xcvr_native_a10_functions_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..8ed2369d39b57aea4e81061216eaab25f5e05314
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/altera_xcvr_native_a10_functions_h.sv
@@ -0,0 +1,154 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common functions for Arria 10 Native PHY IP
+//
+`timescale 1 ps/1 ps
+
+package altera_xcvr_native_a10_functions_h;
+
+ localparam MAX_CONVERSION_SIZE_ALT_XCVR_NATIVE_A10 = 128;
+ localparam MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10 = 64;
+ localparam integer MAX_CHARS_ALT_XCVR_NATIVE_A10 = 86; // To accomodate LONG parameter lists.
+
+ ////////////////////////////////////////////////////////////////////
+ // Return the number of bits required to represent an integer
+ // E.g. 0->1; 1->1; 2->2; 3->2 ... 31->5; 32->6
+ //
+ function integer clogb2_alt_xcvr_native_a10;
+ input integer input_num;
+ begin
+ for (clogb2_alt_xcvr_native_a10=0; input_num>0; clogb2_alt_xcvr_native_a10=clogb2_alt_xcvr_native_a10+1)
+ input_num = input_num >> 1;
+ if(clogb2_alt_xcvr_native_a10 == 0)
+ clogb2_alt_xcvr_native_a10 = 1;
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Used to calculate the value of the "hssi_10g_tx_pcs_comp_cnt"
+ // parameter for a givin channel in a bonded configuration
+ //
+ // @param channels - Number of channels in the interface
+ // @param pcs_bonding_master - PCS master channel index
+ // @param channel_index - Index of channel within interface to determine
+ // parameter value for.
+ //
+ // @return An integer value for the parameter "hssi_10g_tx_pcs_comp_cnt".
+ function [7:0] get_comp_cnt_alt_xcvr_native_a10;
+ input integer channels;
+ input integer pcs_bonding_master;
+ input integer channel_index;
+
+ integer max_index;
+ integer comp_cnt;
+ begin
+ // Determine the index of the master
+ max_index = (pcs_bonding_master > (channels - pcs_bonding_master)) ? pcs_bonding_master
+ : (channels-pcs_bonding_master);
+ // Determine the index of this channel
+ if (channel_index == pcs_bonding_master)
+ comp_cnt = max_index;
+ else if (channel_index < pcs_bonding_master)
+ comp_cnt = max_index - (pcs_bonding_master - channel_index);
+ else
+ comp_cnt = max_index - (channel_index - pcs_bonding_master);
+ // Convert index to count value
+ comp_cnt = comp_cnt * 2;
+ get_comp_cnt_alt_xcvr_native_a10 = comp_cnt[7:0];
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Used to calculate the value of the distance of current channel to mcgb
+ //
+ // @param pcs_bonding_master - PCS master channel index
+ // @param channel_index - Index of channel within interface to determine
+ // parameter value for.
+ //
+ // @return An 4 bits value for the parameter lower 3 showing distance, if MSB 1 then the current channel is above the mcgb
+ function [3:0] get_mcgb_location_alt_xcvr_native_a10(
+ input integer pcs_bonding_master,
+ input integer channel_index
+ );
+ integer distance;
+ begin
+ if (channel_index < pcs_bonding_master) begin
+ distance = pcs_bonding_master-channel_index;
+ get_mcgb_location_alt_xcvr_native_a10 = {1'b1,distance[2:0]};
+ end else begin
+ distance = channel_index-pcs_bonding_master;
+ get_mcgb_location_alt_xcvr_native_a10 = {1'b0,distance[2:0]};
+ end
+ end
+ endfunction
+
+
+ function automatic [MAX_CONVERSION_SIZE_ALT_XCVR_NATIVE_A10-1:0] str_2_bin_alt_xcvr_native_a10;
+ input [MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10*8-1:0] instring;
+
+ integer this_char;
+ integer i;
+ begin
+ // Initialize accumulator
+ str_2_bin_alt_xcvr_native_a10 = {MAX_CONVERSION_SIZE_ALT_XCVR_NATIVE_A10{1'b0}};
+ for(i=MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10-1;i>=0;i=i-1) begin
+ this_char = instring[i*8+:8];
+ // Add value of this digit
+ if(this_char >= 48 && this_char <= 57)
+ str_2_bin_alt_xcvr_native_a10 = (str_2_bin_alt_xcvr_native_a10 * 10) + (this_char - 48);
+ end
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Adds an offets to 'scrambler seed' per channel for interlaken as:
+ // (58'h123456789abcde + user_seed + (24'h826a3*lane_number))
+ // see FB 138336 for details
+ //
+ // @param protocol_hint - only interlaken matters
+ // @param user_seed - 58 bit base seed to be modified per channel
+ // @param lane_number - Index of channel within interface to determine
+ // parameter value for.
+ //
+ // @return 58 bits scrambler seed for the channel
+ function [57:0] set_10g_scrm_seed_user_alt_xcvr_native_a10 (
+ input [8*MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10:1] protocol_hint,
+ input [57:0] user_seed,
+ input integer lane_number
+ );
+ set_10g_scrm_seed_user_alt_xcvr_native_a10 = (protocol_hint == "interlaken_mode") ? (58'h123456789abcde + user_seed + (24'h826a3*lane_number)) : user_seed;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Convert an integer to a string
+ function [MAX_CHARS_ALT_XCVR_NATIVE_A10*8-1:0] int2str_alt_xcvr_native_a10(
+ input integer in_int
+ );
+ integer i;
+ integer this_char;
+ i = 0;
+ int2str_alt_xcvr_native_a10 = "";
+ do
+ begin
+ this_char = (in_int % 10) + 48;
+ int2str_alt_xcvr_native_a10[i*8+:8] = this_char[7:0];
+ i=i+1;
+ in_int = in_int / 10;
+ end
+ while(in_int > 0);
+ endfunction
+
+
+endpackage
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/arria10_hps_altera_xcvr_atx_pll_a10_221_syj5sga.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/arria10_hps_altera_xcvr_atx_pll_a10_221_syj5sga.sv
new file mode 100644
index 0000000000000000000000000000000000000000..e24f378fef6fcf6c8fd0cc62adf226c182c576ce
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/arria10_hps_altera_xcvr_atx_pll_a10_221_syj5sga.sv
@@ -0,0 +1,706 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+
+//------------------------------------------------------------------
+// filename: altera_xcvr_atx_pll_a10.sv.terp
+//
+// Description : instantiates avmm and lc-pll
+//
+// Limitation : Intended for NightFury
+//
+// Copyright (c) Altera Corporation 1997-2012
+// All rights reserved
+//-------------------------------------------------------------------
+//
+// NOTEs
+// - comments marked with OPEN means there is an issue that needs to be resolved but cannot be done due to lack of information.
+// - comments marked with TODO means there is an issue that needs to be resolved and there is enough information already for the issue to be resolved.
+//
+//-------------------------------------------------------------------
+
+
+// OPEN should we remove timescale?
+`timescale 1 ns / 1 ns
+
+module arria10_hps_altera_xcvr_atx_pll_a10_221_syj5sga
+#(
+ parameter enable_debug_info = "true", // RANGE false|true NOTE: this is simulation-only parameter, for debug purpose only
+
+ parameter atx_pll_regulator_bypass = "reg_enable",
+ parameter atx_pll_pfd_delay_compensation = "normal_delay",
+ parameter atx_pll_xcpvco_xchgpmplf_cp_current_boost = "normal_setting",
+ parameter atx_pll_pfd_pulse_width = "pulse_width_setting0",
+
+ parameter atx_pll_l_counter_enable = "true", // RANGE true (false)
+ parameter atx_pll_fb_select = "direct_fb", // RANGE (direct_fb) iqtxrxclk_fb
+ parameter atx_pll_bonding_mode = "cpri_bonding", // RANGE (cpri_bonding) pll_bonding NOTE CPRI is for external feedback mode without feedback compensation bonding and PLL is for external feedback with feedback compensation bonding
+ parameter atx_pll_prot_mode = "basic_tx", // RANGE "unused" (basic_tx) "basic_kr_tx" "pcie_gen1_tx" "pcie_gen2_tx" "pcie_gen3_tx" "pcie_gen4_tx" "cei_tx" "qpi_tx" "cpri_tx" "fc_tx" "srio_tx" "gpon_tx" "sdi_tx" "sata_tx" "xaui_tx" "obsai_tx" "gige_tx" "higig_tx" "sonet_tx" "sfp_tx" "xfp_tx" "sfi_tx"
+ parameter atx_pll_silicon_rev = "20nm5es", // RANGE (20nm5es) "20nm5es2" "20nm4" "20nm3" "20nm4qor" "20nm2" "20nm1"
+ parameter atx_pll_bw_sel = "low", // RANGE (low) medium high
+ parameter atx_pll_dsm_mode = "dsm_mode_integer", // RANGE (dsm_mode_integer) dsm_mode_phase
+ parameter atx_pll_reference_clock_frequency = "0 ps",
+ parameter atx_pll_output_clock_frequency = "0 ps",
+ parameter atx_pll_m_counter = 1, // RANGE (1) 2 3 4 5 6 8 9 10 12 15 16 18 20 24 25 30 32 36 40 48 50 60 64 80 100
+ parameter atx_pll_ref_clk_div = 1, // RANGE (1) 2 4 8
+ parameter atx_pll_l_counter = 1, // RANGE (1) 2 4 8 16
+ parameter atx_pll_dsm_fractional_division = "1", // This is a string value of a 32 bitvec
+ parameter atx_pll_tank_band = "lc_band0", // RANGE (lc_band0) lc_band1 lc_band2 lc_band3 lc_band4 lc_band5 lc_band6 lc_band7
+ parameter atx_pll_tank_sel = "lctank0", // RANGE (lctank0) lctank1 lctank2
+ parameter atx_pll_hclk_divide = 1, // RANGE (1) 40 50
+ parameter atx_pll_cgb_div = 1, // RANGE (1) 2 4 8
+ parameter atx_pll_pma_width = 8, // RANGE (8) 10 16 20 32 40 64
+
+ parameter atx_pll_primary_use = "hssi_x1",
+ parameter atx_pll_lc_mode = "lccmu_normal", // RANGE (lccmu_pd) lccmu_normal lccmu_reset
+ parameter atx_pll_lc_atb = "atb_selectdisable", // RANGE (atb_selectdisable) atb_select0 atb_select1 atb_select2 atb_select3 atb_select4 atb_select5 atb_select6 atb_select7 atb_select8 atb_select9 atb_select10 atb_select11 atb_select12 atb_select13 atb_select14 atb_select15 atb_select16 atb_select17 atb_select18 atb_select19 atb_select20 atb_select21 atb_select22 atb_select23 atb_select24 atb_select25 atb_select26 atb_select27 atb_select28 atb_select29 atb_select30
+ parameter atx_pll_cp_compensation_enable = "true", // RANGE false (true)
+ parameter atx_pll_cp_current_setting = "cp_current_setting0", // RANGE (cp_current_setting0) cp_current_setting1 cp_current_setting2 cp_current_setting3 cp_current_setting4 cp_current_setting5 cp_current_setting6 cp_current_setting7 cp_current_setting8 cp_current_setting9 cp_current_setting10 cp_current_setting11
+ parameter atx_pll_cp_testmode = "cp_normal", // RANGE (cp_normal) cp_test_up cp_test_dn cp_tristate
+ parameter atx_pll_cp_lf_3rd_pole_freq = "lf_3rd_pole_setting0", // RANGE (lf_3rd_pole_setting0) lf_3rd_pole_setting1 lf_3rd_pole_setting2 lf_3rd_pole_setting3
+ parameter atx_pll_cp_lf_order = "lf_2nd_order", // RANGE (lf_2nd_order) lf_3rd_order lf_4th_order
+ parameter atx_pll_lf_resistance = "lf_setting0", // RANGE (lf_setting0) lf_setting1 lf_setting2 lf_setting3
+ parameter atx_pll_lf_ripplecap = "lf_ripple_cap_0", // RANGE lf_no_ripple (lf_ripple_cap_0) lf_ripple_cap_1
+ parameter atx_pll_d2a_voltage = "d2a_disable", // RANGE d2a_setting_0 d2a_setting_1 d2a_setting_2 d2a_setting_3 d2a_setting_4 d2a_setting_5 d2a_setting_6 d2a_setting_7 (d2a_disable)
+ parameter atx_pll_dsm_out_sel = "pll_dsm_disable", // RANGE (pll_dsm_disable) pll_dsm_1st_order pll_dsm_2nd_order pll_dsm_3rd_order
+ parameter atx_pll_dsm_ecn_bypass = "false", // RANGE (false) true
+ parameter atx_pll_dsm_ecn_test_en = "false", // RANGE (false) true
+ parameter atx_pll_dsm_fractional_value_ready = "pll_k_ready", // RANGE pll_k_not_ready (pll_k_ready)
+ parameter atx_pll_vco_bypass_enable = "false", // RANGE (false) true
+ parameter atx_pll_cascadeclk_test = "cascadetest_off", // RANGE (cascadetest_off) cascadetest_on
+ parameter atx_pll_tank_voltage_coarse = "vreg_setting_coarse1", // RANGE vreg_setting_coarse0 (vreg_setting_coarse1) vreg_setting_coarse2 vreg_setting_coarse3
+ parameter atx_pll_tank_voltage_fine = "vreg_setting3", // RANGE vreg_setting0 vreg_setting1 vreg_setting2 (vreg_setting3) vreg_setting4 vreg_setting5 vreg_setting6 vreg_setting7
+ parameter atx_pll_output_regulator_supply = "vreg1v_setting1", // RANGE vreg1v_setting0 (vreg1v_setting1) vreg1v_setting2 vreg1v_setting3
+ parameter atx_pll_overrange_voltage = "over_setting3", // RANGE over_setting0 over_setting1 over_setting2 (over_setting3) over_setting4 over_setting5 over_setting6 over_setting7
+ parameter atx_pll_underrange_voltage = "under_setting3", // RANGE under_setting0 under_setting1 under_setting2 (under_setting3) under_setting4 under_setting5 under_setting6 under_setting7
+ parameter atx_pll_is_cascaded_pll = "false", // RANGE (false) true
+ parameter atx_pll_is_otn = "false", // RANGE (false) true
+ parameter atx_pll_is_sdi = "false", // RANGE (false) true
+ parameter atx_pll_side = "side_unknown", // RANGE (side_unknown) left right
+
+ parameter atx_pll_lf_cbig_size = "lf_cbig_setting0" , // RANGE (lf_cbig_setting0) , lf_cbig_setting1 , lf_cbig_setting2 , lf_cbig_setting3 , lf_cbig_setting4
+ parameter atx_pll_iqclk_mux_sel = "power_down" , // RANGE iqtxrxclk0 , iqtxrxclk1 , iqtxrxclk2 , iqtxrxclk3 , iqtxrxclk4 , iqtxrxclk5 , (power_down)
+ parameter atx_pll_enable_hclk = "hclk_disabled" , // RANGE (hclk_disabled), hclk_enable
+ parameter atx_pll_calibration_mode = "cal_off" , // RANGE (cal_off), uc_rst_pll , uc_rst_lf , uc_not_rst
+ parameter atx_pll_datarate = "0 bps" , // RANGE
+ parameter atx_pll_device_variant = "device1" , // RANGE (device1), device2 , device3 , device4 , device5
+ parameter atx_pll_initial_settings = "true" , // RANGE (false), true
+ parameter [4:0] atx_pll_l_counter_scratch = 5'b00001 , // RANGE (5)
+ parameter [2:0] atx_pll_n_counter_scratch = 3'b001 , // RANGE (3)
+ parameter atx_pll_powerdown_mode = "powerup" , // RANGE (powerup) , powerdown
+ parameter atx_pll_sup_mode = "user_mode" , // RANGE (user_mode) , engineering_mode
+ parameter atx_pll_vco_freq = "0 hz", // RANGE
+ parameter atx_pll_fpll_refclk_selection = "select_div_by_2", // RANGE (select_div_by_2), select_vco_output
+ parameter atx_pll_lc_to_fpll_l_counter = "lcounter_setting0", // RANGE (lcounter_setting0) .. lcounter_setting31
+ parameter [4:0] atx_pll_lc_to_fpll_l_counter_scratch = 5'b00000, // RANGE (5)
+
+ parameter hssi_pma_lc_refclk_select_mux_powerdown_mode = "powerup", // RANGE (powerup) powerdown
+ parameter hssi_pma_lc_refclk_select_mux_silicon_rev = "20nm5es", // RANGE (20nm5es) "20nm5es2" "20nm4" "20nm3" "20nm4qor" "20nm2" "20nm1"
+ parameter hssi_refclk_divider_silicon_rev = "20nm5es", // RANGE (20nm5es) "20nm5es2" "20nm4" "20nm3" "20nm4qor" "20nm2" "20nm1"
+ parameter hssi_pma_lc_refclk_select_mux_refclk_select = "ref_iqclk0", // RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+
+ parameter hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping = "ref_iqclk0", // RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+ parameter hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping = "ref_iqclk1", // RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+ parameter hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping = "ref_iqclk2", // RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+ parameter hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping = "ref_iqclk3", // RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+ parameter hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping = "ref_iqclk4", // RANGE (ref_iqclk0) ref_iqclk1 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9 ref_iqclk10 ref_iqclk11 iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 coreclk fixed_clk lvpecl adj_pll_clk power_down
+
+ parameter enable_mcgb = 0, // RANGE (0) 1
+ parameter enable_mcgb_debug_ports_parameters = 0, // RANGE (0) 1
+ parameter hssi_pma_cgb_master_silicon_rev = "20nm5es", // RANGE (20nm5es) "20nm5es2" "20nm4" "20nm3" "20nm4qor" "20nm2" "20nm1"
+ parameter hssi_pma_cgb_master_prot_mode = "basic_tx", // RANGE "unused" (basic_tx) "basic_kr_tx" "pcie_gen1_tx" "pcie_gen2_tx" "pcie_gen3_tx" "pcie_gen4_tx" "cei_tx" "qpi_tx" "cpri_tx" "fc_tx" "srio_tx" "gpon_tx" "sdi_tx" "sata_tx" "xaui_tx" "obsai_tx" "gige_tx" "higig_tx" "sonet_tx" "sfp_tx" "xfp_tx" "sfi_tx"
+ parameter hssi_pma_cgb_master_cgb_enable_iqtxrxclk = "disable_iqtxrxclk", // OPEN in atom default is enable in _hw.tcl default is disable // RANGE disable_iqtxrxclk (enable_iqtxrxclk)
+ parameter hssi_pma_cgb_master_x1_div_m_sel = "divbypass", // RANGE (divbypass) divby2 divby4 divby8
+ parameter hssi_pma_cgb_master_ser_mode = "eight_bit", // RANGE (eight_bit) ten_bit sixteen_bit twenty_bit thirty_two_bit forty_bit sixty_four_bit
+ parameter hssi_pma_cgb_master_datarate = "0 Mbps",
+
+ parameter hssi_pma_cgb_master_cgb_power_down = "normal_cgb", // RANGE normal_cgb (power_down_cgb)
+ parameter hssi_pma_cgb_master_bonding_reset_enable = "allow_bonding_reset", // RANGE disallow_bonding_reset (allow_bonding_reset)
+ parameter hssi_pma_cgb_master_observe_cgb_clocks = "observe_nothing", // RANGE (observe_nothing) observe_x1mux_out
+ parameter hssi_pma_cgb_master_optimal = "true", // RANGE (true) false
+ parameter hssi_pma_cgb_master_op_mode = "enabled", // RANGE (enabled) pwr_down
+ parameter hssi_pma_cgb_master_tx_ucontrol_reset_pcie = "pcscorehip_controls_mcgb", // RANGE (pcscorehip_controls_mcgb) cgb_reset tx_pcie_gen1 tx_pcie_gen2 tx_pcie_gen3 tx_pcie_gen4
+ parameter hssi_pma_cgb_master_vccdreg_output = "vccdreg_nominal", // RANGE (vccdreg_nominal) vccdreg_pos_setting0 vccdreg_pos_setting1 vccdreg_pos_setting2 vccdreg_pos_setting3 vccdreg_pos_setting4 vccdreg_pos_setting5 vccdreg_pos_setting6 vccdreg_pos_setting7 vccdreg_pos_setting8 vccdreg_pos_setting9 vccdreg_pos_setting10 vccdreg_pos_setting11 vccdreg_pos_setting12 vccdreg_pos_setting13 vccdreg_pos_setting14 vccdreg_pos_setting15 reserved1 reserved2 vccdreg_neg_setting0 vccdreg_neg_setting1 vccdreg_neg_setting2 vccdreg_neg_setting3 reserved3 reserved4 reserved5 reserved6 reserved7 reserved8 reserved9 reserved10 reserved11
+ parameter hssi_pma_cgb_master_input_select = "lcpll_top", // RANGE lcpll_bot lcpll_top fpll_bot fpll_top (unused)
+ parameter hssi_pma_cgb_master_input_select_gen3 = "unused" , // RANGE lcpll_bot lcpll_top fpll_bot fpll_top (unused)
+ parameter hssi_pma_cgb_master_pcie_gen3_bitwidth = "pciegen3_wide" , // RANGE (pciegen3_wide) pciegen3_narrow parameter powerdown_mode = "powerup" , //Valid values: powerup , powerdown
+ parameter hssi_pma_cgb_master_powerdown_mode = "powerup" , // RANGE (powerup) powerdown
+ parameter hssi_pma_cgb_master_sup_mode = "user_mode" , // RANGE (user_mode) engineering_mode
+ parameter hssi_pma_cgb_master_initial_settings = "true", // RANGE (false) true
+
+ parameter hip_cal_en = "disable", // Indicates whether HIP is enabled or not. Valid values: disable, enable
+
+
+ // NOTE following are constants, not meant to be changed in instantiations
+ parameter SIZE_AVMM_RDDATA_BUS = 32,
+ parameter SIZE_AVMM_WRDATA_BUS = 32,
+
+ // instantiate paramters for embedded debug
+ parameter rcfg_shared = 0,
+ parameter enable_pll_reconfig = 0,
+ parameter rcfg_jtag_enable = 0,
+ parameter rcfg_emb_strm_enable = 0,
+ parameter rcfg_profile_cnt = 2,
+ parameter dbg_embedded_debug_enable = 0,
+ parameter dbg_capability_reg_enable = 0,
+ parameter dbg_user_identifier = 0,
+ parameter dbg_stat_soft_logic_enable = 0,
+ parameter dbg_ctrl_soft_logic_enable = 0,
+ parameter calibration_en = "disable",
+ parameter enable_analog_resets = 0, // (0,1)
+ // 0 - Disable pll_powerdown and mcgb_rst reset input connections. Still allows soft register override
+ // 1 - Enable pll_powerdown and mcgb_rst reset input connections
+
+ parameter rcfg_separate_avmm_busy = 0 // (0,1)
+ // 0 - AVMM busy is reflected on the waitrequest
+ // 1 - AVMM busy must be read from a soft CSR
+
+ /// TODO all other pll parameters needs to be added
+) (
+ input pll_powerdown,
+ input pll_refclk0,
+ input pll_refclk1,
+ input pll_refclk2,
+ input pll_refclk3,
+ input pll_refclk4,
+ input mcgb_aux_clk0,
+ input mcgb_aux_clk1,
+ input mcgb_aux_clk2,
+ input [1:0] pcie_sw,
+
+ output tx_serial_clk,
+ output tx_serial_clk_gt,
+ output pll_locked,
+ output pll_pcie_clk,
+ output pll_cascade_clk,
+ output atx_to_fpll_cascade_clk,
+
+ input mcgb_rst,
+ output [5:0] tx_bonding_clocks,
+ output mcgb_serial_clk,
+ output [1:0] pcie_sw_done,
+
+ // NOTE: reconfig for PLL
+ input reconfig_clk0,
+ input reconfig_reset0,
+ input reconfig_write0,
+ input reconfig_read0,
+ input [9:0] reconfig_address0, // OPEN [9:0] is bus size defined somewhere
+ input [SIZE_AVMM_WRDATA_BUS-1:0] reconfig_writedata0,
+ output [SIZE_AVMM_RDDATA_BUS-1:0] reconfig_readdata0,
+ output avmm_busy0,
+ output reconfig_waitrequest0,
+ output pll_cal_busy,
+ output hip_cal_done,
+
+ // NOTE: reconfig for CGB
+ input reconfig_clk1,
+ input reconfig_reset1,
+ input reconfig_write1,
+ input reconfig_read1,
+ input [9:0] reconfig_address1,
+ input [SIZE_AVMM_WRDATA_BUS-1:0] reconfig_writedata1,
+ output [SIZE_AVMM_RDDATA_BUS-1:0] reconfig_readdata1,
+ output avmm_busy1,
+ output reconfig_waitrequest1,
+ output mcgb_cal_busy,
+ output mcgb_hip_cal_done,
+
+ // NOTE: Debug related not in hw.tcl
+ output clklow,
+ output fref,
+ output overrange,
+ output underrange
+ /// TODO include other any other ports for debugging?
+);
+
+ localparam avmm_interfaces = ((enable_mcgb==1) && (enable_mcgb_debug_ports_parameters==1)) ? 2 : 1;
+ localparam RCFG_ADDR_BITS = 10;
+
+ localparam MAX_CONVERSION_SIZE_ALT_XCVR_ATX_A10 = 128;
+ localparam MAX_STRING_CHARS_ALT_XCVR_ATX_A10 = 64;
+
+ localparam lcl_enable_analog_resets =
+ `ifdef ALTERA_RESERVED_QIS
+ `ifdef ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS
+ 1; // MACRO override for quartus synthesis. Connect resets
+ `else
+ enable_analog_resets; // parameter option for synthesis
+ `endif // ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS
+ `else
+ 1; // not synthesis. Connect resets
+ `endif // (NOT ALTERA_RESERVED_QIS)
+
+
+ function automatic [MAX_CONVERSION_SIZE_ALT_XCVR_ATX_A10-1:0] str_2_bin_altera_xcvr_atx_pll_a10;
+ input [MAX_STRING_CHARS_ALT_XCVR_ATX_A10*8-1:0] instring;
+
+ integer this_char;
+ integer i;
+ begin
+ // Initialize accumulator
+ str_2_bin_altera_xcvr_atx_pll_a10 = {MAX_CONVERSION_SIZE_ALT_XCVR_ATX_A10{1'b0}};
+ for(i=MAX_STRING_CHARS_ALT_XCVR_ATX_A10-1;i>=0;i=i-1) begin
+ this_char = instring[i*8+:8];
+ // Add value of this digit
+ if(this_char >= 48 && this_char <= 57)
+ str_2_bin_altera_xcvr_atx_pll_a10 = (str_2_bin_altera_xcvr_atx_pll_a10 * 10) + (this_char - 48);
+ end
+ end
+ endfunction
+
+ // String to binary conversions
+ localparam [127:0] temp_atx_pll_dsm_fractional_division = str_2_bin_altera_xcvr_atx_pll_a10(atx_pll_dsm_fractional_division);
+ localparam [31:0] atx_pll_dsm_fractional_division_bin = temp_atx_pll_dsm_fractional_division[31:0];
+
+ localparam lcl_adme_assgn_map = {" assignments {device_revision ",atx_pll_silicon_rev,"}"};
+
+ // upper 24 bits are not used, but should not be left at X
+ //assign reconfig_readdata0[SIZE_AVMM_RDDATA_BUS-1:8] = 0;
+ assign reconfig_readdata1[SIZE_AVMM_RDDATA_BUS-1:8] = 0;
+
+ //-----------------------------------
+ // reconfigAVMM to pllAtoms internal wires
+ // interface #0 to PLL, interface #1 to CGB
+ wire [avmm_interfaces-1 :0] pll_avmm_clk;
+ wire [avmm_interfaces-1 :0] pll_avmm_rstn;
+ wire [avmm_interfaces*8-1 :0] pll_avmm_writedata;
+ wire [avmm_interfaces*9-1 :0] pll_avmm_address;
+ wire [avmm_interfaces-1 :0] pll_avmm_write;
+ wire [avmm_interfaces-1 :0] pll_avmm_read;
+
+ wire [avmm_interfaces*8-1 :0] pll_avmmreaddata_lc; // NOTE only [7:0] is used
+ wire [avmm_interfaces*8-1 :0] pll_avmmreaddata_refclk; // NOTE only [7:0] is used
+ wire [avmm_interfaces*8-1 :0] pll_avmmreaddata_mcgb; // NOTE only [15:8] is used
+ wire [avmm_interfaces-1 :0] pll_blockselect_lc; // NOTE only [0:0] is used
+ wire [avmm_interfaces-1 :0] pll_blockselect_refclk; // NOTE only [0:0] is used
+ wire [avmm_interfaces-1 :0] pll_blockselect_mcgb; // NOTE only [1:1] is used
+
+ //-----------------------------------
+
+ //-----------------------------------
+ // reconfigAVMM to top wrapper wires
+ // interface #0 to PLL, interface #1 to CGB
+ wire [avmm_interfaces-1 :0] reconfig_clk;
+ wire [avmm_interfaces-1 :0] reconfig_reset;
+ wire [avmm_interfaces*8-1 :0] reconfig_writedata;
+ wire [avmm_interfaces*9-1 :0] reconfig_address;
+ wire [avmm_interfaces-1 :0] reconfig_write;
+ wire [avmm_interfaces-1 :0] reconfig_read;
+ wire [avmm_interfaces*8-1 :0] reconfig_readdata;
+ wire [avmm_interfaces-1 :0] reconfig_waitrequest;
+ wire [avmm_interfaces-1 :0] avmm_busy;
+ wire [avmm_interfaces-1 :0] pld_cal_done;
+ wire [avmm_interfaces-1 :0] hip_cal_done_w;
+
+ // AVMM reconfiguration signals for the hardware
+ wire [avmm_interfaces-1:0] avmm_write;
+ wire [avmm_interfaces-1:0] avmm_read;
+ wire [avmm_interfaces-1:0] avmm_waitrequest;
+ wire [avmm_interfaces*8-1:0] avmm_readdata;
+
+ // AVMM reconfiguration signals for embedded debug
+ wire [avmm_interfaces*8-1:0] debug_writedata;
+ wire [avmm_interfaces-1:0] debug_clk;
+ wire [avmm_interfaces-1:0] debug_reset;
+ wire [avmm_interfaces*10-1:0] debug_address;
+ wire [avmm_interfaces-1:0] debug_write;
+ wire [avmm_interfaces-1:0] debug_read;
+ wire [avmm_interfaces-1:0] debug_busy;
+ wire [avmm_interfaces-1:0] debug_waitrequest;
+ wire [avmm_interfaces*8-1:0] debug_readdata;
+
+ // Wires for control signals from the embedded debug
+ wire pll_powerdown_int;
+
+ // Wires for disconnecting pll_powerdown and mcgb_rst
+ // When the parameter "lcl_enable_analog_resets" is set to 0, these wires will be driven to 0.
+ // When the parameter "lcl_enable_analog_resets" is set to 1, these wires will be connected
+ // to the pll_powerdown and mcgb_rst inputs.
+ wire pll_powerdown_input;
+ wire mcgb_rst_input;
+
+ // Analog reset masking. We always connect analog resets for simulation.
+ // For synthesis it is parameter controlled or MACRO overridden
+ generate
+ if(lcl_enable_analog_resets == 1) begin
+ assign pll_powerdown_input = pll_powerdown;
+ assign mcgb_rst_input = mcgb_rst;
+ end else begin
+ assign pll_powerdown_input = 1'b0;
+ assign mcgb_rst_input = 1'b0;
+ end
+ endgenerate
+
+ // avmm signals shared accross all interfaces
+ assign reconfig_clk[0] = debug_clk;
+ assign reconfig_reset[0] = debug_reset;
+ assign reconfig_writedata[7:0] = debug_writedata[7:0];
+ assign reconfig_address[8:0] = debug_address[8:0];
+ assign reconfig_write[0] = debug_write;
+ assign reconfig_read[0] = debug_read;
+ assign debug_readdata[7:0] = reconfig_readdata[7:0];
+ assign debug_waitrequest = reconfig_waitrequest[0];
+
+ assign avmm_busy0 = avmm_busy[0];
+ assign hip_cal_done = hip_cal_done_w[0];
+ //---
+ assign mcgb_cal_busy = 1'b0;
+ assign pll_cal_busy = ~pld_cal_done[0];
+
+ generate
+ if (avmm_interfaces==2) begin
+ assign reconfig_clk[1] = reconfig_clk1;
+ assign reconfig_reset[1] = reconfig_reset1;
+ assign reconfig_writedata[15:8] = reconfig_writedata1[7:0];
+ assign reconfig_address[17:9] = reconfig_address1[18:10];
+ assign reconfig_write[1] = reconfig_write1;
+ assign reconfig_read[1] = reconfig_read1;
+ assign reconfig_readdata1[7:0]=reconfig_readdata[15:8];
+ assign reconfig_waitrequest1 = reconfig_waitrequest[1];
+ assign avmm_busy1 = avmm_busy[1];
+ //assign mcgb_cal_busy = ~pld_cal_done[1];
+ assign mcgb_hip_cal_done = hip_cal_done_w[1];
+ end else begin
+ assign reconfig_readdata1 = 8'b0;
+ assign reconfig_waitrequest1 = 1'b0;
+ assign avmm_busy1 = 1'b0;
+ assign mcgb_hip_cal_done = 1'b0;
+ end
+ endgenerate
+ //-----------------------------------
+
+ //***************************************************************************
+ //************* Embedded JTAG, AVMM and Embedded Streamer Expansion *********
+ alt_xcvr_atx_pll_rcfg_opt_logic_syj5sga #(
+ .dbg_user_identifier (dbg_user_identifier ),
+ .dbg_embedded_debug_enable (dbg_embedded_debug_enable ),
+ .dbg_capability_reg_enable (dbg_capability_reg_enable ),
+ .dbg_stat_soft_logic_enable (dbg_stat_soft_logic_enable ),
+ .dbg_ctrl_soft_logic_enable (dbg_ctrl_soft_logic_enable ),
+ .en_master_cgb (enable_mcgb ),
+ .INTERFACES (1 ),
+ .ADDR_BITS (RCFG_ADDR_BITS ),
+ .ADME_SLAVE_MAP ("altera_xcvr_atx_pll_a10" ),
+ .ADME_ASSGN_MAP (lcl_adme_assgn_map ),
+ .RECONFIG_SHARED (enable_pll_reconfig && rcfg_shared ),
+ .JTAG_ENABLED (enable_pll_reconfig && rcfg_jtag_enable ),
+ .RCFG_EMB_STRM_ENABLED (enable_pll_reconfig && rcfg_emb_strm_enable),
+ .RCFG_PROFILE_CNT (rcfg_profile_cnt )
+ ) alt_xcvr_atx_pll_optional_rcfg_logic (
+ // User reconfig interface ports
+ .reconfig_clk (reconfig_clk0 ),
+ .reconfig_reset (reconfig_reset0 ),
+ .reconfig_write (reconfig_write0 ),
+ .reconfig_read (reconfig_read0 ),
+ .reconfig_address (reconfig_address0 ),
+ .reconfig_writedata (reconfig_writedata0 ),
+ .reconfig_readdata (reconfig_readdata0 ),
+ .reconfig_waitrequest (reconfig_waitrequest0),
+
+ // AVMM ports to transceiver
+ .avmm_clk (debug_clk ),
+ .avmm_reset (debug_reset ),
+ .avmm_write (debug_write ),
+ .avmm_read (debug_read ),
+ .avmm_address (debug_address ),
+ .avmm_writedata (debug_writedata ),
+ .avmm_readdata (debug_readdata ),
+ .avmm_waitrequest (debug_waitrequest ),
+
+ // input signals from the core
+ .in_pll_powerdown (pll_powerdown_input ),
+ .in_pll_locked (pll_locked ),
+ .in_pll_cal_busy (pll_cal_busy ),
+ .in_avmm_busy (avmm_busy0 ),
+
+ // output signals to the ip
+ .out_pll_powerdown (pll_powerdown_int )
+ );
+
+ //***************** End Embedded JTAG and AVMM Expansion ********************
+ //***************************************************************************
+
+
+ //-----------------------------------
+ // PLL STARTS
+ a10_xcvr_atx_pll
+ #(
+ .enable_debug_info(enable_debug_info),
+
+ .atx_pll_regulator_bypass (atx_pll_regulator_bypass),
+ .atx_pll_pfd_delay_compensation (atx_pll_pfd_delay_compensation),
+ .atx_pll_xcpvco_xchgpmplf_cp_current_boost (atx_pll_xcpvco_xchgpmplf_cp_current_boost),
+ .atx_pll_pfd_pulse_width (atx_pll_pfd_pulse_width),
+
+ .atx_pll_l_counter_enable(atx_pll_l_counter_enable),
+ .atx_pll_fb_select(atx_pll_fb_select),
+ .atx_pll_bonding_mode(atx_pll_bonding_mode),
+ .atx_pll_prot_mode(atx_pll_prot_mode),
+ .atx_pll_silicon_rev(atx_pll_silicon_rev),
+ .atx_pll_bw_sel(atx_pll_bw_sel),
+ .atx_pll_dsm_mode(atx_pll_dsm_mode),
+ .atx_pll_reference_clock_frequency(atx_pll_reference_clock_frequency),
+ .atx_pll_output_clock_frequency(atx_pll_output_clock_frequency),
+ .atx_pll_m_counter(atx_pll_m_counter),
+ .atx_pll_ref_clk_div(atx_pll_ref_clk_div),
+ .atx_pll_l_counter(atx_pll_l_counter),
+ .atx_pll_dsm_fractional_division(atx_pll_dsm_fractional_division_bin), // String to bin conversion
+ .atx_pll_tank_band(atx_pll_tank_band),
+ .atx_pll_tank_sel(atx_pll_tank_sel),
+ .atx_pll_hclk_divide(atx_pll_hclk_divide),
+ .atx_pll_cgb_div(atx_pll_cgb_div),
+ .atx_pll_pma_width(atx_pll_pma_width),
+
+ .atx_pll_primary_use (atx_pll_primary_use ),
+ .atx_pll_lc_mode (atx_pll_lc_mode ),
+ .atx_pll_lc_atb (atx_pll_lc_atb ),
+ .atx_pll_cp_compensation_enable (atx_pll_cp_compensation_enable ),
+ .atx_pll_cp_current_setting (atx_pll_cp_current_setting ),
+ .atx_pll_cp_testmode (atx_pll_cp_testmode ),
+ .atx_pll_cp_lf_3rd_pole_freq (atx_pll_cp_lf_3rd_pole_freq ),
+ .atx_pll_cp_lf_order (atx_pll_cp_lf_order ),
+ .atx_pll_lf_resistance (atx_pll_lf_resistance ),
+ .atx_pll_lf_ripplecap (atx_pll_lf_ripplecap ),
+ .atx_pll_d2a_voltage (atx_pll_d2a_voltage ),
+ .atx_pll_dsm_out_sel (atx_pll_dsm_out_sel ),
+ .atx_pll_dsm_ecn_bypass (atx_pll_dsm_ecn_bypass ),
+ .atx_pll_dsm_ecn_test_en (atx_pll_dsm_ecn_test_en ),
+ .atx_pll_dsm_fractional_value_ready (atx_pll_dsm_fractional_value_ready),
+ .atx_pll_vco_bypass_enable (atx_pll_vco_bypass_enable ),
+ .atx_pll_cascadeclk_test (atx_pll_cascadeclk_test ),
+ .atx_pll_tank_voltage_coarse (atx_pll_tank_voltage_coarse ),
+ .atx_pll_tank_voltage_fine (atx_pll_tank_voltage_fine ),
+ .atx_pll_output_regulator_supply (atx_pll_output_regulator_supply ),
+ .atx_pll_overrange_voltage (atx_pll_overrange_voltage ),
+ .atx_pll_underrange_voltage (atx_pll_underrange_voltage ),
+ .atx_pll_is_cascaded_pll (atx_pll_is_cascaded_pll ),
+ .atx_pll_is_otn (atx_pll_is_otn ),
+ .atx_pll_is_sdi (atx_pll_is_sdi ),
+ .atx_pll_side (atx_pll_side ),
+
+ .atx_pll_lf_cbig_size (atx_pll_lf_cbig_size ),
+ .atx_pll_enable_hclk (atx_pll_enable_hclk ),
+ .atx_pll_calibration_mode (atx_pll_calibration_mode ),
+ .atx_pll_datarate (atx_pll_datarate ),
+ .atx_pll_device_variant (atx_pll_device_variant ),
+ .atx_pll_initial_settings (atx_pll_initial_settings ),
+ .atx_pll_l_counter_scratch (atx_pll_l_counter_scratch ),
+ .atx_pll_n_counter_scratch (atx_pll_n_counter_scratch ),
+ .atx_pll_powerdown_mode (atx_pll_powerdown_mode ),
+ .atx_pll_sup_mode (atx_pll_sup_mode ),
+ .atx_pll_vco_freq (atx_pll_vco_freq ),
+ .atx_pll_fpll_refclk_selection (atx_pll_fpll_refclk_selection ),
+ .lc_to_fpll_l_counter (atx_pll_lc_to_fpll_l_counter),
+ .lc_to_fpll_l_counter_scratch (atx_pll_lc_to_fpll_l_counter_scratch),
+
+ .hssi_pma_lc_refclk_select_mux_powerdown_mode(hssi_pma_lc_refclk_select_mux_powerdown_mode),
+ .hssi_pma_lc_refclk_select_mux_refclk_select(hssi_pma_lc_refclk_select_mux_refclk_select),
+ .hssi_pma_lc_refclk_select_mux_silicon_rev(hssi_pma_lc_refclk_select_mux_silicon_rev),
+
+ .hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping (hssi_pma_lc_refclk_select_mux_inclk0_logical_to_physical_mapping),
+ .hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping (hssi_pma_lc_refclk_select_mux_inclk1_logical_to_physical_mapping),
+ .hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping (hssi_pma_lc_refclk_select_mux_inclk2_logical_to_physical_mapping),
+ .hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping (hssi_pma_lc_refclk_select_mux_inclk3_logical_to_physical_mapping),
+ .hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping (hssi_pma_lc_refclk_select_mux_inclk4_logical_to_physical_mapping),
+
+ .hssi_refclk_divider_silicon_rev(hssi_refclk_divider_silicon_rev),
+
+ .enable_mcgb(enable_mcgb),
+ .enable_mcgb_debug_ports_parameters(enable_mcgb_debug_ports_parameters),
+ .hssi_pma_cgb_master_silicon_rev (hssi_pma_cgb_master_silicon_rev),
+ .hssi_pma_cgb_master_prot_mode (hssi_pma_cgb_master_prot_mode),
+ .hssi_pma_cgb_master_cgb_enable_iqtxrxclk (hssi_pma_cgb_master_cgb_enable_iqtxrxclk),
+ .hssi_pma_cgb_master_x1_div_m_sel (hssi_pma_cgb_master_x1_div_m_sel),
+ .hssi_pma_cgb_master_ser_mode (hssi_pma_cgb_master_ser_mode),
+ .hssi_pma_cgb_master_datarate (hssi_pma_cgb_master_datarate),
+
+ .hssi_pma_cgb_master_cgb_power_down (hssi_pma_cgb_master_cgb_power_down ),
+ .hssi_pma_cgb_master_observe_cgb_clocks (hssi_pma_cgb_master_observe_cgb_clocks ),
+ .hssi_pma_cgb_master_op_mode (hssi_pma_cgb_master_op_mode ),
+ .hssi_pma_cgb_master_tx_ucontrol_reset_pcie (hssi_pma_cgb_master_tx_ucontrol_reset_pcie ),
+ .hssi_pma_cgb_master_vccdreg_output (hssi_pma_cgb_master_vccdreg_output ),
+ .hssi_pma_cgb_master_input_select (hssi_pma_cgb_master_input_select ),
+ .hssi_pma_cgb_master_input_select_gen3 (hssi_pma_cgb_master_input_select_gen3 ),
+
+ .hssi_pma_cgb_master_bonding_reset_enable (hssi_pma_cgb_master_bonding_reset_enable ),
+ .hssi_pma_cgb_master_optimal (hssi_pma_cgb_master_optimal ),
+ .hssi_pma_cgb_master_pcie_gen3_bitwidth (hssi_pma_cgb_master_pcie_gen3_bitwidth ),
+ .hssi_pma_cgb_master_powerdown_mode (hssi_pma_cgb_master_powerdown_mode ),
+ .hssi_pma_cgb_master_sup_mode (hssi_pma_cgb_master_sup_mode ),
+ .hssi_pma_cgb_master_initial_settings (hssi_pma_cgb_master_initial_settings )
+ )
+ a10_xcvr_atx_pll_inst (
+ .pll_powerdown(~pll_powerdown_int),
+ .pll_refclk0(pll_refclk0),
+ .pll_refclk1(pll_refclk1),
+ .pll_refclk2(pll_refclk2),
+ .pll_refclk3(pll_refclk3),
+ .pll_refclk4(pll_refclk4),
+
+ .mcgb_aux_clk0(mcgb_aux_clk0),
+ .mcgb_aux_clk1(mcgb_aux_clk1),
+ .mcgb_aux_clk2(mcgb_aux_clk2),
+
+ .mcgb_pcie_sw(pcie_sw),
+
+ .pll_serial_clk_8g(tx_serial_clk),
+ .pll_serial_clk_16g(tx_serial_clk_gt),
+ .pll_locked(pll_locked),
+ .pll_pcie_clk(pll_pcie_clk),
+ .pll_cascade_clk(pll_cascade_clk),
+ .lc_to_fpll_refclk(atx_to_fpll_cascade_clk),
+
+ .mcgb_rst(~mcgb_rst_input),
+ .tx_bonding_clocks(tx_bonding_clocks),
+ .mcgb_serial_clk(mcgb_serial_clk),
+ .mcgb_pcie_sw_done(pcie_sw_done),
+
+ .pll_avmm_clk(pll_avmm_clk),
+ .pll_avmm_rstn(pll_avmm_rstn),
+ .pll_avmm_writedata(pll_avmm_writedata),
+ .pll_avmm_address(pll_avmm_address),
+ .pll_avmm_write(pll_avmm_write),
+ .pll_avmm_read(pll_avmm_read),
+ .pll_avmmreaddata_lc(pll_avmmreaddata_lc),
+ .pll_avmmreaddata_refclk(pll_avmmreaddata_refclk),
+ .pll_blockselect_lc(pll_blockselect_lc),
+ .pll_blockselect_refclk(pll_blockselect_refclk),
+ .pll_avmmreaddata_mcgb(pll_avmmreaddata_mcgb),
+ .pll_blockselect_mcgb(pll_blockselect_mcgb),
+
+ .clklow(clklow),
+ .fref(fref),
+ .overrange(overrange),
+ .underrange(underrange)
+ );
+ // PLL ENDS
+ //-----------------------------------
+
+ //-----------------------------------
+ // Pulling in the rule for calibration attributes from PCS channel RBC
+ localparam arbiter_ctrl = (calibration_en == "enable") ? "uc" : "pld";
+ localparam cal_done = (calibration_en == "enable") ? "cal_done_deassert" : "cal_done_assert";
+ localparam hip_cal_en_fnl = (calibration_en == "enable") ? hip_cal_en : "disable";
+ localparam avmm_busy_en = rcfg_separate_avmm_busy ? "enable" : "disable";
+
+ // AVMM STARTS
+ twentynm_xcvr_avmm
+ #(
+ .avmm_interfaces(avmm_interfaces),
+ .calibration_en(calibration_en),
+ .avmm_busy_en (avmm_busy_en),
+ .arbiter_ctrl(arbiter_ctrl),
+ .cal_done(cal_done),
+ .rcfg_enable(enable_pll_reconfig),
+ .enable_avmm(1),
+ .hip_cal_en(hip_cal_en_fnl)
+ )
+ a10_xcvr_avmm_inst (
+ .avmm_clk( {reconfig_clk } ),
+ .avmm_reset( {reconfig_reset } ),
+ .avmm_writedata( {reconfig_writedata } ),
+ .avmm_address( {reconfig_address } ),
+ .avmm_write( {reconfig_write } ),
+ .avmm_read( {reconfig_read } ),
+ .avmm_readdata( {reconfig_readdata } ),
+ .avmm_waitrequest({reconfig_waitrequest } ),
+ .avmm_busy( {avmm_busy } ),
+ .pld_cal_done( {pld_cal_done } ),
+ .hip_cal_done( {hip_cal_done_w } ),
+
+ .chnl_pll_avmm_clk(pll_avmm_clk),
+ .chnl_pll_avmm_rstn(pll_avmm_rstn),
+ .chnl_pll_avmm_writedata(pll_avmm_writedata),
+ .chnl_pll_avmm_address(pll_avmm_address),
+ .chnl_pll_avmm_write(pll_avmm_write),
+ .chnl_pll_avmm_read(pll_avmm_read),
+
+ .pll_avmmreaddata_lc_pll(pll_avmmreaddata_lc),
+ .pll_avmmreaddata_lc_refclk_select(pll_avmmreaddata_refclk),
+ .pll_avmmreaddata_cgb_master(pll_avmmreaddata_mcgb),
+
+ .pll_blockselect_lc_pll(pll_blockselect_lc),
+ .pll_blockselect_lc_refclk_select(pll_blockselect_refclk),
+ .pll_blockselect_cgb_master(pll_blockselect_mcgb),
+
+ //-----------------------------------
+ // IRRELEVANT PORTS
+ .pma_avmmreaddata_tx_ser ( {avmm_interfaces{8'b0}} ),
+ .pma_avmmreaddata_tx_cgb ( {avmm_interfaces{8'b0}} ),
+ .pma_avmmreaddata_tx_buf ( {avmm_interfaces{8'b0}} ),
+ .pma_avmmreaddata_rx_deser ( {avmm_interfaces{8'b0}} ),
+ .pma_avmmreaddata_rx_buf ( {avmm_interfaces{8'b0}} ),
+ .pma_avmmreaddata_rx_sd ( {avmm_interfaces{8'b0}} ),
+ .pma_avmmreaddata_rx_odi ( {avmm_interfaces{8'b0}} ),
+ .pma_avmmreaddata_rx_dfe ( {avmm_interfaces{8'b0}} ),
+ .pma_avmmreaddata_cdr_pll ( {avmm_interfaces{8'b0}} ),
+ .pma_avmmreaddata_cdr_refclk_select ( {avmm_interfaces{8'b0}} ),
+ .pma_avmmreaddata_pma_adapt ( {avmm_interfaces{8'b0}} ),
+ .pma_blockselect_tx_ser ( {avmm_interfaces{1'b0}} ),
+ .pma_blockselect_tx_cgb ( {avmm_interfaces{1'b0}} ),
+ .pma_blockselect_tx_buf ( {avmm_interfaces{1'b0}} ),
+ .pma_blockselect_rx_deser ( {avmm_interfaces{1'b0}} ),
+ .pma_blockselect_rx_buf ( {avmm_interfaces{1'b0}} ),
+ .pma_blockselect_rx_sd ( {avmm_interfaces{1'b0}} ),
+ .pma_blockselect_rx_odi ( {avmm_interfaces{1'b0}} ),
+ .pma_blockselect_rx_dfe ( {avmm_interfaces{1'b0}} ),
+ .pma_blockselect_cdr_pll ( {avmm_interfaces{1'b0}} ),
+ .pma_blockselect_cdr_refclk_select ( {avmm_interfaces{1'b0}} ),
+ .pma_blockselect_pma_adapt ( {avmm_interfaces{1'b0}} ),
+ .pcs_avmmreaddata_8g_rx_pcs ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_pipe_gen1_2 ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_8g_tx_pcs ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_10g_rx_pcs ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_10g_tx_pcs ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_gen3_rx_pcs ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_pipe_gen3 ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_gen3_tx_pcs ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_krfec_rx_pcs ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_krfec_tx_pcs ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_fifo_rx_pcs ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_fifo_tx_pcs ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_rx_pcs_pld_if ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_com_pcs_pld_if ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_tx_pcs_pld_if ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_rx_pcs_pma_if ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_com_pcs_pma_if ( {avmm_interfaces{8'b0}} ),
+ .pcs_avmmreaddata_tx_pcs_pma_if ( {avmm_interfaces{8'b0}} ),
+ .pcs_blockselect_8g_rx_pcs ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_pipe_gen1_2 ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_8g_tx_pcs ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_10g_rx_pcs ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_10g_tx_pcs ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_gen3_rx_pcs ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_pipe_gen3 ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_gen3_tx_pcs ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_krfec_rx_pcs ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_krfec_tx_pcs ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_fifo_rx_pcs ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_fifo_tx_pcs ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_rx_pcs_pld_if ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_com_pcs_pld_if ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_tx_pcs_pld_if ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_rx_pcs_pma_if ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_com_pcs_pma_if ( {avmm_interfaces{1'b0}} ),
+ .pcs_blockselect_tx_pcs_pma_if ( {avmm_interfaces{1'b0}} ),
+ .pll_avmmreaddata_cmu_fpll ( {avmm_interfaces{8'b0}} ),
+ .pll_avmmreaddata_cmu_fpll_refclk_select ( {avmm_interfaces{8'b0}} ),
+ .pll_blockselect_cmu_fpll ( {avmm_interfaces{1'b0}} ),
+ .pll_blockselect_cmu_fpll_refclk_select ( {avmm_interfaces{1'b0}} )
+ );
+ // AVMM ENDS
+ //-----------------------------------
+endmodule
+
+
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/docs/arria10_hps_altera_xcvr_atx_pll_a10_221_syj5sga_parameters.csv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/docs/arria10_hps_altera_xcvr_atx_pll_a10_221_syj5sga_parameters.csv
new file mode 100644
index 0000000000000000000000000000000000000000..2b6ac614c6e3283ec4fc187a9748c8bd997cf9d6
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/docs/arria10_hps_altera_xcvr_atx_pll_a10_221_syj5sga_parameters.csv
@@ -0,0 +1,72 @@
+NAME,DISPLAY_NAME,ALLOWED_RANGES,DEFAULT_VALUE,DESCRIPTION
+"rcfg_debug","rcfg_debug","0 1","0",""
+"enable_pll_reconfig","Enable dynamic reconfiguration","{0 1}","0","Enables the dynamic reconfiguration interface."
+"rcfg_jtag_enable","Enable Altera Debug Master Endpoint","{0 1}","0","When enabled, the PLL IP includes an embedded Altera Debug Master Endpoint that connects internally Avalon-MM slave interface. The ADME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the "Share reconfiguration interface" option for configurations using more than 1 channel and may also require that a jtag_debug link be included in the system."
+"rcfg_separate_avmm_busy","Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE","{0 1}","0","When enabled, the reconfig_waitrequest will not indicate the status of AVMM arbitration with PreSICE. The AVMM arbitration status will be reflected in a soft status register bit. This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled. For more information, please refer to the User Guide."
+"rcfg_enable_avmm_busy_port","Enable avmm_busy port","{0 1}","0","Enable the port for avmm_busy"
+"set_capability_reg_enable","Enable capability registers","{0 1}","0","Enables capability registers, which provide high level information about the transceiver PLL's configuration"
+"set_user_identifier","Set user-defined IP identifier","0:255","0","Sets a user-defined numeric identifier that can be read from the user_identifer offset when the capability registers are enabled"
+"set_csr_soft_logic_enable","Enable control and status registers","{0 1}","0","Enables soft registers for reading status signals and writing control signals on the phy interface through the embedded debug. Available signals include pll_cal_busy, pll_locked and pll_powerdown. For more details, please refer to the User Guide."
+"rcfg_file_prefix","Configuration file prefix","","altera_xcvr_atx_pll_a10","Specifies the file prefix to use for generated configuration files when enabled. Each variant of the IP should use a unique prefix for configuration files."
+"rcfg_sv_file_enable","Generate SystemVerilog package file","{0 1}","0","When enabled, The IP will generate a SystemVerilog package file named "(Configuration file prefix)_reconfig_parameters.sv" containing parameters defined with the attribute values needed for reconfiguration."
+"rcfg_h_file_enable","Generate C header file","{0 1}","0","When enabled, The IP will generate a C header file named "(Configuration file prefix)_reconfig_parameters.h" containing macros defined with the attribute values needed for reconfiguration."
+"rcfg_txt_file_enable","Generate text file","{0 1}","0","When enabled, The IP will generate a text file named "(Configuration file prefix)_reconfig_parameters.txt" containing the attribute values needed for reconfiguration."
+"rcfg_mif_file_enable","Generate MIF (Memory Initialize File)","{0 1}","0","When enabled The IP will generate an Altera MIF (Memory Initialization File) named "(Configuration file prefix)_reconfig_parameters.mif". The MIF file contains the attribute values needed for reconfiguration in a data format."
+"rcfg_multi_enable","Enable multiple reconfiguration profiles","{0 1}","0","When enabled, you can use the GUI to store multiple configurations. The IP will generate reconfiguration files for all of the stored profiles. The IP will also check your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them."
+"set_rcfg_emb_strm_enable","Enable embedded reconfiguration streamer","{0 1}","0","Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles."
+"rcfg_reduced_files_enable","Generate reduced reconfiguration files","{0 1}","0","When enabled, The Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles."
+"rcfg_profile_cnt","Number of reconfiguration profiles","1 2 3 4 5 6 7 8","2","Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled."
+"rcfg_profile_select","Store current configuration to profile:","0 1","1","Selects which reconfiguration profile to store when clicking the "Store profile" button."
+"rcfg_profile_data0","rcfg_profile_data0","","",""
+"rcfg_profile_data1","rcfg_profile_data1","","",""
+"rcfg_profile_data2","rcfg_profile_data2","","",""
+"rcfg_profile_data3","rcfg_profile_data3","","",""
+"rcfg_profile_data4","rcfg_profile_data4","","",""
+"rcfg_profile_data5","rcfg_profile_data5","","",""
+"rcfg_profile_data6","rcfg_profile_data6","","",""
+"rcfg_profile_data7","rcfg_profile_data7","","",""
+"enable_manual_configuration","enable_manual_configuration","0 1","1",""
+"generate_docs","Generate parameter documentation file","{0 1}","0","When enabled, generation will produce a .CSV file with descriptions of the IP parameters."
+"generate_add_hdl_instance_example","Generate '_hw.tcl' 'add_hdl_instance' example file","{0 1}","0","When enabled, generation will produce a file containing an example of how to use the '_hw.tcl' 'add_hdl_instance' API. The example will be correct for the current configuration of the IP."
+"device_family","device_family","","Arria VI",""
+"device","device","","Unknown",""
+"base_device","base_device","","nightfury5es",""
+"test_mode","Enable Test Mode","{0 1}","0",""
+"enable_pld_atx_cal_busy_port","enable_pld_atx_cal_busy_port","0 1","1",""
+"enable_debug_ports_parameters","Enable debug ports & parameters","{0 1}","0",""
+"support_mode","Support mode","user_mode engineering_mode","user_mode","Selects the support mode (user or engineering). Engineering mode options are not officially supported by Intel or Quartus Prime."
+"message_level","Message level for rule violations","error warning","error","Specifies the messaging level to use for parameter rule violations. Selecting "error" will cause all rule violations to prevent IP generation. Selecting "warning" will display all rule violations as warnings and will allow IP generation in spite of violations."
+"prot_mode","Protocol mode","Basic {PCIe Gen 1} {PCIe Gen 2} {PCIe Gen 3} SDI_cascade OTN_cascade {UPI TX} {SAS TX} OTU2_cascade OTU2E_cascade","Basic","The parameter is used to govern the rules for internal settings of the VCO. This parameter is not a "preset". You must still correctly set all other parameters for your protocol and application. SDI_cascade, OTN_cascade, OTU2_cascade, and OTU2E_cascade are supported cascade mode configurations and enables "ATX to FPLL cascade output port", "manual configuration of counters" and "fractional mode". Protocol mode SDI_cascade enables SDI cascade rule checks and OTN/OTU2/OTU2E_cascade enables OTN cascade rule checks."
+"bw_sel","Bandwidth","low medium high","medium","Specifies the VCO bandwidth."
+"refclk_cnt","Number of PLL reference clocks","1 2 3 4 5","1","Specifies the number of input reference clocks for the ATX PLL."
+"refclk_index","Selected reference clock source","0","0","Specifies the initially selected reference clock input to the ATX PLL."
+"silicon_rev","Silicon revision ES","","false",""
+"primary_pll_buffer","Primary PLL clock output buffer","{GX clock output buffer} {GT clock output buffer}","GX clock output buffer","Specifies initially which PLL output is active. If GX is selected "Enable PLL GX clock output port" should be enabled as well, if GT is selected "Enable PLL GT clock output port" should be enabled as well."
+"enable_8G_path","Enable PLL GX clock output port","{0 1}","1","GX output port feeds x1 clock lines. Must be selected for PLL output frequency smaller than 8.7GHz. If GX is selected in "Primary PLL clock output buffer", the port should be enabled as well."
+"enable_16G_path","Enable PLL GT clock output port","{0 1}","0","GT output port feeds dedicated high speed clock lines. Must be selected for PLL output frequency greater than 8.7GHz. If GT is selected in "Primary PLL clock output buffer", the port should be enabled as well."
+"enable_pcie_clk","Enable PCIe clock output port","{0 1}","0","This is the 500 MHz fixed PCIe clock output port and is intended for PIPE mode. The port should be connected to "pipe hclk input port"."
+"enable_cascade_out","Enable cascade clock output port","{0 1}","0",""
+"enable_hip_cal_done_port","Enable calibration status ports for HIP","{0 1}","0","Enables calibration status port from PLL and Master CGB(if enabled) for HIP"
+"set_hip_cal_en","Enable PCIe hard IP calibration","{0 1}","0","INTERNAL USE ONLY. Enabling this parameter prioritizes the calibration for PCIe hard IP channels."
+"set_output_clock_frequency","PLL output frequency","","625.0","Specifies the target output frequency for the PLL."
+"set_auto_reference_clock_frequency","PLL integer reference clock frequency","61.728395 62.5 63.291139 64.102564 64.935065 65.789474 66.666667 67.567568 68.493151 69.444444 70.422535 71.428571 72.463768 73.529412 74.626866 75.757576 76.923077 78.125 79.365079 80.645161 81.967213 83.333333 84.745763 86.206897 87.719298 89.285714 90.909091 92.592593 94.339623 96.153846 98.039216 100.0 102.040816 104.166667 106.382979 108.695652 111.111111 113.636364 116.27907 119.047619 121.95122 123.45679 125.0 126.582278 128.205128 129.87013 131.578947 133.333333 135.135135 136.986301 138.888889 140.84507 142.857143 144.927536 147.058824 149.253731 151.515152 153.846154 156.25 158.730159 161.290323 163.934426 166.666667 169.491525 172.413793 175.438596 178.571429 181.818182 185.185185 188.679245 192.307692 196.078431 200.0 204.081633 208.333333 212.765957 217.391304 222.222222 227.272727 232.55814 238.095238 243.902439 246.91358 250.0 253.164557 256.410256 259.74026 263.157895 266.666667 270.27027 273.972603 277.777778 281.690141 285.714286 289.855072 294.117647 298.507463 303.030303 307.692308 312.5 317.460317 322.580645 327.868852 333.333333 338.983051 344.827586 350.877193 357.142857 363.636364 370.37037 377.358491 384.615385 392.156863 400.0 408.163265 416.666667 425.531915 434.782609 444.444444 454.545455 465.116279 476.190476 487.804878 493.82716 500.0 506.329114 512.820513 519.480519 526.315789 533.333333 540.540541 547.945205 555.555556 563.380282 571.428571 579.710145 588.235294 597.014925 606.060606 615.384615 625.0 634.920635 645.16129 655.737705 666.666667 677.966102 689.655172 701.754386 714.285714 727.272727 740.740741 754.716981 769.230769 784.313725 800.0","156.25","Selects the input reference clock frequency for the PLL."
+"set_manual_reference_clock_frequency","PLL fractional reference clock frequency","","200.0",""
+"set_fref_clock_frequency","PLL fractional reference clock frequency","","156.25","Selects the fractional reference clock frequency for the PLL."
+"set_m_counter","Multiply factor (M-Counter)","100 80 64 60 50 48 40 36 32 30 25 24 20 18 16 15 12 10 9 8 6 5 4 3 2 1","24","Specifies the M-counter.See the Transceivers User Manual for detailed description."
+"set_ref_clk_div","Divide factor (N-Counter)","1 2 4 8","1","Specifies the N-counter. See the Transceivers User Manual for detailed description."
+"set_l_counter","Divide factor (L-Counter)","1 2 4 8 16","16","Specifies the L-counter and is intended for non-cascade mode. See the Transceivers User Manual for detailed description."
+"set_l_cascade_counter","Divide factor (L-Cascade Counter)","4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31","15","Specifies the L-Cascade counter and is intended for cascade mode. See the Transceivers User Manual for detailed description."
+"set_l_cascade_predivider","predivide factor (L-Cascade Predivider)","1 2","1","Specifies the L-Cascade predivider value and is intended for cascade mode. 1 when vco frequency is less than or equal to 10G and 2 when vco frequency is greater than 10G. See the Transceivers User Manual for detailed description."
+"set_k_counter","Fractional multiply factor (K)","","2000000000","Specifies the K counter. See the Transceivers User Manual for detailed description."
+"set_altera_xcvr_atx_pll_a10_calibration_en","Enable calibration","{0 1}","1","Enable transceiver calibration algorithms."
+"enable_analog_resets","Enable pll_powerdown and mcgb_rst connections","{0 1}","0","INTERNAL USE ONLY. When selected, the pll_powerdown and mcgb_rst input ports will be connected internally in the IP. Otherwise and by default these ports are made present but have no affect when asserted."
+"enable_ext_lockdetect_ports","Enable clklow and fref ports","{0 1}","0","Enables fref and clklow clock ports for external lock detector."
+"enable_mcgb","Include Master Clock Generation Block","{0 1}","0","When enabled Master CGB will be included as part of the IP. PLL output will feed the Master CGB input."
+"mcgb_div","Clock division factor","1 2 4 8","1","Divides the Master CGB clock input before generating bonding clocks."
+"enable_hfreq_clk","Enable x6/xN non-bonded high-speed clock output port","{0 1}","0","This output port can be used to access x6/xN clock lines for non-bonded designs"
+"enable_mcgb_pcie_clksw","Enable PCIe clock switch interface","{0 1}","0","Enables the control signals for PCIe clock switch circuitry"
+"mcgb_aux_clkin_cnt","Number of auxiliary MCGB clock input ports.","0 1","0","Auxiliary input is intended for PCIe Gen3, hence not available in FPLL"
+"enable_bonding_clks","Enable bonding clock output ports","{0 1}","0","Should be enable for bonded designs"
+"enable_fb_comp_bonding","Enable feedback compensation bonding","{0 1}","0",""
+"pma_width","PMA interface width","8 10 16 20 32 40 64","64","PMA-PCS Interface width. Proper value must be selected for bonding clocks to be generated properly for Native PHY IP."
+"enable_pld_mcgb_cal_busy_port","enable_pld_mcgb_cal_busy_port","0 1","0",""
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/twentynm_xcvr_avmm.sv b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/twentynm_xcvr_avmm.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d0b9de824d305c6a08d2254611f6a4f673374896
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_atx_pll_a10_221/synth/twentynm_xcvr_avmm.sv
@@ -0,0 +1,423 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ps/1ps
+
+
+module twentynm_xcvr_avmm
+ #(
+ //PARAM_LIST_START
+ parameter avmm_interfaces = 1, //Number of AVMM interfaces required - one for each bonded_lane, PLL, and Master CGB
+ parameter rcfg_enable = 0, //Enable/disable reconfig interface in the Native PHY or PLL IP
+ parameter enable_avmm = 1, //Enable/disable AVMM atom instantiation
+ parameter arbiter_ctrl = "pld", //Calibration request at start-up. Valid values: "uc","pld".
+ //"uc" =Initial calibration needed at start-up. Internal DPRIO interface is controlled by uC.
+ //"pld"=Initial calibration is not needed at start-up. Internal DPRIO interface is controlled by PLD.
+ parameter calibration_en = "disable", //Indicates whether calibration by Hard Nios is enabled or not.Should be set to DISABLE in case if Nios is absent or needs to be bypassed. Valid values: enable, disable
+ parameter avmm_busy_en = "disable", //Provides a separate interface for determining control of the AVMM bus, and separates its behavior from the avmm_waitreqeust
+ parameter hip_cal_en = "disable", //Indicates whether HIP is enabled or not. Valid values: disable, enable
+ parameter cal_done = "cal_done_assert" //Indicates whether calibration is done. This is the start-up value for the corresponding CRAM. THe CRAM is eventually accessed and updated by the Hard uC during calibration. Valid values: cal_done_assert, cal_done_deassert
+ //PARAM_LIST_END
+ ) (
+ //PORT_LIST_START
+ // AVMM slave interface signals (user)
+ input wire [avmm_interfaces-1 :0] avmm_clk,
+ input wire [avmm_interfaces-1 :0] avmm_reset,
+ input wire [avmm_interfaces*8-1 :0] avmm_writedata,
+ input wire [avmm_interfaces*9-1 :0] avmm_address,
+ input wire [avmm_interfaces-1 :0] avmm_write,
+ input wire [avmm_interfaces-1 :0] avmm_read,
+ output wire [avmm_interfaces*8-1 :0] avmm_readdata,
+ output wire [avmm_interfaces-1 :0] avmm_waitrequest,
+ //AVMM interface busy with calibration
+ output wire [avmm_interfaces-1 :0] avmm_busy,
+ // Calibration Done
+ output wire [avmm_interfaces-1 :0] hip_cal_done, //To HIP
+ output wire [avmm_interfaces-1 :0] pld_cal_done, //To PLD
+
+ // Channel/PLL AVMM interface signals (from AVMM atom fanned-out to all the Channel/PLL atoms)
+ output wire [avmm_interfaces-1 :0] chnl_pll_avmm_clk,
+ output wire [avmm_interfaces-1 :0] chnl_pll_avmm_rstn,
+ output wire [avmm_interfaces*8-1 :0] chnl_pll_avmm_writedata, //Internal AVMM interface is 8-bit wide
+ output wire [avmm_interfaces*9-1 :0] chnl_pll_avmm_address,
+ output wire [avmm_interfaces-1 :0] chnl_pll_avmm_write,
+ output wire [avmm_interfaces-1 :0] chnl_pll_avmm_read,
+
+ // PMA AVMM signals
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_tx_ser, // TX SER readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_tx_cgb, // TX Slave CGB readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_tx_buf, // TX BUF readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_rx_deser, // RX Deser readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_rx_buf, // RX BUF readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_rx_sd, // RX SD readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_rx_odi, // RX ODI readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_rx_dfe, // RX DFE readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_cdr_pll, // CDR readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_cdr_refclk_select, // CDR refclk mux readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pma_avmmreaddata_pma_adapt, // PMA adaptation readdata (8 for each lane)
+
+ input wire [avmm_interfaces-1 :0] pma_blockselect_tx_ser, // TX SER blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pma_blockselect_tx_cgb, // TX Slave CGB blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pma_blockselect_tx_buf, // TX BUF blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pma_blockselect_rx_deser, // RX Deser blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pma_blockselect_rx_buf, // RX BUF blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pma_blockselect_rx_sd, // RX SD blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pma_blockselect_rx_odi, // RX ODI blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pma_blockselect_rx_dfe, // RX DFE blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pma_blockselect_cdr_pll, // CDR blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pma_blockselect_cdr_refclk_select, // CDR refclk mux blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pma_blockselect_pma_adapt, // PMA adaptation blockselect (1 for each lane)
+
+ // PCS Channel AVMM signals
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_8g_rx_pcs, // 8G RX PCS readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_pipe_gen1_2, // Gen1/2 PIPE readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_8g_tx_pcs, // 8G TX PCS readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_10g_rx_pcs, // 10G RX PCS readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_10g_tx_pcs, // 10G TX PCS readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_gen3_rx_pcs, // GEN3 RX PCS readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_pipe_gen3, // GEN3 PIPE readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_gen3_tx_pcs, // GEN3 TX PCS readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_krfec_rx_pcs, // KRFEC RX PCS readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_krfec_tx_pcs, // KRFEC TX PCS readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_fifo_rx_pcs, // FIFO RX PCS readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_fifo_tx_pcs, // FIFO TX PCS readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_rx_pcs_pld_if, // RX PCS PLD IF readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_com_pcs_pld_if, // COM PCS PLD IF readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_tx_pcs_pld_if, // TX PCS PLD IF readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_rx_pcs_pma_if, // RX PCS PMA IF readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_com_pcs_pma_if, // COm PCS PMA IF readdata (8 for each lane)
+ input wire [avmm_interfaces*8-1 :0] pcs_avmmreaddata_tx_pcs_pma_if, // TX PCS PMA IF readdata (8 for each lane)
+
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_8g_rx_pcs, // 8G RX PCS blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_pipe_gen1_2, // Gen1/2 PIPE blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_8g_tx_pcs, // 8G TX PCS blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_10g_rx_pcs, // 10G RX PCS blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_10g_tx_pcs, // 10G TX PCS blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_gen3_rx_pcs, // GEN3 RX PCS blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_pipe_gen3, // GEN3 PIPE blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_gen3_tx_pcs, // GEN3 TX PCS blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_krfec_rx_pcs, // KRFEC RX PCS blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_krfec_tx_pcs, // KRFEC TX PCS blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_fifo_rx_pcs, // FIFO RX PCS blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_fifo_tx_pcs, // FIFO TX PCS blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_rx_pcs_pld_if, // RX PCS PLD IF blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_com_pcs_pld_if, // COM PCS PLD IF blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_tx_pcs_pld_if, // TX PCS PLD IF blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_rx_pcs_pma_if, // RX PCS PMA IF blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_com_pcs_pma_if, // COM PCS PMA IF blockselect (1 for each lane)
+ input wire [avmm_interfaces-1 :0] pcs_blockselect_tx_pcs_pma_if, // TX PCS PMA IF blockselect (1 for each lane)
+
+ // PLL AVMM signals
+ input wire [avmm_interfaces*8-1 :0] pll_avmmreaddata_lc_pll, // LC PLL readdata (8 for each PLL)
+ input wire [avmm_interfaces*8-1 :0] pll_avmmreaddata_lc_refclk_select, // LC Refclk Select Mux readdata (8 for each PLL)
+ input wire [avmm_interfaces*8-1 :0] pll_avmmreaddata_cgb_master, // Master CGB readdata (8 for each PLL)
+ input wire [avmm_interfaces*8-1 :0] pll_avmmreaddata_cmu_fpll, // CMU-FPLL readdata (8 for each PLL)
+ input wire [avmm_interfaces*8-1 :0] pll_avmmreaddata_cmu_fpll_refclk_select, // CMU-FPLL refclk mux readdata (8 for each PLL)
+ // CDR Tx PLL will connect to pma_avmmreaddata_cdr_pll and pma_avmmreaddata_cdr_refclk_select
+ input wire [avmm_interfaces-1 :0] pll_blockselect_lc_pll, // LC PLL blockselect (1 for each PLL)
+ input wire [avmm_interfaces-1 :0] pll_blockselect_lc_refclk_select, // LC Refclk Select Mux blockselect (1 for each PLL)
+ input wire [avmm_interfaces-1 :0] pll_blockselect_cgb_master, // Master CGB blockselect (1 for each PLL)
+ input wire [avmm_interfaces-1 :0] pll_blockselect_cmu_fpll, // CMU-FPLL blockselect (1 for each PLL)
+ input wire [avmm_interfaces-1 :0] pll_blockselect_cmu_fpll_refclk_select // CMU-FPLL refclk mux blockselect (1 for each PLL)
+ // CDR Tx PLL will connect to pma_blockselect_cdr_pll and pma_blockselect_cdr_refclk_select
+
+ //PORT_LIST_END
+ );
+
+wire [avmm_interfaces-1 :0] avmm_reset_sync;
+reg [avmm_interfaces-1 :0] avmm_read_r ={avmm_interfaces{1'b0}};
+wire [avmm_interfaces-1 :0] avmm_waitrequest_read;
+wire [avmm_interfaces-1 :0] avmm_waitrequest_write;
+reg [avmm_interfaces-1 :0] avmm_waitrequest_write_int;
+reg [avmm_interfaces*3-1:0] avmm_read_cycles_cnt;
+reg [avmm_interfaces-1 :0] avmm_busy_r1 = {avmm_interfaces{1'b0}};
+reg [avmm_interfaces-1 :0] avmm_busy_r2 = {avmm_interfaces{1'b0}};
+
+wire [avmm_interfaces-1 :0] avmm_request;
+
+localparam calibration_type = "one_time"; //Not used for now. Virtual attribute with no associated BCM settings. Intended to be set by the IP based on the chosen calibration option and used only by the AVMM sim model to decide whether to release the AVMM interface to the user after start-up or hold on to it until the user request according to the hardware implementation. Valid values: one_time, continuous. Export as parameter if needed.
+
+localparam AVMM_READ_LATENCY = 3'b011; //Read latency in the hardware
+localparam AVMM_READ_CYCLES_CNT_RST_VAL = 3'b111; //Reset value of avmm_read_cycles_cnt. Non-zero and >AVMM_READ_LATENCY for avmm_waitrequest to assert during reset
+localparam ARBITER_BASE_ADDR = 9'h000; //AVMM<->uC arbiter base address
+
+generate begin
+ genvar ig;
+ genvar jg;
+ for(ig=0;ig<avmm_interfaces;ig=ig+1) begin : avmm_atom_insts
+ // Size of blockselect bus as defined in the AVMM atom = Number of HSSI atoms + some buffer = 70
+ wire [70-1:0] chnl_pll_avmm_blockselect;
+ wire [7:0] chnl_pll_avmm_readdata [0:(70-1)];
+ wire [70*8-1:0] chnl_pll_avmm_readdatabus;
+
+ // Assign the incoming avmmreaddata and blockselect signals from all the atoms to
+ // the readdata bus and blockselect bus of the AVMM atom respectively
+ for(jg = 0; jg < 70; jg = jg + 1) begin:avmm_assigns
+ assign chnl_pll_avmm_readdatabus[jg*8+:8] = chnl_pll_avmm_readdata[jg];
+ assign {chnl_pll_avmm_readdata[jg],chnl_pll_avmm_blockselect[jg]} =
+ // TX PMA connections
+ (jg == 0) ? {pma_avmmreaddata_tx_ser [ig*8+:8],pma_blockselect_tx_ser [ig]} :
+ (jg == 1) ? {pma_avmmreaddata_tx_cgb [ig*8+:8],pma_blockselect_tx_cgb [ig]} :
+ (jg == 2) ? {pma_avmmreaddata_tx_buf [ig*8+:8],pma_blockselect_tx_buf [ig]} :
+ // RX PMA (includes CDR) connections
+ (jg == 3) ? {pma_avmmreaddata_rx_deser [ig*8+:8],pma_blockselect_rx_deser [ig]} :
+ (jg == 4) ? {pma_avmmreaddata_rx_buf [ig*8+:8],pma_blockselect_rx_buf [ig]} :
+ (jg == 5) ? {pma_avmmreaddata_rx_sd [ig*8+:8],pma_blockselect_rx_sd [ig]} :
+ (jg == 6) ? {pma_avmmreaddata_rx_odi [ig*8+:8],pma_blockselect_rx_odi [ig]} :
+ (jg == 7) ? {pma_avmmreaddata_rx_dfe [ig*8+:8],pma_blockselect_rx_dfe [ig]} :
+ (jg == 8) ? {pma_avmmreaddata_cdr_pll [ig*8+:8],pma_blockselect_cdr_pll [ig]} :
+ (jg == 9) ? {pma_avmmreaddata_cdr_refclk_select [ig*8+:8],pma_blockselect_cdr_refclk_select [ig]} :
+ (jg == 10) ? {pma_avmmreaddata_pma_adapt [ig*8+:8],pma_blockselect_pma_adapt [ig]} :
+ // PCS connections
+ (jg == 20) ? {pcs_avmmreaddata_8g_rx_pcs [ig*8+:8],pcs_blockselect_8g_rx_pcs [ig]} :
+ (jg == 21) ? {pcs_avmmreaddata_pipe_gen1_2 [ig*8+:8],pcs_blockselect_pipe_gen1_2 [ig]} :
+ (jg == 22) ? {pcs_avmmreaddata_8g_tx_pcs [ig*8+:8],pcs_blockselect_8g_tx_pcs [ig]} :
+ (jg == 23) ? {pcs_avmmreaddata_10g_rx_pcs [ig*8+:8],pcs_blockselect_10g_rx_pcs [ig]} :
+ (jg == 24) ? {pcs_avmmreaddata_10g_tx_pcs [ig*8+:8],pcs_blockselect_10g_tx_pcs [ig]} :
+ (jg == 25) ? {pcs_avmmreaddata_gen3_rx_pcs [ig*8+:8],pcs_blockselect_gen3_rx_pcs [ig]} :
+ (jg == 26) ? {pcs_avmmreaddata_pipe_gen3 [ig*8+:8],pcs_blockselect_pipe_gen3 [ig]} :
+ (jg == 27) ? {pcs_avmmreaddata_gen3_tx_pcs [ig*8+:8],pcs_blockselect_gen3_tx_pcs [ig]} :
+ (jg == 28) ? {pcs_avmmreaddata_krfec_rx_pcs [ig*8+:8],pcs_blockselect_krfec_rx_pcs [ig]} :
+ (jg == 29) ? {pcs_avmmreaddata_krfec_tx_pcs [ig*8+:8],pcs_blockselect_krfec_tx_pcs [ig]} :
+ (jg == 30) ? {pcs_avmmreaddata_fifo_rx_pcs [ig*8+:8],pcs_blockselect_fifo_rx_pcs [ig]} :
+ (jg == 31) ? {pcs_avmmreaddata_fifo_tx_pcs [ig*8+:8],pcs_blockselect_fifo_tx_pcs [ig]} :
+ (jg == 32) ? {pcs_avmmreaddata_rx_pcs_pld_if [ig*8+:8],pcs_blockselect_rx_pcs_pld_if [ig]} :
+ (jg == 33) ? {pcs_avmmreaddata_com_pcs_pld_if [ig*8+:8],pcs_blockselect_com_pcs_pld_if [ig]} :
+ (jg == 34) ? {pcs_avmmreaddata_tx_pcs_pld_if [ig*8+:8],pcs_blockselect_tx_pcs_pld_if [ig]} :
+ (jg == 35) ? {pcs_avmmreaddata_rx_pcs_pma_if [ig*8+:8],pcs_blockselect_rx_pcs_pma_if [ig]} :
+ (jg == 36) ? {pcs_avmmreaddata_com_pcs_pma_if [ig*8+:8],pcs_blockselect_com_pcs_pma_if [ig]} :
+ (jg == 37) ? {pcs_avmmreaddata_tx_pcs_pma_if [ig*8+:8],pcs_blockselect_tx_pcs_pma_if [ig]} :
+ // PLL connections
+ (jg == 50) ? {pll_avmmreaddata_lc_pll [ig*8+:8],pll_blockselect_lc_pll [ig]} :
+ (jg == 51) ? {pll_avmmreaddata_lc_refclk_select [ig*8+:8],pll_blockselect_lc_refclk_select [ig]} :
+ (jg == 52) ? {pll_avmmreaddata_cgb_master [ig*8+:8],pll_blockselect_cgb_master [ig]} :
+ (jg == 53) ? {pll_avmmreaddata_cmu_fpll [ig*8+:8],pll_blockselect_cmu_fpll [ig]} :
+ (jg == 54) ? {pll_avmmreaddata_cmu_fpll_refclk_select [ig*8+:8],pll_blockselect_cmu_fpll_refclk_select [ig]} :
+ {8'd0,1'b0}; //unused indices
+ end //avmm_assigns
+
+ if (enable_avmm == 1) begin
+ // AVMM atom
+ twentynm_hssi_avmm_if
+ #(
+ .arbiter_ctrl (arbiter_ctrl ),
+ .calibration_en (calibration_en ),
+ .hip_cal_en (hip_cal_en ),
+ .cal_done (cal_done ),
+ .calibration_type (calibration_type )
+ ) twentynm_hssi_avmm_if_inst
+ (
+ .avmmrstn (1'b1 ), // Tie-off
+ .avmmclk (avmm_clk [ig] ),
+ .avmmwrite (avmm_write [ig] ),
+ .avmmread (avmm_read [ig] ),
+ .avmmaddress (avmm_address [ig*9+:9] ),
+ .avmmwritedata (avmm_writedata [ig*8+:8] ),
+ .avmmreaddata (avmm_readdata [ig*8+:8] ),
+ .avmmbusy (avmm_busy [ig] ),
+ .avmmrequest (avmm_request [ig] ),
+ .hipcaldone (hip_cal_done [ig] ),
+ .pldcaldone (pld_cal_done [ig] ),
+
+ .clkchnl (chnl_pll_avmm_clk [ig] ),
+ .rstnchnl (chnl_pll_avmm_rstn [ig] ),
+ .writechnl (chnl_pll_avmm_write [ig] ),
+ .readchnl (chnl_pll_avmm_read [ig] ),
+ .regaddrchnl (chnl_pll_avmm_address [ig*9+:9] ),
+ .writedatachnl (chnl_pll_avmm_writedata [ig*8+:8] ),
+
+ .readdatachnl (chnl_pll_avmm_readdatabus ),
+ .blockselect (chnl_pll_avmm_blockselect ),
+
+ .scanmoden (1'b1 ),
+ .scanshiftn (1'b1 ),
+ .avmmreservedin (/*unused*/ ),
+ .avmmreservedout (/*unused*/ )
+ );
+
+ //***********************************************************************************
+ //
+ // Generate avmm_waitrequest
+ //
+ //***********************************************************************************
+ // AVMM slave in hardware:
+ // avmm_write -> variable latency
+ // arbiter register = multi-cycle latency with avmm_busy asserted
+ // other registers = fixed 0-cycle latency
+ // avmm_read -> fixed 3-cycle latency
+
+ // Synchronize the falling edge of incoming reconfig reset
+ // Waitrequest is asserted during reset
+ alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH(2), // Number of flip-flops for retiming
+ .WIDTH (1), // Number of bits to resync
+ .INIT_VALUE (1'b1)
+ ) avmm_reset_sync_inst (
+ .clk (avmm_clk[ig] ),
+ .reset (avmm_reset[ig] ),
+ .d (1'b0 ),
+ .q (avmm_reset_sync[ig])
+ );
+
+ //***********************************************************************************
+ //**************** Generate waitrequest for read operation *************************
+ // Register avmm_read
+ always @ (posedge avmm_clk[ig] or posedge avmm_reset_sync[ig]) begin
+ if (avmm_reset_sync[ig]) begin
+ avmm_read_r[ig] <= 1'b0;
+ end else begin
+ avmm_read_r[ig] <= avmm_read[ig];
+ end
+ end
+
+ // Pipeline registers for avmm_busy
+ // Do not reset these registers so they can track avmm_busy accurately
+ always @ (posedge avmm_clk[ig]) begin
+ avmm_busy_r1[ig] <= avmm_busy[ig];
+ avmm_busy_r2[ig] <= avmm_busy_r1[ig];
+ end
+
+ // Read counter
+ // - reset the counter to a value between 0 and AVMM_READ_LATENCY so that waitrequest is asserted during reset
+ // - after reset de-assertion, flip the counter back to 0 for waitrequest to be de-asserted
+ // - increment the count:
+ // - when avmm_read is asserted
+ // - when avmm_busy_r1 is not asserted => the read operation immediately after recalibration request is served after
+ // avmm_busy_r1 is deasserted
+ // - until AVMM_READ_LATENCY count
+ always @ (posedge avmm_clk[ig] or posedge avmm_reset_sync[ig]) begin
+ if (avmm_reset_sync[ig])
+ avmm_read_cycles_cnt[ig*3+:3] <= AVMM_READ_CYCLES_CNT_RST_VAL;
+ else begin
+ if (~avmm_busy_r1[ig] & avmm_read[ig] & (avmm_read_cycles_cnt[ig*3+:3] == 3'b000))
+ avmm_read_cycles_cnt[ig*3+:3] <= avmm_read_cycles_cnt[ig*3+:3] + 1'b1;
+ else if (~avmm_busy_r1[ig] & (avmm_read_cycles_cnt[ig*3+:3] > 3'b000 && avmm_read_cycles_cnt[ig*3+:3] <= AVMM_READ_LATENCY))
+ avmm_read_cycles_cnt[ig*3+:3] <= avmm_read_cycles_cnt[ig*3+:3] + 1'b1;
+ else
+ avmm_read_cycles_cnt[ig*3+:3] <= 3'b000;
+ end
+ end
+
+ // waitrequest for read
+ assign avmm_waitrequest_read[ig] = (avmm_read[ig] & !avmm_read_r[ig]) | //when avmm_read is asserted
+ (avmm_read_cycles_cnt[ig*3+:3] > 3'b000 && avmm_read_cycles_cnt[ig*3+:3] <= AVMM_READ_LATENCY) | //during current read and possible back-to-back reads wihtout avmm_read being deasserted
+ (avmm_read_cycles_cnt[ig*3+:3] == AVMM_READ_CYCLES_CNT_RST_VAL) ; //during reset
+
+ //***********************************************************************************
+ //**************** Generate waitrequest for write operation ************************
+ // Logic enabled only when the calibration feature is enabled
+ // Assertion - very next clock cycle after receiving the arbiter register write request -> 0x0[0] = 1'b1.
+ // - this write indicates that the user wants to give-up the AVMM interface so that the Microcontroller can perform calibration (recalibration or adaptive).
+ // Deassertion - two clock cycles after avmm_busy is deasserted
+ if(calibration_en == "enable") begin : g_cal_en_wreq
+ always @ (posedge avmm_clk[ig] or posedge avmm_reset_sync[ig]) begin
+ if (avmm_reset_sync[ig])
+ avmm_waitrequest_write_int[ig] <= 1'b0;
+ else begin
+ if ((avmm_write[ig] == 1'b1) && (avmm_address[ig*9+:9] == ARBITER_BASE_ADDR) && (avmm_writedata[ig*8] == 1'b1) && (!avmm_waitrequest_write[ig]))
+ avmm_waitrequest_write_int[ig] <= 1'b1;
+ else if (avmm_waitrequest_write_int[ig] & ~avmm_busy_r1[ig] & ~avmm_busy_r2[ig])
+ avmm_waitrequest_write_int[ig] <= 1'b1;
+ else
+ avmm_waitrequest_write_int[ig] <= avmm_busy_r1[ig];
+ end
+ end
+ assign avmm_waitrequest_write[ig] = avmm_waitrequest_write_int[ig];
+ end else begin : g_cal_dis_wreq
+ assign avmm_waitrequest_write[ig] = 1'b0;
+ end
+
+ //***********************************************************************************
+ // user waitrequest
+ // case: 250182
+ // Allow de-coupling the avmm_busy from the avmm waitrequest to support nios and CPU based
+ // reconfiguration sequences and masters. This will address issues with returning the
+ // avmm bus back to the user, which in turn, due to the long waitrequest, causes the system
+ // to timeout.
+ if ( avmm_busy_en == "enable" ) begin
+ assign avmm_waitrequest[ig] = avmm_waitrequest_read[ig];
+ end else begin
+ assign avmm_waitrequest[ig] = avmm_waitrequest_write[ig] | avmm_waitrequest_read[ig];
+ end
+
+
+ //***************************************************************************************************************
+ //
+ // Generate avmm_request
+ //
+ // When Tx term resistance calibration is enabled in continuous mode, the usemodel
+ // is that the Nios will hold the AVMM interface until requested by the user.
+ // The user will request the AVMM interface, perform reconfiguration, and return
+ // the interface back to the Nios to continue with the adaptive calibration.
+
+ // Offset 0x0:
+ // bit 0 = arbiter control (0=pld, 1=uc)
+ // bit 1 = cal_done status (0=not done, 1=done) --> updated by Nios. Should not be touched by the user.
+ //
+ // If reconfig interface is enabled in the PHY GUI:
+ // * if calibration is enabled and continuous mode is set
+ // Steps to access AVMM interface
+ // 1. User requests the AVMM interface -> offset=0x0, RMW bit 0 = 0
+ // --> Internally, this module generates avmm_request signal that maps to a status register bit in hardware
+ // --> Nios reads this bit if the continuous calibration is enabled and gives up the AVMM interface
+ // 2. When waitrequest is de-asserted, user performs reconfiguration
+ // 3. User requests recalibration and thereby give up the AVMM interface to Nios
+ // -> offset=0x0, RMW bit 0 = 1
+ // * if either calibration is disabled or continuous mode is not set
+ // tie-off avmm_request to 1'b1 => park the avmm_request bit to always be in the user "request" mode
+ //
+ // If reconfig interface is NOT enabled in the PHY GUI:
+ // tie-off avmm_request to 1'b0 => park the avmm_request bit to always be in the "not request" mode => allow Nios to do adaptive calibration
+
+ //***************************************************************************************************************
+ // Assertion - very next clock cycle after receiving the arbiter register write request -> 0x0[0] = 1'b0
+ // - this write indicates that the user wants to get the AVMM interface from the Microcontroller so that the user can perform reconfiguration.
+ // Deassertion - after avmm_busy goes low
+ // - this indicates that the user has received the AVMM interface
+ if(rcfg_enable == 1) begin: g_rcfg_en
+ if ((calibration_en == "enable") && (calibration_type == "continuous")) begin : g_cal_en_req
+ reg [avmm_interfaces-1 :0] avmm_request_int = 1'b0;
+
+ always @ (posedge avmm_clk[ig] or posedge avmm_reset_sync[ig]) begin
+ if (avmm_reset_sync[ig])
+ avmm_request_int[ig] <= 1'b0;
+ else begin
+ if ((avmm_write[ig] == 1'b1) && (avmm_address[ig*9+:9] == ARBITER_BASE_ADDR) && (avmm_writedata[ig*8] == 1'b0) && (!avmm_request_int[ig]))
+ avmm_request_int[ig] <= 1'b1;
+ else if (~avmm_busy_r2[ig])
+ avmm_request_int[ig] <= 1'b0;
+ end
+ end
+ assign avmm_request[ig] = avmm_request_int[ig];
+ end else begin: g_cal_dis_req
+ //Park the interface request favoring the user AVMM
+ assign avmm_request[ig] = 1'b1;
+ end
+ end else begin : g_rcfg_dis
+ //Park the interface request favoring the Nios if reconfiguration is not enabled by the user
+ assign avmm_request[ig] = 1'b0;
+ end
+
+ end else begin //if !(enable_avmm), tie-off AVMM atom outputs
+ assign chnl_pll_avmm_clk [ig] = 1'b0;
+ assign chnl_pll_avmm_rstn [ig] = 1'b1;
+ assign chnl_pll_avmm_writedata [ig*8+:8] = 8'd0;
+ assign chnl_pll_avmm_address [ig*9+:9] = 9'd0;
+ assign chnl_pll_avmm_write [ig] = 1'b0;
+ assign chnl_pll_avmm_read [ig] = 1'b0;
+ end
+ end
+end
+endgenerate
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/a10_avmm_h.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/a10_avmm_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..73f6f7157e844104fe84b5f88f316dcca727e848
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/a10_avmm_h.sv
@@ -0,0 +1,163 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+package a10_avmm_h;
+
+ // localparam to define unused bus
+ localparam RD_UNUSED = 8'h0;
+
+ // localparams for common capability registers
+ localparam A10_XR_ADDR_ID_0 = 9'h0;
+ localparam A10_XR_ADDR_ID_1 = 9'h1;
+ localparam A10_XR_ADDR_ID_2 = 9'h2;
+ localparam A10_XR_ADDR_ID_3 = 9'h3;
+ localparam A10_XR_ADDR_STATUS_EN = 9'h4;
+ localparam A10_XR_ADDR_CONTROL_EN = 9'h5;
+ // Reserve Address 9'h6 to 9'hF for common capablities
+
+ // native phy capability
+ localparam A10_XR_ADDR_NAT_CHNLS = 9'h10;
+ localparam A10_XR_ADDR_NAT_CHNL_NUM = 9'h11;
+ localparam A10_XR_ADDR_NAT_DUPLEX = 9'h12;
+ localparam A10_XR_ADDR_NAT_PRBS_EN = 9'h13;
+ localparam A10_XR_ADDR_NAT_ODI_EN = 9'h14;
+
+ // pll ip capability
+ localparam A10_XR_ADDR_PLL_MCGB_EN = 9'h10;
+
+ // localparams for csr for pll locked and cal busy
+ localparam A10_XR_ADDR_GP_PLL_LOCK = 9'h80;
+ localparam A10_XR_OFFSET_GP_LOCK = 0;
+ localparam A10_XR_OFFSET_GP_CAL_BUSY = 1;
+ localparam A10_XR_OFFSET_GP_AVMM_BUSY = 2;
+ localparam A10_XR_OFFSET_LOCK_UNUSED = 3;
+ localparam A10_XR_LOCK_UNUSED_LEN = 5;
+
+ // localparams for pll powerdown
+ localparam A10_XR_ADDR_GP_PLL_RST = 9'hE0;
+ localparam A10_XR_OFFSET_PLL_RST = 0;
+ localparam A10_XR_OFFSET_PLL_RST_OVR = 1;
+ localparam A10_XR_OFFSET_PLL_RST_UNUSED = 2;
+ localparam A10_XR_PLL_RST_UNUSED_LEN = 6;
+
+ // localparams for csr for lock to ref and lock to data
+ localparam A10_XR_ADDR_GP_RD_LTR = 9'h80;
+ localparam A10_XR_OFFSET_RD_LTD = 0;
+ localparam A10_XR_OFFSET_RD_LTR = 1;
+ localparam A10_XR_OFFSET_LTR_UNUSED = 2;
+ localparam A10_XR_LTR_UNUSED_LEN = 6;
+
+ // localparams for csr for cal busy
+ localparam A10_XR_ADDR_GP_CAL_BUSY = 9'h81;
+ localparam A10_XR_OFFSET_TX_CAL_BUSY = 0;
+ localparam A10_XR_OFFSET_RX_CAL_BUSY = 1;
+ localparam A10_XR_OFFSET_AVMM_BUSY = 2;
+ localparam A10_XR_OFFSET_CAL_DUMMY = 3;
+ localparam A10_XR_OFFSET_TX_CAL_MASK = 4;
+ localparam A10_XR_OFFSET_RX_CAL_MASK = 5;
+ localparam A10_XR_OFFSET_CAL_UNUSED = 6;
+ localparam A10_XR_CAL_UNUSED_LEN = 2;
+
+ // localparams for setting lock to ref and lock to data
+ localparam A10_XR_ADDR_GP_SET_LTR = 9'hE0;
+ localparam A10_XR_OFFSET_SET_LTD = 0;
+ localparam A10_XR_OFFSET_SET_LTR = 1;
+ localparam A10_XR_OFFSET_SET_LTD_OVR = 2;
+ localparam A10_XR_OFFSET_SET_LTR_OVR = 3;
+ localparam A10_XR_OFFSET_SET_LTR_UNUSED = 4;
+ localparam A10_XR_SET_LTR_UNUSED_LEN = 4;
+
+ // localparams for setting loopback
+ localparam A10_XR_ADDR_GP_LPBK = 9'hE1;
+ localparam A10_XR_OFFSET_LPBK = 0;
+ localparam A10_XR_OFFSET_LPBK_UNUSED = 1;
+ localparam A10_XR_LPBK_UNUSED_LEN = 7;
+
+ // localparams for setting channel resets
+ localparam A10_XR_ADDR_CHNL_RESET = 9'hE2;
+ localparam A10_XR_OFFSET_RX_ANA = 0;
+ localparam A10_XR_OFFSET_RX_DIG = 1;
+ localparam A10_XR_OFFSET_TX_ANA = 2;
+ localparam A10_XR_OFFSET_TX_DIG = 3;
+ localparam A10_XR_OFFSET_RX_ANA_OVR = 4;
+ localparam A10_XR_OFFSET_RX_DIG_OVR = 5;
+ localparam A10_XR_OFFSET_TX_ANA_OVR = 6;
+ localparam A10_XR_OFFSET_TX_DIG_OVR = 7;
+
+ // localparams for prbs addresses
+ localparam A10_XR_ADDR_PRBS_CTRL = 9'h100;
+ localparam A10_XR_ADDR_PRBS_ERR_0 = 9'h101;
+ localparam A10_XR_ADDR_PRBS_ERR_1 = 9'h102;
+ localparam A10_XR_ADDR_PRBS_ERR_2 = 9'h103;
+ localparam A10_XR_ADDR_PRBS_ERR_3 = 9'h104;
+ localparam A10_XR_ADDR_PRBS_ERR_4 = 9'h105;
+ localparam A10_XR_ADDR_PRBS_ERR_5 = 9'h106;
+ localparam A10_XR_ADDR_PRBS_ERR_6 = 9'h107;
+ localparam A10_XR_ADDR_PRBS_BIT_0 = 9'h10D;
+ localparam A10_XR_ADDR_PRBS_BIT_1 = 9'h10E;
+ localparam A10_XR_ADDR_PRBS_BIT_2 = 9'h10F;
+ localparam A10_XR_ADDR_PRBS_BIT_3 = 9'h110;
+ localparam A10_XR_ADDR_PRBS_BIT_4 = 9'h111;
+ localparam A10_XR_ADDR_PRBS_BIT_5 = 9'h112;
+ localparam A10_XR_ADDR_PRBS_BIT_6 = 9'h113;
+
+ // localparams for prbs bit offsets
+ localparam A10_XR_OFFSET_PRBS_EN = 0;
+ localparam A10_XR_OFFSET_PRBS_RESET = 1;
+ localparam A10_XR_OFFSET_PRBS_SNAP = 2;
+ localparam A10_XR_OFFSET_PRBS_DONE = 3;
+ localparam A10_XR_OFFSET_PRBS_UNUSED = 4;
+ localparam A10_XR_PRBS_UNUSED_LEN = 4;
+
+ // localparams for odi addresses
+ localparam A10_XR_ADDR_ODI_CTRL = 9'h120;
+ localparam A10_XR_ADDR_ODI_ERR_0 = 9'h121;
+ localparam A10_XR_ADDR_ODI_ERR_1 = 9'h122;
+ localparam A10_XR_ADDR_ODI_ERR_2 = 9'h123;
+ localparam A10_XR_ADDR_ODI_ERR_3 = 9'h124;
+ localparam A10_XR_ADDR_ODI_ERR_4 = 9'h125;
+ localparam A10_XR_ADDR_ODI_ERR_5 = 9'h126;
+ localparam A10_XR_ADDR_ODI_ERR_6 = 9'h127;
+ localparam A10_XR_ADDR_ODI_BIT_0 = 9'h12D;
+ localparam A10_XR_ADDR_ODI_BIT_1 = 9'h12E;
+ localparam A10_XR_ADDR_ODI_BIT_2 = 9'h12F;
+ localparam A10_XR_ADDR_ODI_BIT_3 = 9'h130;
+ localparam A10_XR_ADDR_ODI_BIT_4 = 9'h131;
+ localparam A10_XR_ADDR_ODI_BIT_5 = 9'h132;
+ localparam A10_XR_ADDR_ODI_BIT_6 = 9'h133;
+
+ // localparams for odi bit offsets
+ localparam A10_XR_OFFSET_ODI_EN = 0;
+ localparam A10_XR_OFFSET_ODI_RESET = 1;
+ localparam A10_XR_OFFSET_ODI_SNAP = 2;
+ localparam A10_XR_OFFSET_ODI_DONE = 3;
+ localparam A10_XR_OFFSET_ODI_UNUSED = 4;
+ localparam A10_XR_ODI_UNUSED_LEN = 4;
+
+ // localparams for embedded reconfig addresses
+ // Control reg and offsets
+ localparam A10_XR_ADDR_EMBED_RCFG_CTRL = 9'h140;
+ localparam A10_XR_OFFSET_EMBED_RCFG_CFG_SEL = 0;
+ localparam A10_XR_EMBED_RCFG_CFG_SEL_LEN = 6; //bits [5:0] are alloted for cfg_sel even though GUI currently only supports upto 8 profiles.
+
+ localparam A10_XR_OFFSET_EMBED_RCFG_BCAST_EN = 6;
+ localparam A10_XR_OFFSET_EMBED_RCFG_CFG_LOAD = 7;
+
+ // Status reg and offsets
+ localparam A10_XR_ADDR_EMBED_RCFG_STATUS = 9'h141;
+ localparam A10_XR_OFFSET_EMBED_RCFG_STRM_BUSY = 0;
+
+
+endpackage
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_arbiter.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_arbiter.sv
new file mode 100644
index 0000000000000000000000000000000000000000..7eb77632c6d21f14d681d129b191eacd0de6339b
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_arbiter.sv
@@ -0,0 +1,68 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Clocked priority encoder with state
+//
+// On each clock cycle, updates state to show which request is granted.
+// Most recent grant holder is always the highest priority.
+// If current grant holder is not making a request, while others are,
+// then new grant holder is always the requester with lowest bit number.
+// If no requests, current grant holder retains grant state
+
+// $Header$
+
+`timescale 1 ns / 1 ns
+
+module alt_xcvr_arbiter #(
+ parameter width = 2
+) (
+ input wire clock,
+ input wire [width-1:0] req, // req[n] requests for this cycle
+ output reg [width-1:0] grant // grant[n] means requester n is grantee in this cycle
+);
+
+ wire idle; // idle when no requests
+ wire [width-1:0] keep; // keep[n] means requester n is requesting, and already has the grant
+ // Note: current grantee is always highest priority for next grant
+ wire [width-1:0] take; // take[n] means requester n is requesting, and there are no higher-priority requests
+
+ assign keep = req & grant; // current grantee is always highest priority for next grant
+ assign idle = ~| req; // idle when no requests
+
+ initial begin
+ grant = 0;
+ end
+
+ // grant next state depends on current grant and take priority
+ always @(posedge clock) begin
+ grant <=
+// synthesis translate_off
+ (grant === {width{1'bx}})? {width{1'b0}} :
+// synthesis translate_on
+ keep // if current grantee is requesting, gets to keep grant
+ | ({width{idle}} & grant) // if no requests, grant state remains unchanged
+ | take; // take applies only if current grantee is not requesting
+ end
+
+ // 'take' bus encodes priority. Request with lowest bit number wins when current grantee not requesting
+ assign take[0] = req[0]
+ & (~| (keep & ({width{1'b1}} << 1))); // no 'keep' from lower-priority inputs
+ genvar i;
+ generate
+ for (i=1; i < width; i = i + 1) begin : arb
+ assign take[i] = req[i]
+ & (~| (keep & ({width{1'b1}} << (i+1)))) // no 'keep' from lower-priority inputs
+ & (~| (req & {i{1'b1}})); // no 'req' from higher-priority inputs
+ end
+ endgenerate
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_avmm_csr.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_avmm_csr.sv
new file mode 100644
index 0000000000000000000000000000000000000000..86529b7cea3f6ed8450a827aee577cfc76a62ad5
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_avmm_csr.sv
@@ -0,0 +1,600 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+module alt_xcvr_native_avmm_csr #(
+ parameter dbg_capability_reg_enable = 0,
+ parameter dbg_user_identifier = 0,
+ parameter dbg_stat_soft_logic_enable = 0,
+ parameter dbg_ctrl_soft_logic_enable = 0,
+ parameter channels = 1,
+ parameter channel_num = 1,
+ parameter duplex_mode = 3,
+ parameter dbg_prbs_soft_logic_enable = 0,
+ parameter dbg_odi_soft_logic_enable = 0,
+ parameter rcfg_emb_strm_enable = 0,
+ parameter rcfg_emb_strm_cfg_sel_width = 2
+) (
+ // avmm signals
+ input avmm_clk,
+ input avmm_reset,
+ input [8:0] avmm_address,
+ input [7:0] avmm_writedata,
+ input avmm_write,
+ input avmm_read,
+ output reg [7:0] avmm_readdata,
+ output avmm_waitrequest,
+
+ // prbs ctrl signal
+ input [49:0] prbs_err,
+ input [49:0] prbs_bit,
+ input prbs_done,
+ output prbs_count_en,
+ output prbs_snap,
+ output prbs_reset,
+
+ // odi ctrl signals
+ input [49:0] odi_bit,
+ input [49:0] odi_err,
+ input odi_done,
+ output odi_count_en,
+ output odi_reset,
+ output odi_snap,
+
+ // input status signals from the channel
+ input rx_is_lockedtodata,
+ input rx_is_lockedtoref,
+ input tx_cal_busy,
+ input rx_cal_busy,
+ input avmm_busy,
+
+ // input control signals
+ input rx_prbs_err_clr,
+ input set_rx_locktoref,
+ input set_rx_locktodata,
+ input serial_loopback,
+ input rx_analogreset,
+ input rx_digitalreset,
+ input tx_analogreset,
+ input tx_digitalreset,
+
+ // embedded reconfigsignals
+ input rcfg_emb_strm_busy,
+ input rcfg_emb_strm_chan_sel,
+ output [rcfg_emb_strm_cfg_sel_width-1:0] rcfg_emb_strm_cfg_sel,
+ output rcfg_emb_strm_bcast_en,
+ output rcfg_emb_strm_cfg_load,
+
+ // output control signals to the channel
+ output csr_set_lock_to_data,
+ output csr_set_lock_to_ref,
+ output csr_en_loopback,
+ output csr_rx_analogreset,
+ output csr_rx_digitalreset,
+ output csr_tx_analogreset,
+ output csr_tx_digitalreset,
+ output csr_tx_cal_busy_mask,
+ output csr_rx_cal_busy_mask
+);
+
+// Import package with parameters for the soft addresses and offsets
+import a10_avmm_h::*;
+
+
+// Reg for generating waitrequest and data valid
+reg avmm_valid;
+
+/**********************************************************************/
+// wires and bus declaration
+/**********************************************************************/
+wire [7:0] rd_channel;
+wire [7:0] rd_channel_num;
+wire [7:0] rd_duplex;
+wire [7:0] rd_system_id;
+wire [7:0] rd_prbs_en;
+wire [7:0] rd_odi_en;
+wire [7:0] rd_status_en;
+wire [7:0] rd_control_en;
+wire [7:0] rd_prbs_ctrl;
+wire [7:0] rd_odi_ctrl;
+wire [7:0] rd_ltr_status;
+wire [7:0] rd_set_ltr;
+wire [7:0] rd_loopback;
+wire [7:0] rd_cal_busy;
+wire [7:0] rd_chnl_reset;
+wire [7:0] rd_rcfg_emb_ctrl;
+wire [7:0] rd_rcfg_emb_status;
+wire [49:0] rd_prbs_err;
+wire [49:0] rd_prbs_bit;
+wire [49:0] rd_odi_err;
+wire [49:0] rd_odi_bit;
+
+/**********************************************************************/
+//generate waitrequest
+/**********************************************************************/
+assign avmm_waitrequest = (~avmm_valid & avmm_read);
+
+
+/**********************************************************************/
+// soft CSRs for embedded debug
+/**********************************************************************/
+always@(posedge avmm_clk) begin
+ if(~avmm_read) begin
+ avmm_valid <= 1'b0;
+ avmm_readdata <= RD_UNUSED;
+ end else begin
+ avmm_valid <= avmm_waitrequest;
+ case(avmm_address)
+
+ // Address for Capabilities
+ A10_XR_ADDR_ID_0: avmm_readdata <= rd_system_id;
+ A10_XR_ADDR_STATUS_EN: avmm_readdata <= rd_status_en;
+ A10_XR_ADDR_CONTROL_EN: avmm_readdata <= rd_control_en;
+ A10_XR_ADDR_NAT_CHNLS: avmm_readdata <= rd_channel;
+ A10_XR_ADDR_NAT_CHNL_NUM: avmm_readdata <= rd_channel_num;
+ A10_XR_ADDR_NAT_DUPLEX: avmm_readdata <= rd_duplex;
+ A10_XR_ADDR_NAT_PRBS_EN: avmm_readdata <= rd_prbs_en;
+ A10_XR_ADDR_NAT_ODI_EN: avmm_readdata <= rd_odi_en;
+
+ // Addresses for PRBS
+ A10_XR_ADDR_PRBS_CTRL: avmm_readdata <= rd_prbs_ctrl;
+ A10_XR_ADDR_PRBS_ERR_0: avmm_readdata <= rd_prbs_err[7:0];
+ A10_XR_ADDR_PRBS_ERR_1: avmm_readdata <= rd_prbs_err[15:8];
+ A10_XR_ADDR_PRBS_ERR_2: avmm_readdata <= rd_prbs_err[23:16];
+ A10_XR_ADDR_PRBS_ERR_3: avmm_readdata <= rd_prbs_err[31:24];
+ A10_XR_ADDR_PRBS_ERR_4: avmm_readdata <= rd_prbs_err[39:32];
+ A10_XR_ADDR_PRBS_ERR_5: avmm_readdata <= rd_prbs_err[47:40];
+ A10_XR_ADDR_PRBS_ERR_6: avmm_readdata <= {6'b0, rd_prbs_err[49:48]};
+ A10_XR_ADDR_PRBS_BIT_0: avmm_readdata <= rd_prbs_bit[7:0];
+ A10_XR_ADDR_PRBS_BIT_1: avmm_readdata <= rd_prbs_bit[15:8];
+ A10_XR_ADDR_PRBS_BIT_2: avmm_readdata <= rd_prbs_bit[23:16];
+ A10_XR_ADDR_PRBS_BIT_3: avmm_readdata <= rd_prbs_bit[31:24];
+ A10_XR_ADDR_PRBS_BIT_4: avmm_readdata <= rd_prbs_bit[39:32];
+ A10_XR_ADDR_PRBS_BIT_5: avmm_readdata <= rd_prbs_bit[47:40];
+ A10_XR_ADDR_PRBS_BIT_6: avmm_readdata <= {6'b0, rd_prbs_bit[49:48]};
+
+ // Address for ODI
+ A10_XR_ADDR_ODI_CTRL: avmm_readdata <= rd_odi_ctrl;
+ A10_XR_ADDR_ODI_ERR_0: avmm_readdata <= rd_odi_err[7:0];
+ A10_XR_ADDR_ODI_ERR_1: avmm_readdata <= rd_odi_err[15:8];
+ A10_XR_ADDR_ODI_ERR_2: avmm_readdata <= rd_odi_err[23:16];
+ A10_XR_ADDR_ODI_ERR_3: avmm_readdata <= rd_odi_err[31:24];
+ A10_XR_ADDR_ODI_ERR_4: avmm_readdata <= rd_odi_err[39:32];
+ A10_XR_ADDR_ODI_ERR_5: avmm_readdata <= rd_odi_err[47:40];
+ A10_XR_ADDR_ODI_ERR_6: avmm_readdata <= {6'b0, rd_odi_err[49:48]};
+ A10_XR_ADDR_ODI_BIT_0: avmm_readdata <= rd_odi_bit[7:0];
+ A10_XR_ADDR_ODI_BIT_1: avmm_readdata <= rd_odi_bit[15:8];
+ A10_XR_ADDR_ODI_BIT_2: avmm_readdata <= rd_odi_bit[23:16];
+ A10_XR_ADDR_ODI_BIT_3: avmm_readdata <= rd_odi_bit[31:24];
+ A10_XR_ADDR_ODI_BIT_4: avmm_readdata <= rd_odi_bit[39:32];
+ A10_XR_ADDR_ODI_BIT_5: avmm_readdata <= rd_odi_bit[47:40];
+ A10_XR_ADDR_ODI_BIT_6: avmm_readdata <= {6'b0, rd_odi_bit[49:48]};
+
+ // Address for status registers
+ A10_XR_ADDR_GP_RD_LTR: avmm_readdata <= rd_ltr_status;
+ A10_XR_ADDR_GP_CAL_BUSY: avmm_readdata <= rd_cal_busy;
+
+ // Addresses for control registers
+ A10_XR_ADDR_GP_SET_LTR: avmm_readdata <= rd_set_ltr;
+ A10_XR_ADDR_GP_LPBK: avmm_readdata <= rd_loopback;
+ A10_XR_ADDR_CHNL_RESET: avmm_readdata <= rd_chnl_reset;
+ //Embedded reconfig
+ A10_XR_ADDR_EMBED_RCFG_CTRL: avmm_readdata <= rd_rcfg_emb_ctrl;
+ A10_XR_ADDR_EMBED_RCFG_STATUS: avmm_readdata <= rd_rcfg_emb_status;
+ default: avmm_readdata <= RD_UNUSED;
+ endcase
+ end
+end
+
+/**********************************************************************/
+// Generate Capability Registers
+/**********************************************************************/
+generate if(dbg_capability_reg_enable == 1) begin: g_capability_reg_en
+ assign rd_channel = channels[7:0];
+ assign rd_channel_num = channel_num[7:0];
+ assign rd_duplex = (duplex_mode == "duplex") ? 8'h3 :
+ (duplex_mode == "tx") ? 8'h2 : 8'h1;
+ assign rd_system_id = dbg_user_identifier[7:0];
+ assign rd_prbs_en = dbg_prbs_soft_logic_enable[7:0];
+ assign rd_odi_en = dbg_odi_soft_logic_enable[7:0];
+ assign rd_status_en = dbg_stat_soft_logic_enable[7:0];
+ assign rd_control_en = dbg_ctrl_soft_logic_enable[7:0];
+ end else begin: g_capability_reg_dis
+ assign rd_channel = RD_UNUSED;
+ assign rd_channel_num = RD_UNUSED;
+ assign rd_duplex = RD_UNUSED;
+ assign rd_system_id = RD_UNUSED;
+ assign rd_prbs_en = RD_UNUSED;
+ assign rd_odi_en = RD_UNUSED;
+ assign rd_status_en = RD_UNUSED;
+ assign rd_control_en = RD_UNUSED;
+ end
+endgenerate // End generate for g_capability_reg
+
+
+/**********************************************************************/
+// Generate registers for status signals
+/**********************************************************************/
+generate if(dbg_stat_soft_logic_enable == 1) begin: g_status_reg_en
+
+ /**********************************************************************/
+ // Wires for status signal synchronizers inside generate to avoid un-used wires
+ /**********************************************************************/
+ wire rx_is_ltd_sync;
+ wire rx_is_ltr_sync;
+ wire tx_cal_busy_sync;
+ wire rx_cal_busy_sync;
+
+
+ /**********************************************************************/
+ // Instantiate Synchronizers and read logic for rx_is_lockedtodata and rx_is_lockedtoref
+ /**********************************************************************/
+ alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 2 ) // two bits, one for locktodata and one for locktoref
+ ) rx_is_locked_sync (
+ .clk (avmm_clk),
+ .reset (avmm_reset),
+ .d ({rx_is_lockedtodata, rx_is_lockedtoref}),
+ .q ({rx_is_ltd_sync, rx_is_ltr_sync})
+ );
+
+ assign rd_ltr_status[A10_XR_OFFSET_RD_LTR] = rx_is_ltr_sync;
+ assign rd_ltr_status[A10_XR_OFFSET_RD_LTD] = rx_is_ltd_sync;
+ assign rd_ltr_status[A10_XR_OFFSET_LTR_UNUSED+:A10_XR_LTR_UNUSED_LEN] = {A10_XR_LTR_UNUSED_LEN{1'b0}};
+
+
+ /**********************************************************************/
+ // Instantiate Synchronizers and read logic for avmm busy, cal busy and their masks
+ /**********************************************************************/
+ reg r_set_tx_cal_mask;
+ reg r_set_rx_cal_mask;
+ reg r_avmm_busy;
+
+ // Instantiate Synchronizers and read logic for cal busy and avmm busy
+ alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 2 ) // two bits, one for tx cal busy and one for rx cal busy
+ ) cal_busy (
+ .clk (avmm_clk),
+ .reset (avmm_reset),
+ .d ({rx_cal_busy, tx_cal_busy}),
+ .q ({rx_cal_busy_sync, tx_cal_busy_sync})
+ );
+
+ assign csr_tx_cal_busy_mask = ~r_set_tx_cal_mask;
+ assign csr_rx_cal_busy_mask = ~r_set_rx_cal_mask;
+ assign rd_cal_busy[A10_XR_OFFSET_TX_CAL_BUSY] = tx_cal_busy_sync;
+ assign rd_cal_busy[A10_XR_OFFSET_RX_CAL_BUSY] = rx_cal_busy_sync;
+ assign rd_cal_busy[A10_XR_OFFSET_AVMM_BUSY] = r_avmm_busy;
+ assign rd_cal_busy[A10_XR_OFFSET_CAL_DUMMY] = 1'b0;
+ assign rd_cal_busy[A10_XR_OFFSET_TX_CAL_MASK] = ~r_set_tx_cal_mask;
+ assign rd_cal_busy[A10_XR_OFFSET_RX_CAL_MASK] = ~r_set_rx_cal_mask;
+ assign rd_cal_busy[A10_XR_OFFSET_CAL_UNUSED+:A10_XR_CAL_UNUSED_LEN] = {A10_XR_CAL_UNUSED_LEN{1'b0}};
+
+ // Assure that the avmm_busy register always gets updated
+ always@(posedge avmm_clk) begin
+ // Register the avmm busy signal
+ r_avmm_busy <= avmm_busy;
+ end
+
+ // write cal_busy masks
+ // Due to synthesis option not-gate pushback being optionally enabled, We will hard code its behavior.
+ // this ensures that with or without a reset, the design will behave the same irrespective of the synth
+ // option being enabled in the design.
+ always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ r_set_tx_cal_mask <= 1'b0;
+ r_set_rx_cal_mask <= 1'b0;
+ end else if(avmm_write && avmm_address == A10_XR_ADDR_GP_CAL_BUSY) begin
+ r_set_tx_cal_mask <= ~avmm_writedata[A10_XR_OFFSET_TX_CAL_MASK];
+ r_set_rx_cal_mask <= ~avmm_writedata[A10_XR_OFFSET_RX_CAL_MASK];
+ end
+ end
+
+ end else begin: g_status_reg_dis
+ assign rd_ltr_status = RD_UNUSED;
+ assign rd_cal_busy = RD_UNUSED;
+ assign csr_tx_cal_busy_mask = 1'b1;
+ assign csr_rx_cal_busy_mask = 1'b1;
+ end
+endgenerate //End generate g_status_reg
+
+
+/**********************************************************************/
+// Generate registers for control signals
+/**********************************************************************/
+generate if(dbg_ctrl_soft_logic_enable == 1) begin: g_control_reg
+
+ /**********************************************************************/
+ // Registers for set Lock to ref and set Lock to Data
+ /**********************************************************************/
+ reg r_set_ltr;
+ reg r_set_ltd;
+ reg r_set_ltr_override;
+ reg r_set_ltd_override;
+
+ // readback control registers for set ltr and ltd
+ assign rd_set_ltr[A10_XR_OFFSET_SET_LTR] = r_set_ltr;
+ assign rd_set_ltr[A10_XR_OFFSET_SET_LTD] = r_set_ltd;
+ assign rd_set_ltr[A10_XR_OFFSET_SET_LTR_OVR] = r_set_ltr_override;
+ assign rd_set_ltr[A10_XR_OFFSET_SET_LTD_OVR] = r_set_ltd_override;
+ assign rd_set_ltr[A10_XR_OFFSET_SET_LTR_UNUSED+:A10_XR_SET_LTR_UNUSED_LEN] = {A10_XR_SET_LTR_UNUSED_LEN{1'b0}};
+
+ // assign the output signals to the channel. Use the inputs signal with the control registers
+ assign csr_set_lock_to_ref = (rd_set_ltr[A10_XR_OFFSET_SET_LTR_OVR]) ? rd_set_ltr[A10_XR_OFFSET_SET_LTR] : set_rx_locktoref;
+ assign csr_set_lock_to_data = (rd_set_ltr[A10_XR_OFFSET_SET_LTD_OVR]) ? rd_set_ltr[A10_XR_OFFSET_SET_LTD] : set_rx_locktodata;
+
+ // write control registers for ltr and ltd
+ always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ r_set_ltr <= 1'b0;
+ r_set_ltd <= 1'b0;
+ r_set_ltr_override <= 1'b0;
+ r_set_ltd_override <= 1'b0;
+ end else if(avmm_write && avmm_address == A10_XR_ADDR_GP_SET_LTR) begin
+ r_set_ltr <= avmm_writedata[A10_XR_OFFSET_SET_LTR];
+ r_set_ltd <= avmm_writedata[A10_XR_OFFSET_SET_LTD];
+ r_set_ltr_override <= avmm_writedata[A10_XR_OFFSET_SET_LTR_OVR];
+ r_set_ltd_override <= avmm_writedata[A10_XR_OFFSET_SET_LTD_OVR];
+ end
+ end
+
+
+ /**********************************************************************/
+ // Registers for loopback
+ /**********************************************************************/
+ reg r_loopback;
+
+ // readback control register for enabling loopback
+ assign rd_loopback[A10_XR_OFFSET_LPBK] = r_loopback;
+ assign rd_loopback[A10_XR_OFFSET_LPBK_UNUSED+:A10_XR_LPBK_UNUSED_LEN] = {A10_XR_LPBK_UNUSED_LEN{1'b0}};
+
+ // assign the output signals to the channel
+ assign csr_en_loopback = (rd_loopback[A10_XR_OFFSET_LPBK] || serial_loopback);
+
+ // write control registers for loopback
+ always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ r_loopback <= 1'b0;
+ end else if(avmm_write && avmm_address == A10_XR_ADDR_GP_LPBK) begin
+ r_loopback <= avmm_writedata[A10_XR_OFFSET_LPBK];
+ end
+ end
+
+
+ /**********************************************************************/
+ // Registers for Channel Resets and Overrides
+ /**********************************************************************/
+ reg r_rx_analogreset;
+ reg r_rx_digitalreset;
+ reg r_tx_analogreset;
+ reg r_tx_digitalreset;
+ reg r_rx_analogreset_override;
+ reg r_rx_digitalreset_override;
+ reg r_tx_analogreset_override;
+ reg r_tx_digitalreset_override;
+
+ // readback the control registers for the channel resets and overrides
+ assign rd_chnl_reset[A10_XR_OFFSET_RX_ANA] = r_rx_analogreset;
+ assign rd_chnl_reset[A10_XR_OFFSET_RX_DIG] = r_rx_digitalreset;
+ assign rd_chnl_reset[A10_XR_OFFSET_TX_ANA] = r_tx_analogreset;
+ assign rd_chnl_reset[A10_XR_OFFSET_TX_DIG] = r_tx_digitalreset;
+ assign rd_chnl_reset[A10_XR_OFFSET_RX_ANA_OVR] = r_rx_analogreset_override;
+ assign rd_chnl_reset[A10_XR_OFFSET_RX_DIG_OVR] = r_rx_digitalreset_override;
+ assign rd_chnl_reset[A10_XR_OFFSET_TX_ANA_OVR] = r_tx_analogreset_override;
+ assign rd_chnl_reset[A10_XR_OFFSET_TX_DIG_OVR] = r_tx_digitalreset_override;
+
+ // assign the output signals to the channel
+ assign csr_rx_analogreset = (rd_chnl_reset[A10_XR_OFFSET_RX_ANA_OVR]) ? rd_chnl_reset[A10_XR_OFFSET_RX_ANA] : rx_analogreset;
+ assign csr_rx_digitalreset = (rd_chnl_reset[A10_XR_OFFSET_RX_DIG_OVR]) ? rd_chnl_reset[A10_XR_OFFSET_RX_DIG] : rx_digitalreset;
+ assign csr_tx_analogreset = (rd_chnl_reset[A10_XR_OFFSET_TX_ANA_OVR]) ? rd_chnl_reset[A10_XR_OFFSET_TX_ANA] : tx_analogreset;
+ assign csr_tx_digitalreset = (rd_chnl_reset[A10_XR_OFFSET_TX_DIG_OVR]) ? rd_chnl_reset[A10_XR_OFFSET_TX_DIG] : tx_digitalreset;
+
+ // write reset and reset override registers
+ always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ r_rx_analogreset <= 1'b0;
+ r_rx_digitalreset <= 1'b0;
+ r_tx_analogreset <= 1'b0;
+ r_tx_digitalreset <= 1'b0;
+ r_rx_analogreset_override <= 1'b0;
+ r_rx_digitalreset_override <= 1'b0;
+ r_tx_analogreset_override <= 1'b0;
+ r_tx_digitalreset_override <= 1'b0;
+ end else if(avmm_write && avmm_address == A10_XR_ADDR_CHNL_RESET) begin
+ r_rx_analogreset <= avmm_writedata[A10_XR_OFFSET_RX_ANA];
+ r_rx_digitalreset <= avmm_writedata[A10_XR_OFFSET_RX_DIG];
+ r_tx_analogreset <= avmm_writedata[A10_XR_OFFSET_TX_ANA];
+ r_tx_digitalreset <= avmm_writedata[A10_XR_OFFSET_TX_DIG];
+ r_rx_analogreset_override <= avmm_writedata[A10_XR_OFFSET_RX_ANA_OVR];
+ r_rx_digitalreset_override <= avmm_writedata[A10_XR_OFFSET_RX_DIG_OVR];
+ r_tx_analogreset_override <= avmm_writedata[A10_XR_OFFSET_TX_ANA_OVR];
+ r_tx_digitalreset_override <= avmm_writedata[A10_XR_OFFSET_TX_DIG_OVR];
+ end
+ end
+
+ end else begin: g_control_reg_dis
+ // assign LTR control signals when control registers are disabled
+ assign rd_set_ltr = RD_UNUSED;
+ assign rd_loopback = RD_UNUSED;
+ assign rd_chnl_reset = RD_UNUSED;
+
+ // pass through control signals
+ assign csr_set_lock_to_ref = (set_rx_locktoref);
+ assign csr_set_lock_to_data = (set_rx_locktodata);
+ assign csr_en_loopback = (serial_loopback);
+ assign csr_rx_analogreset = (rx_analogreset);
+ assign csr_rx_digitalreset = (rx_digitalreset);
+ assign csr_tx_analogreset = (tx_analogreset);
+ assign csr_tx_digitalreset = (tx_digitalreset);
+ end
+endgenerate // End generate g_control_reg
+
+/**********************************************************************/
+// Embedded reconfig registers
+/**********************************************************************/
+generate if(rcfg_emb_strm_enable) begin: en_rcfg_reg
+
+ /**********************************************************************/
+ // Generate registers and wires for the reconfig soft logic
+ /**********************************************************************/
+ reg [rcfg_emb_strm_cfg_sel_width-1:0] r_rcfg_emb_strm_cfg_sel;
+ reg r_rcfg_emb_strm_cfg_load;
+ reg r_rcfg_emb_strm_bcast_en;
+ reg rcfg_emb_strm_cfg_load_lock = 1'b0;
+
+ // readback the embedded reconfig control
+ assign rd_rcfg_emb_ctrl = {r_rcfg_emb_strm_cfg_load, r_rcfg_emb_strm_bcast_en, {(A10_XR_EMBED_RCFG_CFG_SEL_LEN-rcfg_emb_strm_cfg_sel_width){1'b0}}, r_rcfg_emb_strm_cfg_sel};
+ assign rd_rcfg_emb_status = {7'b0, rcfg_emb_strm_busy};
+
+ // assign the output signals to the channel
+ assign rcfg_emb_strm_cfg_sel = r_rcfg_emb_strm_cfg_sel;
+ assign rcfg_emb_strm_cfg_load = r_rcfg_emb_strm_cfg_load;
+ assign rcfg_emb_strm_bcast_en = r_rcfg_emb_strm_bcast_en;
+
+ always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ r_rcfg_emb_strm_cfg_sel <= {rcfg_emb_strm_cfg_sel_width{1'b0}};
+ r_rcfg_emb_strm_cfg_load <= 1'b0;
+ r_rcfg_emb_strm_bcast_en <= 1'b0;
+ rcfg_emb_strm_cfg_load_lock <= 1'b0;
+ end else if(avmm_write && avmm_address == A10_XR_ADDR_EMBED_RCFG_CTRL) begin
+ // Write to this register
+ r_rcfg_emb_strm_cfg_sel <= avmm_writedata[A10_XR_OFFSET_EMBED_RCFG_CFG_SEL +: rcfg_emb_strm_cfg_sel_width ];
+ r_rcfg_emb_strm_cfg_load <= avmm_writedata[A10_XR_OFFSET_EMBED_RCFG_CFG_LOAD];
+ r_rcfg_emb_strm_bcast_en <= avmm_writedata[A10_XR_OFFSET_EMBED_RCFG_BCAST_EN];
+ end else if(rcfg_emb_strm_chan_sel & rcfg_emb_strm_busy & ~rcfg_emb_strm_cfg_load_lock) begin
+ // Reset the cfg_load bit when the streaming has started
+ r_rcfg_emb_strm_cfg_load <= 1'b0;
+ rcfg_emb_strm_cfg_load_lock <= 1'b1;
+ end else if(~rcfg_emb_strm_busy & rcfg_emb_strm_cfg_load_lock)
+ rcfg_emb_strm_cfg_load_lock <= 1'b0;
+ end
+ end else begin: g_rcfg_reg_dis
+ assign rd_rcfg_emb_ctrl = RD_UNUSED;
+ assign rd_rcfg_emb_status = RD_UNUSED;
+ assign rcfg_emb_strm_cfg_sel = 1'b0;
+ assign rcfg_emb_strm_bcast_en = 1'b0;
+ assign rcfg_emb_strm_cfg_load = 1'b0;
+ end
+endgenerate //End generate g_rcfg_reg
+
+/**********************************************************************/
+// PRBS Registers and logic
+/**********************************************************************/
+assign rd_prbs_err = prbs_err;
+assign rd_prbs_bit = prbs_bit;
+generate if(dbg_prbs_soft_logic_enable == 1) begin: g_prbs_reg_en
+
+ /**********************************************************************/
+ // wires for synchronizer and registers for control signals to the PRBS accumulation block
+ /**********************************************************************/
+ wire rx_prbs_err_clr_sync;
+ reg r_prbs_reset;
+ reg r_prbs_snap;
+ reg r_prbs_en;
+
+ /**********************************************************************/
+ // Instantiate Synchronizers and read logic for rx_is_lockedtodata and rx_is_lockedtoref
+ /**********************************************************************/
+ alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 1 ) // two bits, one for locktodata and one for locktoref
+ ) prbs_err_clr_sync (
+ .clk (avmm_clk),
+ .reset (avmm_reset),
+ .d (rx_prbs_err_clr),
+ .q (rx_prbs_err_clr_sync)
+ );
+
+ // assign control signals for the PRBS accumulation logic
+ assign prbs_count_en = r_prbs_en;
+ assign prbs_snap = r_prbs_snap;
+ assign prbs_reset = r_prbs_reset || rx_prbs_err_clr_sync;
+
+ // readback data
+ assign rd_prbs_ctrl[A10_XR_OFFSET_PRBS_EN] = r_prbs_en;
+ assign rd_prbs_ctrl[A10_XR_OFFSET_PRBS_RESET] = r_prbs_reset;
+ assign rd_prbs_ctrl[A10_XR_OFFSET_PRBS_SNAP] = r_prbs_snap;
+ assign rd_prbs_ctrl[A10_XR_OFFSET_PRBS_DONE] = prbs_done;
+ assign rd_prbs_ctrl[A10_XR_OFFSET_PRBS_UNUSED+:A10_XR_PRBS_UNUSED_LEN] = {A10_XR_PRBS_UNUSED_LEN{1'b0}};
+
+ // write prbs ctrl reg
+ always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ r_prbs_en <= 1'b0;
+ r_prbs_reset <= 1'b0;
+ r_prbs_snap <= 1'b0;
+ end else if(avmm_write && avmm_address == A10_XR_ADDR_PRBS_CTRL) begin
+ r_prbs_en <= avmm_writedata[A10_XR_OFFSET_PRBS_EN];
+ r_prbs_reset <= avmm_writedata[A10_XR_OFFSET_PRBS_RESET];
+ r_prbs_snap <= avmm_writedata[A10_XR_OFFSET_PRBS_SNAP];
+ end
+ end
+ end else begin: g_prbs_reg_dis
+ assign prbs_reset = (rx_prbs_err_clr);
+ assign rd_prbs_ctrl = RD_UNUSED;
+ assign prbs_count_en = 1'b0;
+ assign prbs_snap = 1'b0;
+ end
+endgenerate //End generate g_prbs_reg
+
+/**********************************************************************/
+// ODI Registers and logic
+/**********************************************************************/
+assign rd_odi_bit = odi_bit;
+assign rd_odi_err = odi_err;
+generate if(dbg_odi_soft_logic_enable == 1) begin: g_odi_reg_en
+
+ /**********************************************************************/
+ // wires for synchronizer and registers for control signals to the odi accumulation block
+ /**********************************************************************/
+ reg r_odi_reset;
+ reg r_odi_snap;
+ reg r_odi_en;
+
+ // assign control signals for the ODI accumulation logic
+ assign odi_count_en = r_odi_en;
+ assign odi_snap = r_odi_snap;
+ assign odi_reset = r_odi_reset;
+
+ // readback data
+ assign rd_odi_ctrl[A10_XR_OFFSET_ODI_EN] = r_odi_en;
+ assign rd_odi_ctrl[A10_XR_OFFSET_ODI_RESET] = r_odi_reset;
+ assign rd_odi_ctrl[A10_XR_OFFSET_ODI_SNAP] = r_odi_snap;
+ assign rd_odi_ctrl[A10_XR_OFFSET_ODI_DONE] = odi_done;
+ assign rd_odi_ctrl[A10_XR_OFFSET_ODI_UNUSED+:A10_XR_ODI_UNUSED_LEN] = {A10_XR_ODI_UNUSED_LEN{1'b0}};
+
+ // write ODI ctrl reg
+ always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ r_odi_en <= 1'b0;
+ r_odi_reset <= 1'b0;
+ r_odi_snap <= 1'b0;
+ end else if(avmm_write && avmm_address == A10_XR_ADDR_ODI_CTRL) begin
+ r_odi_en <= avmm_writedata[A10_XR_OFFSET_ODI_EN];
+ r_odi_reset <= avmm_writedata[A10_XR_OFFSET_ODI_RESET];
+ r_odi_snap <= avmm_writedata[A10_XR_OFFSET_ODI_SNAP];
+ end
+ end
+ end else begin: g_odi_reg_dis
+ assign rd_odi_ctrl = RD_UNUSED;
+ assign odi_reset = 1'b0;
+ assign odi_count_en = 1'b0;
+ assign odi_snap = 1'b0;
+ end
+endgenerate //End generate g_odi_reg
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_odi_accel.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_odi_accel.sv
new file mode 100644
index 0000000000000000000000000000000000000000..d7936ecbb1d934f2604cb649eaf49b1175717ff8
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_odi_accel.sv
@@ -0,0 +1,381 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+module alt_xcvr_native_odi_accel #(
+ parameter DATA_WIDTH = 32
+) (
+ input avmm_clk,
+ input avmm_reset,
+
+ // AVMM signals to the transceiver
+ output reg odi_read,
+ output reg odi_write,
+ output reg [9:0] odi_address,
+ output reg [DATA_WIDTH-1:0] odi_writedata,
+ input [7:0] odi_readdata,
+ input odi_waitrequest,
+
+ // Control signals from CSR
+ input odi_count_en,
+ input odi_snap,
+ input odi_reset,
+
+ // Status signals from ODI
+ output odi_done,
+ output reg [49:0] odi_bit_count,
+ output reg [49:0] odi_err_count
+);
+
+/**********************************************************************/
+// States for the Statemachine
+// General Sequence: idle > odi_start_0 > odi_rstn_1 > odi_rst_0 > odi_start_1 > odi_start_0 > chck_done > read_bits > read_errs
+/**********************************************************************/
+localparam SM_ODI_ACCEL_IDLE = 5'd0;
+localparam SM_ODI_ACCEL_RD_OFST_169 = 5'd1;
+localparam SM_ODI_ACCEL_WR_START_0 = 5'd2;
+localparam SM_ODI_ACCEL_WR_RESET_1 = 5'd3;
+localparam SM_ODI_ACCEL_WR_RESET_0 = 5'd4;
+localparam SM_ODI_ACCEL_WR_START_1 = 5'd5;
+localparam SM_ODI_ACCEL_WR_START_DISABLE= 5'd6;
+localparam SM_ODI_ACCEL_WAIT = 5'd7;
+localparam SM_ODI_ACCEL_RD_ADPT_STAT_BUS= 5'd8;
+localparam SM_ODI_ACCEL_RD_ADPT_STATUS = 5'd9;
+localparam SM_ODI_ACCEL_RD_ADPT_ERR_1 = 5'd10;
+localparam SM_ODI_ACCEL_RD_ADPT_ERR_2 = 5'd11;
+localparam SM_ODI_ACCEL_RD_ADPT_BIT_1 = 5'd12;
+localparam SM_ODI_ACCEL_RD_ADPT_BIT_2 = 5'd13;
+localparam SM_ODI_ACCEL_FINAL_ACCUM = 5'd14;
+
+
+/**********************************************************************/
+// Local wires and registers
+/**********************************************************************/
+reg [4:0] sm_odi_state;
+reg [4:0] sm_odi_next;
+reg [5:0] timeout;
+reg [7:0] lcl_odi_read;
+reg [15:0] adpt_bits;
+reg [15:0] adpt_errs;
+reg [50:0] odi_bit_accumulator;
+reg [50:0] odi_err_accumulator;
+
+
+/**********************************************************************/
+// Statemachine
+/**********************************************************************/
+always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ sm_odi_state <= SM_ODI_ACCEL_IDLE;
+ odi_read <= 1'b0;
+ odi_write <= 1'b0;
+ odi_address <= 10'b0;
+ odi_writedata <= {DATA_WIDTH{1'b0}};
+ adpt_bits <= 16'b0;
+ adpt_errs <= 16'b0;
+ end else if(odi_reset) begin
+ sm_odi_state <= SM_ODI_ACCEL_IDLE;
+ odi_read <= 1'b0;
+ odi_write <= 1'b0;
+ odi_address <= 10'b0;
+ odi_writedata <= {DATA_WIDTH{1'b0}};
+ adpt_bits <= 16'b0;
+ adpt_errs <= 16'b0;
+ end else begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b0;
+ odi_address <= 10'b0;
+ odi_writedata <= {DATA_WIDTH{1'b0}};
+ case(sm_odi_state)
+ SM_ODI_ACCEL_IDLE:
+ begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b0;
+ adpt_bits <= 16'b0;
+ adpt_errs <= 16'b0;
+
+ if(odi_count_en == 1'b1) begin
+ sm_odi_state <= SM_ODI_ACCEL_RD_OFST_169;
+ end
+ end
+
+ SM_ODI_ACCEL_RD_OFST_169:
+ begin
+ if(odi_waitrequest == 1'b0 && odi_read == 1'b1) begin
+ adpt_bits <= 16'b0;
+ adpt_errs <= 16'b0;
+
+ odi_read <= 1'b0;
+ odi_write <= 1'b1;
+ odi_address <= 10'h169;
+ odi_writedata <= {odi_readdata[7:1],1'b0};
+ lcl_odi_read <= odi_readdata;
+
+ sm_odi_state <= SM_ODI_ACCEL_WR_RESET_0;
+ end else begin
+
+ odi_read <= 1'b1;
+ odi_write <= 1'b0;
+ odi_address <= 10'h169;
+
+ sm_odi_state <= SM_ODI_ACCEL_RD_OFST_169;
+ end
+ end
+
+ SM_ODI_ACCEL_WR_RESET_0:
+ begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b1;
+ odi_address <= 10'h169;
+ odi_writedata <= {lcl_odi_read[7:2],2'b00};
+
+ sm_odi_state <= SM_ODI_ACCEL_WR_RESET_1;
+ end
+
+ SM_ODI_ACCEL_WR_RESET_1:
+ begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b1;
+ odi_address <= 10'h169;
+ odi_writedata <= {lcl_odi_read[7:2],2'b10};
+
+ sm_odi_state <= SM_ODI_ACCEL_WR_START_1;
+ end
+
+ SM_ODI_ACCEL_WR_START_1:
+ begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b1;
+ odi_address <= 10'h169;
+ odi_writedata <= {lcl_odi_read[7:2],2'b11};
+
+ sm_odi_state <= SM_ODI_ACCEL_WR_START_DISABLE;
+ end
+
+ SM_ODI_ACCEL_WR_START_DISABLE:
+ begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b1;
+ odi_address <= 10'h169;
+ odi_writedata <= {lcl_odi_read[7:2],2'b10};
+
+ sm_odi_state <= SM_ODI_ACCEL_WAIT;
+ sm_odi_next <= SM_ODI_ACCEL_RD_ADPT_STAT_BUS;
+ end
+ SM_ODI_ACCEL_WAIT:
+ begin
+ odi_write <= 1'b0;
+ odi_read <= 1'b0;
+ odi_address <= odi_address;
+ odi_writedata <= odi_writedata;
+ if(timeout[4] & timeout[3]) begin
+ sm_odi_state <= sm_odi_next;
+ end else begin
+ sm_odi_state <= SM_ODI_ACCEL_WAIT;
+ end
+ end
+
+ SM_ODI_ACCEL_RD_ADPT_STAT_BUS:
+ begin
+
+ if(odi_waitrequest == 1'b0 && odi_read == 1'b1) begin // TODO
+ odi_read <= 1'b0;
+ odi_write <= 1'b1;
+ odi_address <= 10'h14c;
+ odi_writedata <= {odi_readdata[7],7'h2D}; // TODO - mask
+ lcl_odi_read <= odi_readdata;
+
+ sm_odi_state <= SM_ODI_ACCEL_WAIT;
+ sm_odi_next <= SM_ODI_ACCEL_RD_ADPT_STATUS;
+ end else begin
+ odi_read <= 1'b1;
+ odi_write <= 1'b0;
+ odi_address <= 10'h14c;
+ odi_writedata <= 8'h00;
+
+ sm_odi_state <= SM_ODI_ACCEL_RD_ADPT_STAT_BUS;
+ end
+ end
+
+ SM_ODI_ACCEL_RD_ADPT_STATUS:
+ begin
+
+ if(odi_waitrequest == 1'b0 && odi_read == 1'b1) begin // TODO
+ if(odi_readdata[1] == 1'b1) begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b1;
+ odi_address <= 10'h14c;
+ odi_writedata <= {lcl_odi_read[7],7'h2C};
+
+ sm_odi_state <= SM_ODI_ACCEL_WAIT;
+ sm_odi_next <= SM_ODI_ACCEL_RD_ADPT_ERR_1;
+ end else begin
+ sm_odi_state <= SM_ODI_ACCEL_WAIT;
+ end
+ end else begin
+ odi_read <= 1'b1;
+ odi_write <= 1'b0;
+ odi_address <= 10'h177;
+ odi_writedata <= 8'h0;
+ sm_odi_state <= SM_ODI_ACCEL_RD_ADPT_STATUS;
+ end
+ end
+
+ SM_ODI_ACCEL_RD_ADPT_ERR_1:
+ begin
+
+ if(odi_waitrequest == 1'b0 && odi_read == 1'b1) begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b1;
+ odi_address <= 10'h14c;
+ odi_writedata <= {lcl_odi_read[7],7'h2B};
+
+ sm_odi_state <= SM_ODI_ACCEL_WAIT;
+ sm_odi_next <= SM_ODI_ACCEL_RD_ADPT_ERR_2;
+
+ adpt_errs[15:8] <= odi_readdata;
+ end else begin
+ odi_read <= 1'b1;
+ odi_write <= 1'b0;
+ odi_address <= 10'h177;
+ odi_writedata <= 8'h0;
+ sm_odi_state <= SM_ODI_ACCEL_RD_ADPT_ERR_1;
+ end
+ end
+
+ SM_ODI_ACCEL_RD_ADPT_ERR_2:
+ begin
+
+ if(odi_waitrequest == 1'b0 && odi_read == 1'b1) begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b1;
+ odi_address <= 10'h14c;
+ odi_writedata <= {lcl_odi_read[7],7'h2A};
+
+ sm_odi_state <= SM_ODI_ACCEL_WAIT;
+ sm_odi_next <= SM_ODI_ACCEL_RD_ADPT_BIT_1;
+
+ adpt_errs[7:0] <= odi_readdata;
+ end else begin
+ odi_read <= 1'b1;
+ odi_write <= 1'b0;
+ odi_address <= 10'h177;
+ odi_writedata <= 8'h0;
+ sm_odi_state <= SM_ODI_ACCEL_RD_ADPT_ERR_2;
+ end
+ end
+
+ SM_ODI_ACCEL_RD_ADPT_BIT_1:
+ begin
+
+ if(odi_waitrequest == 1'b0 && odi_read == 1'b1) begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b1;
+ odi_address <= 10'h14c;
+ odi_writedata <= {lcl_odi_read[7],7'h29};
+
+ sm_odi_state <= SM_ODI_ACCEL_WAIT;
+ sm_odi_next <= SM_ODI_ACCEL_RD_ADPT_BIT_2;
+
+ adpt_bits[15:8] <= odi_readdata;
+ end else begin
+ odi_read <= 1'b1;
+ odi_write <= 1'b0;
+ odi_address <= 10'h177;
+ odi_writedata <= 8'h0;
+ sm_odi_state <= SM_ODI_ACCEL_RD_ADPT_BIT_1;
+ end
+ end
+
+ SM_ODI_ACCEL_RD_ADPT_BIT_2:
+ begin
+ odi_write <= 1'b0;
+ odi_address <= 10'h177;
+ odi_writedata <= 8'h0;
+
+ if(odi_waitrequest == 1'b0 && odi_read == 1'b1) begin
+ odi_read <= 1'b0;
+ sm_odi_state <= SM_ODI_ACCEL_FINAL_ACCUM;
+ adpt_bits[7:0] <= odi_readdata;
+ end else begin
+ odi_read <= 1'b1;
+ sm_odi_state <= SM_ODI_ACCEL_RD_ADPT_BIT_2;
+ end
+ end
+
+ SM_ODI_ACCEL_FINAL_ACCUM:
+ begin
+ if(odi_count_en == 1'b1) begin
+ sm_odi_state <= SM_ODI_ACCEL_RD_OFST_169;
+ end else begin
+ sm_odi_state <= SM_ODI_ACCEL_IDLE;
+ end
+ end
+
+ default:
+ begin
+ odi_read <= 1'b0;
+ odi_write <= 1'b0;
+ odi_address <= 10'b0;
+ odi_writedata <= {DATA_WIDTH{1'b0}};
+ end
+ endcase
+ end
+end
+
+// Time between polling the odi_done bit to read out the accumualted read/write
+always@(posedge avmm_clk) begin
+ if(sm_odi_state == SM_ODI_ACCEL_WAIT) begin
+ timeout <= timeout + 1'b1;
+ end else begin
+ timeout <= 5'b0;
+ end
+end
+
+
+/**********************************************************************/
+// Accumulate bit and error count!
+/**********************************************************************/
+assign odi_done = odi_bit_accumulator[50];
+always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset == 1'b1) begin
+ odi_bit_count <= 50'b0;
+ odi_err_count <= 50'b0;
+ odi_bit_accumulator <= 51'b0;
+ odi_err_accumulator <= 51'b0;
+ end else if(odi_reset == 1'b1) begin
+ odi_bit_count <= 50'b0;
+ odi_err_count <= 50'b0;
+ odi_bit_accumulator <= 51'b0;
+ odi_err_accumulator <= 51'b0;
+ end else begin
+
+ if(odi_snap) begin
+ odi_bit_count <= odi_bit_accumulator[49:0];
+ odi_err_count <= odi_err_accumulator[49:0];
+ end
+
+ if(sm_odi_state == SM_ODI_ACCEL_FINAL_ACCUM) begin
+ if(odi_done == 1'b1) begin
+ odi_bit_accumulator <= odi_bit_accumulator;
+ odi_err_accumulator <= odi_err_accumulator;
+ end else begin
+ odi_bit_accumulator <= odi_bit_accumulator + adpt_bits;
+ odi_err_accumulator <= odi_err_accumulator + adpt_errs;
+ end
+ end
+ end
+end
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_pipe_retry.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_pipe_retry.sv
new file mode 100644
index 0000000000000000000000000000000000000000..ec633c060ffc58234249f55864eb53d130e13f58
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_pipe_retry.sv
@@ -0,0 +1,259 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ps/1ps
+module alt_xcvr_native_pipe_retry (
+ input pipe_pclk,
+ input tx_digitalreset,
+ input [1:0] pld_rate,
+ input [19:0] pld_testbus,
+ output reg [1:0] rate_retry
+);
+
+/*********************************************************************************/
+// Set localparams for configuring index bits as well as synchronizing the reset
+/*********************************************************************************/
+// if we use a timeout of 127, then the delay for a single attempt is 508ns
+// For an attempt + a restore, its 1us, which corresponds to 1.5us to attempt
+// both a posedge and a negedge launch attempt. The full retry time before
+// a recycle is 2us.
+
+// Timeout value = 2^(lcl_rate_switch_counter_width-2)-1 = 2^7-1 = 127
+localparam lcl_rate_switch_counter_width = 9;
+localparam lcl_index_switch_clock = lcl_rate_switch_counter_width-1;
+localparam lcl_index_restory_pre_rate_sw = lcl_rate_switch_counter_width-2;
+localparam lcl_index_max_counter_timeout = lcl_rate_switch_counter_width-3;
+
+// Register for counter
+reg [lcl_rate_switch_counter_width-1:0] retry_counter;
+
+// Synchronize tx_digitalreset
+wire hv_pipe_clk;
+wire tx_digitalreset_pclk_sync;
+wire tx_digitalresetn_hv_sync;
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 1 ),
+ .SLOW_CLOCK ( 0 ),
+ .INIT_VALUE ( 1 )
+) tx_digitalreset_pclk_inst (
+ .clk (pipe_pclk),
+ .reset (tx_digitalreset),
+ .d (1'b0),
+ .q (tx_digitalreset_pclk_sync)
+);
+
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 1 ),
+ .SLOW_CLOCK ( 0 ),
+ .INIT_VALUE ( 0 )
+) tx_digitalreset_hv_inst (
+ .clk (hv_pipe_clk),
+ .reset (tx_digitalreset),
+ .d (1'b1),
+ .q (tx_digitalresetn_hv_sync)
+);
+
+
+/*********************************************************************************/
+// Take the asynchronous inputs of Rate from the testbus and the user.
+/*********************************************************************************/
+// Delcare local wires and registers
+//reg [2:0] pld_rate_vec_timeout;
+reg [3:0] pma_pld_rate_sync;
+reg [3:0] pld_rate_sync;
+wire [1:0] pma_pld_rate_r;
+wire [1:0] pld_rate_restore;
+wire [1:0] pld_rate_r;
+
+// Assign the buses to the second stage of the reset registers;
+assign pma_pld_rate_r = pma_pld_rate_sync[3:2];
+assign pld_rate_restore = pld_rate_sync[3:2];
+assign pld_rate_r = pld_rate_sync[1:0];
+
+// Set a 2-stage synchronizer chain to minimize resolve spy-glass related issues. Since
+// the If the pld_rate from the core is asynchronous, then run a counter when the rate
+// changes to resolve any issues with bit-skew.
+always@(posedge pipe_pclk or posedge tx_digitalreset_pclk_sync) begin
+ if(tx_digitalreset_pclk_sync) begin
+ pma_pld_rate_sync <= 4'b0;
+ pld_rate_sync <= 4'b0;
+
+ end else begin
+ // 2-bit synchronizer for the testbus
+ pma_pld_rate_sync[1:0] <= pld_testbus[9:8];
+ pma_pld_rate_sync[3:2] <= pma_pld_rate_sync[1:0];
+
+ // 2-bitsynchrnoizer for the user pld_rate
+ pld_rate_sync[1:0] <= pld_rate;
+
+ // when the testbus matches the incoming rate request, update the register.
+ if( (pma_pld_rate_r == pld_rate_r) && (&retry_counter[lcl_index_max_counter_timeout:2]) ) begin
+ pld_rate_sync[3:2] <= pld_rate_sync[1:0];
+ end
+ end
+end
+
+
+/*********************************************************************************/
+// Determine if a retry may be required.
+/*********************************************************************************/
+// Declare local wires
+wire lcl_require_retry;
+reg require_retry;
+
+// A retry is required when the transceiver channel's current rate differes from the
+// requested rate from the core.
+assign lcl_require_retry = (pld_rate_r != pld_rate_restore);
+always@(posedge pipe_pclk) begin
+ require_retry <= lcl_require_retry;
+end
+
+
+/*********************************************************************************/
+// Run the timeout counter to track attempts rate and clock edge attempts
+/*********************************************************************************/
+// Declare local registers and wires
+wire switch_clock_edge;
+wire restore_pre_rate_sw;
+
+// Assign the wires switch_clock_rate and restor_pre_rate_sw for readability purposes.
+assign switch_clock_edge = retry_counter[lcl_index_switch_clock];
+assign restore_pre_rate_sw = retry_counter[lcl_index_restory_pre_rate_sw];
+
+// This block essentially runs two counters: a timeout to sample the ASN_TESTBUS for pcie_rate
+// and rate attmpt counter to track of the current attempt. For efficiency and readability
+// A single physical counter is uses. The upper two bits are the rate attempt counter, and
+// the lower 7 bits compose of the timeout counter
+//
+// Timeout Counter = retry_counter[6:0]
+// Rate Attempt Counter = {switch_clock_edge, switch_clock_edge} = retry_counter[8:7]
+//
+// There are 4 potential combinations for the rate attempt counter (retry_counter[8:7]
+// (0)Posedge clock, (0)requested rate switch (encoding: 0 0)
+// (0)Posedge clock, (1)restore pre-rate switch rate (encoding: 0 1)
+// (1)negedge clock, (0)requested rate switch (encoding: 1 0)
+// (1)negedge clock, (1)restory pre-rate switch rate (encoding: 1 1)
+always@(posedge pipe_pclk or posedge tx_digitalreset_pclk_sync) begin
+ if(tx_digitalreset_pclk_sync) begin
+ retry_counter <= {lcl_rate_switch_counter_width{1'b0}};
+
+ end else begin // end if reset condition
+ if(require_retry) begin
+ retry_counter <= retry_counter + 1'b1;
+
+ end else begin // end if require_retry
+ retry_counter <= {lcl_rate_switch_counter_width{1'b0}};
+
+ end // end else require_retry
+ end // end else reset condition
+end // end always block
+
+
+/*********************************************************************************/
+// Alternate the PCI Rate between transceiver current rate and requested rate
+/*********************************************************************************/
+// Declare local wires
+wire [1:0] retry_attempt;
+
+// Assign the PCIe rate request to the transceiver. Alternates between the transceiver
+// rate and the requested rate from the core. Every timeout from the counter, the rate
+// will either attempt to downtrain/uptrain or restore the current transceiver rate
+assign retry_attempt = (restore_pre_rate_sw == 1'b1) ? pld_rate_restore : pld_rate_r;
+
+
+/*********************************************************************************/
+// Buffer the rate request as well as the clock switch on the PCLK
+/*********************************************************************************/
+// Declare local wires and registers
+wire rate_change_sync;
+wire update_pld_rate_output;
+reg rate_change;
+reg rate_change_edge;
+reg restore_pre_rate_sw_buf;
+reg require_retry_buf;
+reg [1:0] hv_sync_vec_pipe_rate;
+
+// Buffer the rate switch request as well as the clock edge switch on the pclk domain
+always@(posedge pipe_pclk or posedge tx_digitalreset_pclk_sync) begin
+ if(tx_digitalreset_pclk_sync) begin
+ hv_sync_vec_pipe_rate <= 2'b0;
+ require_retry_buf <= 1'b0;
+ restore_pre_rate_sw_buf <= 1'b0;
+ rate_change <= 1'b0;
+ end else begin // end if tx_digitalreset_pclk_sync
+
+ hv_sync_vec_pipe_rate <= retry_attempt;
+ restore_pre_rate_sw_buf <= restore_pre_rate_sw;
+ require_retry_buf <= require_retry;
+ rate_change <= ((restore_pre_rate_sw ^ restore_pre_rate_sw_buf) || (require_retry & ~require_retry_buf)) ? ~rate_change : rate_change;
+ end // end else tx_digitalreseet_sync
+end
+
+
+/*********************************************************************************/
+// Switch clock edge and rate request update
+/*********************************************************************************/
+// Based upon the clock edge requirement, swap the unateness
+assign hv_pipe_clk = (switch_clock_edge == 1'b1) ? ~pipe_pclk : pipe_pclk;
+
+// Since the rate_sw_req is technically asynchronous due to the different clock networks,
+// rate_attempt is on pclk and hv_sync_retry_rate is on HV - after the clock edge switch,
+// the signal needs to be synchornized into the HV clock domain
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 1 ),
+ .SLOW_CLOCK ( 0 ),
+ .INIT_VALUE ( 0 )
+) rate_sw_sync_inst (
+ .clk (hv_pipe_clk),
+ .reset (1'b0),
+ .d (rate_change),
+ .q (rate_change_sync)
+);
+
+// After the rate_sw_req is synchronized (3-clock cycles later) into the hv_pipe_clk domain,
+// the hv_sync_retry_rate can be updated. This register will recycle its value until the
+// value of rate_sw_req_sync is 1'b1. After hv_sync_retry_rate is updated, the rate_sw_req
+// will go to 1'b1, which will take 3-cycles to synchronize, at which point hv_sync_retry_rate
+// will recycle its current value.
+//
+// This offers a 3-cycle window for the value of hv_sync_vec_pipe_rate to stabilize at the input
+// to hv_sync_retry_rate.
+assign update_pld_rate_output = (rate_change_edge ^ rate_change_sync);
+always@(posedge hv_pipe_clk) begin
+ rate_change_edge <= rate_change_sync;
+end
+
+(* altera_attribute = " -name MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER 2 " *)
+dffe hv_sync_retry_rate_r0 (
+ .d (hv_sync_vec_pipe_rate[0]),
+ .clk (hv_pipe_clk),
+ .clrn (tx_digitalresetn_hv_sync),
+ .prn (1'b1),
+ .ena (update_pld_rate_output),
+ .q (rate_retry[0])
+);
+
+(* altera_attribute = " -name MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER 2 " *)
+dffe hv_sync_retry_rate_r1 (
+ .d (hv_sync_vec_pipe_rate[1]),
+ .clk (hv_pipe_clk),
+ .clrn (tx_digitalresetn_hv_sync),
+ .prn (1'b1),
+ .ena (update_pld_rate_output),
+ .q (rate_retry[1])
+);
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_prbs_accum.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_prbs_accum.sv
new file mode 100644
index 0000000000000000000000000000000000000000..4bc3e515619a8e3660f2a14d843fb25f9773cb4e
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_prbs_accum.sv
@@ -0,0 +1,244 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+module alt_xcvr_native_prbs_accum (
+ input avmm_clk,
+ input avmm_reset,
+
+ // Control signals from CSR
+ input prbs_reset,
+ input prbs_snapshot,
+ input prbs_counter_en,
+
+ // Status signals from PRBS
+ output prbs_done_sync,
+ output [49:0] prbs_err_count,
+ output [49:0] prbs_bit_count,
+
+ // Signals from the transceiver
+ input rx_clkout,
+ input prbs_err_signal,
+ input prbs_done_signal
+);
+
+/**********************************************************************/
+// wires for synchronizers
+/**********************************************************************/
+wire avmm_reset_sync;
+wire prbs_reset_sync;
+wire prbs_err_rx_sync;
+wire prbs_done_rx_sync;
+wire avmm_rx_cnt_edge_sync;
+
+/**********************************************************************/
+// Synchronizer for avmm_reset to rx_clkout
+/**********************************************************************/
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 1 ),
+ .INIT_VALUE ( 1 )
+) rx_clk_reset_sync (
+ .clk (rx_clkout),
+ .reset (avmm_reset),
+ .d (1'b0),
+ .q (avmm_reset_sync)
+);
+
+/**********************************************************************/
+// Synchronizer for prbs_reset to rx_clkout
+/**********************************************************************/
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 1 ),
+ .INIT_VALUE ( 1 )
+) rx_clk_prbs_reset_sync (
+ .clk (rx_clkout),
+ .reset (prbs_reset),
+ .d (1'b0),
+ .q (prbs_reset_sync)
+);
+
+/**********************************************************************/
+// Synchronizer for prbs_err to rx_clkout
+/**********************************************************************/
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 2 ),
+ .WIDTH ( 1 ),
+ .INIT_VALUE ( 0 )
+) rx_clk_prbs_err_sync (
+ .clk (rx_clkout),
+ .reset (avmm_reset_sync),
+ .d (prbs_err_signal),
+ .q (prbs_err_rx_sync)
+);
+
+/**********************************************************************/
+// Synchronizer for prbs_done to rx_clkout
+/**********************************************************************/
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 2 ),
+ .WIDTH ( 1 ),
+ .INIT_VALUE ( 0 )
+) rx_clk_prbs_done_sync (
+ .clk (rx_clkout),
+ .reset (avmm_reset_sync),
+ .d (prbs_done_signal),
+ .q (prbs_done_rx_sync)
+);
+
+/**********************************************************************/
+// wires and registers
+/**********************************************************************/
+wire rx_prbs_err_edge;
+wire rx_prbs_cnt_edge;
+wire avmm_prbs_cnt_edge;
+reg rx_prbs_cnt_edge_reg;
+reg rx_prbs_err_edge_reg;
+reg avmm_prbs_cnt_edge_reg;
+reg rx_error_high;
+reg [3:0] rx_consecutive_error;
+reg [7:0] rx_prbs_bit_count;
+reg [7:0] rx_prbs_err_count;
+reg [7:0] rx_prbs_err_snapshot;
+reg [49:0] avmm_prbs_err_count;
+reg [49:0] avmm_prbs_bit_count;
+reg [49:0] avmm_prbs_err_snapshot;
+reg [49:0] avmm_prbs_bit_snapshot;
+
+/**********************************************************************/
+// Logic on rx_clkout for accumulating bits and errors
+/**********************************************************************/
+assign rx_prbs_err_edge = (~rx_prbs_err_edge_reg && prbs_err_rx_sync);
+assign rx_prbs_cnt_edge = (rx_prbs_cnt_edge_reg ^ rx_prbs_bit_count[7]);
+always@(posedge rx_clkout or posedge avmm_reset_sync) begin
+ if(avmm_reset_sync) begin
+ rx_prbs_err_edge_reg <= 1'b0;
+ rx_prbs_cnt_edge_reg <= 1'b0;
+ rx_prbs_bit_count <= 8'b0;
+ rx_prbs_err_count <= 8'b0;
+ rx_prbs_err_snapshot <= 8'b0;
+ rx_consecutive_error <= 4'b0;
+ rx_error_high <= 1'b0;
+ end else if (prbs_reset_sync == 1'b1) begin
+ rx_prbs_err_edge_reg <= 1'b0;
+ rx_prbs_cnt_edge_reg <= 1'b0;
+ rx_prbs_bit_count <= 8'b0;
+ rx_prbs_err_count <= 8'b0;
+ rx_prbs_err_snapshot <= 8'b0;
+ rx_consecutive_error <= 4'b0;
+ rx_error_high <= 1'b0;
+ end else if (prbs_done_rx_sync == 1'b1) begin
+ // prbs error edge
+ rx_prbs_err_edge_reg <= prbs_err_rx_sync;
+
+ // prbs count edge
+ rx_prbs_cnt_edge_reg <= rx_prbs_bit_count[7];
+
+ // If the error signal is high for more than 7 cycles, constantly count errors
+ if(prbs_err_rx_sync == 1'b1) begin
+ if(&rx_consecutive_error) begin
+ rx_consecutive_error <= rx_consecutive_error;
+ end else begin
+ rx_consecutive_error <= rx_consecutive_error + 1'b1;
+ end
+ end else begin
+ rx_consecutive_error <= 4'b0;
+ end
+
+ rx_error_high <= (&rx_consecutive_error);
+
+ // error and bit accumulation
+ rx_prbs_bit_count <= rx_prbs_bit_count + 1'b1;
+ rx_prbs_err_count <= (rx_prbs_cnt_edge) ? {7'b0, rx_prbs_err_edge} : (rx_prbs_err_count + (rx_prbs_err_edge || rx_error_high));
+ rx_prbs_err_snapshot <= (rx_prbs_cnt_edge) ? rx_prbs_err_count : rx_prbs_err_snapshot;
+ end
+end
+
+/**********************************************************************/
+// Synchronizer for prbs_done to avmm_clock
+/**********************************************************************/
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 1 )
+) avmm_clk_prbs_done_sync (
+ .clk (avmm_clk),
+ .reset (avmm_reset),
+ .d (prbs_done_signal),
+ .q (prbs_done_sync)
+);
+
+/**********************************************************************/
+// Synchronizer for bit_count edge to avmm_clock
+/**********************************************************************/
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 1 )
+) avmm_clk_bit_count_edge (
+ .clk (avmm_clk),
+ .reset (avmm_reset),
+ .d (rx_prbs_cnt_edge_reg),
+ .q (avmm_rx_cnt_edge_sync)
+);
+
+
+/**********************************************************************/
+// Logic for overall bit and error count in avmm_clk
+/**********************************************************************/
+assign prbs_err_count = avmm_prbs_err_snapshot;
+assign prbs_bit_count = avmm_prbs_bit_snapshot;
+assign avmm_prbs_cnt_edge = (avmm_prbs_cnt_edge_reg ^ avmm_rx_cnt_edge_sync);
+always@(posedge avmm_clk or posedge avmm_reset) begin
+ if(avmm_reset) begin
+ avmm_prbs_bit_count <= 50'b0;
+ avmm_prbs_err_count <= 50'b0;
+ avmm_prbs_bit_snapshot <= 50'b0;
+ avmm_prbs_err_snapshot <= 50'b0;
+ avmm_prbs_cnt_edge_reg <= 1'b0;
+ end else if(prbs_reset) begin
+ avmm_prbs_bit_count <= 50'b0;
+ avmm_prbs_err_count <= 50'b0;
+ avmm_prbs_bit_snapshot <= 50'b0;
+ avmm_prbs_err_snapshot <= 50'b0;
+ avmm_prbs_cnt_edge_reg <= 1'b0;
+ end else if(prbs_counter_en) begin
+ avmm_prbs_cnt_edge_reg <= avmm_rx_cnt_edge_sync;
+
+ // on an edge of prbs count, accumulate the number of errors and bits
+ if(avmm_prbs_cnt_edge) begin
+ avmm_prbs_bit_count <= avmm_prbs_bit_count + 8'd128;
+ avmm_prbs_err_count <= avmm_prbs_err_count + rx_prbs_err_snapshot;
+ end else begin
+ avmm_prbs_bit_count <= avmm_prbs_bit_count;
+ avmm_prbs_err_count <= avmm_prbs_err_count;
+ end
+
+ // on a snapshot signal, capture the bit and error count to keep them in sync with each other
+ if(prbs_snapshot) begin
+ avmm_prbs_bit_snapshot <= avmm_prbs_bit_count;
+ avmm_prbs_err_snapshot <= avmm_prbs_err_count;
+ end else begin
+ avmm_prbs_bit_snapshot <= avmm_prbs_bit_snapshot;
+ avmm_prbs_err_snapshot <= avmm_prbs_err_snapshot;
+ end
+ end else begin
+ avmm_prbs_bit_count <= avmm_prbs_bit_count;
+ avmm_prbs_err_count <= avmm_prbs_err_count;
+ avmm_prbs_bit_snapshot <= avmm_prbs_bit_snapshot;
+ avmm_prbs_err_snapshot <= avmm_prbs_err_snapshot;
+ avmm_prbs_cnt_edge_reg <= avmm_prbs_cnt_edge_reg;
+ end
+end
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_rcfg_arb.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_rcfg_arb.sv
new file mode 100644
index 0000000000000000000000000000000000000000..0926724e6cc0d9fac1b8752351b5f6d32f6ecdc7
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_rcfg_arb.sv
@@ -0,0 +1,137 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+module alt_xcvr_native_rcfg_arb #(
+ parameter total_masters = 4,
+ parameter channels = 1,
+ parameter address_width = 10,
+ parameter data_width = 32
+) (
+ // Basic AVMM inputs
+ input [channels-1:0] reconfig_clk,
+ input [channels-1:0] reconfig_reset,
+
+ // User AVMM input
+ input [channels-1:0] user_read,
+ input [channels-1:0] user_write,
+ input [channels*address_width-1:0] user_address,
+ input [channels*data_width-1:0] user_writedata,
+ input [channels-1:0] user_read_write,
+ output [channels-1:0] user_waitrequest,
+
+ // Reconfig Steamer AVMM input
+ input [channels-1:0] strm_read,
+ input [channels-1:0] strm_write,
+ input [channels*address_width-1:0] strm_address,
+ input [channels*data_width-1:0] strm_writedata,
+ input [channels-1:0] strm_read_write,
+ output [channels-1:0] strm_waitrequest,
+
+ // ODI AVMM input
+ input [channels-1:0] odi_read,
+ input [channels-1:0] odi_write,
+ input [channels*address_width-1:0] odi_address,
+ input [channels*data_width-1:0] odi_writedata,
+ input [channels-1:0] odi_read_write,
+ output [channels-1:0] odi_waitrequest,
+
+ // ADME AVMM input
+ input [channels-1:0] jtag_read,
+ input [channels-1:0] jtag_write,
+ input [channels*address_width-1:0] jtag_address,
+ input [channels*data_width-1:0] jtag_writedata,
+ input [channels-1:0] jtag_read_write,
+ output [channels-1:0] jtag_waitrequest,
+
+ // PCIe DFE IP
+ input [channels-1:0] pcie_dfe_read,
+ input [channels-1:0] pcie_dfe_write,
+ input [channels*address_width-1:0] pcie_dfe_address,
+ input [channels*data_width-1:0] pcie_dfe_writedata,
+ input [channels-1:0] pcie_dfe_read_write,
+ output [channels-1:0] pcie_dfe_waitrequest,
+
+ // AVMM output the channel and the CSR
+ input [channels-1:0] avmm_waitrequest,
+ output [channels-1:0] avmm_read,
+ output [channels-1:0] avmm_write,
+ output [channels*address_width-1:0] avmm_address,
+ output [channels*data_width-1:0] avmm_writedata
+);
+
+// General wires
+wire [channels*total_masters-1:0] grant;
+wire [channels-1:0] strm_grants;
+wire [channels-1:0] user_read_write_lcl;
+
+// Variables for the generate loops
+genvar ig; // For bus widths
+genvar jg; // For Channels
+generate for(jg=0;jg<channels;jg=jg+1) begin: g_arb
+
+ /*********************************************************************/
+ // case: 309705
+ // Simulation fix. When the user inputs drive x at the beginning of simulation,
+ // then even after a reset, the grant will have been assigned a value of x.
+ // since there is a loopback in the RTL, the value will continue to be x,
+ // and gets reflected on avmm_readdata and avmm_waitrequest. once an avmm master
+ // requests a read or write, the x value for grant will correct itself.
+ /**********************************************************************/
+ assign user_read_write_lcl[jg] =
+ // synthesis translate_off
+ (user_read_write[jg] === 1'bx) ? 1'b0 :
+ // synthesis translate_on
+ user_read_write[jg];
+
+
+
+ /**********************************************************************/
+ // Per Instance instantiations and assignments
+ // Priority in decreasing order is embedded reconfig -> odi -> user AVMM -> JTAG
+ /**********************************************************************/
+ alt_xcvr_arbiter #(
+ .width (total_masters)
+ ) arbiter_inst (
+ .clock (reconfig_clk[jg]),
+ .req ({jtag_read_write[jg], user_read_write_lcl[jg], odi_read_write[jg], strm_read_write[jg], pcie_dfe_read_write[jg]}),
+ .grant (grant[jg*total_masters+:total_masters])
+ );
+
+ // Assign the grant signal
+ assign strm_grants[jg] = grant[(jg*total_masters)+1];
+
+ // Use the grant as a mask for the varoius read and writs signals
+ // if you or them all together, it will generate the read/write request if any are high
+ // For streamer write/read condition - if broadcasting, wait for all channels to receive grant before asserting write/read
+ assign avmm_write[jg] = |(grant[jg*total_masters+:total_masters] & {jtag_write[jg], user_write[jg], odi_write[jg], ((~&strm_write | &strm_grants) & strm_write[jg]), pcie_dfe_write[jg]});
+ assign avmm_read[jg] = |(grant[jg*total_masters+:total_masters] & {jtag_read[jg], user_read[jg], odi_read[jg], ((~&strm_read | &strm_grants) & strm_read[jg]), pcie_dfe_read[jg]});
+
+ // Split the wait request, and if the grant is asserted to any one master, assert wait request to all others
+ assign {jtag_waitrequest[jg], user_waitrequest[jg], odi_waitrequest[jg], strm_waitrequest[jg], pcie_dfe_waitrequest[jg]} = (~grant[jg*total_masters+:total_masters] | {total_masters{avmm_waitrequest[jg]}});
+
+ // Since thse are busses, the logic must be done in a bit-wise fashion; hence the for loop
+ // Generate the address for the bus width
+ for(ig=0; ig<address_width;ig=ig+1) begin: g_avmm_address
+ assign avmm_address[jg*address_width + ig] = |(grant[jg*total_masters+:total_masters] & {jtag_address[jg*address_width + ig], user_address[jg*address_width + ig], odi_address[jg*address_width + ig], strm_address[jg*address_width + ig], pcie_dfe_address[jg*address_width + ig]});
+ end // End g_avmm_address
+
+ // Generate the write data for the bus width
+ for(ig=0; ig<data_width;ig=ig+1) begin: g_avmm_writdata
+ assign avmm_writedata[jg*data_width+ ig] = |(grant[jg*total_masters+:total_masters] & {jtag_writedata[jg*data_width + ig], user_writedata[jg*data_width + ig],odi_writedata[jg*data_width + ig], strm_writedata[jg*data_width + ig], pcie_dfe_writedata[jg*data_width + ig]});
+ end // End g_avmm_writedata
+
+ end //End for channel-wise for loop
+endgenerate // End generate
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_rcfg_opt_logic_iq5an3y.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_rcfg_opt_logic_iq5an3y.sv
new file mode 100644
index 0000000000000000000000000000000000000000..904e015633e5c60235bf0c5712ebb4202deab2e1
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_rcfg_opt_logic_iq5an3y.sv
@@ -0,0 +1,737 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+module alt_xcvr_native_rcfg_opt_logic_iq5an3y #(
+ // Parameters for the embedded reconfiguration logic
+ parameter dbg_user_identifier = 0,
+ parameter duplex_mode = "duplex",
+ parameter dbg_embedded_debug_enable = 0,
+ parameter dbg_capability_reg_enable = 0,
+ parameter dbg_prbs_soft_logic_enable = 0,
+ parameter dbg_odi_soft_logic_enable = 0,
+ parameter dbg_stat_soft_logic_enable = 0,
+ parameter dbg_ctrl_soft_logic_enable = 0,
+
+ // Parameter for enabling the PCIe DFE IP
+ parameter enable_pcie_dfe_ip = 0,
+ parameter disable_continuous_dfe = 0,
+ parameter sim_reduced_counters = 0,
+ parameter enable_hip = 0,
+
+ // Parameters for the AVMM masters and split interface
+ parameter CHANNELS = 1,
+ parameter RECONFIG_SHARED = 0,
+ parameter JTAG_ENABLED = 0, // Can only be enabled when using a shared reconfig interface
+ parameter ADME_SLAVE_MAP = "altera_xcvr_native_a10",
+ parameter ADME_ASSGN_MAP = " ",
+ parameter RCFG_EMB_STRM_ENABLED = 0, // Enable the embedded reconfiguration streamer logic
+ parameter RCFG_PROFILE_CNT = 2, // Number of configuration profiles for embedded streamer
+
+ // The following are not intended to be directly set
+ parameter IFACES = RECONFIG_SHARED ? 1 : CHANNELS,
+ parameter ADDR_BITS = 10,
+ parameter SEL_BITS = (RECONFIG_SHARED ? altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(CHANNELS-1) : 0),
+ parameter DATA_WIDTH = 32
+
+) (
+ // User reconfig interface ports
+ input [IFACES-1:0] reconfig_clk,
+ input [IFACES-1:0] reconfig_reset,
+ input [IFACES-1:0] reconfig_write,
+ input [IFACES-1:0] reconfig_read,
+ input [IFACES*(ADDR_BITS+SEL_BITS)-1:0] reconfig_address,
+ input [IFACES*DATA_WIDTH-1:0] reconfig_writedata,
+ output [IFACES*DATA_WIDTH-1:0] reconfig_readdata,
+ output [IFACES-1:0] reconfig_waitrequest,
+
+ // AVMM ports to transceiver Split bychannel
+ output [CHANNELS-1:0] avmm_clk,
+ output [CHANNELS-1:0] avmm_reset,
+ output [CHANNELS-1:0] avmm_write,
+ output [CHANNELS-1:0] avmm_read,
+ output [CHANNELS*ADDR_BITS-1:0] avmm_address,
+ output [CHANNELS*8-1:0] avmm_writedata,
+ input [CHANNELS*8-1:0] avmm_readdata,
+ input [CHANNELS-1:0] avmm_waitrequest,
+
+ // input signals for PCIe DFE IP
+ input ltssm_detect_quiet,
+ input ltssm_detect_active,
+ input ltssm_rcvr_phase_two,
+ input [1:0] pcie_rate,
+ input hip_reduce_counters,
+
+ // input signals from the PHY for PRBSerror accumulation
+ input [CHANNELS-1:0] prbs_err_signal,
+ input [CHANNELS-1:0] prbs_done_signal,
+
+ // input rx_clkout
+ input [CHANNELS-1:0] in_rx_clkout,
+
+ // input status signals
+ input [CHANNELS-1:0] in_rx_is_lockedtoref,
+ input [CHANNELS-1:0] in_rx_is_lockedtodata,
+ input [CHANNELS-1:0] in_tx_cal_busy,
+ input [CHANNELS-1:0] in_rx_cal_busy,
+ input [CHANNELS-1:0] in_avmm_busy,
+
+ // input control signals
+ input [CHANNELS-1:0] in_rx_prbs_err_clr,
+ input [CHANNELS-1:0] in_set_rx_locktoref,
+ input [CHANNELS-1:0] in_set_rx_locktodata,
+ input [CHANNELS-1:0] in_en_serial_lpbk,
+ input [CHANNELS-1:0] in_rx_analogreset,
+ input [CHANNELS-1:0] in_rx_digitalreset,
+ input [CHANNELS-1:0] in_tx_analogreset,
+ input [CHANNELS-1:0] in_tx_digitalreset,
+
+ // output control signals to the phy
+ output [CHANNELS-1:0] out_prbs_err_clr,
+ output [CHANNELS-1:0] out_set_rx_locktoref,
+ output [CHANNELS-1:0] out_set_rx_locktodata,
+ output [CHANNELS-1:0] out_en_serial_lpbk,
+ output [CHANNELS-1:0] out_rx_analogreset,
+ output [CHANNELS-1:0] out_rx_digitalreset,
+ output [CHANNELS-1:0] out_tx_analogreset,
+ output [CHANNELS-1:0] out_tx_digitalreset,
+ output [CHANNELS-1:0] out_tx_cal_busy_mask,
+ output [CHANNELS-1:0] out_rx_cal_busy_mask
+);
+
+/**********************************************************************/
+// Per Instance instantiations and assignments
+/**********************************************************************/
+localparam CHANNEL_SEL_WIDTH = altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(CHANNELS-1);
+localparam ENABLED_JTAG_MASTERS = 1 + dbg_odi_soft_logic_enable + JTAG_ENABLED + RCFG_EMB_STRM_ENABLED + enable_pcie_dfe_ip;
+localparam RCFG_EMB_STRM_CFG_SEL_WIDTH = altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(RCFG_PROFILE_CNT-1);
+
+
+// Raw rmbedded reconfig signals (always independent)
+wire [CHANNELS-1:0] rcfg_emb_strm_write;
+wire [CHANNELS-1:0] rcfg_emb_strm_read;
+wire [CHANNELS*ADDR_BITS-1:0] rcfg_emb_strm_address;
+wire [CHANNELS*DATA_WIDTH-1:0] rcfg_emb_strm_writedata;
+wire [CHANNELS-1:0] rcfg_emb_strm_waitrequest;
+
+// User AVMM signals expanded to independent channels
+wire [CHANNELS-1:0] split_user_write;
+wire [CHANNELS-1:0] split_user_read;
+wire [CHANNELS*ADDR_BITS-1:0] split_user_address;
+wire [CHANNELS*DATA_WIDTH-1:0] split_user_writedata;
+wire [CHANNELS-1:0] split_user_waitrequest;
+
+// ODI AVMM signals
+wire [CHANNELS-1:0] odi_write;
+wire [CHANNELS-1:0] odi_read;
+wire [CHANNELS*ADDR_BITS-1:0] odi_address;
+wire [CHANNELS*DATA_WIDTH-1:0] odi_writedata;
+wire [CHANNELS-1:0] odi_waitrequest;
+
+// PCIe DFE ip
+wire [CHANNELS-1:0] split_pcie_dfe_write;
+wire [CHANNELS-1:0] split_pcie_dfe_read;
+wire [CHANNELS*ADDR_BITS-1:0] split_pcie_dfe_address;
+wire [CHANNELS*DATA_WIDTH-1:0] split_pcie_dfe_writedata;
+wire [CHANNELS-1:0] split_pcie_dfe_waitrequest;
+wire pcie_dfe_avmm_lock;
+
+// JTAG signals expanded to independent channels
+wire [CHANNELS-1:0] split_jtag_write;
+wire [CHANNELS-1:0] split_jtag_read;
+wire [CHANNELS*ADDR_BITS-1:0] split_jtag_address;
+wire [CHANNELS*DATA_WIDTH-1:0] split_jtag_writedata;
+wire [CHANNELS-1:0] split_jtag_waitrequest;
+
+// Additional arbitration signals for soft CSR
+wire [CHANNELS-1:0] chnl_write;
+wire [CHANNELS-1:0] chnl_read;
+wire [CHANNELS-1:0] chnl_busy;
+wire [CHANNELS-1:0] chnl_waitrequest;
+wire [CHANNELS*8-1:0] chnl_readdata;
+
+// embedded reconfig signals
+wire [CHANNELS-1:0] rcfg_emb_strm_busy;
+wire [CHANNELS-1:0] rcfg_emb_strm_chan_sel;
+wire [CHANNELS*RCFG_EMB_STRM_CFG_SEL_WIDTH-1:0] rcfg_emb_strm_cfg_sel;
+wire [CHANNELS-1:0] rcfg_emb_strm_bcast_en;
+wire [CHANNELS-1:0] rcfg_emb_strm_cfg_load;
+
+// Read_write signals to assist with prioritizing arbitrarion
+wire [CHANNELS-1:0] user_read_write;
+wire [CHANNELS-1:0] odi_read_write;
+wire [CHANNELS-1:0] pcie_dfe_read_write;
+wire [CHANNELS-1:0] jtag_read_write;
+wire [CHANNELS-1:0] rcfg_emb_strm_read_write;
+
+// Wires for converting between data widths
+wire [CHANNELS*DATA_WIDTH-1:0] expanded_avmm_readdata;
+wire [CHANNELS*DATA_WIDTH-1:0] expanded_avmm_writedata;
+
+// Wires for control and status signals between the various masters
+wire [CHANNELS-1:0] odi_done;
+wire [CHANNELS-1:0] prbs_done_sync;
+wire [CHANNELS*50-1:0] prbs_err_count;
+wire [CHANNELS*50-1:0] prbs_bit_count;
+wire [CHANNELS*50-1:0] odi_err_count;
+wire [CHANNELS*50-1:0] odi_bit_count;
+
+
+// Wires for qmap cleanup
+wire lcl_g_arbiter_dis;
+wire lcl_g_avmm_csr_dis;
+wire lcl_ground;
+
+// Warning Removal
+assign lcl_g_avmm_csr_dis = &{1'b0,
+ rcfg_emb_strm_busy,
+ prbs_done_sync,
+ odi_done,
+ prbs_err_count,
+ prbs_bit_count,
+ odi_bit_count,
+ odi_err_count};
+assign lcl_g_arbiter_dis = &{1'b0,
+ rcfg_emb_strm_address,
+ rcfg_emb_strm_writedata,
+ odi_address,
+ odi_writedata,
+ split_pcie_dfe_address,
+ split_pcie_dfe_writedata,
+ split_jtag_address,
+ split_jtag_writedata,
+ user_read_write,
+ odi_read_write,
+ pcie_dfe_read_write,
+ jtag_read_write,
+ rcfg_emb_strm_read_write};
+assign lcl_ground = &{1'b0,
+ lcl_g_avmm_csr_dis,
+ lcl_g_arbiter_dis};
+
+// Generate variable for channel numbers
+genvar ig;
+
+
+/**********************************************************************/
+// Generate Statement for the Shared vs Split user interface
+/**********************************************************************/
+generate
+ // Expand the AVMM signals from the channel to the 32-bit interface of the user
+ for(ig=0;ig<CHANNELS;ig=ig+1) begin: g_expanded_avmm_signals
+ assign expanded_avmm_readdata [ig*DATA_WIDTH +: DATA_WIDTH] = {24'd0,chnl_readdata [ig*8 +: 8]};
+ assign avmm_writedata [ig*8 +: 8] = expanded_avmm_writedata [ig*DATA_WIDTH +: 8];
+ end
+
+
+ /**********************************************************************/
+ // Split the reconfig interface to the independent channel when using shared reconfig
+ /**********************************************************************/
+ if(!RECONFIG_SHARED) begin : g_not_shared
+ // Signals are already split, so wire straight through
+ assign avmm_clk = reconfig_clk;
+ assign avmm_reset = reconfig_reset;
+
+ assign split_user_write = reconfig_write;
+ assign split_user_read = reconfig_read;
+ assign split_user_address = reconfig_address;
+ assign split_user_writedata = reconfig_writedata;
+ assign reconfig_readdata = expanded_avmm_readdata;
+ assign reconfig_waitrequest = ({CHANNELS{lcl_ground}} | split_user_waitrequest);
+
+ // If we are using a shared interface
+ end else begin : g_shared
+ wire [CHANNEL_SEL_WIDTH-1:0] rcfg_if_sel;
+
+ // Generate interface select based on upper address bits
+ assign rcfg_if_sel = reconfig_address[ADDR_BITS+:CHANNEL_SEL_WIDTH];
+ assign reconfig_readdata = expanded_avmm_readdata[rcfg_if_sel*DATA_WIDTH +: DATA_WIDTH];
+ assign reconfig_waitrequest = split_user_waitrequest[rcfg_if_sel];
+
+ for(ig=0;ig<CHANNELS;ig=ig+1) begin : g_shared
+ // Split shared signals to independent channels
+ assign avmm_clk [ig] = reconfig_clk;
+ assign avmm_reset [ig] = reconfig_reset;
+
+ assign split_user_write [ig] = reconfig_write & (rcfg_if_sel == ig) | lcl_ground;
+ assign split_user_read [ig] = reconfig_read & (rcfg_if_sel == ig);
+ assign split_user_address [ig*ADDR_BITS +: ADDR_BITS] = reconfig_address[0+:ADDR_BITS];
+ assign split_user_writedata [ig*DATA_WIDTH +: DATA_WIDTH] = reconfig_writedata;
+ end
+ end //End g_not_shared
+endgenerate
+
+
+/**********************************************************************/
+// Embedded JTAG Debug Master (ADME)
+/**********************************************************************/
+generate if(JTAG_ENABLED) begin : g_jtag
+
+ // Set the slave type for the ADME. Since the span needs to be a string, 2^(total addr_bits) will
+ // give the max value, however since the adme uses byte alignment, shift the span by two bits.
+ localparam set_slave_span = altera_xcvr_native_a10_functions_h::int2str_alt_xcvr_native_a10(2**(ADDR_BITS+CHANNEL_SEL_WIDTH+2));
+ localparam set_slave_map = {"{typeName ",ADME_SLAVE_MAP," address 0x0 span ",set_slave_span," hpath {}",ADME_ASSGN_MAP,"}"};
+
+ // Raw JTAG signals
+ wire jtag_write;
+ wire jtag_read;
+ wire [(ADDR_BITS+CHANNEL_SEL_WIDTH)-1:0] jtag_address;
+ wire [DATA_WIDTH-1:0] jtag_writedata;
+ wire [DATA_WIDTH-1:0] jtag_readdata;
+ wire jtag_waitrequest;
+ wire jtag_readdatavalid;
+ wire [CHANNEL_SEL_WIDTH-1:0] jtag_if_sel;
+
+ // Generate channel select based on upper address bits
+ assign jtag_if_sel = jtag_address[ADDR_BITS+:CHANNEL_SEL_WIDTH];
+ assign jtag_readdata = expanded_avmm_readdata[jtag_if_sel*DATA_WIDTH +: DATA_WIDTH];
+ assign jtag_waitrequest = split_jtag_waitrequest[jtag_if_sel];
+
+ // Split shared signals to independent channels
+ for(ig=0;ig<CHANNELS;ig=ig+1) begin: g_expanded_avmm_signals
+ assign split_jtag_write [ig] = jtag_write & (jtag_if_sel == ig);
+ assign split_jtag_read [ig] = jtag_read & (jtag_if_sel == ig);
+ assign split_jtag_address [ig*ADDR_BITS +: ADDR_BITS] = jtag_address[0+:ADDR_BITS];
+ assign split_jtag_writedata [ig*DATA_WIDTH +: DATA_WIDTH] = jtag_writedata[DATA_WIDTH-1:0];
+ end
+
+ // When doing RTL sims, remove the altera_debug_master_endpoint, as
+ // there is no RTL simulation model. Pre and Post Fit sims are ok.
+ `ifdef ALTERA_RESERVED_QIS
+ altera_debug_master_endpoint
+ #(
+ .ADDR_WIDTH ( (ADDR_BITS+CHANNEL_SEL_WIDTH) ),
+ .DATA_WIDTH ( DATA_WIDTH ),
+ .HAS_RDV ( 0 ),
+ .SLAVE_MAP ( set_slave_map ),
+ .PREFER_HOST ( " " ),
+ .CLOCK_RATE_CLK ( 0 )
+ ) adme (
+ .clk ( reconfig_clk ),
+ .reset ( reconfig_reset ),
+ .master_write ( jtag_write ),
+ .master_read ( jtag_read ),
+ .master_address ( jtag_address ),
+ .master_writedata ( jtag_writedata ),
+ .master_waitrequest ( jtag_waitrequest ),
+ .master_readdatavalid ( jtag_readdatavalid ),
+ .master_readdata ( jtag_readdata )
+ );
+ `else
+ assign jtag_write = 1'b0;
+ assign jtag_read = 1'b0;
+ assign jtag_address = {(ADDR_BITS+CHANNEL_SEL_WIDTH){1'b0}};
+ assign jtag_writedata = {DATA_WIDTH{1'b0}};
+ `endif
+
+ // If we have not enabled the ADME
+ end else begin : g_jtag_disable
+ assign split_jtag_write = {CHANNELS{1'b0}};
+ assign split_jtag_read = {CHANNELS{1'b0}};
+ assign split_jtag_address = {(CHANNELS*ADDR_BITS){1'b0}};
+ assign split_jtag_writedata = {(CHANNELS*DATA_WIDTH){1'b0}};
+ end
+endgenerate // End g_jtag
+
+
+/**********************************************************************/
+// Enable the PCIe DFE IP
+/**********************************************************************/
+generate if(enable_pcie_dfe_ip) begin : g_pcie_dfe_ip
+ // Raw JTAG signals
+ wire pcie_dfe_write;
+ wire pcie_dfe_read;
+ wire [(ADDR_BITS+CHANNEL_SEL_WIDTH)-1:0] pcie_dfe_address;
+ wire [DATA_WIDTH-1:0] pcie_dfe_writedata;
+ wire [DATA_WIDTH-1:0] pcie_dfe_readdata;
+ wire pcie_dfe_waitrequest;
+ wire [CHANNEL_SEL_WIDTH-1:0] pcie_dfe_if_sel;
+
+ // Generate channel select based on upper address bits
+ assign pcie_dfe_if_sel = pcie_dfe_address[ADDR_BITS+:CHANNEL_SEL_WIDTH];
+ assign pcie_dfe_readdata = expanded_avmm_readdata[pcie_dfe_if_sel*DATA_WIDTH +: DATA_WIDTH];
+ assign pcie_dfe_waitrequest = split_pcie_dfe_waitrequest[pcie_dfe_if_sel];
+
+ // Split shared signals to independent channels
+ for(ig=0;ig<CHANNELS;ig=ig+1) begin: g_expanded_avmm_signals
+ assign split_pcie_dfe_write [ig] = pcie_dfe_write & (pcie_dfe_if_sel == ig);
+ assign split_pcie_dfe_read [ig] = pcie_dfe_read & (pcie_dfe_if_sel == ig);
+ assign split_pcie_dfe_address [ig*ADDR_BITS +: ADDR_BITS] = pcie_dfe_address[0+:ADDR_BITS];
+ assign split_pcie_dfe_writedata [ig*DATA_WIDTH +: DATA_WIDTH] = pcie_dfe_writedata[DATA_WIDTH-1:0];
+ end
+
+
+ altera_xcvr_native_pcie_dfe_ip #(
+ .num_channels ( CHANNELS ),
+ .disable_continuous_dfe ( disable_continuous_dfe ),
+ .enable_hip ( enable_hip ),
+ .sim_reduced_counters ( sim_reduced_counters ),
+ .avmm_sel_bits ( CHANNEL_SEL_WIDTH ),
+ .avmm_addr_bits ( ADDR_BITS )
+ ) altera_xcvr_native_pcie_dfe_ip_inst (
+ .clock ( reconfig_clk ),
+ .reset ( reconfig_reset ),
+ .ltssm_detect_quiet ( ltssm_detect_quiet ),
+ .ltssm_detect_active ( ltssm_detect_active ),
+ .ltssm_rcvr_phase_two ( ltssm_rcvr_phase_two ),
+ .pcie_rate_sw ( pcie_rate ),
+
+ // HIP only port for reduced counters
+ .hip_reduce_counters ( hip_reduce_counters ),
+
+ // Reconfig Interface to the transceiver
+ .xcvr_rcfg_waitrequest ( pcie_dfe_waitrequest ),
+ .xcvr_rcfg_readdata ( pcie_dfe_readdata ),
+ .xcvr_rcfg_lock ( pcie_dfe_avmm_lock ),
+ .xcvr_rcfg_read ( pcie_dfe_read ),
+ .xcvr_rcfg_write ( pcie_dfe_write ),
+ .xcvr_rcfg_address ( pcie_dfe_address ),
+ .xcvr_rcfg_writedata ( pcie_dfe_writedata )
+ );
+
+ end else begin : g_disable_pcie_dfe_ip
+ assign pcie_dfe_avmm_lock = 1'b0;
+ assign split_pcie_dfe_write = {CHANNELS{1'b0}};
+ assign split_pcie_dfe_read = {CHANNELS{1'b0}};
+ assign split_pcie_dfe_address = {(CHANNELS*ADDR_BITS){1'b0}};
+ assign split_pcie_dfe_writedata = {(CHANNELS*DATA_WIDTH){1'b0}};
+ end
+endgenerate
+
+
+/**********************************************************************/
+// Embedded Reconfig Streamer
+/**********************************************************************/
+generate if(RCFG_EMB_STRM_ENABLED) begin : g_rcfg_strm_enable //TODO check to see if there is parameter redundancy
+
+ alt_xcvr_native_rcfg_strm_top_iq5an3y #(
+ .xcvr_rcfg_interfaces ( CHANNELS ),
+ .xcvr_rcfg_addr_width ( ADDR_BITS ),
+ .xcvr_rcfg_data_width ( DATA_WIDTH ),
+ .rcfg_profile_cnt ( RCFG_PROFILE_CNT )
+ )rcfg_strm_top_inst(
+ .clk ( reconfig_clk[0] ), // All clock bits should be driven by the same source if using independent interface
+ .reset ( |reconfig_reset ), // Any reset bit will reset the reconfig streamer
+ .cfg_sel ( rcfg_emb_strm_cfg_sel ),
+ .bcast_en ( rcfg_emb_strm_bcast_en ),
+ .cfg_load ( rcfg_emb_strm_cfg_load ),
+ .chan_sel ( rcfg_emb_strm_chan_sel ),
+ .stream_busy ( rcfg_emb_strm_busy ),
+ .xcvr_reconfig_write ( rcfg_emb_strm_write ),
+ .xcvr_reconfig_read ( rcfg_emb_strm_read ),
+ .xcvr_reconfig_address ( rcfg_emb_strm_address ),
+ .xcvr_reconfig_writedata ( rcfg_emb_strm_writedata ),
+ .xcvr_reconfig_readdata ( expanded_avmm_readdata ),
+ .xcvr_reconfig_waitrequest ( rcfg_emb_strm_waitrequest )
+ );
+
+ // If we disable the reconfig streamer
+ end else begin: g_rcfg_strm_disable
+ assign rcfg_emb_strm_write = {CHANNELS{1'b0}};
+ assign rcfg_emb_strm_read = {CHANNELS{1'b0}};
+ assign rcfg_emb_strm_address = {(CHANNELS*ADDR_BITS){1'b0}};
+ assign rcfg_emb_strm_writedata = {CHANNELS{32'b0}};
+ assign rcfg_emb_strm_busy = {CHANNELS{1'b0}};
+ end
+endgenerate // End g_rcfg_strm_enable
+
+
+/**********************************************************************/
+// AVMM Master read/write signals.
+/**********************************************************************/
+assign user_read_write = split_user_read | split_user_write; // Bits asserted for corresponding channels from/to which user avmm is currently reading/writing
+assign jtag_read_write = split_jtag_read | split_jtag_write; // Bits asserted for corresponding channels from/to which jtag is currently reading/writing
+assign rcfg_emb_strm_read_write = rcfg_emb_strm_read | rcfg_emb_strm_write; // Bits asserted for corresponding channels from/to which embedded streamer is currently reading/writing
+assign odi_read_write = odi_read | odi_write;
+assign pcie_dfe_read_write = split_pcie_dfe_read | split_pcie_dfe_write | {CHANNELS{pcie_dfe_avmm_lock}};
+
+/**********************************************************************/
+// AVMM Arbiter. Instantiated once per channel, however to handle streaming
+// broadcast, the channel-wise instantiation is handled within the arbiter.
+/**********************************************************************/
+generate if (ENABLED_JTAG_MASTERS > 1) begin: g_arbiber_enable
+ alt_xcvr_native_rcfg_arb #(
+ .total_masters ( 5 ),
+ .channels ( CHANNELS ),
+ .address_width ( ADDR_BITS ),
+ .data_width ( DATA_WIDTH )
+ ) alt_xcvr_rcfg_arb (
+ // Basic AVMM inputs
+ .reconfig_clk ( avmm_clk ),
+ .reconfig_reset ( avmm_reset ),
+
+ // User AVMM input
+ .user_read ( split_user_read ),
+ .user_write ( split_user_write ),
+ .user_address ( split_user_address ),
+ .user_writedata ( split_user_writedata ),
+ .user_read_write ( user_read_write ),
+ .user_waitrequest ( split_user_waitrequest ),
+
+ // Reconfig Steamer AVMM input
+ .strm_read ( rcfg_emb_strm_read ),
+ .strm_write ( rcfg_emb_strm_write ),
+ .strm_address ( rcfg_emb_strm_address ),
+ .strm_writedata ( rcfg_emb_strm_writedata ),
+ .strm_read_write ( rcfg_emb_strm_read_write ),
+ .strm_waitrequest ( rcfg_emb_strm_waitrequest ),
+
+ // ODI AVMM input
+ .odi_read ( odi_read ),
+ .odi_write ( odi_write ),
+ .odi_address ( odi_address ),
+ .odi_writedata ( odi_writedata ),
+ .odi_read_write ( odi_read_write ),
+ .odi_waitrequest ( odi_waitrequest ),
+
+ // ADME AVMM input
+ .jtag_read ( split_jtag_read ),
+ .jtag_write ( split_jtag_write ),
+ .jtag_address ( split_jtag_address ),
+ .jtag_writedata ( split_jtag_writedata ),
+ .jtag_read_write ( jtag_read_write ),
+ .jtag_waitrequest ( split_jtag_waitrequest ),
+
+ // PCIe DFE
+ .pcie_dfe_read ( split_pcie_dfe_read ),
+ .pcie_dfe_write ( split_pcie_dfe_write ),
+ .pcie_dfe_address ( split_pcie_dfe_address ),
+ .pcie_dfe_writedata ( split_pcie_dfe_writedata ),
+ .pcie_dfe_read_write ( pcie_dfe_read_write ),
+ .pcie_dfe_waitrequest ( split_pcie_dfe_waitrequest ),
+
+ // AVMM output the channel and the CSR
+ .avmm_waitrequest ( chnl_waitrequest ),
+ .avmm_read ( chnl_read ),
+ .avmm_write ( chnl_write ),
+ .avmm_address ( avmm_address ),
+ .avmm_writedata ( expanded_avmm_writedata )
+ );
+ end else begin: g_arbiter_disable
+ // Pass through signals
+ assign split_user_waitrequest = chnl_waitrequest;
+ assign chnl_read = split_user_read;
+ assign chnl_write = split_user_write;
+ assign expanded_avmm_writedata = split_user_writedata;
+ assign avmm_address = split_user_address;
+
+ end
+endgenerate // End g_arbiter
+
+
+/**********************************************************************/
+// Per Channel instantiations and assignments
+/**********************************************************************/
+generate for(ig=0;ig<CHANNELS;ig=ig+1) begin: g_optional_chnl_reconfig_logic
+
+wire [CHANNELS-1:0] csr_prbs_snapshot;
+wire [CHANNELS-1:0] csr_prbs_count_en;
+wire [CHANNELS-1:0] csr_odi_count_en;
+wire [CHANNELS-1:0] csr_odi_snap;
+wire [CHANNELS-1:0] csr_odi_reset;
+
+ /**********************************************************************/
+ // Instantiate the Soft CSR
+ /**********************************************************************/
+ if(dbg_embedded_debug_enable) begin: g_avmm_csr_enabled
+
+ // Instantiate wires as part of generate to avoid warnings about unused wires.
+ // AVMM reconfiguration signals for embedded debug
+ wire [CHANNELS-1:0] debug_write;
+ wire [CHANNELS-1:0] debug_read;
+ wire [CHANNELS-1:0] debug_waitrequest;
+ wire [CHANNELS*8-1:0] debug_readdata;
+
+ // avmm arbitration for soft csr and channel
+ assign debug_read [ig] = (avmm_address[ig*ADDR_BITS+9]) ? chnl_read [ig] : 1'b0;
+ assign debug_write [ig] = (avmm_address[ig*ADDR_BITS+9]) ? chnl_write [ig] : 1'b0;
+ assign avmm_read [ig] = (avmm_address[ig*ADDR_BITS+9]) ? 1'b0 : chnl_read [ig];
+ assign avmm_write [ig] = (avmm_address[ig*ADDR_BITS+9]) ? 1'b0 : chnl_write [ig];
+ assign chnl_waitrequest [ig] = (avmm_address[ig*ADDR_BITS+9]) ? debug_waitrequest [ig] : avmm_waitrequest [ig];
+ assign chnl_readdata [ig*8+:8] = (avmm_address[ig*ADDR_BITS+9]) ? debug_readdata [ig*8+:8] : avmm_readdata [ig*8+:8];
+
+
+ alt_xcvr_native_avmm_csr #(
+ .channels ( CHANNELS ),
+ .channel_num ( ig ),
+ .dbg_user_identifier ( dbg_user_identifier ),
+ .duplex_mode ( duplex_mode ),
+ .dbg_capability_reg_enable ( dbg_capability_reg_enable ),
+ .dbg_prbs_soft_logic_enable ( dbg_prbs_soft_logic_enable ),
+ .dbg_odi_soft_logic_enable ( dbg_odi_soft_logic_enable ),
+ .dbg_stat_soft_logic_enable ( dbg_stat_soft_logic_enable ),
+ .dbg_ctrl_soft_logic_enable ( dbg_ctrl_soft_logic_enable ),
+ .rcfg_emb_strm_enable ( RCFG_EMB_STRM_ENABLED ),
+ .rcfg_emb_strm_cfg_sel_width ( RCFG_EMB_STRM_CFG_SEL_WIDTH )
+ ) embedded_debug_soft_csr (
+ // avmm signals
+ .avmm_clk ( avmm_clk [ig] ),
+ .avmm_reset ( avmm_reset [ig] ),
+ .avmm_address ( avmm_address [ig*ADDR_BITS+:9] ),
+ .avmm_writedata ( avmm_writedata [ig*8+:8] ),
+ .avmm_write ( debug_write [ig] ),
+ .avmm_read ( debug_read [ig] ),
+ .avmm_readdata ( debug_readdata [ig*8+:8] ),
+ .avmm_waitrequest ( debug_waitrequest [ig] ),
+
+ // prbs control signals
+ .prbs_err ( prbs_err_count [ig*50+:50]),
+ .prbs_bit ( prbs_bit_count [ig*50+:50]),
+ .prbs_done ( prbs_done_sync [ig] ),
+ .prbs_snap ( csr_prbs_snapshot [ig] ),
+ .prbs_count_en ( csr_prbs_count_en [ig] ),
+ .prbs_reset ( out_prbs_err_clr [ig] ),
+
+ // odi ctrl signals
+ .odi_bit ( odi_bit_count [ig*50+:50]),
+ .odi_err ( odi_err_count [ig*50+:50]),
+ .odi_done ( odi_done [ig] ),
+ .odi_count_en ( csr_odi_count_en [ig] ),
+ .odi_reset ( csr_odi_reset [ig] ),
+ .odi_snap ( csr_odi_snap [ig] ),
+
+ // input status signals from the channel
+ .rx_is_lockedtodata ( in_rx_is_lockedtodata [ig] ),
+ .rx_is_lockedtoref ( in_rx_is_lockedtoref [ig] ),
+ .tx_cal_busy ( in_tx_cal_busy [ig] ),
+ .rx_cal_busy ( in_rx_cal_busy [ig] ),
+ .avmm_busy ( in_avmm_busy [ig] ),
+
+ // input control signals
+ .rx_prbs_err_clr ( in_rx_prbs_err_clr [ig] ),
+ .set_rx_locktoref ( in_set_rx_locktoref [ig] ),
+ .set_rx_locktodata ( in_set_rx_locktodata [ig] ),
+ .serial_loopback ( in_en_serial_lpbk [ig] ),
+ .rx_analogreset ( in_rx_analogreset [ig] ),
+ .rx_digitalreset ( in_rx_digitalreset [ig] ),
+ .tx_analogreset ( in_tx_analogreset [ig] ),
+ .tx_digitalreset ( in_tx_digitalreset [ig] ),
+
+ // embedded reconfig signals
+ .rcfg_emb_strm_busy ( rcfg_emb_strm_busy [ig] ),
+ .rcfg_emb_strm_chan_sel ( rcfg_emb_strm_chan_sel [ig] ),
+ .rcfg_emb_strm_cfg_sel ( rcfg_emb_strm_cfg_sel [ig*RCFG_EMB_STRM_CFG_SEL_WIDTH+:RCFG_EMB_STRM_CFG_SEL_WIDTH]),
+ .rcfg_emb_strm_bcast_en ( rcfg_emb_strm_bcast_en [ig] ),
+ .rcfg_emb_strm_cfg_load ( rcfg_emb_strm_cfg_load [ig] ),
+
+
+ // output control signals to the channel
+ .csr_set_lock_to_data ( out_set_rx_locktodata [ig] ),
+ .csr_set_lock_to_ref ( out_set_rx_locktoref [ig] ),
+ .csr_en_loopback ( out_en_serial_lpbk [ig] ),
+ .csr_rx_analogreset ( out_rx_analogreset [ig] ),
+ .csr_rx_digitalreset ( out_rx_digitalreset [ig] ),
+ .csr_tx_analogreset ( out_tx_analogreset [ig] ),
+ .csr_tx_digitalreset ( out_tx_digitalreset [ig] ),
+ .csr_tx_cal_busy_mask ( out_tx_cal_busy_mask [ig] ),
+ .csr_rx_cal_busy_mask ( out_rx_cal_busy_mask [ig] )
+ );
+
+ end else begin: g_avmm_csr_disable
+ // do a pass though for control signals when no embedded debug
+ assign out_prbs_err_clr [ig] = in_rx_prbs_err_clr [ig];
+ assign out_set_rx_locktoref [ig] = in_set_rx_locktoref [ig];
+ assign out_set_rx_locktodata [ig] = in_set_rx_locktodata [ig];
+ assign out_en_serial_lpbk [ig] = in_en_serial_lpbk [ig];
+ assign out_rx_analogreset [ig] = in_rx_analogreset [ig];
+ assign out_rx_digitalreset [ig] = in_rx_digitalreset [ig];
+ assign out_tx_analogreset [ig] = in_tx_analogreset [ig];
+ assign out_tx_digitalreset [ig] = in_tx_digitalreset [ig];
+ assign out_tx_cal_busy_mask [ig] = 1'b1;
+ assign out_rx_cal_busy_mask [ig] = 1'b1;
+
+ // assign these signals to ground when no embedded debug
+ assign avmm_read [ig] = chnl_read [ig];
+ assign avmm_write [ig] = chnl_write [ig];
+ assign chnl_waitrequest [ig] = avmm_waitrequest [ig];
+ assign chnl_readdata [ig*8+:8] = avmm_readdata [ig*8+:8];
+ end
+
+
+ /**********************************************************************/
+ // Instantiate the PRBS accumulators
+ /**********************************************************************/
+ if(dbg_prbs_soft_logic_enable == 1) begin: g_prbs_accumulators_enable
+ alt_xcvr_native_prbs_accum prbs_soft_accumulators (
+ .avmm_clk ( avmm_clk [ig] ),
+ .avmm_reset ( avmm_reset [ig] ),
+
+ // Control signals from CSR
+ .prbs_reset ( out_prbs_err_clr [ig] ),
+ .prbs_snapshot ( csr_prbs_snapshot [ig] ),
+ .prbs_counter_en ( csr_prbs_count_en [ig] ),
+
+ // Status signals from PRBS
+ .prbs_done_sync ( prbs_done_sync [ig] ),
+ .prbs_err_count ( prbs_err_count [ig*50+:50] ),
+ .prbs_bit_count ( prbs_bit_count [ig*50+:50] ),
+
+ // Signals from the transceiver
+ .rx_clkout ( in_rx_clkout [ig] ),
+ .prbs_err_signal ( prbs_err_signal [ig] ),
+ .prbs_done_signal ( prbs_done_signal [ig] )
+ );
+
+ // If PRBS is not enabled
+ end else begin: g_prbs_accumulators_disable
+ assign prbs_err_count[ig*50+:50] = 50'b0;
+ assign prbs_bit_count[ig*50+:50] = 50'b0;
+ assign prbs_done_sync[ig] = 1'b0;
+ end // End g_prbs_accumulators
+
+
+ /**********************************************************************/
+ // Instantiate the ODI accumulators
+ /**********************************************************************/
+ if(dbg_odi_soft_logic_enable == 1) begin: g_odi_accelerator_enable
+ alt_xcvr_native_odi_accel #(
+ .DATA_WIDTH ( DATA_WIDTH )
+ ) odi_soft_accelerator (
+ .avmm_clk ( avmm_clk [ig] ),
+ .avmm_reset ( avmm_reset [ig] ),
+
+ // AVMM signals to the transceiver
+ .odi_read ( odi_read [ig] ),
+ .odi_write ( odi_write [ig] ),
+ .odi_address ( odi_address [ig*ADDR_BITS+:ADDR_BITS] ),
+ .odi_writedata ( odi_writedata [ig*DATA_WIDTH+:DATA_WIDTH]),
+ .odi_readdata ( avmm_readdata [ig*8+:8] ),
+ .odi_waitrequest ( odi_waitrequest [ig] ),
+
+ // Control signals from CSR
+ .odi_count_en ( csr_odi_count_en [ig] ),
+ .odi_snap ( csr_odi_snap [ig] ),
+ .odi_reset ( csr_odi_reset [ig] ),
+
+ // Status signals from ODI
+ .odi_done ( odi_done [ig] ),
+ .odi_bit_count ( odi_bit_count [ig*50+:50] ),
+ .odi_err_count ( odi_err_count [ig*50+:50] )
+ );
+
+ end else begin: g_odi_accelerator_disable
+ assign odi_read[ig] = 1'b0;
+ assign odi_write[ig] = 1'b0;
+ assign odi_done[ig] = 1'b0;
+ assign odi_bit_count[ig*50+:50] = 50'b0;
+ assign odi_err_count[ig*50+:50] = 50'b0;
+ assign odi_address[ig*ADDR_BITS+:ADDR_BITS] = {ADDR_BITS{1'b0}};
+ assign odi_writedata[ig*DATA_WIDTH+:DATA_WIDTH] = {DATA_WIDTH{1'b0}};
+ end // End g_odi_accelerator
+
+ end // End for Loop for channels
+endgenerate
+
+endmodule
+
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_rcfg_opt_logic_sfv7jkq.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_rcfg_opt_logic_sfv7jkq.sv
new file mode 100644
index 0000000000000000000000000000000000000000..a6333d3f901deb52da760c3a42dd1be4cb0de09e
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_native_rcfg_opt_logic_sfv7jkq.sv
@@ -0,0 +1,737 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+module alt_xcvr_native_rcfg_opt_logic_sfv7jkq #(
+ // Parameters for the embedded reconfiguration logic
+ parameter dbg_user_identifier = 0,
+ parameter duplex_mode = "duplex",
+ parameter dbg_embedded_debug_enable = 0,
+ parameter dbg_capability_reg_enable = 0,
+ parameter dbg_prbs_soft_logic_enable = 0,
+ parameter dbg_odi_soft_logic_enable = 0,
+ parameter dbg_stat_soft_logic_enable = 0,
+ parameter dbg_ctrl_soft_logic_enable = 0,
+
+ // Parameter for enabling the PCIe DFE IP
+ parameter enable_pcie_dfe_ip = 0,
+ parameter disable_continuous_dfe = 0,
+ parameter sim_reduced_counters = 0,
+ parameter enable_hip = 0,
+
+ // Parameters for the AVMM masters and split interface
+ parameter CHANNELS = 1,
+ parameter RECONFIG_SHARED = 0,
+ parameter JTAG_ENABLED = 0, // Can only be enabled when using a shared reconfig interface
+ parameter ADME_SLAVE_MAP = "altera_xcvr_native_a10",
+ parameter ADME_ASSGN_MAP = " ",
+ parameter RCFG_EMB_STRM_ENABLED = 0, // Enable the embedded reconfiguration streamer logic
+ parameter RCFG_PROFILE_CNT = 2, // Number of configuration profiles for embedded streamer
+
+ // The following are not intended to be directly set
+ parameter IFACES = RECONFIG_SHARED ? 1 : CHANNELS,
+ parameter ADDR_BITS = 10,
+ parameter SEL_BITS = (RECONFIG_SHARED ? altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(CHANNELS-1) : 0),
+ parameter DATA_WIDTH = 32
+
+) (
+ // User reconfig interface ports
+ input [IFACES-1:0] reconfig_clk,
+ input [IFACES-1:0] reconfig_reset,
+ input [IFACES-1:0] reconfig_write,
+ input [IFACES-1:0] reconfig_read,
+ input [IFACES*(ADDR_BITS+SEL_BITS)-1:0] reconfig_address,
+ input [IFACES*DATA_WIDTH-1:0] reconfig_writedata,
+ output [IFACES*DATA_WIDTH-1:0] reconfig_readdata,
+ output [IFACES-1:0] reconfig_waitrequest,
+
+ // AVMM ports to transceiver Split bychannel
+ output [CHANNELS-1:0] avmm_clk,
+ output [CHANNELS-1:0] avmm_reset,
+ output [CHANNELS-1:0] avmm_write,
+ output [CHANNELS-1:0] avmm_read,
+ output [CHANNELS*ADDR_BITS-1:0] avmm_address,
+ output [CHANNELS*8-1:0] avmm_writedata,
+ input [CHANNELS*8-1:0] avmm_readdata,
+ input [CHANNELS-1:0] avmm_waitrequest,
+
+ // input signals for PCIe DFE IP
+ input ltssm_detect_quiet,
+ input ltssm_detect_active,
+ input ltssm_rcvr_phase_two,
+ input [1:0] pcie_rate,
+ input hip_reduce_counters,
+
+ // input signals from the PHY for PRBSerror accumulation
+ input [CHANNELS-1:0] prbs_err_signal,
+ input [CHANNELS-1:0] prbs_done_signal,
+
+ // input rx_clkout
+ input [CHANNELS-1:0] in_rx_clkout,
+
+ // input status signals
+ input [CHANNELS-1:0] in_rx_is_lockedtoref,
+ input [CHANNELS-1:0] in_rx_is_lockedtodata,
+ input [CHANNELS-1:0] in_tx_cal_busy,
+ input [CHANNELS-1:0] in_rx_cal_busy,
+ input [CHANNELS-1:0] in_avmm_busy,
+
+ // input control signals
+ input [CHANNELS-1:0] in_rx_prbs_err_clr,
+ input [CHANNELS-1:0] in_set_rx_locktoref,
+ input [CHANNELS-1:0] in_set_rx_locktodata,
+ input [CHANNELS-1:0] in_en_serial_lpbk,
+ input [CHANNELS-1:0] in_rx_analogreset,
+ input [CHANNELS-1:0] in_rx_digitalreset,
+ input [CHANNELS-1:0] in_tx_analogreset,
+ input [CHANNELS-1:0] in_tx_digitalreset,
+
+ // output control signals to the phy
+ output [CHANNELS-1:0] out_prbs_err_clr,
+ output [CHANNELS-1:0] out_set_rx_locktoref,
+ output [CHANNELS-1:0] out_set_rx_locktodata,
+ output [CHANNELS-1:0] out_en_serial_lpbk,
+ output [CHANNELS-1:0] out_rx_analogreset,
+ output [CHANNELS-1:0] out_rx_digitalreset,
+ output [CHANNELS-1:0] out_tx_analogreset,
+ output [CHANNELS-1:0] out_tx_digitalreset,
+ output [CHANNELS-1:0] out_tx_cal_busy_mask,
+ output [CHANNELS-1:0] out_rx_cal_busy_mask
+);
+
+/**********************************************************************/
+// Per Instance instantiations and assignments
+/**********************************************************************/
+localparam CHANNEL_SEL_WIDTH = altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(CHANNELS-1);
+localparam ENABLED_JTAG_MASTERS = 1 + dbg_odi_soft_logic_enable + JTAG_ENABLED + RCFG_EMB_STRM_ENABLED + enable_pcie_dfe_ip;
+localparam RCFG_EMB_STRM_CFG_SEL_WIDTH = altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(RCFG_PROFILE_CNT-1);
+
+
+// Raw rmbedded reconfig signals (always independent)
+wire [CHANNELS-1:0] rcfg_emb_strm_write;
+wire [CHANNELS-1:0] rcfg_emb_strm_read;
+wire [CHANNELS*ADDR_BITS-1:0] rcfg_emb_strm_address;
+wire [CHANNELS*DATA_WIDTH-1:0] rcfg_emb_strm_writedata;
+wire [CHANNELS-1:0] rcfg_emb_strm_waitrequest;
+
+// User AVMM signals expanded to independent channels
+wire [CHANNELS-1:0] split_user_write;
+wire [CHANNELS-1:0] split_user_read;
+wire [CHANNELS*ADDR_BITS-1:0] split_user_address;
+wire [CHANNELS*DATA_WIDTH-1:0] split_user_writedata;
+wire [CHANNELS-1:0] split_user_waitrequest;
+
+// ODI AVMM signals
+wire [CHANNELS-1:0] odi_write;
+wire [CHANNELS-1:0] odi_read;
+wire [CHANNELS*ADDR_BITS-1:0] odi_address;
+wire [CHANNELS*DATA_WIDTH-1:0] odi_writedata;
+wire [CHANNELS-1:0] odi_waitrequest;
+
+// PCIe DFE ip
+wire [CHANNELS-1:0] split_pcie_dfe_write;
+wire [CHANNELS-1:0] split_pcie_dfe_read;
+wire [CHANNELS*ADDR_BITS-1:0] split_pcie_dfe_address;
+wire [CHANNELS*DATA_WIDTH-1:0] split_pcie_dfe_writedata;
+wire [CHANNELS-1:0] split_pcie_dfe_waitrequest;
+wire pcie_dfe_avmm_lock;
+
+// JTAG signals expanded to independent channels
+wire [CHANNELS-1:0] split_jtag_write;
+wire [CHANNELS-1:0] split_jtag_read;
+wire [CHANNELS*ADDR_BITS-1:0] split_jtag_address;
+wire [CHANNELS*DATA_WIDTH-1:0] split_jtag_writedata;
+wire [CHANNELS-1:0] split_jtag_waitrequest;
+
+// Additional arbitration signals for soft CSR
+wire [CHANNELS-1:0] chnl_write;
+wire [CHANNELS-1:0] chnl_read;
+wire [CHANNELS-1:0] chnl_busy;
+wire [CHANNELS-1:0] chnl_waitrequest;
+wire [CHANNELS*8-1:0] chnl_readdata;
+
+// embedded reconfig signals
+wire [CHANNELS-1:0] rcfg_emb_strm_busy;
+wire [CHANNELS-1:0] rcfg_emb_strm_chan_sel;
+wire [CHANNELS*RCFG_EMB_STRM_CFG_SEL_WIDTH-1:0] rcfg_emb_strm_cfg_sel;
+wire [CHANNELS-1:0] rcfg_emb_strm_bcast_en;
+wire [CHANNELS-1:0] rcfg_emb_strm_cfg_load;
+
+// Read_write signals to assist with prioritizing arbitrarion
+wire [CHANNELS-1:0] user_read_write;
+wire [CHANNELS-1:0] odi_read_write;
+wire [CHANNELS-1:0] pcie_dfe_read_write;
+wire [CHANNELS-1:0] jtag_read_write;
+wire [CHANNELS-1:0] rcfg_emb_strm_read_write;
+
+// Wires for converting between data widths
+wire [CHANNELS*DATA_WIDTH-1:0] expanded_avmm_readdata;
+wire [CHANNELS*DATA_WIDTH-1:0] expanded_avmm_writedata;
+
+// Wires for control and status signals between the various masters
+wire [CHANNELS-1:0] odi_done;
+wire [CHANNELS-1:0] prbs_done_sync;
+wire [CHANNELS*50-1:0] prbs_err_count;
+wire [CHANNELS*50-1:0] prbs_bit_count;
+wire [CHANNELS*50-1:0] odi_err_count;
+wire [CHANNELS*50-1:0] odi_bit_count;
+
+
+// Wires for qmap cleanup
+wire lcl_g_arbiter_dis;
+wire lcl_g_avmm_csr_dis;
+wire lcl_ground;
+
+// Warning Removal
+assign lcl_g_avmm_csr_dis = &{1'b0,
+ rcfg_emb_strm_busy,
+ prbs_done_sync,
+ odi_done,
+ prbs_err_count,
+ prbs_bit_count,
+ odi_bit_count,
+ odi_err_count};
+assign lcl_g_arbiter_dis = &{1'b0,
+ rcfg_emb_strm_address,
+ rcfg_emb_strm_writedata,
+ odi_address,
+ odi_writedata,
+ split_pcie_dfe_address,
+ split_pcie_dfe_writedata,
+ split_jtag_address,
+ split_jtag_writedata,
+ user_read_write,
+ odi_read_write,
+ pcie_dfe_read_write,
+ jtag_read_write,
+ rcfg_emb_strm_read_write};
+assign lcl_ground = &{1'b0,
+ lcl_g_avmm_csr_dis,
+ lcl_g_arbiter_dis};
+
+// Generate variable for channel numbers
+genvar ig;
+
+
+/**********************************************************************/
+// Generate Statement for the Shared vs Split user interface
+/**********************************************************************/
+generate
+ // Expand the AVMM signals from the channel to the 32-bit interface of the user
+ for(ig=0;ig<CHANNELS;ig=ig+1) begin: g_expanded_avmm_signals
+ assign expanded_avmm_readdata [ig*DATA_WIDTH +: DATA_WIDTH] = {24'd0,chnl_readdata [ig*8 +: 8]};
+ assign avmm_writedata [ig*8 +: 8] = expanded_avmm_writedata [ig*DATA_WIDTH +: 8];
+ end
+
+
+ /**********************************************************************/
+ // Split the reconfig interface to the independent channel when using shared reconfig
+ /**********************************************************************/
+ if(!RECONFIG_SHARED) begin : g_not_shared
+ // Signals are already split, so wire straight through
+ assign avmm_clk = reconfig_clk;
+ assign avmm_reset = reconfig_reset;
+
+ assign split_user_write = reconfig_write;
+ assign split_user_read = reconfig_read;
+ assign split_user_address = reconfig_address;
+ assign split_user_writedata = reconfig_writedata;
+ assign reconfig_readdata = expanded_avmm_readdata;
+ assign reconfig_waitrequest = ({CHANNELS{lcl_ground}} | split_user_waitrequest);
+
+ // If we are using a shared interface
+ end else begin : g_shared
+ wire [CHANNEL_SEL_WIDTH-1:0] rcfg_if_sel;
+
+ // Generate interface select based on upper address bits
+ assign rcfg_if_sel = reconfig_address[ADDR_BITS+:CHANNEL_SEL_WIDTH];
+ assign reconfig_readdata = expanded_avmm_readdata[rcfg_if_sel*DATA_WIDTH +: DATA_WIDTH];
+ assign reconfig_waitrequest = split_user_waitrequest[rcfg_if_sel];
+
+ for(ig=0;ig<CHANNELS;ig=ig+1) begin : g_shared
+ // Split shared signals to independent channels
+ assign avmm_clk [ig] = reconfig_clk;
+ assign avmm_reset [ig] = reconfig_reset;
+
+ assign split_user_write [ig] = reconfig_write & (rcfg_if_sel == ig) | lcl_ground;
+ assign split_user_read [ig] = reconfig_read & (rcfg_if_sel == ig);
+ assign split_user_address [ig*ADDR_BITS +: ADDR_BITS] = reconfig_address[0+:ADDR_BITS];
+ assign split_user_writedata [ig*DATA_WIDTH +: DATA_WIDTH] = reconfig_writedata;
+ end
+ end //End g_not_shared
+endgenerate
+
+
+/**********************************************************************/
+// Embedded JTAG Debug Master (ADME)
+/**********************************************************************/
+generate if(JTAG_ENABLED) begin : g_jtag
+
+ // Set the slave type for the ADME. Since the span needs to be a string, 2^(total addr_bits) will
+ // give the max value, however since the adme uses byte alignment, shift the span by two bits.
+ localparam set_slave_span = altera_xcvr_native_a10_functions_h::int2str_alt_xcvr_native_a10(2**(ADDR_BITS+CHANNEL_SEL_WIDTH+2));
+ localparam set_slave_map = {"{typeName ",ADME_SLAVE_MAP," address 0x0 span ",set_slave_span," hpath {}",ADME_ASSGN_MAP,"}"};
+
+ // Raw JTAG signals
+ wire jtag_write;
+ wire jtag_read;
+ wire [(ADDR_BITS+CHANNEL_SEL_WIDTH)-1:0] jtag_address;
+ wire [DATA_WIDTH-1:0] jtag_writedata;
+ wire [DATA_WIDTH-1:0] jtag_readdata;
+ wire jtag_waitrequest;
+ wire jtag_readdatavalid;
+ wire [CHANNEL_SEL_WIDTH-1:0] jtag_if_sel;
+
+ // Generate channel select based on upper address bits
+ assign jtag_if_sel = jtag_address[ADDR_BITS+:CHANNEL_SEL_WIDTH];
+ assign jtag_readdata = expanded_avmm_readdata[jtag_if_sel*DATA_WIDTH +: DATA_WIDTH];
+ assign jtag_waitrequest = split_jtag_waitrequest[jtag_if_sel];
+
+ // Split shared signals to independent channels
+ for(ig=0;ig<CHANNELS;ig=ig+1) begin: g_expanded_avmm_signals
+ assign split_jtag_write [ig] = jtag_write & (jtag_if_sel == ig);
+ assign split_jtag_read [ig] = jtag_read & (jtag_if_sel == ig);
+ assign split_jtag_address [ig*ADDR_BITS +: ADDR_BITS] = jtag_address[0+:ADDR_BITS];
+ assign split_jtag_writedata [ig*DATA_WIDTH +: DATA_WIDTH] = jtag_writedata[DATA_WIDTH-1:0];
+ end
+
+ // When doing RTL sims, remove the altera_debug_master_endpoint, as
+ // there is no RTL simulation model. Pre and Post Fit sims are ok.
+ `ifdef ALTERA_RESERVED_QIS
+ altera_debug_master_endpoint
+ #(
+ .ADDR_WIDTH ( (ADDR_BITS+CHANNEL_SEL_WIDTH) ),
+ .DATA_WIDTH ( DATA_WIDTH ),
+ .HAS_RDV ( 0 ),
+ .SLAVE_MAP ( set_slave_map ),
+ .PREFER_HOST ( " " ),
+ .CLOCK_RATE_CLK ( 0 )
+ ) adme (
+ .clk ( reconfig_clk ),
+ .reset ( reconfig_reset ),
+ .master_write ( jtag_write ),
+ .master_read ( jtag_read ),
+ .master_address ( jtag_address ),
+ .master_writedata ( jtag_writedata ),
+ .master_waitrequest ( jtag_waitrequest ),
+ .master_readdatavalid ( jtag_readdatavalid ),
+ .master_readdata ( jtag_readdata )
+ );
+ `else
+ assign jtag_write = 1'b0;
+ assign jtag_read = 1'b0;
+ assign jtag_address = {(ADDR_BITS+CHANNEL_SEL_WIDTH){1'b0}};
+ assign jtag_writedata = {DATA_WIDTH{1'b0}};
+ `endif
+
+ // If we have not enabled the ADME
+ end else begin : g_jtag_disable
+ assign split_jtag_write = {CHANNELS{1'b0}};
+ assign split_jtag_read = {CHANNELS{1'b0}};
+ assign split_jtag_address = {(CHANNELS*ADDR_BITS){1'b0}};
+ assign split_jtag_writedata = {(CHANNELS*DATA_WIDTH){1'b0}};
+ end
+endgenerate // End g_jtag
+
+
+/**********************************************************************/
+// Enable the PCIe DFE IP
+/**********************************************************************/
+generate if(enable_pcie_dfe_ip) begin : g_pcie_dfe_ip
+ // Raw JTAG signals
+ wire pcie_dfe_write;
+ wire pcie_dfe_read;
+ wire [(ADDR_BITS+CHANNEL_SEL_WIDTH)-1:0] pcie_dfe_address;
+ wire [DATA_WIDTH-1:0] pcie_dfe_writedata;
+ wire [DATA_WIDTH-1:0] pcie_dfe_readdata;
+ wire pcie_dfe_waitrequest;
+ wire [CHANNEL_SEL_WIDTH-1:0] pcie_dfe_if_sel;
+
+ // Generate channel select based on upper address bits
+ assign pcie_dfe_if_sel = pcie_dfe_address[ADDR_BITS+:CHANNEL_SEL_WIDTH];
+ assign pcie_dfe_readdata = expanded_avmm_readdata[pcie_dfe_if_sel*DATA_WIDTH +: DATA_WIDTH];
+ assign pcie_dfe_waitrequest = split_pcie_dfe_waitrequest[pcie_dfe_if_sel];
+
+ // Split shared signals to independent channels
+ for(ig=0;ig<CHANNELS;ig=ig+1) begin: g_expanded_avmm_signals
+ assign split_pcie_dfe_write [ig] = pcie_dfe_write & (pcie_dfe_if_sel == ig);
+ assign split_pcie_dfe_read [ig] = pcie_dfe_read & (pcie_dfe_if_sel == ig);
+ assign split_pcie_dfe_address [ig*ADDR_BITS +: ADDR_BITS] = pcie_dfe_address[0+:ADDR_BITS];
+ assign split_pcie_dfe_writedata [ig*DATA_WIDTH +: DATA_WIDTH] = pcie_dfe_writedata[DATA_WIDTH-1:0];
+ end
+
+
+ altera_xcvr_native_pcie_dfe_ip #(
+ .num_channels ( CHANNELS ),
+ .disable_continuous_dfe ( disable_continuous_dfe ),
+ .enable_hip ( enable_hip ),
+ .sim_reduced_counters ( sim_reduced_counters ),
+ .avmm_sel_bits ( CHANNEL_SEL_WIDTH ),
+ .avmm_addr_bits ( ADDR_BITS )
+ ) altera_xcvr_native_pcie_dfe_ip_inst (
+ .clock ( reconfig_clk ),
+ .reset ( reconfig_reset ),
+ .ltssm_detect_quiet ( ltssm_detect_quiet ),
+ .ltssm_detect_active ( ltssm_detect_active ),
+ .ltssm_rcvr_phase_two ( ltssm_rcvr_phase_two ),
+ .pcie_rate_sw ( pcie_rate ),
+
+ // HIP only port for reduced counters
+ .hip_reduce_counters ( hip_reduce_counters ),
+
+ // Reconfig Interface to the transceiver
+ .xcvr_rcfg_waitrequest ( pcie_dfe_waitrequest ),
+ .xcvr_rcfg_readdata ( pcie_dfe_readdata ),
+ .xcvr_rcfg_lock ( pcie_dfe_avmm_lock ),
+ .xcvr_rcfg_read ( pcie_dfe_read ),
+ .xcvr_rcfg_write ( pcie_dfe_write ),
+ .xcvr_rcfg_address ( pcie_dfe_address ),
+ .xcvr_rcfg_writedata ( pcie_dfe_writedata )
+ );
+
+ end else begin : g_disable_pcie_dfe_ip
+ assign pcie_dfe_avmm_lock = 1'b0;
+ assign split_pcie_dfe_write = {CHANNELS{1'b0}};
+ assign split_pcie_dfe_read = {CHANNELS{1'b0}};
+ assign split_pcie_dfe_address = {(CHANNELS*ADDR_BITS){1'b0}};
+ assign split_pcie_dfe_writedata = {(CHANNELS*DATA_WIDTH){1'b0}};
+ end
+endgenerate
+
+
+/**********************************************************************/
+// Embedded Reconfig Streamer
+/**********************************************************************/
+generate if(RCFG_EMB_STRM_ENABLED) begin : g_rcfg_strm_enable //TODO check to see if there is parameter redundancy
+
+ alt_xcvr_native_rcfg_strm_top_sfv7jkq #(
+ .xcvr_rcfg_interfaces ( CHANNELS ),
+ .xcvr_rcfg_addr_width ( ADDR_BITS ),
+ .xcvr_rcfg_data_width ( DATA_WIDTH ),
+ .rcfg_profile_cnt ( RCFG_PROFILE_CNT )
+ )rcfg_strm_top_inst(
+ .clk ( reconfig_clk[0] ), // All clock bits should be driven by the same source if using independent interface
+ .reset ( |reconfig_reset ), // Any reset bit will reset the reconfig streamer
+ .cfg_sel ( rcfg_emb_strm_cfg_sel ),
+ .bcast_en ( rcfg_emb_strm_bcast_en ),
+ .cfg_load ( rcfg_emb_strm_cfg_load ),
+ .chan_sel ( rcfg_emb_strm_chan_sel ),
+ .stream_busy ( rcfg_emb_strm_busy ),
+ .xcvr_reconfig_write ( rcfg_emb_strm_write ),
+ .xcvr_reconfig_read ( rcfg_emb_strm_read ),
+ .xcvr_reconfig_address ( rcfg_emb_strm_address ),
+ .xcvr_reconfig_writedata ( rcfg_emb_strm_writedata ),
+ .xcvr_reconfig_readdata ( expanded_avmm_readdata ),
+ .xcvr_reconfig_waitrequest ( rcfg_emb_strm_waitrequest )
+ );
+
+ // If we disable the reconfig streamer
+ end else begin: g_rcfg_strm_disable
+ assign rcfg_emb_strm_write = {CHANNELS{1'b0}};
+ assign rcfg_emb_strm_read = {CHANNELS{1'b0}};
+ assign rcfg_emb_strm_address = {(CHANNELS*ADDR_BITS){1'b0}};
+ assign rcfg_emb_strm_writedata = {CHANNELS{32'b0}};
+ assign rcfg_emb_strm_busy = {CHANNELS{1'b0}};
+ end
+endgenerate // End g_rcfg_strm_enable
+
+
+/**********************************************************************/
+// AVMM Master read/write signals.
+/**********************************************************************/
+assign user_read_write = split_user_read | split_user_write; // Bits asserted for corresponding channels from/to which user avmm is currently reading/writing
+assign jtag_read_write = split_jtag_read | split_jtag_write; // Bits asserted for corresponding channels from/to which jtag is currently reading/writing
+assign rcfg_emb_strm_read_write = rcfg_emb_strm_read | rcfg_emb_strm_write; // Bits asserted for corresponding channels from/to which embedded streamer is currently reading/writing
+assign odi_read_write = odi_read | odi_write;
+assign pcie_dfe_read_write = split_pcie_dfe_read | split_pcie_dfe_write | {CHANNELS{pcie_dfe_avmm_lock}};
+
+/**********************************************************************/
+// AVMM Arbiter. Instantiated once per channel, however to handle streaming
+// broadcast, the channel-wise instantiation is handled within the arbiter.
+/**********************************************************************/
+generate if (ENABLED_JTAG_MASTERS > 1) begin: g_arbiber_enable
+ alt_xcvr_native_rcfg_arb #(
+ .total_masters ( 5 ),
+ .channels ( CHANNELS ),
+ .address_width ( ADDR_BITS ),
+ .data_width ( DATA_WIDTH )
+ ) alt_xcvr_rcfg_arb (
+ // Basic AVMM inputs
+ .reconfig_clk ( avmm_clk ),
+ .reconfig_reset ( avmm_reset ),
+
+ // User AVMM input
+ .user_read ( split_user_read ),
+ .user_write ( split_user_write ),
+ .user_address ( split_user_address ),
+ .user_writedata ( split_user_writedata ),
+ .user_read_write ( user_read_write ),
+ .user_waitrequest ( split_user_waitrequest ),
+
+ // Reconfig Steamer AVMM input
+ .strm_read ( rcfg_emb_strm_read ),
+ .strm_write ( rcfg_emb_strm_write ),
+ .strm_address ( rcfg_emb_strm_address ),
+ .strm_writedata ( rcfg_emb_strm_writedata ),
+ .strm_read_write ( rcfg_emb_strm_read_write ),
+ .strm_waitrequest ( rcfg_emb_strm_waitrequest ),
+
+ // ODI AVMM input
+ .odi_read ( odi_read ),
+ .odi_write ( odi_write ),
+ .odi_address ( odi_address ),
+ .odi_writedata ( odi_writedata ),
+ .odi_read_write ( odi_read_write ),
+ .odi_waitrequest ( odi_waitrequest ),
+
+ // ADME AVMM input
+ .jtag_read ( split_jtag_read ),
+ .jtag_write ( split_jtag_write ),
+ .jtag_address ( split_jtag_address ),
+ .jtag_writedata ( split_jtag_writedata ),
+ .jtag_read_write ( jtag_read_write ),
+ .jtag_waitrequest ( split_jtag_waitrequest ),
+
+ // PCIe DFE
+ .pcie_dfe_read ( split_pcie_dfe_read ),
+ .pcie_dfe_write ( split_pcie_dfe_write ),
+ .pcie_dfe_address ( split_pcie_dfe_address ),
+ .pcie_dfe_writedata ( split_pcie_dfe_writedata ),
+ .pcie_dfe_read_write ( pcie_dfe_read_write ),
+ .pcie_dfe_waitrequest ( split_pcie_dfe_waitrequest ),
+
+ // AVMM output the channel and the CSR
+ .avmm_waitrequest ( chnl_waitrequest ),
+ .avmm_read ( chnl_read ),
+ .avmm_write ( chnl_write ),
+ .avmm_address ( avmm_address ),
+ .avmm_writedata ( expanded_avmm_writedata )
+ );
+ end else begin: g_arbiter_disable
+ // Pass through signals
+ assign split_user_waitrequest = chnl_waitrequest;
+ assign chnl_read = split_user_read;
+ assign chnl_write = split_user_write;
+ assign expanded_avmm_writedata = split_user_writedata;
+ assign avmm_address = split_user_address;
+
+ end
+endgenerate // End g_arbiter
+
+
+/**********************************************************************/
+// Per Channel instantiations and assignments
+/**********************************************************************/
+generate for(ig=0;ig<CHANNELS;ig=ig+1) begin: g_optional_chnl_reconfig_logic
+
+wire [CHANNELS-1:0] csr_prbs_snapshot;
+wire [CHANNELS-1:0] csr_prbs_count_en;
+wire [CHANNELS-1:0] csr_odi_count_en;
+wire [CHANNELS-1:0] csr_odi_snap;
+wire [CHANNELS-1:0] csr_odi_reset;
+
+ /**********************************************************************/
+ // Instantiate the Soft CSR
+ /**********************************************************************/
+ if(dbg_embedded_debug_enable) begin: g_avmm_csr_enabled
+
+ // Instantiate wires as part of generate to avoid warnings about unused wires.
+ // AVMM reconfiguration signals for embedded debug
+ wire [CHANNELS-1:0] debug_write;
+ wire [CHANNELS-1:0] debug_read;
+ wire [CHANNELS-1:0] debug_waitrequest;
+ wire [CHANNELS*8-1:0] debug_readdata;
+
+ // avmm arbitration for soft csr and channel
+ assign debug_read [ig] = (avmm_address[ig*ADDR_BITS+9]) ? chnl_read [ig] : 1'b0;
+ assign debug_write [ig] = (avmm_address[ig*ADDR_BITS+9]) ? chnl_write [ig] : 1'b0;
+ assign avmm_read [ig] = (avmm_address[ig*ADDR_BITS+9]) ? 1'b0 : chnl_read [ig];
+ assign avmm_write [ig] = (avmm_address[ig*ADDR_BITS+9]) ? 1'b0 : chnl_write [ig];
+ assign chnl_waitrequest [ig] = (avmm_address[ig*ADDR_BITS+9]) ? debug_waitrequest [ig] : avmm_waitrequest [ig];
+ assign chnl_readdata [ig*8+:8] = (avmm_address[ig*ADDR_BITS+9]) ? debug_readdata [ig*8+:8] : avmm_readdata [ig*8+:8];
+
+
+ alt_xcvr_native_avmm_csr #(
+ .channels ( CHANNELS ),
+ .channel_num ( ig ),
+ .dbg_user_identifier ( dbg_user_identifier ),
+ .duplex_mode ( duplex_mode ),
+ .dbg_capability_reg_enable ( dbg_capability_reg_enable ),
+ .dbg_prbs_soft_logic_enable ( dbg_prbs_soft_logic_enable ),
+ .dbg_odi_soft_logic_enable ( dbg_odi_soft_logic_enable ),
+ .dbg_stat_soft_logic_enable ( dbg_stat_soft_logic_enable ),
+ .dbg_ctrl_soft_logic_enable ( dbg_ctrl_soft_logic_enable ),
+ .rcfg_emb_strm_enable ( RCFG_EMB_STRM_ENABLED ),
+ .rcfg_emb_strm_cfg_sel_width ( RCFG_EMB_STRM_CFG_SEL_WIDTH )
+ ) embedded_debug_soft_csr (
+ // avmm signals
+ .avmm_clk ( avmm_clk [ig] ),
+ .avmm_reset ( avmm_reset [ig] ),
+ .avmm_address ( avmm_address [ig*ADDR_BITS+:9] ),
+ .avmm_writedata ( avmm_writedata [ig*8+:8] ),
+ .avmm_write ( debug_write [ig] ),
+ .avmm_read ( debug_read [ig] ),
+ .avmm_readdata ( debug_readdata [ig*8+:8] ),
+ .avmm_waitrequest ( debug_waitrequest [ig] ),
+
+ // prbs control signals
+ .prbs_err ( prbs_err_count [ig*50+:50]),
+ .prbs_bit ( prbs_bit_count [ig*50+:50]),
+ .prbs_done ( prbs_done_sync [ig] ),
+ .prbs_snap ( csr_prbs_snapshot [ig] ),
+ .prbs_count_en ( csr_prbs_count_en [ig] ),
+ .prbs_reset ( out_prbs_err_clr [ig] ),
+
+ // odi ctrl signals
+ .odi_bit ( odi_bit_count [ig*50+:50]),
+ .odi_err ( odi_err_count [ig*50+:50]),
+ .odi_done ( odi_done [ig] ),
+ .odi_count_en ( csr_odi_count_en [ig] ),
+ .odi_reset ( csr_odi_reset [ig] ),
+ .odi_snap ( csr_odi_snap [ig] ),
+
+ // input status signals from the channel
+ .rx_is_lockedtodata ( in_rx_is_lockedtodata [ig] ),
+ .rx_is_lockedtoref ( in_rx_is_lockedtoref [ig] ),
+ .tx_cal_busy ( in_tx_cal_busy [ig] ),
+ .rx_cal_busy ( in_rx_cal_busy [ig] ),
+ .avmm_busy ( in_avmm_busy [ig] ),
+
+ // input control signals
+ .rx_prbs_err_clr ( in_rx_prbs_err_clr [ig] ),
+ .set_rx_locktoref ( in_set_rx_locktoref [ig] ),
+ .set_rx_locktodata ( in_set_rx_locktodata [ig] ),
+ .serial_loopback ( in_en_serial_lpbk [ig] ),
+ .rx_analogreset ( in_rx_analogreset [ig] ),
+ .rx_digitalreset ( in_rx_digitalreset [ig] ),
+ .tx_analogreset ( in_tx_analogreset [ig] ),
+ .tx_digitalreset ( in_tx_digitalreset [ig] ),
+
+ // embedded reconfig signals
+ .rcfg_emb_strm_busy ( rcfg_emb_strm_busy [ig] ),
+ .rcfg_emb_strm_chan_sel ( rcfg_emb_strm_chan_sel [ig] ),
+ .rcfg_emb_strm_cfg_sel ( rcfg_emb_strm_cfg_sel [ig*RCFG_EMB_STRM_CFG_SEL_WIDTH+:RCFG_EMB_STRM_CFG_SEL_WIDTH]),
+ .rcfg_emb_strm_bcast_en ( rcfg_emb_strm_bcast_en [ig] ),
+ .rcfg_emb_strm_cfg_load ( rcfg_emb_strm_cfg_load [ig] ),
+
+
+ // output control signals to the channel
+ .csr_set_lock_to_data ( out_set_rx_locktodata [ig] ),
+ .csr_set_lock_to_ref ( out_set_rx_locktoref [ig] ),
+ .csr_en_loopback ( out_en_serial_lpbk [ig] ),
+ .csr_rx_analogreset ( out_rx_analogreset [ig] ),
+ .csr_rx_digitalreset ( out_rx_digitalreset [ig] ),
+ .csr_tx_analogreset ( out_tx_analogreset [ig] ),
+ .csr_tx_digitalreset ( out_tx_digitalreset [ig] ),
+ .csr_tx_cal_busy_mask ( out_tx_cal_busy_mask [ig] ),
+ .csr_rx_cal_busy_mask ( out_rx_cal_busy_mask [ig] )
+ );
+
+ end else begin: g_avmm_csr_disable
+ // do a pass though for control signals when no embedded debug
+ assign out_prbs_err_clr [ig] = in_rx_prbs_err_clr [ig];
+ assign out_set_rx_locktoref [ig] = in_set_rx_locktoref [ig];
+ assign out_set_rx_locktodata [ig] = in_set_rx_locktodata [ig];
+ assign out_en_serial_lpbk [ig] = in_en_serial_lpbk [ig];
+ assign out_rx_analogreset [ig] = in_rx_analogreset [ig];
+ assign out_rx_digitalreset [ig] = in_rx_digitalreset [ig];
+ assign out_tx_analogreset [ig] = in_tx_analogreset [ig];
+ assign out_tx_digitalreset [ig] = in_tx_digitalreset [ig];
+ assign out_tx_cal_busy_mask [ig] = 1'b1;
+ assign out_rx_cal_busy_mask [ig] = 1'b1;
+
+ // assign these signals to ground when no embedded debug
+ assign avmm_read [ig] = chnl_read [ig];
+ assign avmm_write [ig] = chnl_write [ig];
+ assign chnl_waitrequest [ig] = avmm_waitrequest [ig];
+ assign chnl_readdata [ig*8+:8] = avmm_readdata [ig*8+:8];
+ end
+
+
+ /**********************************************************************/
+ // Instantiate the PRBS accumulators
+ /**********************************************************************/
+ if(dbg_prbs_soft_logic_enable == 1) begin: g_prbs_accumulators_enable
+ alt_xcvr_native_prbs_accum prbs_soft_accumulators (
+ .avmm_clk ( avmm_clk [ig] ),
+ .avmm_reset ( avmm_reset [ig] ),
+
+ // Control signals from CSR
+ .prbs_reset ( out_prbs_err_clr [ig] ),
+ .prbs_snapshot ( csr_prbs_snapshot [ig] ),
+ .prbs_counter_en ( csr_prbs_count_en [ig] ),
+
+ // Status signals from PRBS
+ .prbs_done_sync ( prbs_done_sync [ig] ),
+ .prbs_err_count ( prbs_err_count [ig*50+:50] ),
+ .prbs_bit_count ( prbs_bit_count [ig*50+:50] ),
+
+ // Signals from the transceiver
+ .rx_clkout ( in_rx_clkout [ig] ),
+ .prbs_err_signal ( prbs_err_signal [ig] ),
+ .prbs_done_signal ( prbs_done_signal [ig] )
+ );
+
+ // If PRBS is not enabled
+ end else begin: g_prbs_accumulators_disable
+ assign prbs_err_count[ig*50+:50] = 50'b0;
+ assign prbs_bit_count[ig*50+:50] = 50'b0;
+ assign prbs_done_sync[ig] = 1'b0;
+ end // End g_prbs_accumulators
+
+
+ /**********************************************************************/
+ // Instantiate the ODI accumulators
+ /**********************************************************************/
+ if(dbg_odi_soft_logic_enable == 1) begin: g_odi_accelerator_enable
+ alt_xcvr_native_odi_accel #(
+ .DATA_WIDTH ( DATA_WIDTH )
+ ) odi_soft_accelerator (
+ .avmm_clk ( avmm_clk [ig] ),
+ .avmm_reset ( avmm_reset [ig] ),
+
+ // AVMM signals to the transceiver
+ .odi_read ( odi_read [ig] ),
+ .odi_write ( odi_write [ig] ),
+ .odi_address ( odi_address [ig*ADDR_BITS+:ADDR_BITS] ),
+ .odi_writedata ( odi_writedata [ig*DATA_WIDTH+:DATA_WIDTH]),
+ .odi_readdata ( avmm_readdata [ig*8+:8] ),
+ .odi_waitrequest ( odi_waitrequest [ig] ),
+
+ // Control signals from CSR
+ .odi_count_en ( csr_odi_count_en [ig] ),
+ .odi_snap ( csr_odi_snap [ig] ),
+ .odi_reset ( csr_odi_reset [ig] ),
+
+ // Status signals from ODI
+ .odi_done ( odi_done [ig] ),
+ .odi_bit_count ( odi_bit_count [ig*50+:50] ),
+ .odi_err_count ( odi_err_count [ig*50+:50] )
+ );
+
+ end else begin: g_odi_accelerator_disable
+ assign odi_read[ig] = 1'b0;
+ assign odi_write[ig] = 1'b0;
+ assign odi_done[ig] = 1'b0;
+ assign odi_bit_count[ig*50+:50] = 50'b0;
+ assign odi_err_count[ig*50+:50] = 50'b0;
+ assign odi_address[ig*ADDR_BITS+:ADDR_BITS] = {ADDR_BITS{1'b0}};
+ assign odi_writedata[ig*DATA_WIDTH+:DATA_WIDTH] = {DATA_WIDTH{1'b0}};
+ end // End g_odi_accelerator
+
+ end // End for Loop for channels
+endgenerate
+
+endmodule
+
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_resync.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_resync.sv
new file mode 100644
index 0000000000000000000000000000000000000000..2f0f3fe0b7b8c3b0f584954c44bc70c1ddd88480
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/alt_xcvr_resync.sv
@@ -0,0 +1,97 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Module: alt_xcvr_resync
+//
+// Description:
+// A general purpose resynchronization module.
+//
+// Parameters:
+// SYNC_CHAIN_LENGTH
+// - Specifies the length of the synchronizer chain for metastability
+// retiming.
+// WIDTH
+// - Specifies the number of bits you want to synchronize. Controls the width of the
+// d and q ports.
+// SLOW_CLOCK - USE WITH CAUTION.
+// - Leaving this setting at its default will create a standard resynch circuit that
+// merely passes the input data through a chain of flip-flops. This setting assumes
+// that the input data has a pulse width longer than one clock cycle sufficient to
+// satisfy setup and hold requirements on at least one clock edge.
+// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
+// circuit that will capture the input data regardless of the pulse width and
+// its relationship to the clock. However it is more difficult to apply static
+// timing constraints as it ties the data input to the clock input of the flop.
+// This implementation assumes the data rate is slow enough
+// INIT_VALUE
+// - Specifies the initial values of the synchronization registers.
+//
+// Apply embedded false path timing constraint
+(* altera_attribute = "-name SDC_STATEMENT \"set regs [get_registers -nowarn *alt_xcvr_resync*sync_r[0]]; if {[llength [query_collection -report -all $regs]] > 0} {set_false_path -to $regs}\"" *)
+
+`timescale 1ps/1ps
+
+module alt_xcvr_resync #(
+ parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming. Must be >1
+ parameter WIDTH = 1, // Number of bits to resync
+ parameter SLOW_CLOCK = 0, // See description above
+ parameter INIT_VALUE = 0
+ ) (
+ input wire clk,
+ input wire reset,
+ input wire [WIDTH-1:0] d,
+ output wire [WIDTH-1:0] q
+ );
+
+localparam INT_LEN = (SYNC_CHAIN_LENGTH > 1) ? SYNC_CHAIN_LENGTH : 2;
+localparam [INT_LEN-1:0] L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};
+
+genvar ig;
+
+// Generate a synchronizer chain for each bit
+generate begin
+ for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
+ wire d_in; // Input to sychronization chain.
+ (* altera_attribute = "disable_da_rule=D103" *)
+ reg [INT_LEN-1:0] sync_r = L_INIT_VALUE;
+
+ assign q[ig] = sync_r[INT_LEN-1]; // Output signal
+
+ always @(posedge clk or posedge reset)
+ if(reset)
+ sync_r <= L_INIT_VALUE;
+ else
+ sync_r <= {sync_r[INT_LEN-2:0],d_in};
+
+ // Generate asynchronous capture circuit if specified.
+ if(SLOW_CLOCK == 0) begin
+ assign d_in = d[ig];
+ end else begin
+ wire d_clk;
+ reg d_r = L_INIT_VALUE[0];
+ wire clr_n;
+
+ assign d_clk = d[ig];
+ assign d_in = d_r;
+ assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
+
+ // Asynchronously latch the input signal.
+ always @(posedge d_clk or negedge clr_n)
+ if(!clr_n) d_r <= 1'b0;
+ else if(d_clk) d_r <= 1'b1;
+ end // SLOW_CLOCK
+ end // for loop
+end // generate
+endgenerate
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_a10_false_paths.sdc b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_a10_false_paths.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..158c2a2e08b872c2db2461c3aaaa8643b7673b0d
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_a10_false_paths.sdc
@@ -0,0 +1,184 @@
+# (C) 2001-2023 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions and other
+# software and tools, and its AMPP partner logic functions, and any output
+# files from any of the foregoing (including device programming or simulation
+# files), and any associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License Subscription
+# Agreement, Intel FPGA IP License Agreement, or other applicable
+# license agreement, including, without limitation, that your use is for the
+# sole purpose of programming logic devices manufactured by Intel and sold by
+# Intel or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+
+# For more information, please refer to the Transceiver User Guide.
+
+# Non-bonded Native PHY configurations
+#
+# False paths can be set on tx_digitalreset because each channel is
+# independent of every other channel in the same instance. Use the false
+# path exceptions to remove the tx_digialreset dependency. The following
+# three constraints can be enabled and must be modified to include the
+# name of the native phy instance to avoid accidentally constraining
+# tx_digitalresets for unrelated Native PHY instances.
+#
+# set_false_path -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_pmaif_tx_pld_rst_n]
+# set_false_path -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_8g_g3_tx_pld_rst_n]
+# set_false_path -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_10g_krfec_tx_pld_rst_n]
+
+
+# Bonded Native PHY configurations
+#
+# A false path cannot be set on tx_digitalreset from the reset controller
+# since a skew relationship for tx_digitalreset to the transceiver channels
+# must be maintained. The -exlude to_clock ensures the that the data delay
+# is matched between channels. The following constraints should be modified for
+# hierarchy and skew to match design requirements, where the max_skew should
+# satisfy the following: max_skew = tx_clkout_period/2. The 1ns skew covers
+# tx_clkout frequency of 500Mhz, and can be relaxed based upon the design.
+
+# set_max_skew -exclude to_clock \
+ -from [get_registers *altera_xcvr_reset_control*tx_digitalreset*r_reset] \
+ -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_*_tx_pld_rst_n] 1ns
+
+# To allow the max_skew constraint to be honored while avoiding recover/removal
+# violations, the reset paths are further constrained with a min/max delay. By
+# setting a a large min/max delay, the signal is, for all intents and purposes,
+# unbounded, and will be treated as if it were a false path. This gives the
+# benefits of set_false_path exception while allowing the path to be further
+# constrained to meet design requirements. These min/max delay constraints
+# are NOT the same as a false path, and in non-bonded configuration, where
+# applicable, a flase path should be set.
+
+if { [get_collection_size [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_pmaif_tx_pld_rst_n]] > 0 } {
+ set_max_delay -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_pmaif_tx_pld_rst_n] 50ns
+ set_min_delay -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_pmaif_tx_pld_rst_n] -50ns
+}
+
+if { [get_collection_size [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_8g_g3_tx_pld_rst_n]] > 0 } {
+ set_max_delay -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_8g_g3_tx_pld_rst_n] 50ns
+ set_min_delay -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_8g_g3_tx_pld_rst_n] -50ns
+}
+
+if { [get_collection_size [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_10g_krfec_tx_pld_rst_n]] > 0 } {
+ set_max_delay -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_10g_krfec_tx_pld_rst_n] 50ns
+ set_min_delay -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_10g_krfec_tx_pld_rst_n] -50ns
+}
+
+# PCS liberty files have been modified to add a 0 recovery check
+# The two SDCs below bound tx_analogreset and rx_analogreset
+if { [get_collection_size [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_pma_txpma_rstb]] > 0 } {
+ set_max_delay -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_pma_txpma_rstb] 20ns
+ set_min_delay -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_pma_txpma_rstb] -10ns
+}
+
+if { [get_collection_size [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_pma_rxpma_rstb]] > 0 } {
+ set_max_delay -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_pma_rxpma_rstb] 20ns
+ set_min_delay -to [get_pins -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_pma_rxpma_rstb] -10ns
+}
+
+
+# Create a set of all asynchronous signals to be looped over for setting false paths
+set altera_xcvr_native_a10_async_signals {
+ pld_10g_krfec_rx_pld_rst_n
+ pld_10g_krfec_rx_clr_errblk_cnt
+ pld_10g_rx_clr_ber_count
+ pld_10g_tx_diag_status
+ pld_10g_tx_bitslip
+ pld_8g_g3_rx_pld_rst_n
+ pld_8g_a1a2_size
+ pld_8g_bitloc_rev_en
+ pld_8g_byte_rev_en
+ pld_8g_encdt
+ pld_8g_tx_boundary_sel
+ pld_8g_rxpolarity
+ pld_pmaif_rx_pld_rst_n
+ pld_bitslip
+ pld_rx_prbs_err_clr
+ pld_polinv_tx
+ pld_polinv_rx
+}
+
+if { [ info exists altera_xcvr_native_a10_async_xcvr_pins ] } {
+ unset altera_xcvr_native_a10_async_xcvr_pins
+}
+
+# Set false paths for each item in the set
+foreach altera_xcvr_native_a10_async_signale_name $altera_xcvr_native_a10_async_signals {
+ set altera_xcvr_native_a10_async_xcvr_pins [get_pins -nowarn -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|${altera_xcvr_native_a10_async_signale_name}*]
+ if { [get_collection_size $altera_xcvr_native_a10_async_xcvr_pins] > 0 } {
+ set_false_path -to $altera_xcvr_native_a10_async_xcvr_pins
+ }
+}
+
+# pld_10g_rx_align_clr pin has two timing arcs; one w.r.t rx_coreclkin and the other w.r.t rx_pma_clk (case:294191)
+# The arc w.r.t rx_pma_clk is asynchronous, distinguishing the arcs based on destination register name
+# To Node: pld_10g_rx_align_clr_reg.reg -> rx_pma_clk
+# To Node: pld_10g_rx_align_clr_fifo.reg -> rx_coreclkin
+set altera_xcvr_native_a10_async_xcvr_pins [get_pins -nowarn -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_10g_rx_align_clr*]
+if {[get_collection_size $altera_xcvr_native_a10_async_xcvr_pins] > 0} {
+ set_false_path -to *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*inst_twentynm_hssi_10g_rx_pcs~pld_10g_rx_align_clr_reg.reg
+}
+
+# For TX burst enable, even though its an asynchronous signal, set a bound, since we need the fitter to place it some-what close to the periphery for interlaken
+set altera_xcvr_native_a10_async_xcvr_pins [get_pins -nowarn -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_10g_tx_burst_en*]
+if { [get_collection_size $altera_xcvr_native_a10_async_xcvr_pins] > 0 } {
+ set_max_delay -to $altera_xcvr_native_a10_async_xcvr_pins 20ns
+ set_min_delay -to $altera_xcvr_native_a10_async_xcvr_pins -20ns
+}
+
+# When using the PRBS Error Accumulation logic, set multicycle constraints to reduce routing effor and congestion. Also false path the asynchronous resets
+if { [get_collection_size [get_registers -nowarn *xcvr_native*optional_chnl_reconfig_logic*prbs_accumulators_enable*prbs_soft_accumulators\|rx_prbs_err_snapshot*]] > 0 } {
+ set_max_delay -from [get_registers *xcvr_native*optional_chnl_reconfig_logic*prbs_accumulators_enable*prbs_soft_accumulators\|rx_prbs_err_snapshot*] \
+ -to [get_registers *xcvr_native*optional_chnl_reconfig_logic*prbs_accumulators_enable*prbs_soft_accumulators\|avmm_prbs_err_count*] \
+ 15
+ set_min_delay -from [get_registers *xcvr_native*optional_chnl_reconfig_logic*prbs_accumulators_enable*prbs_soft_accumulators\|rx_prbs_err_snapshot*] \
+ -to [get_registers *xcvr_native*optional_chnl_reconfig_logic*prbs_accumulators_enable*prbs_soft_accumulators\|avmm_prbs_err_count*] \
+ -8
+
+ set_false_path -through [get_pins -compatibility_mode *xcvr_native*optional_chnl_reconfig_logic*prbs_accumulators_enable*prbs_soft_accumulators\|rx_clk_reset_sync*sync_r*clrn] \
+ -to [get_registers *xcvr_native*optional_chnl_reconfig_logic*prbs_accumulators_enable*prbs_soft_accumulators\|rx_clk_reset_sync*sync_r[?]]
+ set_false_path -from [get_registers *xcvr_native*optional_chnl_reconfig_logic*avmm_csr_enabled*embedded_debug_soft_csr*prbs_reg*] \
+ -to [get_registers *xcvr_native*optional_chnl_reconfig_logic*prbs_accumulators_enable*prbs_soft_accumulators\|rx_clk_prbs_reset_sync*sync_r[?]]
+}
+
+# When the PIPE Retry circuit is enabled for Gen2, include the following SDC constraint
+if { [get_collection_size [get_registers -nowarn *xcvr_native*alt_xcvr_native_pipe_retry*hv_sync_retry_rate*]] > 0 } {
+ if { [string equal "quartus_sta" $::TimeQuestInfo(nameofexecutable)] } {
+ set altera_xcvr_native_a10_pld_rate [get_pins -nowarn -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*\|pld_rate*]
+ if { [get_collection_size $altera_xcvr_native_a10_pld_rate] > 0 } {
+ set_false_path -to $altera_xcvr_native_a10_pld_rate
+ }
+ }
+
+ set_false_path -through [get_pins -nowarn -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*pld_test_data*] \
+ -to [get_registers *xcvr_native*alt_xcvr_native_pipe_retry*pma_pld_rate_sync[0]]
+ set_false_path -through [get_pins -nowarn -compatibility_mode *twentynm_xcvr_native_inst\|*inst_twentynm_pcs\|*twentynm_hssi_*_pld_pcs_interface*pld_test_data*] \
+ -to [get_registers *xcvr_native*alt_xcvr_native_pipe_retry*pma_pld_rate_sync[1]]
+ set_false_path -to [get_registers *xcvr_native*alt_xcvr_native_pipe_retry*tx_digitalreset_pclk_inst*sync_r[*]]
+ set_false_path -to [get_registers *xcvr_native*alt_xcvr_native_pipe_retry*tx_digitalreset_hv_inst*sync_r[*]]
+ set_max_delay -from [get_registers *xcvr_native*alt_xcvr_native_pipe_retry*hv_sync_vec_pipe_rate*] \
+ -to [get_registers *xcvr_native*alt_xcvr_native_pipe_retry*hv_sync_retry_rate*] 8
+ set_min_delay -from [get_registers *xcvr_native*alt_xcvr_native_pipe_retry*hv_sync_vec_pipe_rate*] \
+ -to [get_registers *xcvr_native*alt_xcvr_native_pipe_retry*hv_sync_retry_rate*] -4
+}
+
+if { [get_collection_size [get_registers -nowarn *xcvr_native*g_pipe_rate_g1_g3*int_pipe_rate_sync[*]]] > 0 } {
+ set_min_delay -to [get_registers -nowarn *xcvr_native*g_pipe_rate_g1_g3*int_pipe_rate_sync[0]] -4
+ set_max_delay -to [get_registers -nowarn *xcvr_native*g_pipe_rate_g1_g3*int_pipe_rate_sync[0]] 12
+
+ set_min_delay -to [get_registers -nowarn *xcvr_native*g_pipe_rate_g1_g3*int_pipe_rate_sync[1]] -4
+ set_max_delay -to [get_registers -nowarn *xcvr_native*g_pipe_rate_g1_g3*int_pipe_rate_sync[1]] 12
+}
+
+if { [get_collection_size [get_registers -nowarn *xcvr_native*altera_xcvr_native_pcie_dfe_ip*pcie_rate*]] > 0 } {
+ set_min_delay -to [get_registers -nowarn *xcvr_native*altera_xcvr_native_pcie_dfe_ip*pcie_rate[*]] -4
+ set_max_delay -to [get_registers -nowarn *xcvr_native*altera_xcvr_native_pcie_dfe_ip*pcie_rate[*]] 30
+
+ set_min_delay -to [get_registers -nowarn *xcvr_native*altera_xcvr_native_pcie_dfe_ip*pcie_rate_sync[0]] -4
+ set_max_delay -to [get_registers -nowarn *xcvr_native*altera_xcvr_native_pcie_dfe_ip*pcie_rate_sync[0]] 30
+
+ set_min_delay -to [get_registers -nowarn *xcvr_native*altera_xcvr_native_pcie_dfe_ip*pcie_rate_sync[1]] -4
+ set_max_delay -to [get_registers -nowarn *xcvr_native*altera_xcvr_native_pcie_dfe_ip*pcie_rate_sync[1]] 30
+}
+
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_a10_functions_h.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_a10_functions_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..8ed2369d39b57aea4e81061216eaab25f5e05314
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_a10_functions_h.sv
@@ -0,0 +1,154 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+//
+// Common functions for Arria 10 Native PHY IP
+//
+`timescale 1 ps/1 ps
+
+package altera_xcvr_native_a10_functions_h;
+
+ localparam MAX_CONVERSION_SIZE_ALT_XCVR_NATIVE_A10 = 128;
+ localparam MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10 = 64;
+ localparam integer MAX_CHARS_ALT_XCVR_NATIVE_A10 = 86; // To accomodate LONG parameter lists.
+
+ ////////////////////////////////////////////////////////////////////
+ // Return the number of bits required to represent an integer
+ // E.g. 0->1; 1->1; 2->2; 3->2 ... 31->5; 32->6
+ //
+ function integer clogb2_alt_xcvr_native_a10;
+ input integer input_num;
+ begin
+ for (clogb2_alt_xcvr_native_a10=0; input_num>0; clogb2_alt_xcvr_native_a10=clogb2_alt_xcvr_native_a10+1)
+ input_num = input_num >> 1;
+ if(clogb2_alt_xcvr_native_a10 == 0)
+ clogb2_alt_xcvr_native_a10 = 1;
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Used to calculate the value of the "hssi_10g_tx_pcs_comp_cnt"
+ // parameter for a givin channel in a bonded configuration
+ //
+ // @param channels - Number of channels in the interface
+ // @param pcs_bonding_master - PCS master channel index
+ // @param channel_index - Index of channel within interface to determine
+ // parameter value for.
+ //
+ // @return An integer value for the parameter "hssi_10g_tx_pcs_comp_cnt".
+ function [7:0] get_comp_cnt_alt_xcvr_native_a10;
+ input integer channels;
+ input integer pcs_bonding_master;
+ input integer channel_index;
+
+ integer max_index;
+ integer comp_cnt;
+ begin
+ // Determine the index of the master
+ max_index = (pcs_bonding_master > (channels - pcs_bonding_master)) ? pcs_bonding_master
+ : (channels-pcs_bonding_master);
+ // Determine the index of this channel
+ if (channel_index == pcs_bonding_master)
+ comp_cnt = max_index;
+ else if (channel_index < pcs_bonding_master)
+ comp_cnt = max_index - (pcs_bonding_master - channel_index);
+ else
+ comp_cnt = max_index - (channel_index - pcs_bonding_master);
+ // Convert index to count value
+ comp_cnt = comp_cnt * 2;
+ get_comp_cnt_alt_xcvr_native_a10 = comp_cnt[7:0];
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Used to calculate the value of the distance of current channel to mcgb
+ //
+ // @param pcs_bonding_master - PCS master channel index
+ // @param channel_index - Index of channel within interface to determine
+ // parameter value for.
+ //
+ // @return An 4 bits value for the parameter lower 3 showing distance, if MSB 1 then the current channel is above the mcgb
+ function [3:0] get_mcgb_location_alt_xcvr_native_a10(
+ input integer pcs_bonding_master,
+ input integer channel_index
+ );
+ integer distance;
+ begin
+ if (channel_index < pcs_bonding_master) begin
+ distance = pcs_bonding_master-channel_index;
+ get_mcgb_location_alt_xcvr_native_a10 = {1'b1,distance[2:0]};
+ end else begin
+ distance = channel_index-pcs_bonding_master;
+ get_mcgb_location_alt_xcvr_native_a10 = {1'b0,distance[2:0]};
+ end
+ end
+ endfunction
+
+
+ function automatic [MAX_CONVERSION_SIZE_ALT_XCVR_NATIVE_A10-1:0] str_2_bin_alt_xcvr_native_a10;
+ input [MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10*8-1:0] instring;
+
+ integer this_char;
+ integer i;
+ begin
+ // Initialize accumulator
+ str_2_bin_alt_xcvr_native_a10 = {MAX_CONVERSION_SIZE_ALT_XCVR_NATIVE_A10{1'b0}};
+ for(i=MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10-1;i>=0;i=i-1) begin
+ this_char = instring[i*8+:8];
+ // Add value of this digit
+ if(this_char >= 48 && this_char <= 57)
+ str_2_bin_alt_xcvr_native_a10 = (str_2_bin_alt_xcvr_native_a10 * 10) + (this_char - 48);
+ end
+ end
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Adds an offets to 'scrambler seed' per channel for interlaken as:
+ // (58'h123456789abcde + user_seed + (24'h826a3*lane_number))
+ // see FB 138336 for details
+ //
+ // @param protocol_hint - only interlaken matters
+ // @param user_seed - 58 bit base seed to be modified per channel
+ // @param lane_number - Index of channel within interface to determine
+ // parameter value for.
+ //
+ // @return 58 bits scrambler seed for the channel
+ function [57:0] set_10g_scrm_seed_user_alt_xcvr_native_a10 (
+ input [8*MAX_STRING_CHARS_ALT_XCVR_NATIVE_A10:1] protocol_hint,
+ input [57:0] user_seed,
+ input integer lane_number
+ );
+ set_10g_scrm_seed_user_alt_xcvr_native_a10 = (protocol_hint == "interlaken_mode") ? (58'h123456789abcde + user_seed + (24'h826a3*lane_number)) : user_seed;
+ endfunction
+
+ ////////////////////////////////////////////////////////////////////
+ // Convert an integer to a string
+ function [MAX_CHARS_ALT_XCVR_NATIVE_A10*8-1:0] int2str_alt_xcvr_native_a10(
+ input integer in_int
+ );
+ integer i;
+ integer this_char;
+ i = 0;
+ int2str_alt_xcvr_native_a10 = "";
+ do
+ begin
+ this_char = (in_int % 10) + 48;
+ int2str_alt_xcvr_native_a10[i*8+:8] = this_char[7:0];
+ i=i+1;
+ in_int = in_int / 10;
+ end
+ while(in_int > 0);
+ endfunction
+
+
+endpackage
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_pcie_dfe_ip.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_pcie_dfe_ip.sv
new file mode 100644
index 0000000000000000000000000000000000000000..64bd0c3aea514a28f424630f21b376e42a8a071e
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_pcie_dfe_ip.sv
@@ -0,0 +1,392 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ps/1ps
+
+// Revision 2.1
+(* altera_attribute = " -name GLOBAL_SIGNAL OFF -to \"alt_xcvr_resync:reset_pulse_inst|resync_chains[0].sync_r[2]\" " *)
+module altera_xcvr_native_pcie_dfe_ip #(
+ parameter num_channels = 8,
+ parameter disable_continuous_dfe = 0,
+ parameter enable_hip = 0,
+ parameter sim_reduced_counters = 0,
+ parameter avmm_sel_bits = 3,
+ parameter avmm_addr_bits = 10
+) (
+ input clock,
+ input reset,
+ input ltssm_detect_quiet,
+ input ltssm_detect_active,
+ input ltssm_rcvr_phase_two,
+ input [1:0] pcie_rate_sw,
+
+ // HIP only signal for supporting reduced sim counters
+ input hip_reduce_counters,
+
+ // Reconfig Interface to the transceiver
+ input xcvr_rcfg_waitrequest,
+ input [31:0] xcvr_rcfg_readdata,
+ output xcvr_rcfg_lock,
+ output xcvr_rcfg_read,
+ output xcvr_rcfg_write,
+ output [avmm_sel_bits+avmm_addr_bits-1:0] xcvr_rcfg_address,
+ output [31:0] xcvr_rcfg_writedata
+);
+
+///////////////////////////////////////////////////////////////////////////////
+// Import parameters
+///////////////////////////////////////////////////////////////////////////////
+import altera_xcvr_native_pcie_dfe_params_h::*;
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Import parameters
+///////////////////////////////////////////////////////////////////////////////
+wire reduceded_sim_counter;
+assign reduceded_sim_counter = (enable_hip) ? hip_reduce_counters : sim_reduced_counters[0];
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Lock out the Reconfig Interface from the user
+// wires and registers
+///////////////////////////////////////////////////////////////////////////////
+wire reset_sync;
+wire gen3_speed;
+wire gen12_speed;
+wire rate_change;
+wire detect_skew_timeout;
+wire ltssm_detect;
+wire indexed_all_channels;
+wire ltssm_rcvr_phase_two_sync;
+wire ltssm_detect_active_sync;
+wire ltssm_detect_quiet_sync;
+wire process_running_done;
+wire [30:0] mgmt_master_address;
+wire [NUM_PIO_IN-1:0] pio_to_mgmt_master;
+wire [NUM_PIO_OUT-1:0] pio_from_mgmt_master;
+
+reg modeb_not_restored;
+reg process_go;
+reg process_running;
+reg en_continuous_dfe;
+reg phase2_not_request;
+reg [1:0] pcie_rate;
+reg [1:0] current_rate;
+reg [2:0] detect_skew_cnt;
+reg [2:0] vec_timeout;
+reg [3:0] sm_state;
+reg [3:0] pcie_rate_sync;
+reg [20:0] timer_counter;
+reg [20:0] timer_threshold;
+reg [avmm_sel_bits-1:0] channel_count;
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Assign statements for control/status signals
+///////////////////////////////////////////////////////////////////////////////
+assign gen3_speed = (enable_hip) ? (pcie_rate == 2'b11) : (pcie_rate == 2'b10);
+assign gen12_speed = (enable_hip) ? (pcie_rate != 2'b11) : (pcie_rate != 2'b10);
+assign rate_change = (current_rate != pcie_rate);
+assign ltssm_detect = (ltssm_detect_quiet_sync | ltssm_detect_active_sync);
+assign detect_skew_timeout = (detect_skew_cnt == 3'h7);
+assign process_running_done = (~pio_from_mgmt_master[PIO_OUT_RUNNING] && process_running);
+assign indexed_all_channels = ((channel_count == (num_channels-1)) && process_running_done);
+
+// Lock out the Reconfig Interface from the user
+assign xcvr_rcfg_lock = (sm_state != SM_IDLE);
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Create a reset pulse
+///////////////////////////////////////////////////////////////////////////////
+(*preserve*) reg reg0 = 1'b0;
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 1 ),
+ .INIT_VALUE ( 1 )
+) reset_pulse_inst (
+ .clk (clock),
+ .reset (reset),
+ .d (reg0),
+ .q (reset_sync)
+);
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Synchronize the rate signal as well as the status signals
+///////////////////////////////////////////////////////////////////////////////
+always@(posedge clock or posedge reset_sync) begin
+ if(reset_sync) begin
+ vec_timeout <= 3'b0;
+ pcie_rate_sync <= 4'b0;
+ pcie_rate <= 2'b0;
+ end else begin
+ pcie_rate_sync <= {pcie_rate_sync[1:0], pcie_rate_sw};
+
+ if(pcie_rate != pcie_rate_sync[3:2]) begin
+ if(vec_timeout != 3'b111) begin
+ vec_timeout <= vec_timeout + 3'b1;
+ end else begin
+ pcie_rate <= pcie_rate_sync[3:2];
+ end
+ end else begin
+ vec_timeout <= 3'b0;
+ end
+ end
+end
+
+alt_xcvr_resync #(
+ .SYNC_CHAIN_LENGTH ( 3 ),
+ .WIDTH ( 3 ),
+ .INIT_VALUE ( 0 )
+) ltssm_state_sync_inst (
+ .clk (clock),
+ .reset (reset_sync),
+ .d ({ltssm_rcvr_phase_two, ltssm_detect_active, ltssm_detect_quiet}),
+ .q ({ltssm_rcvr_phase_two_sync, ltssm_detect_active_sync, ltssm_detect_quiet_sync})
+);
+
+///////////////////////////////////////////////////////////////////////////////
+// Small counter for skew alignment
+// If we are not in detect,
+///////////////////////////////////////////////////////////////////////////////
+always@(posedge clock or posedge reset_sync)begin
+ if(reset_sync) begin
+ detect_skew_cnt <= 3'b0;
+ end else begin
+ if(ltssm_detect) begin
+ detect_skew_cnt <= 3'b0;
+ end else begin
+ if(detect_skew_timeout) begin
+ detect_skew_cnt <= detect_skew_cnt;
+ end else begin
+ detect_skew_cnt <= detect_skew_cnt + 3'b1;
+ end
+ end
+ end
+end
+
+
+///////////////////////////////////////////////////////////////////////////////
+// register stage for edge detection
+///////////////////////////////////////////////////////////////////////////////
+always@(posedge clock or posedge reset_sync) begin
+ if(reset_sync) begin
+ process_running <= 1'b0;
+ end else begin
+ process_running <= pio_from_mgmt_master[PIO_OUT_RUNNING];
+ end
+end
+
+
+///////////////////////////////////////////////////////////////////////////////
+// State machine
+///////////////////////////////////////////////////////////////////////////////
+always@(posedge clock or posedge reset_sync) begin
+ if(reset_sync) begin
+ sm_state <= SM_POWERUP;
+ process_go <= 1'b0;
+ current_rate <= 2'b0;
+ modeb_not_restored <= 1'b1;
+ en_continuous_dfe <= 1'b1;
+ phase2_not_request <= 1'b0;
+ timer_counter <= 21'b0;
+ timer_threshold <= (reduceded_sim_counter) ? 21'd1200 : 21'd1200000;
+
+ end else begin
+ // default the process_go signal for all states unless otherwise specified
+ process_go <= 1'b0;
+
+ case(sm_state)
+ // Powerup state to do a one-time readback on the calibration status
+ SM_POWERUP: begin
+ sm_state <= SM_CHECK_CAL_STATUS;
+ end
+
+ SM_CHECK_CAL_STATUS: begin
+ // Intercept the AVMM read from the mgmt_master
+ if((xcvr_rcfg_address[avmm_addr_bits-1:0] == ADDR_CALIBRATION) && xcvr_rcfg_read == 1'b1 && xcvr_rcfg_waitrequest == 1'b0) begin
+ en_continuous_dfe <= xcvr_rcfg_readdata[BIT_CALIBRATION];
+ sm_state <= SM_IDLE;
+ end
+ end
+
+ SM_IDLE: begin
+ current_rate <= pcie_rate;
+ modeb_not_restored <= (detect_skew_timeout) ? 1'b1 : modeb_not_restored;
+ phase2_not_request <= (ltssm_rcvr_phase_two_sync) ? phase2_not_request : 1'b1;
+ timer_counter <= 21'b0;
+
+
+ // State Transitions. If we are changin rates, execute the rate change
+ // current speed is decoded via combinational logic
+ if (rate_change) begin
+ sm_state <= SM_EXECUTE_RATE_SW;
+ end
+
+ // Restoring mode B must be done everytime we enter detect quiet. This is
+ // to ensure that the adaptation block can re-run phase 2. If we enter
+ // recovery equalization phase 2, then we must restore mode b fo re-running
+ // phase 2
+ else if(ltssm_detect_quiet_sync && modeb_not_restored || ltssm_rcvr_phase_two_sync && phase2_not_request) begin
+ sm_state <= SM_RESTORE_MODEB;
+ end
+ end
+
+ SM_EXECUTE_RATE_SW: begin
+ process_go <= 1'b1;
+
+ if(indexed_all_channels) begin
+ sm_state <= SM_IDLE;
+ end
+ end
+
+ SM_RESTORE_MODEB: begin
+ // Set the timer threshold for a 12ms timeout
+ timer_threshold <= (reduceded_sim_counter) ? 21'd1200 : 21'd1200000;
+ timer_counter <= (reduceded_sim_counter) ? 21'b0 : timer_counter + 21'b1;
+
+ // Run process over all channels
+ process_go <= 1'b1;
+
+ // Set modeb_not_restored to 0
+ modeb_not_restored <= 1'b0;
+
+ if(indexed_all_channels) begin
+ if(ltssm_rcvr_phase_two_sync)
+ sm_state <= SM_TIMEOUT_CTLE;
+ else
+ sm_state <= SM_IDLE;
+ end
+ end
+
+ SM_TIMEOUT_CTLE: begin
+ // Set the timer threshold for a 12ms timeout
+ timer_threshold <= (reduceded_sim_counter) ? 21'd1200 : 21'd1200000;
+
+ // Check the timeout, else run the counter
+ if(timer_counter == timer_threshold) begin
+ timer_counter <= 21'b0;
+ sm_state <= SM_EXECUTE_CTLE;
+ end else begin
+ timer_counter <= timer_counter + 21'b1;
+ end
+ end
+
+ SM_EXECUTE_CTLE: begin
+ // Set the timer threshold for a 10ms timeout
+ timer_threshold <= (reduceded_sim_counter) ? 21'd1000 : 21'd1000000;
+ timer_counter <= (reduceded_sim_counter) ? 21'b0 : timer_counter + 21'b1;
+
+ // Run process over all channels
+ process_go <= 1'b1;
+
+ if(indexed_all_channels) begin
+ sm_state <= SM_TIMEOUT_DFE;
+ end
+ end
+
+ SM_TIMEOUT_DFE: begin
+ // Set the timer threshold for a 10ms timeout
+ timer_threshold <= (reduceded_sim_counter) ? 21'd1000 : 21'd1000000;
+
+ // Check the timeout, else run the counter
+ if(timer_counter == timer_threshold) begin
+ timer_counter <= 21'b0;
+ sm_state <= SM_EXECUTE_DFE;
+ end else begin
+ timer_counter <= timer_counter + 21'b1;
+ end
+
+ end
+
+ SM_EXECUTE_DFE: begin
+ // Indicate that the flow has been run
+ phase2_not_request <= 1'b0;
+
+ // Run the process over all channels
+ process_go <= 1'b1;
+
+ if(indexed_all_channels) begin
+ sm_state <= SM_IDLE;
+ end
+ end
+
+ default: begin
+ process_go <= 1'b0;
+ sm_state <= SM_IDLE;
+ end
+
+ endcase
+ end
+end
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Assigns for the Control Signals for the mgmt_master
+///////////////////////////////////////////////////////////////////////////////
+assign pio_to_mgmt_master[PIO_IN_GO] = process_go;
+assign pio_to_mgmt_master[PIO_IN_SW_GEN_1_2] = ((sm_state == SM_EXECUTE_RATE_SW) && gen12_speed);
+assign pio_to_mgmt_master[PIO_IN_SW_GEN_3] = ((sm_state == SM_EXECUTE_RATE_SW) && gen3_speed);
+assign pio_to_mgmt_master[PIO_IN_RESTORE_MODEB] = (sm_state == SM_RESTORE_MODEB);
+assign pio_to_mgmt_master[PIO_IN_PHASE2_CTLE] = (sm_state == SM_EXECUTE_CTLE);
+assign pio_to_mgmt_master[PIO_IN_PHASE2_DFE] = (sm_state == SM_EXECUTE_DFE);
+assign pio_to_mgmt_master[PIO_IN_CONTINUOUS_DFE] = (disable_continuous_dfe) ? 1'b0 : en_continuous_dfe;
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Channel Indexing for the addressing
+///////////////////////////////////////////////////////////////////////////////
+assign xcvr_rcfg_address = {channel_count, mgmt_master_address[avmm_addr_bits-1:0]};
+always@(posedge clock or posedge reset_sync) begin
+ if(reset_sync) begin
+ channel_count <= {avmm_sel_bits{1'b0}};
+ end else begin
+ if (sm_state == SM_EXECUTE_RATE_SW || sm_state == SM_RESTORE_MODEB || sm_state == SM_EXECUTE_CTLE || sm_state == SM_EXECUTE_DFE) begin
+ if(channel_count == (num_channels - 1)) begin
+ channel_count <= channel_count;
+ end else begin
+ channel_count <= channel_count + process_running_done;
+ end
+ end else begin
+ channel_count <= {avmm_sel_bits{1'b0}};
+ end
+ end
+end
+
+
+///////////////////////////////////////////////////////////////////////////////
+// mgmt_master cpu for reconfiguration.
+///////////////////////////////////////////////////////////////////////////////
+pcie_mgmt_master #(
+ .CLOCKS_PER_SECOND ( 100000000 ), // Used for time calculations
+ .PIO_OUT_SIZE ( NUM_PIO_OUT ), // Width of PIO output port
+ .PIO_IN_SIZE ( NUM_PIO_IN ), // Width of PIO input port
+ .PIO_OUT_INIT_VALUE ( 0 ), // Initial value for pio_out registers
+ .MEM_DEPTH ( num_channels * NUM_ADDR_PER_CHNL + 1), // Depth of the memory for DFE and CTLE
+ .ROM_DEPTH ( 1024 ) // Depth of command ROM
+
+ ) pcie_mgmt_master_for_dfe (
+ .clk ( clock ),
+ .reset ( reset_sync ),
+ .av_write ( xcvr_rcfg_write ),
+ .av_read ( xcvr_rcfg_read ),
+ .av_address ( mgmt_master_address ),
+ .av_writedata ( xcvr_rcfg_writedata ),
+ .av_readdata ( xcvr_rcfg_readdata ),
+ .av_waitrequest ( xcvr_rcfg_waitrequest ),
+ .pio_out ( pio_from_mgmt_master ),
+ .pio_in ( pio_to_mgmt_master )
+);
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_pcie_dfe_params_h.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_pcie_dfe_params_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1b5e93b44cb7c4102f0825bbfd90e88b4bcebc78
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/altera_xcvr_native_pcie_dfe_params_h.sv
@@ -0,0 +1,81 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Revision 2.0
+package altera_xcvr_native_pcie_dfe_params_h;
+ // Program Labels for Jumps
+ localparam PRGM_BEGIN = 1;
+ localparam PRGM_SW_GEN3 = 2;
+ localparam PRGM_PHASE2_CTLE = 3;
+ localparam PRGM_PHASE2_DFE = 4;
+ localparam PRGM_SW_GEN1_2 = 5;
+ localparam PRGM_RESTORE_MODEB = 6;
+ localparam PRGM_SKIP_MANUAL_DFE = 7;
+ localparam PRGM_SKIP_CONT_DFE = 8;
+ localparam PRGM_SKIP_DFE_LOAD = 9;
+ localparam PRGM_SKIP_DFE_HOLD = 10;
+ localparam PRGM_SKIP_DFE_MODE_8 = 11;
+
+ // Labels for PIO in
+ localparam NUM_PIO_IN = 7;
+
+ localparam PIO_IN_GO = 0;
+ localparam PIO_IN_SW_GEN_1_2 = 1;
+ localparam PIO_IN_SW_GEN_3 = 2;
+ localparam PIO_IN_RESTORE_MODEB = 3;
+ localparam PIO_IN_PHASE2_CTLE = 4;
+ localparam PIO_IN_PHASE2_DFE = 5;
+ localparam PIO_IN_CONTINUOUS_DFE= 6;
+
+ // Labels for PIO out
+ localparam NUM_PIO_OUT = 7;
+
+ localparam PIO_OUT_ERROR = 0;
+ localparam PIO_OUT_RUNNING = 1;
+ localparam PIO_OUT_SW_GEN_1_2 = 2;
+ localparam PIO_OUT_SW_GEN_3 = 3;
+ localparam PIO_OUT_RESTORE_MODEB= 4;
+ localparam PIO_OUT_PHASE2_CTLE = 5;
+ localparam PIO_OUT_PHASE2_DFE = 6;
+
+ // Static settings
+ localparam FORCE_JUMP = 1;
+ localparam GEN1_GEN2_CTLE_VAL = 32'h00;
+
+ // Test parameters
+ localparam TST_MUX_DELAY = 30;
+ localparam SLEEP_DELAY = 5;
+
+ // Parameters for indexing through mem
+ localparam NUM_ADDR_PER_CHNL = 12;
+ localparam INDX_ADDR_CTLE = 0;
+ localparam NUM_ADDR_CTLE = 1;
+ localparam INDX_ADDR_DFE = 1;
+ localparam NUM_ADDR_DFE = 11;
+
+ // Calibration status
+ localparam ADDR_CALIBRATION = 10'h103;
+ localparam BIT_CALIBRATION = 5;
+
+ // DFE IP States
+ localparam SM_POWERUP = 4'h0;
+ localparam SM_CHECK_CAL_STATUS = 4'h1;
+ localparam SM_IDLE = 4'h2;
+ localparam SM_EXECUTE_RATE_SW = 4'h3;
+ localparam SM_RESTORE_MODEB = 4'h4;
+ localparam SM_TIMEOUT_CTLE = 4'h5;
+ localparam SM_EXECUTE_CTLE = 4'h6;
+ localparam SM_TIMEOUT_DFE = 4'h7;
+ localparam SM_EXECUTE_DFE = 4'h8;
+
+endpackage
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/arria10_hps_altera_xcvr_native_a10_221_iq5an3y.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/arria10_hps_altera_xcvr_native_a10_221_iq5an3y.sv
new file mode 100644
index 0000000000000000000000000000000000000000..ce5d7a78f6ead1579db8e62babf82c433841fda1
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/arria10_hps_altera_xcvr_native_a10_221_iq5an3y.sv
@@ -0,0 +1,2691 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+
+
+module arria10_hps_altera_xcvr_native_a10_221_iq5an3y
+ #(
+ //---------------------
+ // Common parameters
+ //---------------------
+ parameter device_revision = "20nm5es", // (20nm5es, 20nm5es2, 20nm4, 20nm3, 20nm4qor,20nm2, 20nm1)
+
+ parameter duplex_mode = "duplex", // (tx,rx,duplex)
+ parameter channels = 1, // legal values 1+
+
+ parameter enable_calibration = 1, // (0,1)
+ // 0 - Disable transceiver calibration
+ // 1 - Enable transceiver calibration
+
+ parameter enable_analog_resets = 1, // (0,1)
+ // 0 - Disable tx_analog and rx_analog reset input connections. Still allows soft register override
+ // 1 - Enable tx_analog and rx_analog reset input connections
+
+ parameter enable_reset_sequence = 1, // (0,1)
+ // 0 - Disable reset sequencing
+ // 1 - Enable reset sequencing
+
+ // TX PMA
+ parameter bonded_mode = "not_bonded", // (not_bonded,pma_only,pma_pcs) not_bonded-Disable bonding,
+ // pma_only - Enable PMA only bonding
+ // pma_pcs - Enable PMA and PCS bonding
+ parameter pcs_bonding_master = 0, // (0:channels-1), Specifies PCS bonding master
+ parameter plls = 1, // (1,2,3,4)
+ parameter number_physical_bonding_clocks = 1, // (1,2,3,4)
+ parameter cdr_refclk_cnt = 1, // (1,2,3,4,5)
+ parameter enable_hip = 0, // (0,1) 0 - Not PCIe HIP, 1 - PCIe HIP
+
+ //----------------------
+ // Reconfiguration options
+ //----------------------
+ parameter rcfg_enable = 0, // (0,1)
+ // 0 - Disable the AVMM reconfiguration interface.
+ // 1 - Enable the AVMM reconfiguration interface.
+
+ parameter rcfg_shared = 0, // (0,1)
+ // 0 - Present separate AVMM interface for each channel,
+ // 1 - Present shared AVMM interface for all channels using address decoding.
+ // Bits [n:10] of "reconfig_address" select the channel to address.
+ // Bit [9] selects between soft registers (1) and HSSI channel registers (0)
+ // Bits [8:0] of "reconfig_address" provide the register offset within soft or hard register space.
+
+ parameter rcfg_jtag_enable = 0, // (0,1)
+ // 0 - Disable embedded debug master
+ // 1 - Enable embedded JTAG master. Requires "rcfg_shared==1".
+
+ parameter rcfg_separate_avmm_busy = 0, // (0,1)
+ // 0 - AVMM busy is reflected on the waitrequest
+ // 1 - AVMM busy must be read from a soft CSR
+ // Atom parameters
+ parameter dbg_embedded_debug_enable = 0, // enables embedded debug blocks
+ parameter dbg_capability_reg_enable = 0, // enables capability registers to describe the debug endpoint
+ parameter dbg_user_identifier = 0, // user-assigned value to either define phy_ip or to link associated ip
+ parameter dbg_stat_soft_logic_enable = 0, // enables soft logic to read status signals through avmm
+ parameter dbg_ctrl_soft_logic_enable = 0, // enables soft logic to write control signals through avmm
+ parameter dbg_prbs_soft_logic_enable = 0, // enables soft logic for prbs err accumulation
+ parameter dbg_odi_soft_logic_enable = 0,
+
+ parameter rcfg_emb_strm_enable = 0, // (0,1)
+ // 0 - Disable embedded reconfiguration streamer
+ // 1 - Enable embedded reconfiguration streamer
+
+ parameter rcfg_profile_cnt = 2, //Number of configuration profiles for embedded reconfiguration streamer
+
+ // ADME Parameters
+ parameter adme_prot_mode = "basic_tx",
+ parameter adme_data_rate = "5000000000",
+
+ // Parameters for the PCIe DFE IP
+ parameter enable_pcie_dfe_ip = 0,
+ parameter sim_reduced_counters = 0,
+ parameter disable_continuous_dfe = 0,
+
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_hip_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_hrdrstctl_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_prot_mode_rx = "disabled_prot_mode_rx" ,//basic_10gpcs_krfec_rx basic_10gpcs_rx basic_8gpcs_rm_disable_rx basic_8gpcs_rm_enable_rx cpri_8b10b_rx disabled_prot_mode_rx fortyg_basekr_krfec_rx gige_1588_rx gige_rx interlaken_rx pcie_g1_capable_rx pcie_g2_capable_rx pcie_g3_capable_rx pcs_direct_rx prbs_rx prp_krfec_rx prp_rx sfis_rx teng_1588_basekr_krfec_rx teng_1588_baser_rx teng_basekr_krfec_rx teng_baser_rx teng_sdi_rx
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx = "individual_rx" ,//ctrl_master_rx ctrl_slave_abv_rx ctrl_slave_blw_rx individual_rx
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_pma_dw_rx = "pma_8b_rx" ,//pcie_g3_dyn_dw_rx pma_10b_rx pma_16b_rx pma_20b_rx pma_32b_rx pma_40b_rx pma_64b_rx pma_8b_rx
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_pld_fifo_mode_rx = "fifo_rx" ,//fifo_rx reg_rx
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_shared_fifo_width_rx = "single_rx" ,//double_rx single_rx
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_low_latency_en_rx = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_func_mode = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_frequency_rules_en = "disable" ,//disable enable
+ parameter [29:0] hssi_rx_pld_pcs_interface_hd_chnl_pma_rx_clk_hz = 30'd0 ,//0:1073741823
+ parameter [29:0] hssi_rx_pld_pcs_interface_hd_chnl_pld_rx_clk_hz = 30'd0 ,//0:1073741823
+ parameter [29:0] hssi_rx_pld_pcs_interface_hd_chnl_fref_clk_hz = 30'd0 ,//0:1073741823
+ parameter [29:0] hssi_rx_pld_pcs_interface_hd_chnl_clklow_clk_hz = 30'd0 ,//0:1073741823
+ parameter hssi_rx_pld_pcs_interface_hd_fifo_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_fifo_prot_mode_rx = "teng_mode_rx" ,//non_teng_mode_rx teng_mode_rx
+ parameter hssi_rx_pld_pcs_interface_hd_fifo_shared_fifo_width_rx = "single_rx" ,//double_rx single_rx
+ parameter hssi_rx_pld_pcs_interface_hd_10g_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_10g_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_10g_pma_dw_rx = "pma_64b_rx" ,//pma_32b_rx pma_40b_rx pma_64b_rx
+ parameter hssi_rx_pld_pcs_interface_hd_10g_fifo_mode_rx = "fifo_rx" ,//fifo_rx reg_rx
+ parameter hssi_rx_pld_pcs_interface_hd_10g_prot_mode_rx = "disabled_prot_mode_rx" ,//basic_krfec_mode_rx basic_mode_rx disabled_prot_mode_rx interlaken_mode_rx sfis_mode_rx teng_1588_krfec_mode_rx teng_1588_mode_rx teng_baser_krfec_mode_rx teng_baser_mode_rx teng_sdi_mode_rx test_prp_krfec_mode_rx test_prp_mode_rx
+ parameter hssi_rx_pld_pcs_interface_hd_10g_low_latency_en_rx = "enable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_10g_shared_fifo_width_rx = "single_rx" ,//double_rx single_rx
+ parameter hssi_rx_pld_pcs_interface_hd_10g_test_bus_mode = "tx" ,//rx tx
+ parameter hssi_rx_pld_pcs_interface_hd_8g_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_8g_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_8g_prot_mode_rx = "disabled_prot_mode_rx" ,//basic_rm_disable_rx basic_rm_enable_rx cpri_rx cpri_rx_tx_rx disabled_prot_mode_rx gige_1588_rx gige_rx pipe_g1_rx pipe_g2_rx pipe_g3_rx
+ parameter hssi_rx_pld_pcs_interface_hd_8g_hip_mode = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_8g_pma_dw_rx = "pma_8b_rx" ,//pma_10b_rx pma_16b_rx pma_20b_rx pma_8b_rx
+ parameter hssi_rx_pld_pcs_interface_hd_8g_fifo_mode_rx = "fifo_rx" ,//fifo_rx reg_rx
+ parameter hssi_rx_pld_pcs_interface_hd_g3_prot_mode = "disabled_prot_mode" ,//disabled_prot_mode pipe_g1 pipe_g2 pipe_g3
+ parameter hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx = "disabled_prot_mode_rx" ,//basic_mode_rx disabled_prot_mode_rx fortyg_basekr_mode_rx teng_1588_basekr_mode_rx teng_basekr_mode_rx
+ parameter hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode = "tx" ,//rx tx
+ parameter hssi_rx_pld_pcs_interface_hd_pmaif_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_pmaif_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_pmaif_sim_mode = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_pmaif_prot_mode_rx = "disabled_prot_mode_rx" ,//disabled_prot_mode_rx eightg_basic_mode_rx eightg_g3_pcie_g3_hip_mode_rx eightg_g3_pcie_g3_pld_mode_rx eightg_only_pld_mode_rx eightg_pcie_g12_hip_mode_rx eightg_pcie_g12_pld_mode_rx pcs_direct_mode_rx prbs_mode_rx teng_basic_mode_rx teng_krfec_mode_rx teng_sfis_sdi_mode_rx
+ parameter hssi_rx_pld_pcs_interface_hd_pmaif_pma_dw_rx = "pma_8b_rx" ,//pcie_g3_dyn_dw_rx pma_10b_rx pma_16b_rx pma_20b_rx pma_32b_rx pma_40b_rx pma_64b_rx pma_8b_rx
+ parameter hssi_rx_pld_pcs_interface_hd_pldif_prot_mode_rx = "disabled_prot_mode_rx" ,//disabled_prot_mode_rx eightg_and_g3_pld_fifo_mode_rx eightg_and_g3_reg_mode_hip_rx eightg_and_g3_reg_mode_rx pcs_direct_reg_mode_rx teng_and_krfec_pld_fifo_mode_rx teng_and_krfec_reg_mode_rx teng_pld_fifo_mode_rx teng_reg_mode_rx
+ parameter hssi_rx_pld_pcs_interface_hd_pldif_hrdrstctl_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_pcs_rx_block_sel = "pcs_direct" ,//eightg pcs_direct teng
+ parameter hssi_rx_pld_pcs_interface_pcs_rx_clk_sel = "pld_rx_clk" ,//pcs_rx_clk pld_rx_clk
+ parameter hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en = "hip_rx_enable" ,//hip_rx_disable hip_rx_enable
+ parameter hssi_rx_pld_pcs_interface_pcs_rx_output_sel = "teng_output" ,//krfec_output teng_output
+ parameter hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel = "teng_clk_out" ,//eightg_clk_out pma_rx_clk pma_rx_clk_user teng_clk_out
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_hip_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_hrdrstctl_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx = "disabled_prot_mode_tx" ,//basic_10gpcs_krfec_tx basic_10gpcs_tx basic_8gpcs_tx cpri_8b10b_tx disabled_prot_mode_tx fortyg_basekr_krfec_tx gige_1588_tx gige_tx interlaken_tx pcie_g1_capable_tx pcie_g2_capable_tx pcie_g3_capable_tx pcs_direct_tx prbs_tx prp_krfec_tx prp_tx sfis_tx sqwave_tx teng_1588_basekr_krfec_tx teng_1588_baser_tx teng_basekr_krfec_tx teng_baser_tx teng_sdi_tx uhsif_tx
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx = "individual_tx" ,//ctrl_master_tx ctrl_slave_abv_tx ctrl_slave_blw_tx individual_tx
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_pma_dw_tx = "pma_8b_tx" ,//pcie_g3_dyn_dw_tx pma_10b_tx pma_16b_tx pma_20b_tx pma_32b_tx pma_40b_tx pma_64b_tx pma_8b_tx
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_pld_fifo_mode_tx = "fifo_tx" ,//fastreg_tx fifo_tx reg_tx
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_shared_fifo_width_tx = "single_tx" ,//double_tx single_tx
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_low_latency_en_tx = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_func_mode = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_frequency_rules_en = "disable" ,//disable enable
+ parameter [29:0] hssi_tx_pld_pcs_interface_hd_chnl_pma_tx_clk_hz = 30'd0 ,//0:1073741823
+ parameter [29:0] hssi_tx_pld_pcs_interface_hd_chnl_pld_tx_clk_hz = 30'd0 ,//0:1073741823
+ parameter [29:0] hssi_tx_pld_pcs_interface_hd_chnl_pld_uhsif_tx_clk_hz = 30'd0 ,//0:1073741823
+ parameter hssi_tx_pld_pcs_interface_hd_fifo_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_fifo_prot_mode_tx = "teng_mode_tx" ,//non_teng_mode_tx teng_mode_tx
+ parameter hssi_tx_pld_pcs_interface_hd_fifo_shared_fifo_width_tx = "single_tx" ,//double_tx single_tx
+ parameter hssi_tx_pld_pcs_interface_hd_10g_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_10g_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_10g_pma_dw_tx = "pma_64b_tx" ,//pma_32b_tx pma_40b_tx pma_64b_tx
+ parameter hssi_tx_pld_pcs_interface_hd_10g_fifo_mode_tx = "fifo_tx" ,//fastreg_tx fifo_tx reg_tx
+ parameter hssi_tx_pld_pcs_interface_hd_10g_prot_mode_tx = "disabled_prot_mode_tx" ,//basic_krfec_mode_tx basic_mode_tx disabled_prot_mode_tx interlaken_mode_tx sfis_mode_tx teng_1588_krfec_mode_tx teng_1588_mode_tx teng_baser_krfec_mode_tx teng_baser_mode_tx teng_sdi_mode_tx test_prp_krfec_mode_tx test_prp_mode_tx
+ parameter hssi_tx_pld_pcs_interface_hd_10g_low_latency_en_tx = "enable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_10g_shared_fifo_width_tx = "single_tx" ,//double_tx single_tx
+ parameter hssi_tx_pld_pcs_interface_hd_8g_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_8g_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx = "disabled_prot_mode_tx" ,//basic_tx cpri_rx_tx_tx cpri_tx disabled_prot_mode_tx gige_1588_tx gige_tx pipe_g1_tx pipe_g2_tx pipe_g3_tx
+ parameter hssi_tx_pld_pcs_interface_hd_8g_hip_mode = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_8g_pma_dw_tx = "pma_8b_tx" ,//pma_10b_tx pma_16b_tx pma_20b_tx pma_8b_tx
+ parameter hssi_tx_pld_pcs_interface_hd_8g_fifo_mode_tx = "fifo_tx" ,//fastreg_tx fifo_tx reg_tx
+ parameter hssi_tx_pld_pcs_interface_hd_g3_prot_mode = "disabled_prot_mode" ,//disabled_prot_mode pipe_g1 pipe_g2 pipe_g3
+ parameter hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx = "disabled_prot_mode_tx" ,//basic_mode_tx disabled_prot_mode_tx fortyg_basekr_mode_tx teng_1588_basekr_mode_tx teng_basekr_mode_tx
+ parameter hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_pmaif_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_pmaif_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_pmaif_sim_mode = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_pmaif_prot_mode_tx = "disabled_prot_mode_tx" ,//disabled_prot_mode_tx eightg_basic_mode_tx eightg_g3_pcie_g3_hip_mode_tx eightg_g3_pcie_g3_pld_mode_tx eightg_only_pld_mode_tx eightg_pcie_g12_hip_mode_tx eightg_pcie_g12_pld_mode_tx pcs_direct_mode_tx prbs_mode_tx sqwave_mode_tx teng_basic_mode_tx teng_krfec_mode_tx teng_sfis_sdi_mode_tx uhsif_direct_mode_tx uhsif_reg_mode_tx
+ parameter hssi_tx_pld_pcs_interface_hd_pmaif_pma_dw_tx = "pma_8b_tx" ,//pcie_g3_dyn_dw_tx pma_10b_tx pma_16b_tx pma_20b_tx pma_32b_tx pma_40b_tx pma_64b_tx pma_8b_tx
+ parameter hssi_tx_pld_pcs_interface_hd_pldif_prot_mode_tx = "disabled_prot_mode_tx" ,//disabled_prot_mode_tx eightg_and_g3_fastreg_mode_tx eightg_and_g3_pld_fifo_mode_tx eightg_and_g3_reg_mode_hip_tx eightg_and_g3_reg_mode_tx pcs_direct_fastreg_mode_tx teng_and_krfec_fastreg_mode_tx teng_and_krfec_pld_fifo_mode_tx teng_and_krfec_reg_mode_tx teng_fastreg_mode_tx teng_pld_fifo_mode_tx teng_reg_mode_tx uhsif_mode_tx
+ parameter hssi_tx_pld_pcs_interface_hd_pldif_hrdrstctl_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_clk_source = "teng" ,//eightg pma_clk teng
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_data_source = "hip_disable" ,//hip_disable hip_enable
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en = "delay1_clk_disable" ,//delay1_clk_disable delay1_clk_enable
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel = "pld_tx_clk" ,//pcs_tx_clk pld_tx_clk
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl = "delay1_path0" ,//delay1_path0 delay1_path1 delay1_path2 delay1_path3 delay1_path4
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel = "one_ff_delay" ,//one_ff_delay two_ff_delay
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en = "delay2_clk_disable" ,//delay2_clk_disable delay2_clk_enable
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl = "delay2_path0" ,//delay2_path0 delay2_path1 delay2_path2 delay2_path3 delay2_path4
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_output_sel = "teng_output" ,//krfec_output teng_output
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel = "teng_clk_out" ,//eightg_clk_out pma_tx_clk pma_tx_clk_user teng_clk_out
+ parameter hssi_krfec_tx_pcs_burst_err = "burst_err_dis" ,//burst_err_dis burst_err_en
+ parameter hssi_krfec_tx_pcs_burst_err_len = "burst_err_len1" ,//burst_err_len1 burst_err_len10 burst_err_len11 burst_err_len12 burst_err_len13 burst_err_len14 burst_err_len15 burst_err_len16 burst_err_len2 burst_err_len3 burst_err_len4 burst_err_len5 burst_err_len6 burst_err_len7 burst_err_len8 burst_err_len9
+ parameter hssi_krfec_tx_pcs_ctrl_bit_reverse = "ctrl_bit_reverse_dis" ,//ctrl_bit_reverse_dis ctrl_bit_reverse_en
+ parameter hssi_krfec_tx_pcs_data_bit_reverse = "data_bit_reverse_dis" ,//data_bit_reverse_dis data_bit_reverse_en
+ parameter hssi_krfec_tx_pcs_enc_frame_query = "enc_query_dis" ,//enc_query_dis enc_query_en
+ parameter hssi_krfec_tx_pcs_low_latency_en = "disable" ,//disable enable
+ parameter hssi_krfec_tx_pcs_pipeln_encoder = "enable" ,//disable enable
+ parameter hssi_krfec_tx_pcs_pipeln_scrambler = "enable" ,//disable enable
+ parameter hssi_krfec_tx_pcs_prot_mode = "disable_mode" ,//basic_mode disable_mode fortyg_basekr_mode teng_1588_basekr_mode teng_basekr_mode
+ parameter hssi_krfec_tx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_krfec_tx_pcs_transcode_err = "trans_err_dis" ,//trans_err_dis trans_err_en
+ parameter hssi_krfec_tx_pcs_transmit_order = "transmit_lsb" ,//transmit_lsb transmit_msb
+ parameter hssi_krfec_tx_pcs_tx_testbus_sel = "overall" ,//encoder1 encoder2 gearbox overall scramble1 scramble2 scramble3
+ parameter hssi_10g_rx_pcs_align_del = "align_del_en" ,//align_del_dis align_del_en
+ parameter hssi_10g_rx_pcs_ber_bit_err_total_cnt = "bit_err_total_cnt_10g" ,//bit_err_total_cnt_10g
+ parameter hssi_10g_rx_pcs_ber_clken = "ber_clk_dis" ,//ber_clk_dis ber_clk_en
+ parameter [20:0] hssi_10g_rx_pcs_ber_xus_timer_window = 21'd19530 ,//0:2097151
+ parameter hssi_10g_rx_pcs_bitslip_mode = "bitslip_dis" ,//bitslip_dis bitslip_en
+ parameter hssi_10g_rx_pcs_blksync_bitslip_type = "bitslip_comb" ,//bitslip_comb bitslip_reg
+ parameter [2:0] hssi_10g_rx_pcs_blksync_bitslip_wait_cnt = 3'd1 ,//0:7
+ parameter hssi_10g_rx_pcs_blksync_bitslip_wait_type = "bitslip_match" ,//bitslip_cnt bitslip_match
+ parameter hssi_10g_rx_pcs_blksync_bypass = "blksync_bypass_dis" ,//blksync_bypass_dis blksync_bypass_en
+ parameter hssi_10g_rx_pcs_blksync_clken = "blksync_clk_dis" ,//blksync_clk_dis blksync_clk_en
+ parameter hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt = "enum_invalid_sh_cnt_10g" ,//enum_invalid_sh_cnt_10g
+ parameter hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock = "knum_sh_cnt_postlock_10g" ,//knum_sh_cnt_postlock_10g
+ parameter hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock = "knum_sh_cnt_prelock_10g" ,//knum_sh_cnt_prelock_10g
+ parameter hssi_10g_rx_pcs_blksync_pipeln = "blksync_pipeln_dis" ,//blksync_pipeln_dis blksync_pipeln_en
+ parameter hssi_10g_rx_pcs_clr_errblk_cnt_en = "disable" ,//disable enable
+ parameter hssi_10g_rx_pcs_control_del = "control_del_all" ,//control_del_all control_del_none
+ parameter hssi_10g_rx_pcs_crcchk_bypass = "crcchk_bypass_dis" ,//crcchk_bypass_dis crcchk_bypass_en
+ parameter hssi_10g_rx_pcs_crcchk_clken = "crcchk_clk_dis" ,//crcchk_clk_dis crcchk_clk_en
+ parameter hssi_10g_rx_pcs_crcchk_inv = "crcchk_inv_dis" ,//crcchk_inv_dis crcchk_inv_en
+ parameter hssi_10g_rx_pcs_crcchk_pipeln = "crcchk_pipeln_dis" ,//crcchk_pipeln_dis crcchk_pipeln_en
+ parameter hssi_10g_rx_pcs_crcflag_pipeln = "crcflag_pipeln_dis" ,//crcflag_pipeln_dis crcflag_pipeln_en
+ parameter hssi_10g_rx_pcs_ctrl_bit_reverse = "ctrl_bit_reverse_dis" ,//ctrl_bit_reverse_dis ctrl_bit_reverse_en
+ parameter hssi_10g_rx_pcs_data_bit_reverse = "data_bit_reverse_dis" ,//data_bit_reverse_dis data_bit_reverse_en
+ parameter hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass = "dec_64b66b_rxsm_bypass_dis" ,//dec_64b66b_rxsm_bypass_dis dec_64b66b_rxsm_bypass_en
+ parameter hssi_10g_rx_pcs_dec64b66b_clken = "dec64b66b_clk_dis" ,//dec64b66b_clk_dis dec64b66b_clk_en
+ parameter hssi_10g_rx_pcs_descrm_bypass = "descrm_bypass_en" ,//descrm_bypass_dis descrm_bypass_en
+ parameter hssi_10g_rx_pcs_descrm_clken = "descrm_clk_dis" ,//descrm_clk_dis descrm_clk_en
+ parameter hssi_10g_rx_pcs_descrm_mode = "async" ,//async sync
+ parameter hssi_10g_rx_pcs_descrm_pipeln = "enable" ,//disable enable
+ parameter hssi_10g_rx_pcs_dft_clk_out_sel = "rx_master_clk" ,//rx_64b66bdec_clk rx_ber_clk rx_blksync_clk rx_crcchk_clk rx_descrm_clk rx_fec_clk rx_frmsync_clk rx_gbexp_clk rx_master_clk rx_rand_clk rx_rdfifo_clk rx_wrfifo_clk
+ parameter hssi_10g_rx_pcs_dis_signal_ok = "dis_signal_ok_dis" ,//dis_signal_ok_dis dis_signal_ok_en
+ parameter hssi_10g_rx_pcs_dispchk_bypass = "dispchk_bypass_dis" ,//dispchk_bypass_dis dispchk_bypass_en
+ parameter hssi_10g_rx_pcs_empty_flag_type = "empty_rd_side" ,//empty_rd_side empty_wr_side
+ parameter hssi_10g_rx_pcs_fast_path = "fast_path_dis" ,//fast_path_dis fast_path_en
+ parameter hssi_10g_rx_pcs_fec_clken = "fec_clk_dis" ,//fec_clk_dis fec_clk_en
+ parameter hssi_10g_rx_pcs_fec_enable = "fec_dis" ,//fec_dis fec_en
+ parameter hssi_10g_rx_pcs_fifo_double_read = "fifo_double_read_dis" ,//fifo_double_read_dis fifo_double_read_en
+ parameter hssi_10g_rx_pcs_fifo_stop_rd = "n_rd_empty" ,//n_rd_empty rd_empty
+ parameter hssi_10g_rx_pcs_fifo_stop_wr = "n_wr_full" ,//n_wr_full wr_full
+ parameter hssi_10g_rx_pcs_force_align = "force_align_dis" ,//force_align_dis force_align_en
+ parameter hssi_10g_rx_pcs_frmsync_bypass = "frmsync_bypass_dis" ,//frmsync_bypass_dis frmsync_bypass_en
+ parameter hssi_10g_rx_pcs_frmsync_clken = "frmsync_clk_dis" ,//frmsync_clk_dis frmsync_clk_en
+ parameter hssi_10g_rx_pcs_frmsync_enum_scrm = "enum_scrm_default" ,//enum_scrm_default
+ parameter hssi_10g_rx_pcs_frmsync_enum_sync = "enum_sync_default" ,//enum_sync_default
+ parameter hssi_10g_rx_pcs_frmsync_flag_type = "all_framing_words" ,//all_framing_words location_only
+ parameter hssi_10g_rx_pcs_frmsync_knum_sync = "knum_sync_default" ,//knum_sync_default
+ parameter [15:0] hssi_10g_rx_pcs_frmsync_mfrm_length = 16'd2048 ,//0:65535
+ parameter hssi_10g_rx_pcs_frmsync_pipeln = "frmsync_pipeln_dis" ,//frmsync_pipeln_dis frmsync_pipeln_en
+ parameter hssi_10g_rx_pcs_full_flag_type = "full_wr_side" ,//full_rd_side full_wr_side
+ parameter hssi_10g_rx_pcs_gb_rx_idwidth = "width_32" ,//width_32 width_40 width_64
+ parameter hssi_10g_rx_pcs_gb_rx_odwidth = "width_66" ,//width_32 width_40 width_50 width_64 width_66 width_67
+ parameter hssi_10g_rx_pcs_gbexp_clken = "gbexp_clk_dis" ,//gbexp_clk_dis gbexp_clk_en
+ parameter hssi_10g_rx_pcs_low_latency_en = "enable" ,//disable enable
+ parameter hssi_10g_rx_pcs_lpbk_mode = "lpbk_dis" ,//lpbk_dis lpbk_en
+ parameter hssi_10g_rx_pcs_master_clk_sel = "master_rx_pma_clk" ,//master_refclk_dig master_rx_pma_clk master_tx_pma_clk
+ parameter hssi_10g_rx_pcs_pempty_flag_type = "pempty_rd_side" ,//pempty_rd_side pempty_wr_side
+ parameter hssi_10g_rx_pcs_pfull_flag_type = "pfull_wr_side" ,//pfull_rd_side pfull_wr_side
+ parameter hssi_10g_rx_pcs_phcomp_rd_del = "phcomp_rd_del2" ,//phcomp_rd_del2 phcomp_rd_del3 phcomp_rd_del4
+ parameter hssi_10g_rx_pcs_pld_if_type = "fifo" ,//fifo reg
+ parameter hssi_10g_rx_pcs_prot_mode = "disable_mode" ,//basic_krfec_mode basic_mode disable_mode interlaken_mode sfis_mode teng_1588_krfec_mode teng_1588_mode teng_baser_krfec_mode teng_baser_mode teng_sdi_mode test_prp_krfec_mode test_prp_mode
+ parameter hssi_10g_rx_pcs_rand_clken = "rand_clk_dis" ,//rand_clk_dis rand_clk_en
+ parameter hssi_10g_rx_pcs_rd_clk_sel = "rd_rx_pma_clk" ,//rd_refclk_dig rd_rx_pld_clk rd_rx_pma_clk
+ parameter hssi_10g_rx_pcs_rdfifo_clken = "rdfifo_clk_dis" ,//rdfifo_clk_dis rdfifo_clk_en
+ parameter hssi_10g_rx_pcs_rx_fifo_write_ctrl = "blklock_stops" ,//blklock_ignore blklock_stops
+ parameter hssi_10g_rx_pcs_rx_scrm_width = "bit64" ,//bit64 bit66 bit67
+ parameter hssi_10g_rx_pcs_rx_sh_location = "lsb" ,//lsb msb
+ parameter hssi_10g_rx_pcs_rx_signal_ok_sel = "synchronized_ver" ,//nonsync_ver synchronized_ver
+ parameter hssi_10g_rx_pcs_rx_sm_bypass = "rx_sm_bypass_dis" ,//rx_sm_bypass_dis rx_sm_bypass_en
+ parameter hssi_10g_rx_pcs_rx_sm_hiber = "rx_sm_hiber_en" ,//rx_sm_hiber_dis rx_sm_hiber_en
+ parameter hssi_10g_rx_pcs_rx_sm_pipeln = "rx_sm_pipeln_dis" ,//rx_sm_pipeln_dis rx_sm_pipeln_en
+ parameter hssi_10g_rx_pcs_rx_testbus_sel = "crc32_chk_testbus1" ,//ber_testbus blank_testbus blksync_testbus1 blksync_testbus2 crc32_chk_testbus1 crc32_chk_testbus2 dec64b66b_testbus descramble_testbus frame_sync_testbus1 frame_sync_testbus2 gearbox_exp_testbus random_ver_testbus rxsm_testbus rx_fifo_testbus1 rx_fifo_testbus2
+ parameter hssi_10g_rx_pcs_rx_true_b2b = "b2b" ,//b2b single
+ parameter hssi_10g_rx_pcs_rxfifo_empty = "empty_default" ,//empty_default
+ parameter hssi_10g_rx_pcs_rxfifo_full = "full_default" ,//full_default
+ parameter hssi_10g_rx_pcs_rxfifo_mode = "phase_comp" ,//clk_comp_10g generic_basic generic_interlaken phase_comp phase_comp_dv register_mode
+ parameter [4:0] hssi_10g_rx_pcs_rxfifo_pempty = 5'd2 ,//0:31
+ parameter [4:0] hssi_10g_rx_pcs_rxfifo_pfull = 5'd23 ,//0:31
+ parameter hssi_10g_rx_pcs_stretch_num_stages = "zero_stage" ,//one_stage three_stage two_stage zero_stage
+ parameter hssi_10g_rx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_10g_rx_pcs_test_mode = "test_off" ,//pseudo_random test_off
+ parameter hssi_10g_rx_pcs_wrfifo_clken = "wrfifo_clk_dis" ,//wrfifo_clk_dis wrfifo_clk_en
+ parameter hssi_10g_tx_pcs_bitslip_en = "bitslip_dis" ,//bitslip_dis bitslip_en
+ parameter hssi_10g_tx_pcs_bonding_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_10g_tx_pcs_bonding_dft_val = "dft_0" ,//dft_0 dft_1
+ parameter hssi_10g_tx_pcs_crcgen_bypass = "crcgen_bypass_dis" ,//crcgen_bypass_dis crcgen_bypass_en
+ parameter hssi_10g_tx_pcs_crcgen_clken = "crcgen_clk_dis" ,//crcgen_clk_dis crcgen_clk_en
+ parameter hssi_10g_tx_pcs_crcgen_err = "crcgen_err_dis" ,//crcgen_err_dis crcgen_err_en
+ parameter hssi_10g_tx_pcs_crcgen_inv = "crcgen_inv_dis" ,//crcgen_inv_dis crcgen_inv_en
+ parameter hssi_10g_tx_pcs_ctrl_bit_reverse = "ctrl_bit_reverse_dis" ,//ctrl_bit_reverse_dis ctrl_bit_reverse_en
+ parameter hssi_10g_tx_pcs_data_bit_reverse = "data_bit_reverse_dis" ,//data_bit_reverse_dis data_bit_reverse_en
+ parameter hssi_10g_tx_pcs_dft_clk_out_sel = "tx_master_clk" ,//tx_64b66benc_txsm_clk tx_crcgen_clk tx_dispgen_clk tx_fec_clk tx_frmgen_clk tx_gbred_clk tx_master_clk tx_rdfifo_clk tx_scrm_clk tx_wrfifo_clk
+ parameter hssi_10g_tx_pcs_dispgen_bypass = "dispgen_bypass_dis" ,//dispgen_bypass_dis dispgen_bypass_en
+ parameter hssi_10g_tx_pcs_dispgen_clken = "dispgen_clk_dis" ,//dispgen_clk_dis dispgen_clk_en
+ parameter hssi_10g_tx_pcs_dispgen_err = "dispgen_err_dis" ,//dispgen_err_dis dispgen_err_en
+ parameter hssi_10g_tx_pcs_dispgen_pipeln = "dispgen_pipeln_dis" ,//dispgen_pipeln_dis dispgen_pipeln_en
+ parameter hssi_10g_tx_pcs_empty_flag_type = "empty_rd_side" ,//empty_rd_side empty_wr_side
+ parameter hssi_10g_tx_pcs_enc_64b66b_txsm_bypass = "enc_64b66b_txsm_bypass_dis" ,//enc_64b66b_txsm_bypass_dis enc_64b66b_txsm_bypass_en
+ parameter hssi_10g_tx_pcs_enc64b66b_txsm_clken = "enc64b66b_txsm_clk_dis" ,//enc64b66b_txsm_clk_dis enc64b66b_txsm_clk_en
+ parameter hssi_10g_tx_pcs_fastpath = "fastpath_dis" ,//fastpath_dis fastpath_en
+ parameter hssi_10g_tx_pcs_fec_clken = "fec_clk_dis" ,//fec_clk_dis fec_clk_en
+ parameter hssi_10g_tx_pcs_fec_enable = "fec_dis" ,//fec_dis fec_en
+ parameter hssi_10g_tx_pcs_fifo_double_write = "fifo_double_write_dis" ,//fifo_double_write_dis fifo_double_write_en
+ parameter hssi_10g_tx_pcs_fifo_reg_fast = "fifo_reg_fast_dis" ,//fifo_reg_fast_dis fifo_reg_fast_en
+ parameter hssi_10g_tx_pcs_fifo_stop_rd = "n_rd_empty" ,//n_rd_empty rd_empty
+ parameter hssi_10g_tx_pcs_fifo_stop_wr = "n_wr_full" ,//n_wr_full wr_full
+ parameter hssi_10g_tx_pcs_frmgen_burst = "frmgen_burst_dis" ,//frmgen_burst_dis frmgen_burst_en
+ parameter hssi_10g_tx_pcs_frmgen_bypass = "frmgen_bypass_dis" ,//frmgen_bypass_dis frmgen_bypass_en
+ parameter hssi_10g_tx_pcs_frmgen_clken = "frmgen_clk_dis" ,//frmgen_clk_dis frmgen_clk_en
+ parameter [15:0] hssi_10g_tx_pcs_frmgen_mfrm_length = 16'd2048 ,//0:65535
+ parameter hssi_10g_tx_pcs_frmgen_pipeln = "frmgen_pipeln_dis" ,//frmgen_pipeln_dis frmgen_pipeln_en
+ parameter hssi_10g_tx_pcs_frmgen_pyld_ins = "frmgen_pyld_ins_dis" ,//frmgen_pyld_ins_dis frmgen_pyld_ins_en
+ parameter hssi_10g_tx_pcs_frmgen_wordslip = "frmgen_wordslip_dis" ,//frmgen_wordslip_dis frmgen_wordslip_en
+ parameter hssi_10g_tx_pcs_full_flag_type = "full_wr_side" ,//full_rd_side full_wr_side
+ parameter hssi_10g_tx_pcs_gb_pipeln_bypass = "enable" ,//disable enable
+ parameter hssi_10g_tx_pcs_gb_tx_idwidth = "width_50" ,//width_32 width_40 width_50 width_64 width_66 width_67
+ parameter hssi_10g_tx_pcs_gb_tx_odwidth = "width_32" ,//width_32 width_40 width_64
+ parameter hssi_10g_tx_pcs_gbred_clken = "gbred_clk_dis" ,//gbred_clk_dis gbred_clk_en
+ parameter hssi_10g_tx_pcs_low_latency_en = "enable" ,//disable enable
+ parameter hssi_10g_tx_pcs_master_clk_sel = "master_tx_pma_clk" ,//master_refclk_dig master_tx_pma_clk
+ parameter hssi_10g_tx_pcs_pempty_flag_type = "pempty_rd_side" ,//pempty_rd_side pempty_wr_side
+ parameter hssi_10g_tx_pcs_pfull_flag_type = "pfull_wr_side" ,//pfull_rd_side pfull_wr_side
+ parameter hssi_10g_tx_pcs_phcomp_rd_del = "phcomp_rd_del2" ,//phcomp_rd_del2 phcomp_rd_del3 phcomp_rd_del4
+ parameter hssi_10g_tx_pcs_pld_if_type = "fifo" ,//fastreg fifo reg
+ parameter hssi_10g_tx_pcs_prot_mode = "disable_mode" ,//basic_krfec_mode basic_mode disable_mode interlaken_mode sfis_mode teng_1588_krfec_mode teng_1588_mode teng_baser_krfec_mode teng_baser_mode teng_sdi_mode test_prp_krfec_mode test_prp_mode
+ parameter hssi_10g_tx_pcs_pseudo_random = "all_0" ,//all_0 two_lf
+ parameter hssi_10g_tx_pcs_pseudo_seed_a = "288230376151711743" ,//NOVAL
+ parameter hssi_10g_tx_pcs_pseudo_seed_b = "288230376151711743" ,//NOVAL
+ parameter hssi_10g_tx_pcs_random_disp = "disable" ,//disable enable
+ parameter hssi_10g_tx_pcs_rdfifo_clken = "rdfifo_clk_dis" ,//rdfifo_clk_dis rdfifo_clk_en
+ parameter hssi_10g_tx_pcs_scrm_bypass = "scrm_bypass_dis" ,//scrm_bypass_dis scrm_bypass_en
+ parameter hssi_10g_tx_pcs_scrm_clken = "scrm_clk_dis" ,//scrm_clk_dis scrm_clk_en
+ parameter hssi_10g_tx_pcs_scrm_mode = "async" ,//async sync
+ parameter hssi_10g_tx_pcs_scrm_pipeln = "enable" ,//disable enable
+ parameter hssi_10g_tx_pcs_sh_err = "sh_err_dis" ,//sh_err_dis sh_err_en
+ parameter hssi_10g_tx_pcs_sop_mark = "sop_mark_dis" ,//sop_mark_dis sop_mark_en
+ parameter hssi_10g_tx_pcs_stretch_num_stages = "zero_stage" ,//one_stage three_stage two_stage zero_stage
+ parameter hssi_10g_tx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_10g_tx_pcs_test_mode = "test_off" ,//pseudo_random test_off
+ parameter hssi_10g_tx_pcs_tx_scrm_err = "scrm_err_dis" ,//scrm_err_dis scrm_err_en
+ parameter hssi_10g_tx_pcs_tx_scrm_width = "bit64" ,//bit64 bit66 bit67
+ parameter hssi_10g_tx_pcs_tx_sh_location = "lsb" ,//lsb msb
+ parameter hssi_10g_tx_pcs_tx_sm_bypass = "tx_sm_bypass_dis" ,//tx_sm_bypass_dis tx_sm_bypass_en
+ parameter hssi_10g_tx_pcs_tx_sm_pipeln = "tx_sm_pipeln_dis" ,//tx_sm_pipeln_dis tx_sm_pipeln_en
+ parameter hssi_10g_tx_pcs_tx_testbus_sel = "crc32_gen_testbus1" ,//blank_testbus crc32_gen_testbus1 crc32_gen_testbus2 disp_gen_testbus1 disp_gen_testbus2 enc64b66b_testbus frame_gen_testbus1 frame_gen_testbus2 gearbox_red_testbus scramble_testbus txsm_testbus tx_cp_bond_testbus tx_fifo_testbus1 tx_fifo_testbus2
+ parameter hssi_10g_tx_pcs_txfifo_empty = "empty_default" ,//empty_default
+ parameter hssi_10g_tx_pcs_txfifo_full = "full_default" ,//full_default
+ parameter hssi_10g_tx_pcs_txfifo_mode = "phase_comp" ,//basic_generic interlaken_generic phase_comp register_mode
+ parameter [3:0] hssi_10g_tx_pcs_txfifo_pempty = 4'd2 ,//0:15
+ parameter [3:0] hssi_10g_tx_pcs_txfifo_pfull = 4'd11 ,//0:15
+ parameter hssi_10g_tx_pcs_wr_clk_sel = "wr_tx_pma_clk" ,//wr_refclk_dig wr_tx_pld_clk wr_tx_pma_clk
+ parameter hssi_10g_tx_pcs_wrfifo_clken = "wrfifo_clk_dis" ,//wrfifo_clk_dis wrfifo_clk_en
+ parameter hssi_8g_rx_pcs_auto_error_replacement = "dis_err_replace" ,//dis_err_replace en_err_replace
+ parameter hssi_8g_rx_pcs_bit_reversal = "dis_bit_reversal" ,//dis_bit_reversal en_bit_reversal
+ parameter hssi_8g_rx_pcs_bonding_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_8g_rx_pcs_bonding_dft_val = "dft_0" ,//dft_0 dft_1
+ parameter hssi_8g_rx_pcs_bypass_pipeline_reg = "dis_bypass_pipeline" ,//dis_bypass_pipeline en_bypass_pipeline
+ parameter hssi_8g_rx_pcs_byte_deserializer = "dis_bds" ,//dis_bds en_bds_by_2 en_bds_by_2_det en_bds_by_4
+ parameter hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask = "dis_rxvalid_mask" ,//dis_rxvalid_mask en_rxvalid_mask
+ parameter [19:0] hssi_8g_rx_pcs_clkcmp_pattern_n = 20'd0 ,//0:1048575
+ parameter [19:0] hssi_8g_rx_pcs_clkcmp_pattern_p = 20'd0 ,//0:1048575
+ parameter hssi_8g_rx_pcs_clock_gate_bds_dec_asn = "dis_bds_dec_asn_clk_gating" ,//dis_bds_dec_asn_clk_gating en_bds_dec_asn_clk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_cdr_eidle = "dis_cdr_eidle_clk_gating" ,//dis_cdr_eidle_clk_gating en_cdr_eidle_clk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk = "dis_dw_pc_wrclk_gating" ,//dis_dw_pc_wrclk_gating en_dw_pc_wrclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_dw_rm_rd = "dis_dw_rm_rdclk_gating" ,//dis_dw_rm_rdclk_gating en_dw_rm_rdclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_dw_rm_wr = "dis_dw_rm_wrclk_gating" ,//dis_dw_rm_wrclk_gating en_dw_rm_wrclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_dw_wa = "dis_dw_wa_clk_gating" ,//dis_dw_wa_clk_gating en_dw_wa_clk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_pc_rdclk = "dis_pc_rdclk_gating" ,//dis_pc_rdclk_gating en_pc_rdclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk = "dis_sw_pc_wrclk_gating" ,//dis_sw_pc_wrclk_gating en_sw_pc_wrclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_sw_rm_rd = "dis_sw_rm_rdclk_gating" ,//dis_sw_rm_rdclk_gating en_sw_rm_rdclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_sw_rm_wr = "dis_sw_rm_wrclk_gating" ,//dis_sw_rm_wrclk_gating en_sw_rm_wrclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_sw_wa = "dis_sw_wa_clk_gating" ,//dis_sw_wa_clk_gating en_sw_wa_clk_gating
+ parameter hssi_8g_rx_pcs_clock_observation_in_pld_core = "internal_sw_wa_clk" ,//internal_cdr_eidle_clk internal_clk_2_b internal_dw_rm_rd_clk internal_dw_rm_wr_clk internal_dw_rx_wr_clk internal_dw_wa_clk internal_rx_pma_clk_gen3 internal_rx_rcvd_clk_gen3 internal_rx_rd_clk internal_sm_rm_wr_clk internal_sw_rm_rd_clk internal_sw_rx_wr_clk internal_sw_wa_clk
+ parameter hssi_8g_rx_pcs_eidle_entry_eios = "dis_eidle_eios" ,//dis_eidle_eios en_eidle_eios
+ parameter hssi_8g_rx_pcs_eidle_entry_iei = "dis_eidle_iei" ,//dis_eidle_iei en_eidle_iei
+ parameter hssi_8g_rx_pcs_eidle_entry_sd = "dis_eidle_sd" ,//dis_eidle_sd en_eidle_sd
+ parameter hssi_8g_rx_pcs_eightb_tenb_decoder = "dis_8b10b" ,//dis_8b10b en_8b10b_ibm en_8b10b_sgx
+ parameter hssi_8g_rx_pcs_err_flags_sel = "err_flags_wa" ,//err_flags_8b10b err_flags_wa
+ parameter hssi_8g_rx_pcs_fixed_pat_det = "dis_fixed_patdet" ,//dis_fixed_patdet en_fixed_patdet
+ parameter [3:0] hssi_8g_rx_pcs_fixed_pat_num = 4'd15 ,//0:15
+ parameter hssi_8g_rx_pcs_force_signal_detect = "en_force_signal_detect" ,//dis_force_signal_detect en_force_signal_detect
+ parameter hssi_8g_rx_pcs_gen3_clk_en = "disable_clk" ,//disable_clk enable_clk
+ parameter hssi_8g_rx_pcs_gen3_rx_clk_sel = "rcvd_clk" ,//en_dig_clk1_8g rcvd_clk
+ parameter hssi_8g_rx_pcs_gen3_tx_clk_sel = "tx_pma_clk" ,//en_dig_clk2_8g tx_pma_clk
+ parameter hssi_8g_rx_pcs_hip_mode = "dis_hip" ,//dis_hip en_hip
+ parameter hssi_8g_rx_pcs_ibm_invalid_code = "dis_ibm_invalid_code" ,//dis_ibm_invalid_code en_ibm_invalid_code
+ parameter hssi_8g_rx_pcs_invalid_code_flag_only = "dis_invalid_code_only" ,//dis_invalid_code_only en_invalid_code_only
+ parameter hssi_8g_rx_pcs_pad_or_edb_error_replace = "replace_edb" ,//replace_edb replace_edb_dynamic replace_pad
+ parameter hssi_8g_rx_pcs_pcs_bypass = "dis_pcs_bypass" ,//dis_pcs_bypass en_pcs_bypass
+ parameter hssi_8g_rx_pcs_phase_comp_rdptr = "enable_rdptr" ,//disable_rdptr enable_rdptr
+ parameter hssi_8g_rx_pcs_phase_compensation_fifo = "low_latency" ,//low_latency normal_latency pld_ctrl_low_latency pld_ctrl_normal_latency register_fifo
+ parameter hssi_8g_rx_pcs_pipe_if_enable = "dis_pipe_rx" ,//dis_pipe_rx en_pipe3_rx en_pipe_rx
+ parameter hssi_8g_rx_pcs_pma_dw = "eight_bit" ,//eight_bit sixteen_bit ten_bit twenty_bit
+ parameter hssi_8g_rx_pcs_polinv_8b10b_dec = "dis_polinv_8b10b_dec" ,//dis_polinv_8b10b_dec en_polinv_8b10b_dec
+ parameter hssi_8g_rx_pcs_prot_mode = "gige" ,//basic_rm_disable basic_rm_enable cpri cpri_rx_tx disabled_prot_mode gige gige_1588 pipe_g1 pipe_g2 pipe_g3
+ parameter hssi_8g_rx_pcs_rate_match = "dis_rm" ,//dis_rm dw_basic_rm gige_rm pipe_rm pipe_rm_0ppm sw_basic_rm
+ parameter hssi_8g_rx_pcs_rate_match_del_thres = "dis_rm_del_thres" ,//dis_rm_del_thres dw_basic_rm_del_thres gige_rm_del_thres pipe_rm_0ppm_del_thres pipe_rm_del_thres sw_basic_rm_del_thres
+ parameter hssi_8g_rx_pcs_rate_match_empty_thres = "dis_rm_empty_thres" ,//dis_rm_empty_thres dw_basic_rm_empty_thres gige_rm_empty_thres pipe_rm_0ppm_empty_thres pipe_rm_empty_thres sw_basic_rm_empty_thres
+ parameter hssi_8g_rx_pcs_rate_match_full_thres = "dis_rm_full_thres" ,//dis_rm_full_thres dw_basic_rm_full_thres gige_rm_full_thres pipe_rm_0ppm_full_thres pipe_rm_full_thres sw_basic_rm_full_thres
+ parameter hssi_8g_rx_pcs_rate_match_ins_thres = "dis_rm_ins_thres" ,//dis_rm_ins_thres dw_basic_rm_ins_thres gige_rm_ins_thres pipe_rm_0ppm_ins_thres pipe_rm_ins_thres sw_basic_rm_ins_thres
+ parameter hssi_8g_rx_pcs_rate_match_start_thres = "dis_rm_start_thres" ,//dis_rm_start_thres dw_basic_rm_start_thres gige_rm_start_thres pipe_rm_0ppm_start_thres pipe_rm_start_thres sw_basic_rm_start_thres
+ parameter hssi_8g_rx_pcs_rx_clk_free_running = "en_rx_clk_free_run" ,//dis_rx_clk_free_run en_rx_clk_free_run
+ parameter hssi_8g_rx_pcs_rx_clk2 = "rcvd_clk_clk2" ,//rcvd_clk_clk2 refclk_dig2_clk2 tx_pma_clock_clk2
+ parameter hssi_8g_rx_pcs_rx_pcs_urst = "en_rx_pcs_urst" ,//dis_rx_pcs_urst en_rx_pcs_urst
+ parameter hssi_8g_rx_pcs_rx_rcvd_clk = "rcvd_clk_rcvd_clk" ,//rcvd_clk_rcvd_clk tx_pma_clock_rcvd_clk
+ parameter hssi_8g_rx_pcs_rx_rd_clk = "pld_rx_clk" ,//pld_rx_clk rx_clk
+ parameter hssi_8g_rx_pcs_rx_refclk = "dis_refclk_sel" ,//dis_refclk_sel en_refclk_sel
+ parameter hssi_8g_rx_pcs_rx_wr_clk = "rx_clk2_div_1_2_4" ,//rx_clk2_div_1_2_4 txfifo_rd_clk
+ parameter hssi_8g_rx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_8g_rx_pcs_symbol_swap = "dis_symbol_swap" ,//dis_symbol_swap en_symbol_swap
+ parameter hssi_8g_rx_pcs_sync_sm_idle_eios = "dis_syncsm_idle" ,//dis_syncsm_idle en_syncsm_idle
+ parameter hssi_8g_rx_pcs_test_bus_sel = "tx_testbus" ,//pcie_ctrl_testbus rm_testbus rx_ctrl_plane_testbus rx_ctrl_testbus tx_ctrl_plane_testbus tx_testbus wa_testbus
+ parameter hssi_8g_rx_pcs_tx_rx_parallel_loopback = "dis_plpbk" ,//dis_plpbk en_plpbk
+ parameter hssi_8g_rx_pcs_wa_boundary_lock_ctrl = "bit_slip" ,//auto_align_pld_ctrl bit_slip deterministic_latency sync_sm
+ parameter [9:0] hssi_8g_rx_pcs_wa_clk_slip_spacing = 10'd16 ,//0:1023
+ parameter hssi_8g_rx_pcs_wa_det_latency_sync_status_beh = "assert_sync_status_non_imm" ,//assert_sync_status_imm assert_sync_status_non_imm dont_care_assert_sync
+ parameter hssi_8g_rx_pcs_wa_disp_err_flag = "dis_disp_err_flag" ,//dis_disp_err_flag en_disp_err_flag
+ parameter hssi_8g_rx_pcs_wa_kchar = "dis_kchar" ,//dis_kchar en_kchar
+ parameter hssi_8g_rx_pcs_wa_pd = "wa_pd_10" ,//wa_pd_10 wa_pd_16_dw wa_pd_16_sw wa_pd_20 wa_pd_32 wa_pd_40 wa_pd_7 wa_pd_8_dw wa_pd_8_sw
+ parameter hssi_8g_rx_pcs_wa_pd_data = "0" ,//NOVAL
+ parameter hssi_8g_rx_pcs_wa_pd_polarity = "dis_pd_both_pol" ,//dis_pd_both_pol dont_care_both_pol en_pd_both_pol
+ parameter hssi_8g_rx_pcs_wa_pld_controlled = "dis_pld_ctrl" ,//dis_pld_ctrl level_sensitive_dw pld_ctrl_sw rising_edge_sensitive_dw
+ parameter [5:0] hssi_8g_rx_pcs_wa_renumber_data = 6'd0 ,//0:63
+ parameter [7:0] hssi_8g_rx_pcs_wa_rgnumber_data = 8'd0 ,//0:255
+ parameter [7:0] hssi_8g_rx_pcs_wa_rknumber_data = 8'd0 ,//0:255
+ parameter [1:0] hssi_8g_rx_pcs_wa_rosnumber_data = 2'd0 ,//0:3
+ parameter [12:0] hssi_8g_rx_pcs_wa_rvnumber_data = 13'd0 ,//0:8191
+ parameter hssi_8g_rx_pcs_wa_sync_sm_ctrl = "gige_sync_sm" ,//dw_basic_sync_sm fibre_channel_sync_sm gige_sync_sm pipe_sync_sm sw_basic_sync_sm
+ parameter [11:0] hssi_8g_rx_pcs_wait_cnt = 12'd0 ,//0:4095
+ parameter hssi_8g_tx_pcs_bit_reversal = "dis_bit_reversal" ,//dis_bit_reversal en_bit_reversal
+ parameter hssi_8g_tx_pcs_bonding_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_8g_tx_pcs_bonding_dft_val = "dft_0" ,//dft_0 dft_1
+ parameter hssi_8g_tx_pcs_bypass_pipeline_reg = "dis_bypass_pipeline" ,//dis_bypass_pipeline en_bypass_pipeline
+ parameter hssi_8g_tx_pcs_byte_serializer = "dis_bs" ,//dis_bs en_bs_by_2 en_bs_by_4
+ parameter hssi_8g_tx_pcs_clock_gate_bs_enc = "dis_bs_enc_clk_gating" ,//dis_bs_enc_clk_gating en_bs_enc_clk_gating
+ parameter hssi_8g_tx_pcs_clock_gate_dw_fifowr = "dis_dw_fifowr_clk_gating" ,//dis_dw_fifowr_clk_gating en_dw_fifowr_clk_gating
+ parameter hssi_8g_tx_pcs_clock_gate_fiford = "dis_fiford_clk_gating" ,//dis_fiford_clk_gating en_fiford_clk_gating
+ parameter hssi_8g_tx_pcs_clock_gate_sw_fifowr = "dis_sw_fifowr_clk_gating" ,//dis_sw_fifowr_clk_gating en_sw_fifowr_clk_gating
+ parameter hssi_8g_tx_pcs_clock_observation_in_pld_core = "internal_refclk_b" ,//internal_dw_fifo_wr_clk internal_fifo_rd_clk internal_pipe_tx_clk_out_gen3 internal_refclk_b internal_sw_fifo_wr_clk internal_tx_clk_out_gen3
+ parameter hssi_8g_tx_pcs_data_selection_8b10b_encoder_input = "normal_data_path" ,//gige_idle_conversion normal_data_path
+ parameter hssi_8g_tx_pcs_dynamic_clk_switch = "dis_dyn_clk_switch" ,//dis_dyn_clk_switch en_dyn_clk_switch
+ parameter hssi_8g_tx_pcs_eightb_tenb_disp_ctrl = "dis_disp_ctrl" ,//dis_disp_ctrl en_disp_ctrl en_ib_disp_ctrl
+ parameter hssi_8g_tx_pcs_eightb_tenb_encoder = "dis_8b10b" ,//dis_8b10b en_8b10b_ibm en_8b10b_sgx
+ parameter hssi_8g_tx_pcs_force_echar = "dis_force_echar" ,//dis_force_echar en_force_echar
+ parameter hssi_8g_tx_pcs_force_kchar = "dis_force_kchar" ,//dis_force_kchar en_force_kchar
+ parameter hssi_8g_tx_pcs_gen3_tx_clk_sel = "tx_pma_clk" ,//dis_tx_clk tx_pma_clk
+ parameter hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel = "func_clk" ,//dis_tx_pipe_clk func_clk
+ parameter hssi_8g_tx_pcs_hip_mode = "dis_hip" ,//dis_hip en_hip
+ parameter hssi_8g_tx_pcs_pcs_bypass = "dis_pcs_bypass" ,//dis_pcs_bypass en_pcs_bypass
+ parameter hssi_8g_tx_pcs_phase_comp_rdptr = "enable_rdptr" ,//disable_rdptr enable_rdptr
+ parameter hssi_8g_tx_pcs_phase_compensation_fifo = "low_latency" ,//low_latency normal_latency pld_ctrl_low_latency pld_ctrl_normal_latency register_fifo
+ parameter hssi_8g_tx_pcs_phfifo_write_clk_sel = "pld_tx_clk" ,//pld_tx_clk tx_clk
+ parameter hssi_8g_tx_pcs_pma_dw = "eight_bit" ,//eight_bit sixteen_bit ten_bit twenty_bit
+ parameter hssi_8g_tx_pcs_prot_mode = "basic" ,//basic cpri cpri_rx_tx disabled_prot_mode gige gige_1588 pipe_g1 pipe_g2 pipe_g3
+ parameter hssi_8g_tx_pcs_refclk_b_clk_sel = "tx_pma_clock" ,//refclk_dig tx_pma_clock
+ parameter hssi_8g_tx_pcs_revloop_back_rm = "dis_rev_loopback_rx_rm" ,//dis_rev_loopback_rx_rm en_rev_loopback_rx_rm
+ parameter hssi_8g_tx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_8g_tx_pcs_symbol_swap = "dis_symbol_swap" ,//dis_symbol_swap en_symbol_swap
+ parameter hssi_8g_tx_pcs_tx_bitslip = "dis_tx_bitslip" ,//dis_tx_bitslip en_tx_bitslip
+ parameter hssi_8g_tx_pcs_tx_compliance_controlled_disparity = "dis_txcompliance" ,//dis_txcompliance en_txcompliance_pipe2p0 en_txcompliance_pipe3p0
+ parameter hssi_8g_tx_pcs_tx_fast_pld_reg = "dis_tx_fast_pld_reg" ,//dis_tx_fast_pld_reg en_tx_fast_pld_reg
+ parameter hssi_8g_tx_pcs_txclk_freerun = "dis_freerun_tx" ,//dis_freerun_tx en_freerun_tx
+ parameter hssi_8g_tx_pcs_txpcs_urst = "en_txpcs_urst" ,//dis_txpcs_urst en_txpcs_urst
+ parameter cdr_pll_pma_width = 8 ,//8 10 16 20 32 40 64
+ parameter cdr_pll_cgb_div = 1 ,//1:2 4 8
+ parameter cdr_pll_is_cascaded_pll = "false" ,//false true
+ parameter cdr_pll_datarate = "0 bps" ,//NOVAL
+ parameter [4:0] cdr_pll_lpd_counter = 5'd1 ,//0:31
+ parameter [4:0] cdr_pll_lpfd_counter = 5'd1 ,//0:31
+ parameter [5:0] cdr_pll_n_counter_scratch = 6'd1 ,//0:63
+ parameter cdr_pll_output_clock_frequency = "0 hz" ,//NOVAL
+ parameter cdr_pll_reference_clock_frequency = "0 hz" ,//NOVAL
+ parameter [4:0] cdr_pll_set_cdr_vco_speed = 5'd1 ,//0:31
+ parameter [7:0] cdr_pll_set_cdr_vco_speed_fix = 8'd0 ,//0:255
+ parameter cdr_pll_vco_freq = "0 hz" ,//NOVAL
+ parameter cdr_pll_atb_select_control = "atb_off" ,//atb_off atb_select_tp_1 atb_select_tp_10 atb_select_tp_11 atb_select_tp_12 atb_select_tp_13 atb_select_tp_14 atb_select_tp_15 atb_select_tp_2 atb_select_tp_3 atb_select_tp_4 atb_select_tp_5 atb_select_tp_6 atb_select_tp_7 atb_select_tp_8 atb_select_tp_9
+ parameter cdr_pll_auto_reset_on = "auto_reset_on" ,//auto_reset_off auto_reset_on
+ parameter cdr_pll_bbpd_data_pattern_filter_select = "bbpd_data_pat_off" ,//bbpd_data_pat_1 bbpd_data_pat_2 bbpd_data_pat_3 bbpd_data_pat_off
+ parameter cdr_pll_bw_sel = "low" ,//high low medium
+ parameter cdr_pll_cdr_odi_select = "sel_cdr" ,//sel_cdr sel_odi
+ parameter cdr_pll_cdr_phaselock_mode = "no_ignore_lock" ,//ignore_lock no_ignore_lock
+ parameter cdr_pll_cdr_powerdown_mode = "power_down" ,//power_down power_up
+ parameter cdr_pll_chgpmp_current_pd = "cp_current_pd_setting0" ,//cp_current_pd_setting0 cp_current_pd_setting1 cp_current_pd_setting2 cp_current_pd_setting3 cp_current_pd_setting4
+ parameter cdr_pll_chgpmp_current_pfd = "cp_current_pfd_setting0" ,//cp_current_pfd_setting0 cp_current_pfd_setting1 cp_current_pfd_setting2 cp_current_pfd_setting3 cp_current_pfd_setting4
+ parameter cdr_pll_chgpmp_replicate = "true" ,//false true
+ parameter cdr_pll_chgpmp_testmode = "cp_test_disable" ,//cp_test_disable cp_test_dn cp_test_up cp_tristate
+ parameter cdr_pll_clklow_mux_select = "clklow_mux_cdr_fbclk" ,//clklow_mux_cdr_fbclk clklow_mux_dfe_test clklow_mux_fpll_test1 clklow_mux_reserved_1 clklow_mux_reserved_2 clklow_mux_reserved_3 clklow_mux_reserved_4 clklow_mux_rx_deser_pclk_test
+ parameter cdr_pll_diag_loopback_enable = "false" ,//false true
+ parameter cdr_pll_disable_up_dn = "true" ,//false true
+ parameter cdr_pll_fref_clklow_div = 1 ,//1:2 4 8
+ parameter cdr_pll_fref_mux_select = "fref_mux_cdr_refclk" ,//fref_mux_cdr_refclk fref_mux_fpll_test0 fref_mux_reserved_1 fref_mux_reserved_2 fref_mux_reserved_3 fref_mux_reserved_4 fref_mux_reserved_5 fref_mux_tx_ser_pclk_test
+ parameter cdr_pll_gpon_lck2ref_control = "gpon_lck2ref_off" ,//gpon_lck2ref_off gpon_lck2ref_on
+ parameter cdr_pll_initial_settings = "false" ,//false true
+ parameter cdr_pll_lck2ref_delay_control = "lck2ref_delay_off" ,//lck2ref_delay_1 lck2ref_delay_2 lck2ref_delay_3 lck2ref_delay_4 lck2ref_delay_5 lck2ref_delay_6 lck2ref_delay_7 lck2ref_delay_off
+ parameter cdr_pll_lf_resistor_pd = "lf_pd_setting0" ,//lf_pd_setting0 lf_pd_setting1 lf_pd_setting2 lf_pd_setting3
+ parameter cdr_pll_lf_resistor_pfd = "lf_pfd_setting0" ,//lf_pfd_setting0 lf_pfd_setting1 lf_pfd_setting2 lf_pfd_setting3
+ parameter cdr_pll_lf_ripple_cap = "lf_no_ripple" ,//lf_no_ripple lf_ripple_cap1
+ parameter cdr_pll_loop_filter_bias_select = "lpflt_bias_off" ,//lpflt_bias_1 lpflt_bias_2 lpflt_bias_3 lpflt_bias_4 lpflt_bias_5 lpflt_bias_6 lpflt_bias_7 lpflt_bias_off
+ parameter cdr_pll_loopback_mode = "loopback_disabled" ,//loopback_disabled loopback_received_data loopback_recovered_data
+ parameter cdr_pll_ltd_ltr_micro_controller_select = "ltd_ltr_pcs" ,//ltd_ltr_pcs ltd_ucontroller ltr_ucontroller
+ parameter cdr_pll_m_counter = 1 ,//1:6 8:10 12 15:16 18 20 24:25 30 32:33 36 40 48 50 60 64 80 100
+ parameter cdr_pll_n_counter = 1 ,//1:2 4 8
+ parameter cdr_pll_pd_fastlock_mode = "false" ,//false true
+ parameter cdr_pll_pd_l_counter = 1 ,//0:2 4 8 16
+ parameter cdr_pll_pfd_l_counter = 1 ,//0:2 4 8 16 100
+ parameter cdr_pll_primary_use = "cmu" ,//cdr cmu
+ parameter cdr_pll_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter cdr_pll_requires_gt_capable_channel = "false" ,//false true
+ parameter cdr_pll_reverse_serial_loopback = "no_loopback" ,//loopback_data_0_1 loopback_data_no_posttap loopback_data_with_posttap no_loopback
+ parameter cdr_pll_set_cdr_v2i_enable = "true" ,//false true
+ parameter cdr_pll_set_cdr_vco_reset = "false" ,//false true
+ parameter cdr_pll_set_cdr_vco_speed_pciegen3 = "cdr_vco_max_speedbin_pciegen3" ,//cdr_vco_max_speedbin_pciegen3 cdr_vco_min_speedbin_pciegen3
+ parameter cdr_pll_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter cdr_pll_tx_pll_prot_mode = "txpll_unused" ,//txpll_enable txpll_enable_pcie txpll_unused
+ parameter cdr_pll_txpll_hclk_driver_enable = "false" ,//false true
+ parameter cdr_pll_vco_overrange_voltage = "vco_overrange_off" ,// new
+ parameter cdr_pll_vco_underrange_voltage = "vco_underrange_off" ,// new
+ parameter cdr_pll_fb_select = "direct_fb" ,//direct_fb iqtxrxclk_fb
+ parameter cdr_pll_uc_ro_cal = "uc_ro_cal_off" ,//uc_ro_cal_off uc_ro_cal_on
+ parameter cdr_pll_iqclk_mux_sel = "power_down" ,//iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 power_down
+ parameter cdr_pll_pcie_gen = "non_pcie" ,//non_pcie pcie_gen1_100mhzref pcie_gen1_125mhzref pcie_gen2_100mhzref pcie_gen2_125mhzref pcie_gen3_100mhzref pcie_gen3_125mhzref
+ parameter [7:0] cdr_pll_set_cdr_input_freq_range = 8'b11111111 ,
+ parameter cdr_pll_chgpmp_current_dn_trim = "cp_current_trimming_dn_setting0" ,
+ parameter cdr_pll_chgpmp_up_pd_trim_double = "normal_up_trim_current" ,
+ parameter cdr_pll_chgpmp_current_up_pd = "cp_current_pd_up_setting0" ,
+ parameter cdr_pll_chgpmp_current_up_trim = "cp_current_trimming_up_setting0" ,
+ parameter cdr_pll_chgpmp_dn_pd_trim_double = "normal_dn_trim_current" ,
+ parameter cdr_pll_cal_vco_count_length = "sel_8b_count" ,// new
+ parameter cdr_pll_chgpmp_current_dn_pd = "cp_current_pd_dn_setting0" ,
+ parameter pma_rx_odi_datarate = "0 bps" ,//NOVAL
+ parameter pma_rx_odi_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_rx_odi_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_rx_buf_bypass_eqz_stages_234 = "bypass_off" ,//bypass_off byypass_stages_234
+ parameter pma_rx_buf_datarate = "0 bps" ,//NOVAL
+ parameter pma_rx_buf_diag_lp_en = "dlp_off" ,//dlp_off dlp_on
+ parameter pma_rx_buf_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_rx_buf_qpi_enable = "non_qpi_mode" ,//non_qpi_mode qpi_mode
+ parameter pma_rx_buf_rx_refclk_divider = "bypass_divider" ,//bypass_divider divide_by_2
+ parameter pma_rx_buf_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_rx_buf_loopback_modes = "lpbk_disable" ,//lpbk_disable post_cdr pre_cdr
+ parameter pma_rx_buf_refclk_en = "disable" ,//disable enable
+ parameter pma_rx_buf_pm_tx_rx_pcie_gen = "non_pcie" ,//non_pcie pcie_gen1_100mhzref pcie_gen1_125mhzref pcie_gen2_100mhzref pcie_gen2_125mhzref pcie_gen3_100mhzref pcie_gen3_125mhzref
+ parameter pma_rx_buf_pm_tx_rx_pcie_gen_bitwidth = "pcie_gen3_32b" ,//pcie_gen3_16b pcie_gen3_32b
+ parameter pma_rx_buf_pm_tx_rx_cvp_mode = "cvp_off" ,//cvp_off cvp_on
+ parameter pma_rx_buf_xrx_path_uc_cal_enable = "rx_cal_off" ,//rx_cal_off rx_cal_on
+ parameter pma_rx_buf_xrx_path_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_rx_buf_xrx_path_prot_mode = "unused" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_rx_buf_xrx_path_datarate = "0 bps" ,//NOVAL
+ parameter [7:0] pma_rx_buf_xrx_path_datawidth = 8'd0 ,//0:255
+ parameter pma_rx_buf_xrx_path_pma_rx_divclk_hz = "0" ,//NOVAL
+ parameter pma_tx_buf_datarate = "0 bps" ,//NOVAL
+ parameter pma_tx_buf_prot_mode = "basic_tx" ,//basic_kr_tx basic_tx cei_tx cpri_tx fc_tx gige_tx gpon_tx higig_tx obsai_tx pcie_gen1_tx pcie_gen2_tx pcie_gen3_tx pcie_gen4_tx qpi_tx sata_tx sdi_tx sfi_tx sfp_tx sonet_tx srio_tx unused xaui_tx xfp_tx
+ parameter pma_tx_buf_rx_det = "mode_0" ,//mode_0 mode_1 mode_10 mode_11 mode_12 mode_13 mode_14 mode_15 mode_2 mode_3 mode_4 mode_5 mode_6 mode_7 mode_8 mode_9
+ parameter pma_tx_buf_rx_det_output_sel = "rx_det_pcie_out" ,//rx_det_pcie_out rx_det_qpi_out
+ parameter pma_tx_buf_rx_det_pdb = "rx_det_off" ,//rx_det_off rx_det_on
+ parameter pma_tx_buf_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_tx_buf_user_fir_coeff_ctrl_sel = "ram_ctl" ,//dynamic_ctl ram_ctl
+ parameter pma_tx_buf_xtx_path_prot_mode = "basic_tx" ,//basic_kr_tx basic_tx cei_tx cpri_tx fc_tx gige_tx gpon_tx higig_tx obsai_tx pcie_gen1_tx pcie_gen2_tx pcie_gen3_tx pcie_gen4_tx qpi_tx sata_tx sdi_tx sfi_tx sfp_tx sonet_tx srio_tx unused xaui_tx xfp_tx
+ parameter pma_tx_buf_xtx_path_datarate = "0 bps" ,//NOVAL
+ parameter [7:0] pma_tx_buf_xtx_path_datawidth = 8'd0 ,//0:255
+ parameter [3:0] pma_tx_buf_xtx_path_clock_divider_ratio = 4'd0 ,//0:15
+ parameter pma_tx_buf_xtx_path_pma_tx_divclk_hz = "0" ,//NOVAL
+ parameter pma_tx_buf_xtx_path_tx_pll_clk_hz = "0 hz" ,//NOVAL
+ parameter pma_tx_buf_xtx_path_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_adapt_datarate = "0 bps" ,//NOVAL
+ parameter pma_adapt_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_adapt_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_adapt_adapt_mode = "dfe_vga" ,//ctle ctle_vga ctle_vga_dfe dfe_vga manual
+ parameter pma_cdr_refclk_powerdown_mode = "powerdown" ,//powerdown powerup
+ parameter pma_cdr_refclk_receiver_detect_src = "core_refclk_src" ,//core_refclk_src iqclk_src
+ parameter pma_cdr_refclk_refclk_select = "ref_iqclk0" ,//adj_pll_clk coreclk fixed_clk iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 lvpecl power_down ref_iqclk0 ref_iqclk1 ref_iqclk10 ref_iqclk11 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9
+ parameter pma_rx_deser_clkdiv_source = "vco_bypass_normal" ,//clklow_to_clkdivrx fref_to_clkdivrx vco_bypass_normal
+ parameter pma_rx_deser_clkdivrx_user_mode = "clkdivrx_user_disabled" ,//clkdivrx_user_disabled clkdivrx_user_clkdiv clkdivrx_user_clkdiv_div2 clkdivrx_user_div33 clkdivrx_user_div40 clkdivrx_user_div66
+ parameter pma_rx_deser_pcie_gen = "non_pcie" ,// pcie_gen1_100mhzref|pcie_gen2_100mhzref|pcie_gen3_100mhzref|pcie_gen1_125mhzref|pcie_gen2_125mhzref|pcie_gen3_125mhzref|non_pcie
+ parameter pma_rx_deser_pcie_gen_bitwidth = "pcie_gen3_32b" ,// pcie_gen3_32b|pcie_gen3_16b
+
+ parameter pma_rx_deser_datarate = "0 bps" ,//NOVAL
+ parameter pma_rx_deser_deser_factor = 8 ,//8 10 16 20 32 40 64
+ parameter pma_rx_deser_force_clkdiv_for_testing = "normal_clkdiv" ,//forced_0 forced_1 normal_clkdiv
+ parameter pma_rx_deser_sdclk_enable = "false" ,//false true
+ parameter pma_rx_deser_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_rx_deser_rst_n_adapt_odi = "no_rst_adapt_odi" ,//no_rst_adapt_odi yes_rst_adapt_odi
+ parameter pma_rx_deser_bitslip_bypass = "bs_bypass_no" ,//bs_bypass_no bs_bypass_yes
+ parameter pma_rx_deser_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_cgb_bitslip_enable = "enable_bitslip" ,//disable_bitslip enable_bitslip
+ parameter pma_cgb_bonding_reset_enable = "allow_bonding_reset" ,//allow_bonding_reset disallow_bonding_reset
+ parameter pma_cgb_datarate = "0 bps" ,//NOVAL
+ parameter pma_cgb_pcie_gen3_bitwidth = "pciegen3_wide" ,//pciegen3_narrow pciegen3_wide
+ parameter pma_cgb_prot_mode = "basic_tx" ,//basic_kr_tx basic_tx cei_tx cpri_tx fc_tx gige_tx gpon_tx higig_tx obsai_tx pcie_gen1_tx pcie_gen2_tx pcie_gen3_tx pcie_gen4_tx qpi_tx sata_tx sdi_tx sfi_tx sfp_tx sonet_tx srio_tx unused xaui_tx xfp_tx
+ parameter pma_cgb_ser_mode = "eight_bit" ,//eight_bit forty_bit sixteen_bit sixty_four_bit ten_bit thirty_two_bit twenty_bit
+ parameter pma_cgb_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_cgb_x1_div_m_sel = "divbypass" ,//divby2 divby4 divby8 divbypass
+ parameter pma_cgb_input_select_x1 = "unused" ,//cdr_txpll_b cdr_txpll_t fpll_bot fpll_top hfclk_x6_dn hfclk_x6_up hfclk_xn_dn hfclk_xn_up lcpll_bot lcpll_hs lcpll_top same_ch_txpll unused
+ parameter pma_cgb_input_select_gen3 = "unused" ,//cdr_txpll_b cdr_txpll_t fpll_bot fpll_top hfclk_x6_dn hfclk_x6_up hfclk_xn_dn hfclk_xn_up lcpll_bot lcpll_hs lcpll_top same_ch_txpll unused
+ parameter pma_cgb_input_select_xn = "unused" ,//sel_cgb_loc sel_x6_dn sel_x6_up sel_xn_dn sel_xn_up unused
+ parameter pma_cgb_tx_ucontrol_en = "disable" ,//disable enable
+ parameter pma_rx_dfe_datarate = "0 bps" ,//NOVAL
+ parameter pma_rx_dfe_pdb = "dfe_enable" ,//dfe_enable dfe_powerdown dfe_reset
+ parameter pma_rx_dfe_pdb_fixedtap = "fixtap_dfe_powerdown" ,//fixtap_dfe_enable fixtap_dfe_powerdown
+ parameter pma_rx_dfe_pdb_floattap = "floattap_dfe_powerdown" ,//floattap_dfe_enable floattap_dfe_powerdown
+ parameter pma_rx_dfe_pdb_fxtap4t7 = "fxtap4t7_powerdown" ,//fxtap4t7_enable fxtap4t7_powerdown
+ parameter pma_rx_dfe_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_rx_dfe_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_rx_sd_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_rx_sd_sd_output_off = 1 ,//0:28
+ parameter pma_rx_sd_sd_output_on = 1 ,//0:15
+ parameter pma_rx_sd_sd_pdb = "sd_off" ,//sd_off sd_on
+ parameter pma_rx_sd_sd_threshold = 3 ,//0:15
+ parameter pma_rx_sd_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_tx_ser_ser_clk_divtx_user_sel = "divtx_user_33" ,//divtx_user_1 divtx_user_2 divtx_user_33 divtx_user_40 divtx_user_66 divtx_user_off
+ parameter pma_tx_ser_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_tx_ser_prot_mode = "basic_tx" ,//basic_kr_tx basic_tx cei_tx cpri_tx fc_tx gige_tx gpon_tx higig_tx obsai_tx pcie_gen1_tx pcie_gen2_tx pcie_gen3_tx pcie_gen4_tx qpi_tx sata_tx sdi_tx sfi_tx sfp_tx sonet_tx srio_tx unused xaui_tx xfp_tx
+ parameter [2:0] hssi_pipe_gen1_2_elec_idle_delay_val = 3'd0 ,//0:7
+ parameter hssi_pipe_gen1_2_error_replace_pad = "replace_edb" ,//replace_edb replace_pad
+ parameter hssi_pipe_gen1_2_hip_mode = "dis_hip" ,//dis_hip en_hip
+ parameter hssi_pipe_gen1_2_ind_error_reporting = "dis_ind_error_reporting" ,//dis_ind_error_reporting en_ind_error_reporting
+ parameter [2:0] hssi_pipe_gen1_2_phystatus_delay_val = 3'd0 ,//0:7
+ parameter hssi_pipe_gen1_2_phystatus_rst_toggle = "dis_phystatus_rst_toggle" ,//dis_phystatus_rst_toggle en_phystatus_rst_toggle
+ parameter hssi_pipe_gen1_2_pipe_byte_de_serializer_en = "dont_care_bds" ,//dis_bds dont_care_bds en_bds_by_2
+ parameter hssi_pipe_gen1_2_prot_mode = "pipe_g1" ,//basic disabled_prot_mode pipe_g1 pipe_g2 pipe_g3
+ parameter hssi_pipe_gen1_2_rx_pipe_enable = "dis_pipe_rx" ,//dis_pipe_rx en_pipe3_rx en_pipe_rx
+ parameter hssi_pipe_gen1_2_rxdetect_bypass = "dis_rxdetect_bypass" ,//dis_rxdetect_bypass en_rxdetect_bypass
+ parameter hssi_pipe_gen1_2_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_pipe_gen1_2_tx_pipe_enable = "dis_pipe_tx" ,//dis_pipe_tx en_pipe3_tx en_pipe_tx
+ parameter hssi_pipe_gen1_2_txswing = "dis_txswing" ,//dis_txswing en_txswing
+ parameter hssi_common_pld_pcs_interface_dft_clk_out_en = "dft_clk_out_disable" ,//dft_clk_out_disable dft_clk_out_enable
+ parameter hssi_common_pld_pcs_interface_dft_clk_out_sel = "teng_rx_dft_clk" ,//eightg_rx_dft_clk eightg_tx_dft_clk pmaif_dft_clk teng_rx_dft_clk teng_tx_dft_clk
+ parameter hssi_common_pld_pcs_interface_hrdrstctrl_en = "hrst_dis" ,//hrst_dis hrst_en
+ parameter hssi_common_pld_pcs_interface_pcs_testbus_block_sel = "eightg" ,//eightg g3pcs krfec pma_if teng
+ parameter hssi_common_pcs_pma_interface_asn_clk_enable = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_asn_enable = "dis_asn" ,//dis_asn en_asn
+ parameter hssi_common_pcs_pma_interface_block_sel = "eight_g_pcs" ,//eight_g_pcs pcie_gen3
+ parameter hssi_common_pcs_pma_interface_bypass_early_eios = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_pcie_switch = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_pma_ltr = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_pma_sw_done = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_ppm_lock = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_txdetectrx = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_cdr_control = "en_cdr_ctrl" ,//dis_cdr_ctrl en_cdr_ctrl
+ parameter hssi_common_pcs_pma_interface_cid_enable = "en_cid_mode" ,//dis_cid_mode en_cid_mode
+ parameter [15:0] hssi_common_pcs_pma_interface_data_mask_count = 16'd2500 ,//0:65535
+ parameter [2:0] hssi_common_pcs_pma_interface_data_mask_count_multi = 3'd1 ,//0:7
+ parameter hssi_common_pcs_pma_interface_dft_observation_clock_selection = "dft_clk_obsrv_tx0" ,//dft_clk_obsrv_asn0 dft_clk_obsrv_asn1 dft_clk_obsrv_clklow dft_clk_obsrv_fref dft_clk_obsrv_hclk dft_clk_obsrv_rx dft_clk_obsrv_tx0 dft_clk_obsrv_tx1 dft_clk_obsrv_tx2 dft_clk_obsrv_tx3 dft_clk_obsrv_tx4
+ parameter [7:0] hssi_common_pcs_pma_interface_early_eios_counter = 8'd50 ,//0:255
+ parameter hssi_common_pcs_pma_interface_force_freqdet = "force_freqdet_dis" ,//force0_freqdet_en force1_freqdet_en force_freqdet_dis
+ parameter hssi_common_pcs_pma_interface_free_run_clk_enable = "true" ,//false true
+ parameter hssi_common_pcs_pma_interface_ignore_sigdet_g23 = "false" ,//false true
+ parameter [6:0] hssi_common_pcs_pma_interface_pc_en_counter = 7'd55 ,//0:127
+ parameter [4:0] hssi_common_pcs_pma_interface_pc_rst_counter = 5'd23 ,//0:31
+ parameter hssi_common_pcs_pma_interface_pcie_hip_mode = "hip_disable" ,//hip_disable hip_enable
+ parameter hssi_common_pcs_pma_interface_ph_fifo_reg_mode = "phfifo_reg_mode_dis" ,//phfifo_reg_mode_dis phfifo_reg_mode_en
+ parameter [5:0] hssi_common_pcs_pma_interface_phfifo_flush_wait = 6'd36 ,//0:63
+ parameter hssi_common_pcs_pma_interface_pipe_if_g3pcs = "pipe_if_8gpcs" ,//pipe_if_8gpcs pipe_if_g3pcs
+ parameter [17:0] hssi_common_pcs_pma_interface_pma_done_counter = 18'd175000 ,//0:262143
+ parameter hssi_common_pcs_pma_interface_pma_if_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_common_pcs_pma_interface_pma_if_dft_val = "dft_0" ,//dft_0 dft_1
+ parameter hssi_common_pcs_pma_interface_ppm_cnt_rst = "ppm_cnt_rst_dis" ,//ppm_cnt_rst_dis ppm_cnt_rst_en
+ parameter hssi_common_pcs_pma_interface_ppm_deassert_early = "deassert_early_dis" ,//deassert_early_dis deassert_early_en
+ parameter hssi_common_pcs_pma_interface_ppm_gen1_2_cnt = "cnt_32k" ,//cnt_32k cnt_64k
+ parameter hssi_common_pcs_pma_interface_ppm_post_eidle_delay = "cnt_200_cycles" ,//cnt_200_cycles cnt_400_cycles
+ parameter hssi_common_pcs_pma_interface_ppmsel = "ppmsel_300" ,//ppmsel_100 ppmsel_1000 ppmsel_125 ppmsel_200 ppmsel_250 ppmsel_2500 ppmsel_300 ppmsel_500 ppmsel_5000 ppmsel_62p5 ppmsel_disable ppm_other
+ parameter hssi_common_pcs_pma_interface_prot_mode = "disable_prot_mode" ,//disable_prot_mode other_protocols pipe_g12 pipe_g3
+ parameter hssi_common_pcs_pma_interface_rxvalid_mask = "rxvalid_mask_en" ,//rxvalid_mask_dis rxvalid_mask_en
+ parameter [11:0] hssi_common_pcs_pma_interface_sigdet_wait_counter = 12'd2500 ,//0:4095
+ parameter [2:0] hssi_common_pcs_pma_interface_sigdet_wait_counter_multi = 3'd1 ,//0:7
+ parameter hssi_common_pcs_pma_interface_sim_mode = "disable" ,//disable enable
+ parameter hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en = "true" ,//false true
+ parameter hssi_common_pcs_pma_interface_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_common_pcs_pma_interface_testout_sel = "ppm_det_test" ,//asn_test pma_pll_test ppm_det_test prbs_gen_test prbs_ver_test rxpmaif_test uhsif_1_test uhsif_2_test uhsif_3_test
+ parameter [3:0] hssi_common_pcs_pma_interface_wait_clk_on_off_timer = 4'd4 ,//0:15
+ parameter [4:0] hssi_common_pcs_pma_interface_wait_pipe_synchronizing = 5'd23 ,//0:31
+ parameter [10:0] hssi_common_pcs_pma_interface_wait_send_syncp_fbkp = 11'd250 ,//0:2047
+ parameter hssi_common_pcs_pma_interface_ppm_det_buckets = "ppm_100_bucket" ,//disable_prot ppm_100_bucket ppm_300_100_bucket ppm_300_bucket
+ parameter hssi_tx_pcs_pma_interface_bypass_pma_txelecidle = "false" ,//false true
+ parameter hssi_tx_pcs_pma_interface_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pcs_pma_interface_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pcs_pma_interface_master_clk_sel = "master_tx_pma_clk" ,//master_refclk_dig master_tx_pma_clk
+ parameter hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx = "other_prot_mode" ,//other_prot_mode pipe_g12 pipe_g3
+ parameter hssi_tx_pcs_pma_interface_pldif_datawidth_mode = "pldif_data_10bit" ,//pldif_data_10bit pldif_data_8bit
+ parameter hssi_tx_pcs_pma_interface_pma_dw_tx = "pma_8b_tx" ,//pcie_g3_dyn_dw_tx pma_10b_tx pma_16b_tx pma_20b_tx pma_32b_tx pma_40b_tx pma_64b_tx pma_8b_tx
+ parameter hssi_tx_pcs_pma_interface_pma_if_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_tx_pcs_pma_interface_pmagate_en = "pmagate_dis" ,//pmagate_dis pmagate_en
+ parameter hssi_tx_pcs_pma_interface_prbs_clken = "prbs_clk_dis" ,//prbs_clk_dis prbs_clk_en
+ parameter hssi_tx_pcs_pma_interface_prbs_gen_pat = "prbs_gen_dis" ,//prbs_15 prbs_23 prbs_31 prbs_9 prbs_gen_dis
+ parameter hssi_tx_pcs_pma_interface_prbs9_dwidth = "prbs9_64b" ,//prbs9_10b prbs9_64b
+ parameter hssi_tx_pcs_pma_interface_prot_mode_tx = "disabled_prot_mode_tx" ,//disabled_prot_mode_tx eightg_basic_mode_tx eightg_g3_pcie_g3_hip_mode_tx eightg_g3_pcie_g3_pld_mode_tx eightg_only_pld_mode_tx eightg_pcie_g12_hip_mode_tx eightg_pcie_g12_pld_mode_tx pcs_direct_mode_tx prbs_mode_tx sqwave_mode_tx teng_basic_mode_tx teng_krfec_mode_tx teng_sfis_sdi_mode_tx uhsif_direct_mode_tx uhsif_reg_mode_tx
+ parameter hssi_tx_pcs_pma_interface_sq_wave_num = "sq_wave_4" ,//sq_wave_1 sq_wave_4 sq_wave_6 sq_wave_8 sq_wave_default
+ parameter hssi_tx_pcs_pma_interface_sqwgen_clken = "sqwgen_clk_dis" ,//sqwgen_clk_dis sqwgen_clk_en
+ parameter hssi_tx_pcs_pma_interface_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion = "tx_dyn_polinv_dis" ,//tx_dyn_polinv_dis tx_dyn_polinv_en
+ parameter hssi_tx_pcs_pma_interface_tx_pma_data_sel = "pld_dir" ,//block_sel_default directed_uhsif_dat eight_g_pcs pcie_gen3 pld_dir prbs_pat registered_uhsif_dat sq_wave_pat ten_g_pcs
+ parameter hssi_tx_pcs_pma_interface_tx_static_polarity_inversion = "tx_stat_polinv_dis" ,//tx_stat_polinv_dis tx_stat_polinv_en
+ parameter hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock = "uhsif_filt_stepsz_b4lock_4" ,//uhsif_filt_stepsz_b4lock_2 uhsif_filt_stepsz_b4lock_4 uhsif_filt_stepsz_b4lock_6 uhsif_filt_stepsz_b4lock_8
+ parameter [3:0] hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value = 4'd11 ,//0:15
+ parameter hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock = "uhsif_filt_cntthr_b4lock_16" ,//uhsif_filt_cntthr_b4lock_16 uhsif_filt_cntthr_b4lock_24 uhsif_filt_cntthr_b4lock_32 uhsif_filt_cntthr_b4lock_8
+ parameter hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period = "uhsif_dcn_test_period_4" ,//uhsif_dcn_test_period_12 uhsif_dcn_test_period_16 uhsif_dcn_test_period_4 uhsif_dcn_test_period_8
+ parameter hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable = "uhsif_dcn_test_mode_disable" ,//uhsif_dcn_test_mode_disable uhsif_dcn_test_mode_enable
+ parameter hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh = "uhsif_dzt_cnt_thr_4" ,//uhsif_dzt_cnt_thr_2 uhsif_dzt_cnt_thr_4 uhsif_dzt_cnt_thr_6 uhsif_dzt_cnt_thr_8
+ parameter hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable = "uhsif_dzt_enable" ,//uhsif_dzt_disable uhsif_dzt_enable
+ parameter hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window = "uhsif_dzt_obr_win_32" ,//uhsif_dzt_obr_win_16 uhsif_dzt_obr_win_32 uhsif_dzt_obr_win_48 uhsif_dzt_obr_win_64
+ parameter hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size = "uhsif_dzt_skipsz_8" ,//uhsif_dzt_skipsz_12 uhsif_dzt_skipsz_16 uhsif_dzt_skipsz_4 uhsif_dzt_skipsz_8
+ parameter hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel = "uhsif_index_internal" ,//uhsif_index_cram uhsif_index_internal
+ parameter hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin = "uhsif_dcn_margin_4" ,//uhsif_dcn_margin_2 uhsif_dcn_margin_3 uhsif_dcn_margin_4 uhsif_dcn_margin_5
+ parameter [7:0] hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value = 8'd128 ,//0:255
+ parameter hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control = "uhsif_dft_dz_det_val_0" ,//uhsif_dft_dz_det_val_0 uhsif_dft_dz_det_val_1
+ parameter hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control = "uhsif_dft_up_val_0" ,//uhsif_dft_up_val_0 uhsif_dft_up_val_1
+ parameter hssi_tx_pcs_pma_interface_uhsif_enable = "uhsif_disable" ,//uhsif_disable uhsif_enable
+ parameter hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock = "uhsif_lkd_segsz_aflock_2048" ,//uhsif_lkd_segsz_aflock_1024 uhsif_lkd_segsz_aflock_2048 uhsif_lkd_segsz_aflock_4096 uhsif_lkd_segsz_aflock_512
+ parameter hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock = "uhsif_lkd_segsz_b4lock_32" ,//uhsif_lkd_segsz_b4lock_128 uhsif_lkd_segsz_b4lock_16 uhsif_lkd_segsz_b4lock_32 uhsif_lkd_segsz_b4lock_64
+ parameter [3:0] hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value = 4'd8 ,//0:15
+ parameter [3:0] hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value = 4'd8 ,//0:15
+ parameter [3:0] hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value = 4'd3 ,//0:15
+ parameter [3:0] hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value = 4'd3 ,//0:15
+ parameter hssi_rx_pcs_pma_interface_block_sel = "eight_g_pcs" ,//direct_pld eight_g_pcs ten_g_pcs
+ parameter hssi_rx_pcs_pma_interface_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pcs_pma_interface_clkslip_sel = "pld" ,//pld slip_eight_g_pcs
+ parameter hssi_rx_pcs_pma_interface_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pcs_pma_interface_master_clk_sel = "master_rx_pma_clk" ,//master_refclk_dig master_rx_pma_clk master_tx_pma_clk
+ parameter hssi_rx_pcs_pma_interface_pldif_datawidth_mode = "pldif_data_10bit" ,//pldif_data_10bit pldif_data_8bit
+ parameter hssi_rx_pcs_pma_interface_pma_dw_rx = "pma_8b_rx" ,//pcie_g3_dyn_dw_rx pma_10b_rx pma_16b_rx pma_20b_rx pma_32b_rx pma_40b_rx pma_64b_rx pma_8b_rx
+ parameter hssi_rx_pcs_pma_interface_pma_if_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_rx_pcs_pma_interface_pma_if_dft_val = "dft_0" ,//dft_0 dft_1
+ parameter hssi_rx_pcs_pma_interface_prbs_clken = "prbs_clk_dis" ,//prbs_clk_dis prbs_clk_en
+ parameter hssi_rx_pcs_pma_interface_prbs_ver = "prbs_off" ,//prbs_15 prbs_23 prbs_31 prbs_9 prbs_off
+ parameter hssi_rx_pcs_pma_interface_prbs9_dwidth = "prbs9_64b" ,//prbs9_10b prbs9_64b
+ parameter hssi_rx_pcs_pma_interface_prot_mode_rx = "disabled_prot_mode_rx" ,//disabled_prot_mode_rx eightg_basic_mode_rx eightg_g3_pcie_g3_hip_mode_rx eightg_g3_pcie_g3_pld_mode_rx eightg_only_pld_mode_rx eightg_pcie_g12_hip_mode_rx eightg_pcie_g12_pld_mode_rx pcs_direct_mode_rx prbs_mode_rx teng_basic_mode_rx teng_krfec_mode_rx teng_sfis_sdi_mode_rx
+ parameter hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion = "rx_dyn_polinv_dis" ,//rx_dyn_polinv_dis rx_dyn_polinv_en
+ parameter hssi_rx_pcs_pma_interface_rx_lpbk_en = "lpbk_dis" ,//lpbk_dis lpbk_en
+ parameter hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok = "unforce_sig_ok" ,//force_sig_ok unforce_sig_ok
+ parameter hssi_rx_pcs_pma_interface_rx_prbs_mask = "prbsmask128" ,//prbsmask1024 prbsmask128 prbsmask256 prbsmask512
+ parameter hssi_rx_pcs_pma_interface_rx_prbs_mode = "teng_mode" ,//eightg_mode teng_mode
+ parameter hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel = "sel_sig_det" ,//sel_sig_det sel_sig_ok
+ parameter hssi_rx_pcs_pma_interface_rx_static_polarity_inversion = "rx_stat_polinv_dis" ,//rx_stat_polinv_dis rx_stat_polinv_en
+ parameter hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en = "uhsif_lpbk_dis" ,//uhsif_lpbk_dis uhsif_lpbk_en
+ parameter hssi_rx_pcs_pma_interface_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_fifo_tx_pcs_double_write_mode = "double_write_dis" ,//double_write_dis double_write_en
+ parameter hssi_fifo_tx_pcs_prot_mode = "teng_mode" ,//non_teng_mode teng_mode
+ parameter hssi_fifo_rx_pcs_double_read_mode = "double_read_dis" ,//double_read_dis double_read_en
+ parameter hssi_fifo_rx_pcs_prot_mode = "teng_mode" ,//non_teng_mode teng_mode
+ parameter hssi_krfec_rx_pcs_blksync_cor_en = "detect" ,//correct detect
+ parameter hssi_krfec_rx_pcs_bypass_gb = "bypass_dis" ,//bypass_dis bypass_en
+ parameter hssi_krfec_rx_pcs_clr_ctrl = "both_enabled" ,//both_enabled corr_cnt_only uncorr_cnt_only
+ parameter hssi_krfec_rx_pcs_ctrl_bit_reverse = "ctrl_bit_reverse_dis" ,//ctrl_bit_reverse_dis ctrl_bit_reverse_en
+ parameter hssi_krfec_rx_pcs_data_bit_reverse = "data_bit_reverse_dis" ,//data_bit_reverse_dis data_bit_reverse_en
+ parameter hssi_krfec_rx_pcs_dv_start = "with_blklock" ,//with_blklock with_blksync
+ parameter hssi_krfec_rx_pcs_err_mark_type = "err_mark_10g" ,//err_mark_10g err_mark_40g
+ parameter hssi_krfec_rx_pcs_error_marking_en = "err_mark_dis" ,//err_mark_dis err_mark_en
+ parameter hssi_krfec_rx_pcs_low_latency_en = "disable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_lpbk_mode = "lpbk_dis" ,//lpbk_dis lpbk_en
+ parameter [7:0] hssi_krfec_rx_pcs_parity_invalid_enum = 8'd8 ,//0:255
+ parameter [3:0] hssi_krfec_rx_pcs_parity_valid_num = 4'd4 ,//0:15
+ parameter hssi_krfec_rx_pcs_pipeln_blksync = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_descrm = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_errcorrect = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_errtrap_ind = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_errtrap_lfsr = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_errtrap_loc = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_errtrap_pat = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_gearbox = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_syndrm = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_trans_dec = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_prot_mode = "disable_mode" ,//basic_mode disable_mode fortyg_basekr_mode teng_1588_basekr_mode teng_basekr_mode
+ parameter hssi_krfec_rx_pcs_receive_order = "receive_lsb" ,//receive_lsb receive_msb
+ parameter hssi_krfec_rx_pcs_rx_testbus_sel = "overall" ,//blksync blksync_cntrs decoder_master_sm decoder_master_sm_cntrs decoder_rd_sm errtrap_ind1 errtrap_ind2 errtrap_ind3 errtrap_ind4 errtrap_ind5 errtrap_loc errtrap_pat1 errtrap_pat2 errtrap_pat3 errtrap_pat4 errtrap_sm fast_search fast_search_cntrs gb_and_trans overall syndrm1 syndrm2 syndrm_sm
+ parameter hssi_krfec_rx_pcs_signal_ok_en = "sig_ok_dis" ,//sig_ok_dis sig_ok_en
+ parameter hssi_krfec_rx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_pipe_gen3_bypass_rx_detection_enable = "false" ,//false true
+ parameter [2:0] hssi_pipe_gen3_bypass_rx_preset = 3'd0 ,//0:7
+ parameter hssi_pipe_gen3_bypass_rx_preset_enable = "false" ,//false true
+ parameter [17:0] hssi_pipe_gen3_bypass_tx_coefficent = 18'd0 ,//0:262143
+ parameter hssi_pipe_gen3_bypass_tx_coefficent_enable = "false" ,//false true
+ parameter [2:0] hssi_pipe_gen3_elecidle_delay_g3 = 3'd6 ,//0:7
+ parameter hssi_pipe_gen3_ind_error_reporting = "dis_ind_error_reporting" ,//dis_ind_error_reporting en_ind_error_reporting
+ parameter hssi_pipe_gen3_mode = "pipe_g1" ,//disable_pcs pipe_g1 pipe_g2 pipe_g3
+ parameter [2:0] hssi_pipe_gen3_phy_status_delay_g12 = 3'd5 ,//0:7
+ parameter [2:0] hssi_pipe_gen3_phy_status_delay_g3 = 3'd5 ,//0:7
+ parameter hssi_pipe_gen3_phystatus_rst_toggle_g12 = "dis_phystatus_rst_toggle" ,//dis_phystatus_rst_toggle en_phystatus_rst_toggle
+ parameter hssi_pipe_gen3_phystatus_rst_toggle_g3 = "dis_phystatus_rst_toggle_g3" ,//dis_phystatus_rst_toggle_g3 en_phystatus_rst_toggle_g3
+ parameter hssi_pipe_gen3_rate_match_pad_insertion = "dis_rm_fifo_pad_ins" ,//dis_rm_fifo_pad_ins en_rm_fifo_pad_ins
+ parameter hssi_pipe_gen3_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_pipe_gen3_test_out_sel = "disable_test_out" ,//disable_test_out pipe_ctrl_test_out pipe_test_out1 pipe_test_out2 pipe_test_out3 rx_test_out tx_test_out
+ parameter hssi_gen3_tx_pcs_mode = "gen3_func" ,//disable_pcs gen3_func
+ parameter hssi_gen3_tx_pcs_reverse_lpbk = "rev_lpbk_en" ,//rev_lpbk_dis rev_lpbk_en
+ parameter hssi_gen3_tx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter [4:0] hssi_gen3_tx_pcs_tx_bitslip = 5'd0 ,//0:31
+ parameter hssi_gen3_tx_pcs_tx_gbox_byp = "bypass_gbox" ,//bypass_gbox enable_gbox
+ parameter hssi_gen3_rx_pcs_block_sync = "enable_block_sync" ,//bypass_block_sync enable_block_sync
+ parameter hssi_gen3_rx_pcs_block_sync_sm = "enable_blk_sync_sm" ,//disable_blk_sync_sm enable_blk_sync_sm
+ parameter hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn = "enable" ,//disable enable
+ parameter hssi_gen3_rx_pcs_lpbk_force = "lpbk_frce_dis" ,//lpbk_frce_dis lpbk_frce_en
+ parameter hssi_gen3_rx_pcs_mode = "gen3_func" ,//disable_pcs gen3_func
+ parameter hssi_gen3_rx_pcs_rate_match_fifo = "enable_rm_fifo_600ppm" ,//bypass_rm_fifo enable_rm_fifo_0ppm enable_rm_fifo_600ppm
+ parameter hssi_gen3_rx_pcs_rate_match_fifo_latency = "regular_latency" ,//low_latency regular_latency
+ parameter hssi_gen3_rx_pcs_reverse_lpbk = "rev_lpbk_en" ,//rev_lpbk_dis rev_lpbk_en
+ parameter hssi_gen3_rx_pcs_rx_b4gb_par_lpbk = "b4gb_par_lpbk_dis" ,//b4gb_par_lpbk_dis b4gb_par_lpbk_en
+ parameter hssi_gen3_rx_pcs_rx_force_balign = "en_force_balign" ,//dis_force_balign en_force_balign
+ parameter hssi_gen3_rx_pcs_rx_ins_del_one_skip = "ins_del_one_skip_en" ,//ins_del_one_skip_dis ins_del_one_skip_en
+ parameter [3:0] hssi_gen3_rx_pcs_rx_num_fixed_pat = 4'd8 ,//0:15
+ parameter hssi_gen3_rx_pcs_rx_test_out_sel = "rx_test_out0" ,//rx_test_out0 rx_test_out1
+ parameter hssi_gen3_rx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_10g_rx_pcs_advanced_user_mode = "disable" ,//disable enable
+ parameter hssi_10g_tx_pcs_advanced_user_mode = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_10g_advanced_user_mode_rx = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_transparent_pcs_rx = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_10g_advanced_user_mode_tx = "disable" ,//disable enable
+ parameter pma_adapt_adp_1s_ctle_bypass = "radp_1s_ctle_bypass_0" ,//radp_1s_ctle_bypass_0|radp_1s_ctle_bypass_1
+ parameter pma_adapt_adp_4s_ctle_bypass = "radp_4s_ctle_bypass_0" ,//radp_4s_ctle_bypass_0|radp_4s_ctle_bypass_1
+ parameter pma_adapt_adp_ctle_adapt_cycle_window = "radp_ctle_adapt_cycle_window_6" ,//radp_ctle_adapt_cycle_window_0|radp_ctle_adapt_cycle_window_1|radp_ctle_adapt_cycle_window_2|radp_ctle_adapt_cycle_window_3|radp_ctle_adapt_cycle_window_4|radp_ctle_adapt_cycle_window_5|radp_ctle_adapt_cycle_window_6|radp_ctle_adapt_cycle_window_7
+ parameter pma_adapt_adp_ctle_en = "radp_ctle_disable" ,//radp_ctle_disable|radp_ctle_enable
+ parameter pma_adapt_adp_dfe_fltap_bypass = "radp_dfe_fltap_bypass_0" ,//radp_dfe_fltap_bypass_0|radp_dfe_fltap_bypass_1
+ parameter pma_adapt_adp_dfe_fltap_en = "radp_dfe_fltap_disable" ,//radp_dfe_fltap_disable|radp_dfe_fltap_enable
+ parameter pma_adapt_adp_dfe_fxtap_bypass = "radp_dfe_fxtap_bypass_0" ,//radp_dfe_fxtap_bypass_0|radp_dfe_fxtap_bypass_1
+ parameter pma_adapt_adp_dfe_fxtap_en = "radp_dfe_fxtap_disable" ,//radp_dfe_fxtap_disable|radp_dfe_fxtap_enable
+ parameter pma_adapt_adp_dfe_fxtap_hold_en = "radp_dfe_fxtap_not_held" ,//radp_dfe_fxtap_not_held|radp_dfe_fxtap_hold
+ parameter pma_adapt_adp_dfe_mode = "radp_dfe_mode_0" ,//radp_dfe_mode_0|radp_dfe_mode_1|radp_dfe_mode_2|radp_dfe_mode_3|radp_dfe_mode_4|radp_dfe_mode_5|radp_dfe_mode_6|radp_dfe_mode_7
+ parameter pma_adapt_adp_mode = "radp_mode_0" ,//radp_mode_0|radp_mode_1|radp_mode_2|radp_mode_3|radp_mode_4|radp_mode_5|radp_mode_6|radp_mode_7|radp_mode_8|radp_mode_9|radp_mode_10|radp_mode_11|radp_mode_12|radp_mode_13|radp_mode_14|radp_mode_15
+ parameter pma_adapt_adp_onetime_dfe = "radp_onetime_dfe_0" ,//radp_onetime_dfe_0|radp_onetime_dfe_1
+ parameter pma_adapt_adp_vga_bypass = "radp_vga_bypass_0" ,//radp_vga_bypass_0|radp_vga_bypass_1
+ parameter pma_adapt_adp_vga_en = "radp_vga_disable" ,//radp_vga_disable|radp_vga_enable
+ parameter pma_adapt_adp_vref_bypass = "radp_vref_bypass_0" ,//radp_vref_bypass_0|radp_vref_bypass_1
+ parameter pma_adapt_adp_vref_en = "radp_vref_disable" ,//radp_vref_disable|radp_vref_enable
+ parameter pma_adapt_odi_dfe_spec_en = "rodi_dfe_spec_en_0" ,//rodi_dfe_spec_en_0|rodi_dfe_spec_en_1
+ parameter pma_rx_dfe_dft_en = "dft_disable" ,//dft_disable|dft_enalbe
+ parameter pma_rx_odi_step_ctrl_sel = "feedback_mode" ,//dprio_mode|feedback_mode|jm_mode
+
+ parameter hip_cal_en = "disable" //Indicates whether HIP is enabled or not. Valid values: disable, enable
+ ) (
+ //------------------------
+ // Common Ports
+ //------------------------
+ // Resets
+ input wire [channels-1:0] tx_analogreset, // TX PMA reset
+ input wire [channels-1:0] tx_digitalreset, // TX PCS reset
+ input wire [channels-1:0] rx_analogreset, // RX PMA reset
+ input wire [channels-1:0] rx_digitalreset, // RX PCS reset
+
+ output wire [channels-1:0] tx_cal_busy, // TX calibration in progress
+ output wire [channels-1:0] rx_cal_busy, // RX calibration in progress
+ output wire [channels-1:0] avmm_busy,
+
+ // TX serial clocks
+ input wire [channels-1:0] tx_serial_clk0, // clkout from external PLL
+ input wire [channels-1:0] tx_serial_clk1, // clkout from external PLL
+ input wire [channels-1:0] tx_serial_clk2, // clkout from external PLL
+ input wire [channels-1:0] tx_serial_clk3, // clkout from external PLL
+ // Bonding clocks
+ input wire [channels*6-1:0] tx_bonding_clocks, // Bonding clock bundle from Master CGB
+ input wire [channels*6-1:0] tx_bonding_clocks1, // Bonding clock bundle from Master CGB
+ input wire [channels*6-1:0] tx_bonding_clocks2, // Bonding clock bundle from Master CGB
+ input wire [channels*6-1:0] tx_bonding_clocks3, // Bonding clock bundle from Master CGB
+ // CDR reference clocks
+ input wire rx_cdr_refclk0, // RX PLL reference clock 0
+ input wire rx_cdr_refclk1, // RX PLL reference clock 1
+ input wire rx_cdr_refclk2, // RX PLL reference clock 2
+ input wire rx_cdr_refclk3, // RX PLL reference clock 3
+ input wire rx_cdr_refclk4, // RX PLL reference clock 4
+ // TX and RX serial ports
+ output wire [channels-1:0] tx_serial_data, // TX serial data output to HSSI pin
+ input wire [channels-1:0] rx_serial_data, // RX serial data input from HSSI pin
+ // PMA control ports
+ input wire [channels-1:0] rx_pma_clkslip, // Slip RX PMA by one clock cycle
+ input wire [channels-1:0] rx_seriallpbken, // Enable TX-to-RX loopback
+ input wire [channels-1:0] rx_set_locktodata,// Set CDR to manual lock to data mode
+ input wire [channels-1:0] rx_set_locktoref, // Set CDR to manual lock to reference mode
+ // PMA status ports
+ output wire [channels-1:0] rx_is_lockedtoref, // CDR is in lock to reference mode
+ output wire [channels-1:0] rx_is_lockedtodata, // CDR is in lock to data mode
+
+ // QPI specific ports
+ input wire [channels-1:0] rx_pma_qpipulldn,
+ input wire [channels-1:0] tx_pma_qpipulldn,
+ input wire [channels-1:0] tx_pma_qpipullup,
+ input wire [channels-1:0] tx_pma_txdetectrx,
+ input wire [channels-1:0] tx_pma_elecidle, // TX electrical idle
+ output wire [channels-1:0] tx_pma_rxfound,
+
+ // Common ports
+ //PPM detector clocks
+ output wire [channels-1:0] rx_clklow, // RX Low freq recovered clock, PPM detector specific
+ output wire [channels-1:0] rx_fref, // RX PFD reference clock, PPM detector specific
+
+ //-------------------------
+ // Common datapath ports
+ //-------------------------
+ // Clock ports
+ input wire [channels-1:0] tx_coreclkin, // TX parallel clock input
+ input wire [channels-1:0] rx_coreclkin, // RX parallel clock input
+ output wire [channels-1:0] tx_clkout, // TX Parallel clock output
+ output wire [channels-1:0] rx_clkout, // RX parallel clock output
+ output wire [channels-1:0] tx_pma_clkout, // TX clock output from PMA
+ output wire [channels-1:0] rx_pma_clkout, // RX clock output from PMA
+ output wire [channels-1:0] tx_pma_div_clkout, // TX clock output from PMA (programmable divider)
+ output wire [channels-1:0] rx_pma_div_clkout, // RX clock output from PMA (programmable divider)
+ output wire [channels-1:0] tx_pma_iqtxrx_clkout, // TX clock output from PMA to iqtxrx lines (for cascading)
+ output wire [channels-1:0] rx_pma_iqtxrx_clkout, // RX clock output from PMA to iqtxrx lines (for cascading)
+ // parallel data ports
+ input wire [channels*128-1:0] tx_parallel_data, // PCS TX parallel data interface
+ output wire [channels*128-1:0] rx_parallel_data, // PCS RX parallel data interface
+ input wire [channels*18-1:0] tx_control, // PCS TX control data
+ output wire [channels*20-1:0] rx_control, // PCS RX control data
+ // Polarity inversion
+ input wire [channels-1:0] tx_polinv, // TX polarity inversion
+ input wire [channels-1:0] rx_polinv, // RX polarity inversion
+ // Bitslip
+ input wire [channels-1:0] rx_bitslip, // RX bitslip (Standard and Enhanced PCS). Asynchronous. Rising edge triggers single bit slip.
+ // Adaptation
+ input wire [channels-1:0] rx_adapt_reset, // For adaptation engine control: user needs to apply reset first
+ input wire [channels-1:0] rx_adapt_start, // For adaptation engine control: user, after releasing reset, needs to apply start
+ // PRBS
+ input wire [channels-1:0] rx_prbs_err_clr,
+ output wire [channels-1:0] rx_prbs_done,
+ output wire [channels-1:0] rx_prbs_err,
+ // Ultra high-speed interface
+ input wire [channels-1:0] tx_uhsif_clk, // Ultra high-speed interface clock input
+ output wire [channels-1:0] tx_uhsif_clkout, // Ultra high-speed interface clock output
+ output wire [channels-1:0] tx_uhsif_lock, // Ultra high-speed interface status
+
+ //-------------------------
+ // Standard datapath ports
+ //-------------------------
+ // Phase compensation FIFOs
+ output wire [channels-1:0] tx_std_pcfifo_full, //Phase comp. FIFO full
+ output wire [channels-1:0] tx_std_pcfifo_empty, //Phase comp. FIFO empty
+ output wire [channels-1:0] rx_std_pcfifo_full, //Phase comp. FIFO full
+ output wire [channels-1:0] rx_std_pcfifo_empty, //Phase comp. FIFO empty
+ // Bit reversal
+ input wire [channels-1:0] rx_std_bitrev_ena,
+ // Byte (de)serializer
+ input wire [channels-1:0] rx_std_byterev_ena,
+ // Bit slip
+ input wire [channels*5-1:0] tx_std_bitslipboundarysel,
+ output wire [channels*5-1:0] rx_std_bitslipboundarysel,
+ // Word align/Deterministic SM
+ input wire [channels-1:0] rx_std_wa_patternalign,
+ input wire [channels-1:0] rx_std_wa_a1a2size,
+ // Rate Match FIFO
+ output wire [channels-1:0] rx_std_rmfifo_full, //Rate Match FIFO full
+ output wire [channels-1:0] rx_std_rmfifo_empty, //Rate Match FIFO empty
+ // PCIe
+ output wire [channels-1:0] rx_std_signaldetect,
+
+ //-------------------------
+ // Enhanced datapath ports
+ //-------------------------
+ // TxFIFO/RxFIFO
+ input wire [channels-1:0] tx_enh_data_valid,
+//input wire [channels-1:0] tx_enh_wordslip, // Engg mode feature so not enabled
+ output wire [channels-1:0] tx_enh_fifo_full,
+ output wire [channels-1:0] tx_enh_fifo_pfull,
+ output wire [channels-1:0] tx_enh_fifo_empty,
+ output wire [channels-1:0] tx_enh_fifo_pempty,
+ output wire [channels*4-1:0] tx_enh_fifo_cnt,
+
+ input wire [channels-1:0] rx_enh_fifo_rd_en,
+ output wire [channels-1:0] rx_enh_data_valid,
+ output wire [channels-1:0] rx_enh_fifo_full,
+ output wire [channels-1:0] rx_enh_fifo_pfull,
+ output wire [channels-1:0] rx_enh_fifo_empty,
+ output wire [channels-1:0] rx_enh_fifo_pempty,
+ output wire [channels-1:0] rx_enh_fifo_del,
+ output wire [channels-1:0] rx_enh_fifo_insert,
+ output wire [channels*5-1:0] rx_enh_fifo_cnt,
+ output wire [channels-1:0] rx_enh_fifo_align_val,
+ input wire [channels-1:0] rx_enh_fifo_align_clr, // Active high. User Align clear signal for RX FIFO when it's used as a deskew FIFO in Interlaken mode. When it asserts, FIFO is reset and it looks for new alignment pattern. It's don't care for non-Interlaken mode
+
+ // Frame generator/sync
+ output wire [channels-1:0] tx_enh_frame,
+ input wire [channels-1:0] tx_enh_frame_burst_en,
+ input wire [channels*2-1:0] tx_enh_frame_diag_status,
+
+ output wire [channels-1:0] rx_enh_frame,
+ output wire [channels-1:0] rx_enh_frame_lock,
+ output wire [channels*2-1:0] rx_enh_frame_diag_status,
+
+ // CRC chk
+ output wire [channels-1:0] rx_enh_crc32_err,
+
+ // BER
+ output wire [channels-1:0] rx_enh_highber,
+ input wire [channels-1:0] rx_enh_highber_clr_cnt,
+
+ // 64B/66B specific 10GBASER signal
+ input wire [channels-1:0] rx_enh_clr_errblk_count,
+
+ // Block sync
+ output wire [channels-1:0] rx_enh_blk_lock,
+
+ // Bit slip
+ input wire [channels*7-1:0] tx_enh_bitslip,
+
+ //-------------------------
+ // HIP ports
+ //-------------------------
+ input wire [channels*64-1:0] tx_hip_data,
+ output wire [channels*51-1:0] rx_hip_data,
+ output wire hip_pipe_pclk,
+ output wire hip_fixedclk,
+ output wire [channels -1:0] hip_frefclk,
+ output wire [channels*8 -1:0] hip_ctrl,
+ output wire [channels -1:0] hip_cal_done,
+
+ //-----
+ // PCIe/PIPE
+ //-----
+ input wire ltssm_detect_quiet,
+ input wire ltssm_detect_active,
+ input wire ltssm_rcvr_phase_two,
+ input wire hip_reduce_counters,
+ input wire [1:0] pcie_rate,
+ input wire [(enable_hip?channels*2:2)-1:0] pipe_rate,
+ input wire [1:0] pipe_sw_done,
+ output wire [1:0] pipe_sw,
+ input wire pipe_hclk_in,
+ output wire pipe_hclk_out,
+ input wire [channels*18-1:0] pipe_g3_txdeemph,
+ input wire [channels*3 -1:0] pipe_g3_rxpresethint,
+ input wire [channels*3 -1:0] pipe_rx_eidleinfersel,
+ output wire [channels -1:0] pipe_rx_elecidle,
+ input wire [channels -1:0] pipe_rx_polarity,
+
+ // -----
+ // optional reset ack
+ // -----
+ output reg [channels - 1:0] tx_analogreset_ack,
+ output reg [channels - 1:0] rx_analogreset_ack,
+
+ //--------------------------
+ // Reconfiguration interface
+ //--------------------------
+ input wire [(rcfg_enable&&rcfg_shared ? 1 : channels)-1:0] reconfig_clk,
+ input wire [(rcfg_enable&&rcfg_shared ? 1 : channels)-1:0] reconfig_reset,
+ input wire [(rcfg_enable&&rcfg_shared ? 1 : channels)-1:0] reconfig_write,
+ input wire [(rcfg_enable&&rcfg_shared ? 1 : channels)-1:0] reconfig_read,
+ input wire [(rcfg_enable&&rcfg_shared ? (10+altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(channels-1)) : (10*channels))-1:0] reconfig_address,
+ input wire [(rcfg_enable&&rcfg_shared ? 1 : channels)*32-1:0] reconfig_writedata,
+ output wire [(rcfg_enable&&rcfg_shared ? 1 : channels)*32-1:0] reconfig_readdata,
+ output wire [(rcfg_enable&&rcfg_shared ? 1 : channels)-1:0] reconfig_waitrequest
+);
+
+localparam RCFG_ADDR_BITS = 10;
+
+localparam xcvr_native_mode = (duplex_mode == "duplex") ? "mode_duplex"
+ : (duplex_mode == "tx") ? "mode_tx_only"
+ : "mode_rx_only";
+localparam calibration_en = enable_calibration ? "enable" : "disable";
+localparam arbiter_ctrl = enable_calibration ? "uc" : "pld";
+localparam cal_done = enable_calibration ? "cal_done_deassert" : "cal_done_assert";
+localparam avmm_busy_en = rcfg_separate_avmm_busy ? "enable" : "disable";
+
+localparam enable_pcs_bonding = (bonded_mode == "pma_pcs") ? 1 : 0;
+localparam lcl_pcs_bonding_master = enable_pcs_bonding ? pcs_bonding_master : channels / 2;
+localparam lcl_adme_assgn_map = {" assignments {dataRate ",adme_data_rate," protMode ",adme_prot_mode," device_revision ",device_revision,"}"};
+
+
+// Use model
+// 1. By default, PHY will connect analog resets and enable sequencing
+// lcl_enable_analog_resets = 1; lcl_enable_reset_sequence = 1
+// 2. Users have to use option in the GUI to disconnect analog resets for a PHY configuration or
+// Users have to use ALTERA_XCVR_A10_DISCONNECT_ANALOG_RESETS to disconnect resets for the entire design
+// lcl_enable_analog_resets = enable_analog_resets (0); lcl_enable_reset_sequence = enable_reset_sequence (0)
+// 3. Users have to use ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS to restore old behavior of resets
+// lcl_enable_analog_resets = 1; lcl_enable_reset_sequence = 0
+
+localparam lcl_enable_analog_resets =
+`ifdef ALTERA_RESERVED_QIS
+ `ifdef ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS
+ 1; // MACRO override for quartus synthesis. Connect resets
+ `else
+ `ifdef ALTERA_XCVR_A10_DISCONNECT_ANALOG_RESETS
+ 0;
+ `else
+ enable_analog_resets;
+ `endif
+ `endif
+`else
+ 1; // not synthesis. Connect resets
+`endif // (NOT ALTERA_RESERVED_QIS)
+
+localparam lcl_enable_reset_sequence =
+`ifdef ALTERA_RESERVED_QIS
+ `ifdef ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS
+ 0; // MACRO override for quartus synthesis
+ `else
+ `ifdef ALTERA_XCVR_A10_DISCONNECT_ANALOG_RESETS
+ 0;
+ `else
+ enable_reset_sequence;
+ `endif
+ `endif
+`else
+ 0; // not synthesis
+`endif // (NOT ALTERA_RESERVED_QIS)
+
+localparam lcl_disable_pipe_rate_retry =
+`ifdef ALTERA_XCVR_A10_PIPE_RATE_RETRY_BYPASS
+ 1 ; //MACRO override to disable the retry circuit
+`else
+ 0 ; //default, enable retry
+`endif
+
+// AVMM reconfiguration interface signals
+wire [channels-1:0] avmm_clk;
+wire [channels-1:0] avmm_reset;
+wire [channels-1:0] avmm_write;
+wire [channels-1:0] avmm_read;
+wire [channels*RCFG_ADDR_BITS-1:0] avmm_address;
+wire [channels*8-1:0] avmm_writedata;
+wire [channels*8-1:0] avmm_readdata;
+wire [channels-1:0] avmm_waitrequest;
+
+// wires for control signals from embedded debug
+wire [channels-1:0] int_rx_prbs_err_clr;
+wire [channels-1:0] int_rx_set_locktoref;
+wire [channels-1:0] int_rx_set_locktodata;
+wire [channels-1:0] int_rx_seriallpbken;
+wire [channels-1:0] int_tx_analogreset;
+wire [channels-1:0] tx_analogreset_to_pma;
+wire [channels-1:0] int_tx_digitalreset;
+wire [channels-1:0] int_rx_analogreset;
+wire [channels-1:0] rx_analogreset_to_pma;
+wire [channels-1:0] int_rx_digitalreset;
+
+// Wires for disconnecting tx_analogreset and rx_analogreset
+wire [channels-1:0] tx_analogreset_input;
+wire [channels-1:0] rx_analogreset_input;
+
+wire [channels-1:0] int_tx_cal_busy_mask; // TX calibration in progress
+wire [channels-1:0] int_rx_cal_busy_mask; // RX calibration in progress
+
+wire [channels-1:0] pld_cal_done;
+
+wire [1:0] int_pcie_rate_sw;
+
+assign tx_cal_busy = ~pld_cal_done & int_tx_cal_busy_mask;
+assign rx_cal_busy = ~pld_cal_done & int_rx_cal_busy_mask;
+assign int_pcie_rate_sw = (enable_hip) ? pcie_rate : pipe_rate;
+
+//***************************************************************************
+//************* Embedded JTAG, AVMM and Embedded Streamer Expansion *********
+alt_xcvr_native_rcfg_opt_logic_iq5an3y #(
+ .dbg_user_identifier ( dbg_user_identifier ),
+ .duplex_mode ( duplex_mode ),
+ .dbg_embedded_debug_enable ( dbg_embedded_debug_enable ),
+ .dbg_capability_reg_enable ( dbg_capability_reg_enable ),
+ .dbg_prbs_soft_logic_enable ( dbg_prbs_soft_logic_enable ),
+ .dbg_odi_soft_logic_enable ( dbg_odi_soft_logic_enable ),
+ .dbg_stat_soft_logic_enable ( dbg_stat_soft_logic_enable ),
+ .dbg_ctrl_soft_logic_enable ( dbg_ctrl_soft_logic_enable ),
+ .enable_pcie_dfe_ip ( enable_pcie_dfe_ip ),
+ .disable_continuous_dfe ( disable_continuous_dfe ),
+ .sim_reduced_counters ( sim_reduced_counters ),
+ .enable_hip ( enable_hip ),
+ .CHANNELS ( channels ),
+ .ADDR_BITS ( RCFG_ADDR_BITS ),
+ .ADME_SLAVE_MAP ( "altera_xcvr_native_a10" ),
+ .ADME_ASSGN_MAP ( lcl_adme_assgn_map ),
+ .RECONFIG_SHARED ( rcfg_enable && rcfg_shared ),
+ .JTAG_ENABLED ( rcfg_enable && rcfg_jtag_enable ),
+ .RCFG_EMB_STRM_ENABLED ( rcfg_enable && rcfg_emb_strm_enable ),
+ .RCFG_PROFILE_CNT ( rcfg_profile_cnt )
+) alt_xcvr_native_optional_rcfg_logic (
+ // User reconfig interface ports
+ .reconfig_clk ( reconfig_clk ),
+ .reconfig_reset ( reconfig_reset ),
+ .reconfig_write ( reconfig_write ),
+ .reconfig_read ( reconfig_read ),
+ .reconfig_address ( reconfig_address ),
+ .reconfig_writedata ( reconfig_writedata ),
+ .reconfig_readdata ( reconfig_readdata ),
+ .reconfig_waitrequest ( reconfig_waitrequest ),
+
+ // AVMM ports to transceiver
+ .avmm_clk ( avmm_clk ),
+ .avmm_reset ( avmm_reset ),
+ .avmm_write ( avmm_write ),
+ .avmm_read ( avmm_read ),
+ .avmm_address ( avmm_address ),
+ .avmm_writedata ( avmm_writedata ),
+ .avmm_readdata ( avmm_readdata ),
+ .avmm_waitrequest ( avmm_waitrequest ),
+
+ // input signals for PCIe DFE IP
+ .ltssm_detect_quiet ( ltssm_detect_quiet ),
+ .ltssm_detect_active ( ltssm_detect_active ),
+ .ltssm_rcvr_phase_two ( ltssm_rcvr_phase_two ),
+ .pcie_rate ( int_pcie_rate_sw ),
+ .hip_reduce_counters ( hip_reduce_counters ),
+
+ // input signals from the PHYfor PRBS error accumulation
+ .prbs_err_signal ( rx_prbs_err ),
+ .prbs_done_signal ( rx_prbs_done ),
+
+ // input rx_clkout for PRBS
+ .in_rx_clkout ( rx_clkout ),
+
+ // input status signals from the transceiver
+ .in_rx_is_lockedtoref ( rx_is_lockedtoref ),
+ .in_rx_is_lockedtodata ( rx_is_lockedtodata ),
+ .in_tx_cal_busy ( tx_cal_busy ),
+ .in_rx_cal_busy ( rx_cal_busy ),
+ .in_avmm_busy ( avmm_busy ),
+
+ // input control signals from the core
+ .in_rx_prbs_err_clr ( rx_prbs_err_clr ),
+ .in_set_rx_locktoref ( rx_set_locktoref ),
+ .in_set_rx_locktodata ( rx_set_locktodata ),
+ .in_en_serial_lpbk ( rx_seriallpbken ),
+ .in_rx_analogreset ( rx_analogreset_input ),
+ .in_rx_digitalreset ( rx_digitalreset ),
+ .in_tx_analogreset ( tx_analogreset_input ),
+ .in_tx_digitalreset ( tx_digitalreset ),
+
+ // output control signals to the phy
+ .out_prbs_err_clr ( int_rx_prbs_err_clr ),
+ .out_set_rx_locktoref ( int_rx_set_locktoref ),
+ .out_set_rx_locktodata ( int_rx_set_locktodata ),
+ .out_en_serial_lpbk ( int_rx_seriallpbken ),
+ .out_rx_analogreset ( int_rx_analogreset ),
+ .out_rx_digitalreset ( int_rx_digitalreset ),
+ .out_tx_analogreset ( int_tx_analogreset ),
+ .out_tx_digitalreset ( int_tx_digitalreset ),
+ .out_tx_cal_busy_mask ( int_tx_cal_busy_mask ),
+ .out_rx_cal_busy_mask ( int_rx_cal_busy_mask )
+);
+
+//***************** End Embedded JTAG and AVMM Expansion ********************
+//***************************************************************************
+
+
+// Bonding wires
+wire [4:0] bond_pcs10g_in_bot [channels-1:0];
+wire [4:0] bond_pcs10g_in_top [channels-1:0];
+wire [4:0] bond_pcs10g_out_bot [channels-1:0];
+wire [4:0] bond_pcs10g_out_top [channels-1:0];
+
+wire [12:0] bond_pcs8g_in_bot [channels-1:0];
+wire [12:0] bond_pcs8g_in_top [channels-1:0];
+wire [12:0] bond_pcs8g_out_bot [channels-1:0];
+wire [12:0] bond_pcs8g_out_top [channels-1:0];
+
+wire [11:0] bond_pmaif_in_bot [channels-1:0];
+wire [11:0] bond_pmaif_in_top [channels-1:0];
+wire [11:0] bond_pmaif_out_bot [channels-1:0];
+wire [11:0] bond_pmaif_out_top [channels-1:0];
+
+wire [channels*20-1:0] pld_testbus_for_rate;
+genvar ig;
+
+generate
+ for(ig=0;ig<channels;ig=ig+1) begin : g_xcvr_native_insts
+ wire [1:0] int_pipe_sw_done;
+ wire [1:0] int_pipe_sw;
+ wire int_pipe_hclk_out;
+ wire int_hip_pipe_pclk;
+ wire int_hip_fixedclk;
+ wire [1:0] int_pipe_rate;
+
+ wire int_in_pld_8g_g3_rx_pld_rst_n;
+ wire int_in_pld_8g_g3_tx_pld_rst_n;
+ wire int_in_pld_10g_krfec_rx_pld_rst_n;
+ wire int_in_pld_10g_krfec_tx_pld_rst_n;
+ wire int_in_pld_pmaif_rx_pld_rst_n;
+ wire int_in_pld_pmaif_tx_pld_rst_n;
+
+ assign int_in_pld_8g_g3_rx_pld_rst_n = ~int_rx_digitalreset[ig];
+ assign int_in_pld_8g_g3_tx_pld_rst_n = ~int_tx_digitalreset[ig];
+
+ // If we are in HIP
+ if(enable_hip) begin
+ assign int_pipe_rate = pipe_rate[ig*2+:2];
+ assign int_in_pld_10g_krfec_rx_pld_rst_n = 1'b0;
+ assign int_in_pld_10g_krfec_tx_pld_rst_n = 1'b0;
+ assign int_in_pld_pmaif_rx_pld_rst_n = 1'b0;
+ assign int_in_pld_pmaif_tx_pld_rst_n = 1'b0;
+ end else begin
+
+
+ // If its the master channel, assign the pld_rate
+ if(ig == lcl_pcs_bonding_master) begin: g_pipe_pld_rate_master_channel
+
+ // Use a macro to bypass the retry circuit
+ if(hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx == "pipe_g2_tx" && lcl_disable_pipe_rate_retry == 0) begin: g_alt_xcvr_native_pipe_retry_g2
+
+ alt_xcvr_native_pipe_retry alt_xcvr_native_pipe_retry_inst (
+ /*input */ .pipe_pclk (tx_coreclkin[ig]),
+ /*input */ .tx_digitalreset (tx_digitalreset[ig]),
+ /*input [1:0] */ .pld_rate (pipe_rate),
+ /*input [19:0] */ .pld_testbus (pld_testbus_for_rate[20*ig+:20]),
+ /*output reg [1:0] */ .rate_retry (int_pipe_rate)
+ );
+
+ end else if (hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx == "pipe_g3_tx") begin: g_pipe_rate_g3
+
+ (* altera_attribute = " -name MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER 2; -name GLOBAL_SIGNAL OFF -from \"twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interface_pld_pcs_tx_clk_out\" " *)
+ reg [1:0] int_pipe_rate_reg = 2'b0;
+
+ (* altera_attribute = " -name GLOBAL_SIGNAL OFF -from \"twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interface_pld_pcs_tx_clk_out\" " *)
+ reg [7:0] int_pipe_rate_sync = 8'b0;
+
+ (* altera_attribute = " -name GLOBAL_SIGNAL OFF -from \"twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interface_pld_pcs_tx_clk_out\" " *)
+ reg [2:0] int_pipe_rate_delay = 3'b0;
+
+ assign int_pipe_rate = int_pipe_rate_reg;
+ always@(posedge tx_clkout[ig]) begin
+ // shift register to set a synchronizer
+ int_pipe_rate_sync[5:0] <= {int_pipe_rate_sync[3:0], pipe_rate};
+
+ // if the last stage of the synchronizer is not the same as the
+ // one before it, run a counter then udpate the final register stage
+ if(int_pipe_rate_sync[7:6] == int_pipe_rate_sync[5:4]) begin
+ int_pipe_rate_delay <= 3'b0;
+ end else begin
+
+ // if the counter is full (7-bit count) update the final stage
+ if(&int_pipe_rate_delay) begin
+ int_pipe_rate_sync[7:6] <= int_pipe_rate_sync[5:4];
+ end else begin
+ int_pipe_rate_delay <= int_pipe_rate_delay + 3'b1;
+ end
+ end
+
+ int_pipe_rate_reg <= int_pipe_rate_sync[7:6];
+ end
+ end else begin: g_no_pipe_rate
+ assign int_pipe_rate = pipe_rate;
+ end
+
+ end else begin: g_pipe_pld_rate_non_master
+ assign int_pipe_rate = 2'b0;
+ end
+
+ assign int_in_pld_10g_krfec_rx_pld_rst_n = ~int_rx_digitalreset[ig];
+ assign int_in_pld_10g_krfec_tx_pld_rst_n = ~int_tx_digitalreset[ig];
+ assign int_in_pld_pmaif_rx_pld_rst_n = ~int_rx_digitalreset[ig];
+ assign int_in_pld_pmaif_tx_pld_rst_n = ~int_tx_digitalreset[ig];
+ end
+
+ // Option 1: enable reset sequencing and analog resets, insert reset endpoint for TX and RX
+ if(lcl_enable_analog_resets == 1 && lcl_enable_reset_sequence == 1 && !enable_hip) begin: g_analog_resets_default
+ // connect resets
+ assign tx_analogreset_input[ig] = tx_analogreset[ig];
+ assign rx_analogreset_input[ig] = rx_analogreset[ig];
+
+ if(duplex_mode == "duplex" || duplex_mode == "tx") begin: g_tre_tx_endpoint
+ altera_transceiver_reset_endpoint reset_endpoint_tx (
+ .tre_reset_req(int_tx_analogreset[ig]),
+ .tre_reset_in(tx_analogreset_to_pma[ig])
+ );
+
+ always @(*) begin
+ tx_analogreset_ack[ig] = tx_analogreset_to_pma[ig];
+ end
+
+ end else begin: g_tre_tx_no_endpoint
+ assign tx_analogreset_to_pma[ig] = 1'b0;
+
+ always @(*) begin
+ tx_analogreset_ack[ig] = 1'b0;
+ end
+
+ end
+
+ if(duplex_mode == "duplex" || duplex_mode == "rx") begin: g_tre_rx_endpoint
+ altera_transceiver_reset_endpoint reset_endpoint_rx (
+ .tre_reset_req(int_rx_analogreset[ig]),
+ .tre_reset_in(rx_analogreset_to_pma[ig])
+ );
+
+ always @(*) begin
+ rx_analogreset_ack[ig] = rx_analogreset_to_pma[ig];
+ end
+
+ end else begin: g_tre_rx_no_end_point
+ assign rx_analogreset_to_pma[ig] = 1'b0;
+
+ always @(*) begin
+ rx_analogreset_ack[ig] = 1'b0;
+ end
+
+ end
+
+ end else if(lcl_enable_analog_resets == 0 && lcl_enable_reset_sequence == 0 && !enable_hip) begin: g_analog_resets_disconnect // Option 2: disconnect analog resets
+ assign tx_analogreset_input[ig] = 1'b0;
+ assign rx_analogreset_input[ig] = 1'b0;
+ assign tx_analogreset_to_pma[ig] = int_tx_analogreset[ig];
+ assign rx_analogreset_to_pma[ig] = int_rx_analogreset[ig];
+
+ always @(*) begin
+ tx_analogreset_ack[ig] = 1'b0;
+ rx_analogreset_ack[ig] = 1'b0;
+ end
+
+ end else begin: g_analog_resets_connect // Option 3: restore old style reset connection
+ assign tx_analogreset_input[ig] = tx_analogreset[ig];
+ assign rx_analogreset_input[ig] = rx_analogreset[ig];
+ assign tx_analogreset_to_pma[ig] = int_tx_analogreset[ig];
+ assign rx_analogreset_to_pma[ig] = int_rx_analogreset[ig];
+
+ `ifdef ALTERA_RESERVED_QIS
+ always @(*) begin
+ tx_analogreset_ack[ig] = tx_analogreset_to_pma[ig];
+ rx_analogreset_ack[ig] = rx_analogreset_to_pma[ig];
+ end
+ `else
+ initial begin
+ tx_analogreset_ack[ig] = 1'b0;
+ rx_analogreset_ack[ig] = 1'b0;
+ end
+
+ always @(*) begin
+ #70000;
+ tx_analogreset_ack[ig] = tx_analogreset_to_pma[ig];
+ rx_analogreset_ack[ig] = rx_analogreset_to_pma[ig];
+ end
+ `endif
+ end
+
+ // PCIe HIP clock selections
+ if((ig == 0 && enable_hip && channels == 2) ||
+ (ig == 3 && enable_hip && (channels == 4 || channels == 8)) ||
+ (ig == 0 && (!enable_hip || channels == 1))) begin
+ assign hip_pipe_pclk = int_hip_pipe_pclk;
+ assign hip_fixedclk = int_hip_fixedclk;
+ end
+
+ // PCIe rate switch signals
+ if(ig == lcl_pcs_bonding_master) begin
+ assign int_pipe_sw_done = pipe_sw_done;
+ assign pipe_sw = int_pipe_sw;
+ assign pipe_hclk_out = int_pipe_hclk_out;
+ end else begin
+ assign int_pipe_sw_done = 2'b00;
+ end
+ // Bonding connections
+ if(enable_pcs_bonding) begin : g_bonding_connections
+ if(ig == (channels-1)) begin
+ assign bond_pcs10g_in_top[ig] = 5'd0;
+ assign bond_pcs8g_in_top[ig] = 13'd0;
+ assign bond_pmaif_in_top[ig] = 12'd0;
+ end else begin
+ assign bond_pcs10g_in_top[ig] = bond_pcs10g_out_bot[ig+1];
+ assign bond_pcs8g_in_top[ig] = bond_pcs8g_out_bot[ig+1];
+ assign bond_pmaif_in_top[ig] = bond_pmaif_out_bot[ig+1];
+ end
+
+ if(ig == 0) begin
+ assign bond_pcs10g_in_bot[ig] = 5'd0;
+ assign bond_pcs8g_in_bot[ig] = 13'd0;
+ assign bond_pmaif_in_bot[ig] = 12'd0;
+ end else begin
+ assign bond_pcs10g_in_bot[ig] = bond_pcs10g_out_top[ig-1];
+ assign bond_pcs8g_in_bot[ig] = bond_pcs8g_out_top[ig-1];
+ assign bond_pmaif_in_bot[ig] = bond_pmaif_out_top[ig-1];
+ end
+ end else begin : g_no_bonding_connections
+ assign bond_pcs10g_in_top[ig] = 5'd0;
+ assign bond_pcs10g_in_bot[ig] = 5'd0;
+ assign bond_pcs8g_in_top[ig] = 13'd0;
+ assign bond_pcs8g_in_bot[ig] = 13'd0;
+ assign bond_pmaif_in_top[ig] = 12'd0;
+ assign bond_pmaif_in_bot[ig] = 12'd0;
+ end
+ // End bonding connections
+
+ localparam [3:0] lcl_pma_tx_buf_mcgb_location_for_pcie = altera_xcvr_native_a10_functions_h::get_mcgb_location_alt_xcvr_native_a10(lcl_pcs_bonding_master, ig);
+
+ // Channel level bonding parameters
+ localparam lcl_hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx =
+ (hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx == "individual_tx") ? "individual_tx"
+ : (ig < lcl_pcs_bonding_master) ? "ctrl_slave_blw_tx"
+ : (ig > lcl_pcs_bonding_master) ? "ctrl_slave_abv_tx"
+ : "ctrl_master_tx";
+
+ localparam lcl_hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx =
+ (hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx == "individual_rx") ? "individual_rx"
+ : (ig < lcl_pcs_bonding_master) ? "ctrl_slave_blw_rx"
+ : (ig > lcl_pcs_bonding_master) ? "ctrl_slave_abv_rx"
+ : "ctrl_master_rx";
+
+ localparam lcl_hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding =
+ (hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx != "pcie_g1_capable_tx" && hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx != "pcie_g2_capable_tx" && hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx != "pcie_g3_capable_tx") ? "individual"
+ : (hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx == "individual_tx") ? "individual"
+ : (ig < lcl_pcs_bonding_master) ? "ctrl_slave_blw"
+ : (ig > lcl_pcs_bonding_master) ? "ctrl_slave_abv"
+ : "ctrl_master";
+ localparam lcl_hssi_common_pcs_pma_interface_bypass_pma_sw_done =
+ (hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx == "pcie_g1_capable_tx" || hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx == "pcie_g2_capable_tx" || hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx == "pcie_g3_capable_tx") ?
+ ((lcl_hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding == "ctrl_slave_blw" || lcl_hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding == "ctrl_slave_abv") ? "true"
+ : "false") : "false";
+
+ // PCS level bonding parameters
+ localparam lcl_hssi_tx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_tx = lcl_hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx;
+ localparam lcl_hssi_rx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_rx = lcl_hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx;
+ localparam lcl_hssi_tx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_tx = lcl_hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx;
+ localparam lcl_hssi_rx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_rx = lcl_hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx;
+ localparam lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding = lcl_hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding;
+
+
+ localparam lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_consumption = enable_pcs_bonding ?
+ (ig < lcl_pcs_bonding_master) ? "bundled_slave_below"
+ : (ig > lcl_pcs_bonding_master) ? "bundled_slave_above"
+ : "bundled_master"
+ : "individual";
+ localparam lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption = (lcl_hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx == "individual_rx")? "individual"
+ : (ig < lcl_pcs_bonding_master) ? "bundled_slave_below"
+ : (ig > lcl_pcs_bonding_master) ? "bundled_slave_above"
+ : "bundled_master";
+
+ localparam lcl_hssi_10g_tx_pcs_ctrl_plane_bonding = enable_pcs_bonding ?
+ (ig < lcl_pcs_bonding_master) ? "ctrl_slave_blw"
+ : (ig > lcl_pcs_bonding_master) ? "ctrl_slave_abv"
+ : "ctrl_master"
+ : "individual";
+ localparam [7:0] lcl_hssi_10g_tx_pcs_comp_cnt = enable_pcs_bonding ? altera_xcvr_native_a10_functions_h::get_comp_cnt_alt_xcvr_native_a10(channels, lcl_pcs_bonding_master, ig)
+ : 8'd0;
+
+ localparam lcl_pma_cgb_select_done_master_or_slave = enable_pcs_bonding ? "choose_master_pcie_sw_done" : "choose_slave_pcie_sw_done";
+
+ // following parameters were assigned auto_single before wrapper files were removed
+ localparam lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_compensation = (hssi_8g_rx_pcs_byte_deserializer=="en_bds_by_4") ? "en_compensation" : "dis_compensation";
+ localparam lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_distribution = (lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_consumption=="bundled_master") ? "master_chnl_distr" : "not_master_chnl_distr";
+ localparam lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_distribution = (lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption=="bundled_master") ? "master_chnl_distr" : "not_master_chnl_distr";
+ localparam lcl_hssi_8g_rx_pcs_auto_speed_nego = (((hssi_8g_rx_pcs_prot_mode=="pipe_g3")&&((lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption=="individual")||(lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption=="bundled_master")))) ?
+ "en_asn_g2_freq_scal" :
+ (((hssi_8g_rx_pcs_prot_mode=="pipe_g2")&&((lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption=="individual")||(lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption=="bundled_master")))) ?
+ "en_asn_g2_freq_scal" :
+ "dis_asn";
+
+ localparam lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_compensation = ((hssi_8g_tx_pcs_byte_serializer=="en_bs_by_4")) ? "en_compensation" : "dis_compensation";
+ localparam lcl_hssi_8g_tx_pcs_auto_speed_nego_gen2 = (((hssi_8g_tx_pcs_prot_mode=="pipe_g2")&&((lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_consumption=="individual")||(lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_consumption=="bundled_master")))) ?
+ "en_asn_g2_freq_scal" :
+ "dis_asn_g2";
+
+ localparam lcl_hssi_10g_tx_pcs_compin_sel = ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="individual")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_master")) ?
+ "compin_master" :
+ ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_blw")) ?
+ "compin_slave_bot" :
+ ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "compin_slave_top" :
+ "compin_default";
+ localparam lcl_hssi_10g_tx_pcs_distdwn_master = ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="individual")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_master")) ?
+ "distdwn_master_en" :
+ ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_blw")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "distdwn_master_dis" :
+ "distdwn_master_dis";
+ localparam lcl_hssi_10g_tx_pcs_distup_master = ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="individual")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_master")) ?
+ "distup_master_en" :
+ ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_blw")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "distup_master_dis" :
+ "distup_master_dis";
+ localparam lcl_hssi_10g_tx_pcs_indv = ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="individual")) ?
+ "indv_en" :
+ ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_blw")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_master")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "indv_dis" :
+ "indv_dis";
+ localparam lcl_hssi_10g_tx_pcs_dv_bond = ((lcl_hssi_10g_tx_pcs_indv=="indv_dis")) ? "dv_bond_en" : "dv_bond_dis";
+
+ localparam lcl_hssi_common_pcs_pma_interface_cp_cons_sel = ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="individual")||(lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_master")) ?
+ "cp_cons_master" :
+ ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_blw")) ?
+ "cp_cons_slave_blw" :
+ ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "cp_cons_slave_abv" :
+ "cp_cons_default";
+ localparam lcl_hssi_common_pcs_pma_interface_cp_dwn_mstr = ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="individual")||(lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_master")) ?
+ "true" :
+ ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_blw")||(lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "false" :
+ "true";
+ localparam lcl_hssi_common_pcs_pma_interface_cp_up_mstr = ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="individual")||(lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_master")) ?
+ "true" :
+ ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_blw")||(lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "false" :
+ "true";
+
+ // String to binary conversions
+ localparam [127:0] temp_lcl_hssi_10g_tx_pcs_pseudo_seed_a = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(hssi_10g_tx_pcs_pseudo_seed_a);
+ localparam [127:0] temp_lcl_hssi_10g_tx_pcs_pseudo_seed_b = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(hssi_10g_tx_pcs_pseudo_seed_b);
+ localparam [127:0] temp_lcl_hssi_8g_rx_pcs_wa_pd_data = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(hssi_8g_rx_pcs_wa_pd_data);
+ localparam [127:0] temp_lcl_pma_tx_buf_xtx_path_pma_tx_divclk_hz = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(pma_tx_buf_xtx_path_pma_tx_divclk_hz);
+ localparam [127:0] temp_lcl_pma_rx_buf_xrx_path_pma_rx_divclk_hz = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(pma_rx_buf_xrx_path_pma_rx_divclk_hz);
+ localparam [127:0] temp_lcl_pma_tx_buf_xtx_path_tx_pll_clk_hz = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(pma_tx_buf_xtx_path_tx_pll_clk_hz);
+ localparam [57:0] lcl_hssi_10g_tx_pcs_pseudo_seed_a = altera_xcvr_native_a10_functions_h::set_10g_scrm_seed_user_alt_xcvr_native_a10(hssi_10g_tx_pcs_prot_mode,temp_lcl_hssi_10g_tx_pcs_pseudo_seed_a [57:0],ig); // randomization per channel for interlaken
+ localparam [57:0] lcl_hssi_10g_tx_pcs_pseudo_seed_b = temp_lcl_hssi_10g_tx_pcs_pseudo_seed_b [57:0];
+ localparam [39:0] lcl_hssi_8g_rx_pcs_wa_pd_data = temp_lcl_hssi_8g_rx_pcs_wa_pd_data [39:0];
+ localparam [31:0] lcl_pma_tx_buf_xtx_path_pma_tx_divclk_hz = temp_lcl_pma_tx_buf_xtx_path_pma_tx_divclk_hz[31:0];
+ localparam [31:0] lcl_pma_rx_buf_xrx_path_pma_rx_divclk_hz = temp_lcl_pma_rx_buf_xrx_path_pma_rx_divclk_hz[31:0];
+ localparam [31:0] lcl_pma_tx_buf_xtx_path_tx_pll_clk_hz = temp_lcl_pma_tx_buf_xtx_path_tx_pll_clk_hz[31:0];
+
+
+ twentynm_xcvr_native #(
+
+ .device_revision(device_revision),
+
+ // nf_pcs parameters
+ .xcvr_native_mode (xcvr_native_mode),
+ .bonding_master_ch (0),
+ .bonded_lanes (1),
+ // nf_xcvr_avmm parameters
+ .avmm_interfaces (1),
+ .rcfg_enable (rcfg_enable),
+ .enable_avmm (1),
+ .arbiter_ctrl (arbiter_ctrl),
+ .calibration_en (calibration_en),
+ .avmm_busy_en (avmm_busy_en),
+ .hip_cal_en (hip_cal_en),
+ .cal_done (cal_done),
+
+
+ // Overridden parameters for pcie
+ .pma_tx_buf_mcgb_location_for_pcie(lcl_pma_tx_buf_mcgb_location_for_pcie),
+
+ // Overridden bonding parameters
+ .hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx(lcl_hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx(lcl_hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding (lcl_hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding ),
+ .hssi_tx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_tx (lcl_hssi_tx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_tx ),
+ .hssi_rx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_rx (lcl_hssi_rx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_rx ),
+ .hssi_tx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_tx (lcl_hssi_tx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_tx ),
+ .hssi_rx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_rx (lcl_hssi_rx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_rx ),
+
+ .hssi_8g_rx_pcs_ctrl_plane_bonding_compensation (lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_compensation),
+ .hssi_8g_rx_pcs_ctrl_plane_bonding_consumption (lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption ),
+ .hssi_8g_rx_pcs_ctrl_plane_bonding_distribution (lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_distribution),
+ .hssi_8g_rx_pcs_auto_speed_nego (lcl_hssi_8g_rx_pcs_auto_speed_nego ),
+
+ .hssi_8g_tx_pcs_ctrl_plane_bonding_compensation (lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_compensation),
+ .hssi_8g_tx_pcs_ctrl_plane_bonding_consumption (lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_consumption ),
+ .hssi_8g_tx_pcs_ctrl_plane_bonding_distribution (lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_distribution),
+ .hssi_8g_tx_pcs_auto_speed_nego_gen2 (lcl_hssi_8g_tx_pcs_auto_speed_nego_gen2 ),
+
+ .hssi_10g_tx_pcs_ctrl_plane_bonding (lcl_hssi_10g_tx_pcs_ctrl_plane_bonding),
+ .hssi_10g_tx_pcs_comp_cnt (lcl_hssi_10g_tx_pcs_comp_cnt ),
+ .hssi_10g_tx_pcs_compin_sel (lcl_hssi_10g_tx_pcs_compin_sel ),
+ .hssi_10g_tx_pcs_distdwn_bypass_pipeln ("distdwn_bypass_pipeln_dis" ),
+ .hssi_10g_tx_pcs_distdwn_master (lcl_hssi_10g_tx_pcs_distdwn_master ),
+ .hssi_10g_tx_pcs_distup_bypass_pipeln ("distup_bypass_pipeln_dis" ),
+ .hssi_10g_tx_pcs_distup_master (lcl_hssi_10g_tx_pcs_distup_master ),
+ .hssi_10g_tx_pcs_dv_bond (lcl_hssi_10g_tx_pcs_dv_bond ),
+ .hssi_10g_tx_pcs_indv (lcl_hssi_10g_tx_pcs_indv ),
+
+ .hssi_common_pcs_pma_interface_ctrl_plane_bonding (lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding),
+ .hssi_common_pcs_pma_interface_cp_cons_sel (lcl_hssi_common_pcs_pma_interface_cp_cons_sel ),
+ .hssi_common_pcs_pma_interface_cp_dwn_mstr (lcl_hssi_common_pcs_pma_interface_cp_dwn_mstr ),
+ .hssi_common_pcs_pma_interface_cp_up_mstr (lcl_hssi_common_pcs_pma_interface_cp_up_mstr ),
+
+ // Overridden parameters for twentynm_hssi_pma_cdr_refclk_select_mux
+ .pma_cdr_refclk_inclk0_logical_to_physical_mapping ( "ref_iqclk0" ),
+ .pma_cdr_refclk_inclk1_logical_to_physical_mapping ( (cdr_refclk_cnt > 1) ? "ref_iqclk1" : "power_down"),
+ .pma_cdr_refclk_inclk2_logical_to_physical_mapping ( (cdr_refclk_cnt > 2) ? "ref_iqclk2" : "power_down"),
+ .pma_cdr_refclk_inclk3_logical_to_physical_mapping ( (cdr_refclk_cnt > 3) ? "ref_iqclk3" : "power_down"),
+ .pma_cdr_refclk_inclk4_logical_to_physical_mapping ( (cdr_refclk_cnt > 4) ? "ref_iqclk4" : "power_down"),
+ .pma_cgb_scratch0_x1_clock_src( (bonded_mode == "not_bonded") ? "fpll_bot" : "unused"),
+ .pma_cgb_scratch1_x1_clock_src(((bonded_mode == "not_bonded") && (plls > 1)) ? "lcpll_bot" : "unused"),
+ .pma_cgb_scratch2_x1_clock_src(((bonded_mode == "not_bonded") && (plls > 2)) ? "fpll_top" : "unused"),
+ .pma_cgb_scratch3_x1_clock_src(((bonded_mode == "not_bonded") && (plls > 3)) ? "lcpll_top" : "unused"),
+ //.pma_cgb_scratch0_bonded_clock_src( ((bonded_mode == "pma_only") || (bonded_mode == "pma_pcs"))?
+ // "fpll_bot" : "unused"),
+ //.pma_cgb_scratch1_bonded_clock_src((((bonded_mode == "pma_only") || (bonded_mode == "pma_pcs")) && (number_physical_bonding_clocks > 1)) ?
+ // "lcpll_bot" : "unused"),
+ //.pma_cgb_scratch2_bonded_clock_src((((bonded_mode == "pma_only") || (bonded_mode == "pma_pcs")) && (number_physical_bonding_clocks > 2)) ?
+ // "fpll_top" : "unused"),
+ //.pma_cgb_scratch3_bonded_clock_src((((bonded_mode == "pma_only") || (bonded_mode == "pma_pcs")) && (number_physical_bonding_clocks > 3)) ?
+ // "lcpll_top" : "unused"),
+
+ // parameters for twentynm_hssi_pma_adaptation
+ // parameters for twentynm_hssi_pma_cdr_refclk_select_mux
+ //.pma_cdr_refclk_receiver_detect_src (pma_cdr_refclk_receiver_detect_src),
+ .pma_cdr_refclk_refclk_select (pma_cdr_refclk_refclk_select),
+ .pma_cdr_refclk_powerdown_mode (pma_cdr_refclk_powerdown_mode),
+ // parameters for twentynm_hssi_pma_channel_pll
+ .cdr_pll_atb_select_control (cdr_pll_atb_select_control),
+ .cdr_pll_bbpd_data_pattern_filter_select (cdr_pll_bbpd_data_pattern_filter_select),
+ .cdr_pll_bw_sel (cdr_pll_bw_sel),
+ .cdr_pll_cdr_odi_select (cdr_pll_cdr_odi_select),
+ .cdr_pll_cgb_div (cdr_pll_cgb_div),
+ .cdr_pll_chgpmp_current_pd (cdr_pll_chgpmp_current_pd),
+ .cdr_pll_chgpmp_current_pfd (cdr_pll_chgpmp_current_pfd),
+ .cdr_pll_chgpmp_replicate (cdr_pll_chgpmp_replicate),
+ .cdr_pll_chgpmp_testmode (cdr_pll_chgpmp_testmode),
+ .cdr_pll_clklow_mux_select (cdr_pll_clklow_mux_select),
+ .cdr_pll_diag_loopback_enable (cdr_pll_diag_loopback_enable),
+ .cdr_pll_disable_up_dn (cdr_pll_disable_up_dn),
+ .cdr_pll_fb_select (cdr_pll_fb_select),
+ .cdr_pll_fref_clklow_div (cdr_pll_fref_clklow_div),
+ .cdr_pll_fref_mux_select (cdr_pll_fref_mux_select),
+ .cdr_pll_gpon_lck2ref_control (cdr_pll_gpon_lck2ref_control),
+ .cdr_pll_iqclk_mux_sel (cdr_pll_iqclk_mux_sel),
+ .cdr_pll_is_cascaded_pll (cdr_pll_is_cascaded_pll),
+ .cdr_pll_lck2ref_delay_control (cdr_pll_lck2ref_delay_control),
+ .cdr_pll_lpd_counter (cdr_pll_lpd_counter),
+ .cdr_pll_lpfd_counter (cdr_pll_lpfd_counter),
+ .cdr_pll_lf_resistor_pd (cdr_pll_lf_resistor_pd),
+ .cdr_pll_lf_resistor_pfd (cdr_pll_lf_resistor_pfd),
+ .cdr_pll_lf_ripple_cap (cdr_pll_lf_ripple_cap),
+ .cdr_pll_loop_filter_bias_select (cdr_pll_loop_filter_bias_select),
+ .cdr_pll_loopback_mode (cdr_pll_loopback_mode),
+ .cdr_pll_ltd_ltr_micro_controller_select (cdr_pll_ltd_ltr_micro_controller_select),
+ .cdr_pll_m_counter (cdr_pll_m_counter),
+ .cdr_pll_n_counter (cdr_pll_n_counter),
+ .cdr_pll_n_counter_scratch (cdr_pll_n_counter_scratch),
+ .cdr_pll_output_clock_frequency (cdr_pll_output_clock_frequency),
+ .cdr_pll_pcie_gen (cdr_pll_pcie_gen),
+ .cdr_pll_set_cdr_input_freq_range (cdr_pll_set_cdr_input_freq_range),
+ .cdr_pll_chgpmp_current_dn_trim (cdr_pll_chgpmp_current_dn_trim),
+ .cdr_pll_chgpmp_up_pd_trim_double (cdr_pll_chgpmp_up_pd_trim_double),
+ .cdr_pll_chgpmp_current_up_pd (cdr_pll_chgpmp_current_up_pd),
+ .cdr_pll_chgpmp_current_up_trim (cdr_pll_chgpmp_current_up_trim),
+ .cdr_pll_chgpmp_dn_pd_trim_double (cdr_pll_chgpmp_dn_pd_trim_double),
+ .cdr_pll_cal_vco_count_length (cdr_pll_cal_vco_count_length),
+ .cdr_pll_chgpmp_current_dn_pd (cdr_pll_chgpmp_current_dn_pd),
+ .cdr_pll_pd_fastlock_mode (cdr_pll_pd_fastlock_mode),
+ .cdr_pll_pd_l_counter (cdr_pll_pd_l_counter),
+ .cdr_pll_pfd_l_counter (cdr_pll_pfd_l_counter),
+ .cdr_pll_pma_width (cdr_pll_pma_width),
+ .cdr_pll_primary_use (cdr_pll_primary_use),
+ .cdr_pll_reference_clock_frequency (cdr_pll_reference_clock_frequency),
+// .cdr_pll_requires_gt_capable_channel (cdr_pll_requires_gt_capable_channel ),
+ .cdr_pll_reverse_serial_loopback (cdr_pll_reverse_serial_loopback),
+ .cdr_pll_set_cdr_vco_reset (cdr_pll_set_cdr_vco_reset),
+ .cdr_pll_set_cdr_vco_speed (cdr_pll_set_cdr_vco_speed),
+ .cdr_pll_set_cdr_vco_speed_pciegen3 (cdr_pll_set_cdr_vco_speed_pciegen3),
+ .cdr_pll_set_cdr_v2i_enable (cdr_pll_set_cdr_v2i_enable),
+ .cdr_pll_txpll_hclk_driver_enable (cdr_pll_txpll_hclk_driver_enable),
+ .cdr_pll_vco_overrange_voltage (cdr_pll_vco_overrange_voltage),
+ .cdr_pll_vco_underrange_voltage (cdr_pll_vco_underrange_voltage),
+ .cdr_pll_uc_ro_cal (cdr_pll_uc_ro_cal),
+ .cdr_pll_vco_freq (cdr_pll_vco_freq),
+ .cdr_pll_set_cdr_vco_speed_fix (cdr_pll_set_cdr_vco_speed_fix),
+ .cdr_pll_auto_reset_on (cdr_pll_auto_reset_on),
+ .cdr_pll_cdr_phaselock_mode (cdr_pll_cdr_phaselock_mode),
+ .cdr_pll_cdr_powerdown_mode (cdr_pll_cdr_powerdown_mode),
+ .cdr_pll_initial_settings (cdr_pll_initial_settings),
+ // parameters for pma_adapt
+ .pma_adapt_adapt_mode (pma_adapt_adapt_mode),
+ .pma_adapt_adp_1s_ctle_bypass (pma_adapt_adp_1s_ctle_bypass),
+ .pma_adapt_adp_4s_ctle_bypass (pma_adapt_adp_4s_ctle_bypass),
+ .pma_adapt_adp_ctle_adapt_cycle_window (pma_adapt_adp_ctle_adapt_cycle_window),
+ .pma_adapt_adp_ctle_en (pma_adapt_adp_ctle_en),
+ .pma_adapt_adp_dfe_fltap_bypass (pma_adapt_adp_dfe_fltap_bypass),
+ .pma_adapt_adp_dfe_fltap_en (pma_adapt_adp_dfe_fltap_en),
+ .pma_adapt_adp_dfe_fxtap_bypass (pma_adapt_adp_dfe_fxtap_bypass),
+ .pma_adapt_adp_dfe_fxtap_en (pma_adapt_adp_dfe_fxtap_en),
+ .pma_adapt_adp_dfe_fxtap_hold_en (pma_adapt_adp_dfe_fxtap_hold_en),
+ .pma_adapt_adp_dfe_mode (pma_adapt_adp_dfe_mode),
+ .pma_adapt_adp_mode (pma_adapt_adp_mode),
+ .pma_adapt_adp_onetime_dfe (pma_adapt_adp_onetime_dfe),
+ .pma_adapt_adp_vga_bypass (pma_adapt_adp_vga_bypass),
+ .pma_adapt_adp_vga_en (pma_adapt_adp_vga_en),
+ .pma_adapt_adp_vref_bypass (pma_adapt_adp_vref_bypass),
+ .pma_adapt_adp_vref_en (pma_adapt_adp_vref_en),
+ .pma_adapt_odi_dfe_spec_en (pma_adapt_odi_dfe_spec_en),
+ // parameters for twentynm_hssi_pma_rx_buf
+ .pma_rx_buf_bypass_eqz_stages_234 (pma_rx_buf_bypass_eqz_stages_234),
+ .pma_rx_buf_diag_lp_en (pma_rx_buf_diag_lp_en),
+ .pma_rx_buf_qpi_enable (pma_rx_buf_qpi_enable),
+ .pma_rx_buf_rx_refclk_divider (pma_rx_buf_rx_refclk_divider),
+ .pma_rx_buf_loopback_modes (pma_rx_buf_loopback_modes),
+ .pma_rx_buf_refclk_en (pma_rx_buf_refclk_en),
+ .pma_rx_buf_pm_tx_rx_pcie_gen (pma_rx_buf_pm_tx_rx_pcie_gen),
+ .pma_rx_buf_pm_tx_rx_pcie_gen_bitwidth (pma_rx_buf_pm_tx_rx_pcie_gen_bitwidth),
+ .pma_rx_buf_pm_tx_rx_cvp_mode (pma_rx_buf_pm_tx_rx_cvp_mode),
+ .pma_rx_buf_xrx_path_uc_cal_enable (pma_rx_buf_xrx_path_uc_cal_enable),
+ .pma_rx_buf_xrx_path_datawidth (pma_rx_buf_xrx_path_datawidth),
+ .pma_rx_buf_xrx_path_pma_rx_divclk_hz (lcl_pma_rx_buf_xrx_path_pma_rx_divclk_hz), // String to bin conversion
+ // parameters for twentynm_hssi_pma_rx_deser
+ .pma_rx_deser_clkdivrx_user_mode (pma_rx_deser_clkdivrx_user_mode),
+ .pma_rx_deser_pcie_gen (pma_rx_deser_pcie_gen),
+ .pma_rx_deser_pcie_gen_bitwidth (pma_rx_deser_pcie_gen_bitwidth),
+ .pma_rx_deser_deser_factor (pma_rx_deser_deser_factor),
+ .pma_rx_deser_sdclk_enable (pma_rx_deser_sdclk_enable),
+ .pma_rx_deser_clkdiv_source (pma_rx_deser_clkdiv_source),
+ .pma_rx_deser_force_clkdiv_for_testing (pma_rx_deser_force_clkdiv_for_testing),
+ .pma_rx_deser_rst_n_adapt_odi (pma_rx_deser_rst_n_adapt_odi),
+ .pma_rx_deser_bitslip_bypass (pma_rx_deser_bitslip_bypass),
+ // parameters for twentynm_hssi_pma_rx_dfe
+ .pma_rx_dfe_pdb (pma_rx_dfe_pdb),
+ .pma_rx_dfe_pdb_fixedtap (pma_rx_dfe_pdb_fixedtap),
+ .pma_rx_dfe_pdb_floattap (pma_rx_dfe_pdb_floattap),
+ .pma_rx_dfe_pdb_fxtap4t7 (pma_rx_dfe_pdb_fxtap4t7),
+ .pma_rx_dfe_dft_en (pma_rx_dfe_dft_en),
+ // parameters for twentynm_hssi_pma_rx_odi
+ .pma_rx_odi_step_ctrl_sel (pma_rx_odi_step_ctrl_sel),
+ // parameters for twentynm_hssi_pma_rx_sd
+ .pma_rx_sd_sd_output_off (pma_rx_sd_sd_output_off),
+ .pma_rx_sd_sd_output_on (pma_rx_sd_sd_output_on),
+ .pma_rx_sd_sd_pdb (pma_rx_sd_sd_pdb),
+ //.pma_rx_sd_sd_threshold (pma_rx_sd_sd_threshold),
+ // parameters for twentynm_hssi_pma_tx_buf
+ .pma_tx_buf_rx_det (pma_tx_buf_rx_det),
+ .pma_tx_buf_rx_det_output_sel (pma_tx_buf_rx_det_output_sel),
+ .pma_tx_buf_rx_det_pdb (pma_tx_buf_rx_det_pdb),
+ .pma_tx_buf_user_fir_coeff_ctrl_sel (pma_tx_buf_user_fir_coeff_ctrl_sel),
+ .pma_tx_buf_xtx_path_datawidth (pma_tx_buf_xtx_path_datawidth),
+ .pma_tx_buf_xtx_path_clock_divider_ratio (pma_tx_buf_xtx_path_clock_divider_ratio),
+ .pma_tx_buf_xtx_path_pma_tx_divclk_hz (lcl_pma_tx_buf_xtx_path_pma_tx_divclk_hz), // String to bin conversion
+ //.pma_tx_buf_xtx_path_tx_pll_clk_hz (lcl_pma_tx_buf_xtx_path_tx_pll_clk_hz), // String to bin conversion
+ .pma_tx_buf_xtx_path_tx_pll_clk_hz (pma_tx_buf_xtx_path_tx_pll_clk_hz),
+ // parameters for twentynm_hssi_pma_tx_cgb
+ .pma_cgb_bitslip_enable (pma_cgb_bitslip_enable),
+ .pma_cgb_bonding_reset_enable (pma_cgb_bonding_reset_enable),
+ .pma_cgb_input_select_xn (pma_cgb_input_select_xn),
+ .pma_cgb_input_select_gen3 (pma_cgb_input_select_gen3),
+ .pma_cgb_input_select_x1 (pma_cgb_input_select_x1),
+ .pma_cgb_pcie_gen3_bitwidth (pma_cgb_pcie_gen3_bitwidth),
+ .pma_cgb_select_done_master_or_slave (lcl_pma_cgb_select_done_master_or_slave),
+ .pma_cgb_ser_mode (pma_cgb_ser_mode),
+ .pma_cgb_x1_div_m_sel (pma_cgb_x1_div_m_sel),
+ .pma_cgb_tx_ucontrol_en (pma_cgb_tx_ucontrol_en),
+ // parameters for twentynm_hssi_pma_tx_ser
+ .pma_tx_ser_ser_clk_divtx_user_sel (pma_tx_ser_ser_clk_divtx_user_sel),
+
+ // twentynm_pcs parameters
+ // parameters for twentynm_hssi_10g_rx_pcs
+ .hssi_10g_rx_pcs_advanced_user_mode (hssi_10g_rx_pcs_advanced_user_mode),
+ .hssi_10g_rx_pcs_align_del (hssi_10g_rx_pcs_align_del),
+ .hssi_10g_rx_pcs_ber_bit_err_total_cnt (hssi_10g_rx_pcs_ber_bit_err_total_cnt),
+ .hssi_10g_rx_pcs_ber_clken (hssi_10g_rx_pcs_ber_clken),
+ .hssi_10g_rx_pcs_ber_xus_timer_window (hssi_10g_rx_pcs_ber_xus_timer_window),
+ .hssi_10g_rx_pcs_bitslip_mode (hssi_10g_rx_pcs_bitslip_mode),
+ .hssi_10g_rx_pcs_blksync_bitslip_type (hssi_10g_rx_pcs_blksync_bitslip_type),
+ .hssi_10g_rx_pcs_blksync_bitslip_wait_cnt (hssi_10g_rx_pcs_blksync_bitslip_wait_cnt),
+ .hssi_10g_rx_pcs_blksync_bitslip_wait_type (hssi_10g_rx_pcs_blksync_bitslip_wait_type),
+ .hssi_10g_rx_pcs_blksync_bypass (hssi_10g_rx_pcs_blksync_bypass),
+ .hssi_10g_rx_pcs_blksync_clken (hssi_10g_rx_pcs_blksync_clken),
+ .hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt (hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt),
+ .hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock (hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock),
+ .hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock (hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock),
+ .hssi_10g_rx_pcs_blksync_pipeln (hssi_10g_rx_pcs_blksync_pipeln),
+ .hssi_10g_rx_pcs_clr_errblk_cnt_en (hssi_10g_rx_pcs_clr_errblk_cnt_en),
+ .hssi_10g_rx_pcs_control_del (hssi_10g_rx_pcs_control_del),
+ .hssi_10g_rx_pcs_crcchk_bypass (hssi_10g_rx_pcs_crcchk_bypass),
+ .hssi_10g_rx_pcs_crcchk_clken (hssi_10g_rx_pcs_crcchk_clken),
+ .hssi_10g_rx_pcs_crcchk_inv (hssi_10g_rx_pcs_crcchk_inv),
+ .hssi_10g_rx_pcs_crcchk_pipeln (hssi_10g_rx_pcs_crcchk_pipeln),
+ .hssi_10g_rx_pcs_crcflag_pipeln (hssi_10g_rx_pcs_crcflag_pipeln),
+ .hssi_10g_rx_pcs_ctrl_bit_reverse (hssi_10g_rx_pcs_ctrl_bit_reverse),
+ .hssi_10g_rx_pcs_data_bit_reverse (hssi_10g_rx_pcs_data_bit_reverse),
+ .hssi_10g_rx_pcs_dec64b66b_clken (hssi_10g_rx_pcs_dec64b66b_clken),
+ .hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass (hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass),
+ .hssi_10g_rx_pcs_descrm_bypass (hssi_10g_rx_pcs_descrm_bypass),
+ .hssi_10g_rx_pcs_descrm_clken (hssi_10g_rx_pcs_descrm_clken),
+ .hssi_10g_rx_pcs_descrm_mode (hssi_10g_rx_pcs_descrm_mode),
+ .hssi_10g_rx_pcs_descrm_pipeln (hssi_10g_rx_pcs_descrm_pipeln),
+ .hssi_10g_rx_pcs_dft_clk_out_sel (hssi_10g_rx_pcs_dft_clk_out_sel),
+ .hssi_10g_rx_pcs_dis_signal_ok (hssi_10g_rx_pcs_dis_signal_ok),
+ .hssi_10g_rx_pcs_dispchk_bypass (hssi_10g_rx_pcs_dispchk_bypass),
+ .hssi_10g_rx_pcs_empty_flag_type (hssi_10g_rx_pcs_empty_flag_type),
+ .hssi_10g_rx_pcs_fast_path (hssi_10g_rx_pcs_fast_path),
+ .hssi_10g_rx_pcs_fec_clken (hssi_10g_rx_pcs_fec_clken),
+ .hssi_10g_rx_pcs_fec_enable (hssi_10g_rx_pcs_fec_enable),
+ .hssi_10g_rx_pcs_fifo_double_read (hssi_10g_rx_pcs_fifo_double_read),
+ .hssi_10g_rx_pcs_fifo_stop_rd (hssi_10g_rx_pcs_fifo_stop_rd),
+ .hssi_10g_rx_pcs_fifo_stop_wr (hssi_10g_rx_pcs_fifo_stop_wr),
+ .hssi_10g_rx_pcs_force_align (hssi_10g_rx_pcs_force_align),
+ .hssi_10g_rx_pcs_frmsync_bypass (hssi_10g_rx_pcs_frmsync_bypass),
+ .hssi_10g_rx_pcs_frmsync_clken (hssi_10g_rx_pcs_frmsync_clken),
+ .hssi_10g_rx_pcs_frmsync_enum_scrm (hssi_10g_rx_pcs_frmsync_enum_scrm),
+ .hssi_10g_rx_pcs_frmsync_enum_sync (hssi_10g_rx_pcs_frmsync_enum_sync),
+ .hssi_10g_rx_pcs_frmsync_flag_type (hssi_10g_rx_pcs_frmsync_flag_type),
+ .hssi_10g_rx_pcs_frmsync_knum_sync (hssi_10g_rx_pcs_frmsync_knum_sync),
+ .hssi_10g_rx_pcs_frmsync_mfrm_length (hssi_10g_rx_pcs_frmsync_mfrm_length),
+ .hssi_10g_rx_pcs_frmsync_pipeln (hssi_10g_rx_pcs_frmsync_pipeln),
+ .hssi_10g_rx_pcs_full_flag_type (hssi_10g_rx_pcs_full_flag_type),
+ .hssi_10g_rx_pcs_gb_rx_idwidth (hssi_10g_rx_pcs_gb_rx_idwidth),
+ .hssi_10g_rx_pcs_gb_rx_odwidth (hssi_10g_rx_pcs_gb_rx_odwidth),
+ .hssi_10g_rx_pcs_gbexp_clken (hssi_10g_rx_pcs_gbexp_clken),
+ .hssi_10g_rx_pcs_low_latency_en (hssi_10g_rx_pcs_low_latency_en),
+ .hssi_10g_rx_pcs_lpbk_mode (hssi_10g_rx_pcs_lpbk_mode),
+ .hssi_10g_rx_pcs_master_clk_sel (hssi_10g_rx_pcs_master_clk_sel),
+ .hssi_10g_rx_pcs_pempty_flag_type (hssi_10g_rx_pcs_pempty_flag_type),
+ .hssi_10g_rx_pcs_pfull_flag_type (hssi_10g_rx_pcs_pfull_flag_type),
+ .hssi_10g_rx_pcs_phcomp_rd_del (hssi_10g_rx_pcs_phcomp_rd_del),
+ .hssi_10g_rx_pcs_pld_if_type (hssi_10g_rx_pcs_pld_if_type),
+ .hssi_10g_rx_pcs_rand_clken (hssi_10g_rx_pcs_rand_clken),
+ .hssi_10g_rx_pcs_rd_clk_sel (hssi_10g_rx_pcs_rd_clk_sel),
+ .hssi_10g_rx_pcs_rdfifo_clken (hssi_10g_rx_pcs_rdfifo_clken),
+ .hssi_10g_rx_pcs_rx_fifo_write_ctrl (hssi_10g_rx_pcs_rx_fifo_write_ctrl),
+ .hssi_10g_rx_pcs_rx_scrm_width (hssi_10g_rx_pcs_rx_scrm_width),
+ .hssi_10g_rx_pcs_rx_sh_location (hssi_10g_rx_pcs_rx_sh_location),
+ .hssi_10g_rx_pcs_rx_signal_ok_sel (hssi_10g_rx_pcs_rx_signal_ok_sel),
+ .hssi_10g_rx_pcs_rx_sm_bypass (hssi_10g_rx_pcs_rx_sm_bypass),
+ .hssi_10g_rx_pcs_rx_sm_hiber (hssi_10g_rx_pcs_rx_sm_hiber),
+ .hssi_10g_rx_pcs_rx_sm_pipeln (hssi_10g_rx_pcs_rx_sm_pipeln),
+ .hssi_10g_rx_pcs_rx_testbus_sel (hssi_10g_rx_pcs_rx_testbus_sel),
+ .hssi_10g_rx_pcs_rx_true_b2b (hssi_10g_rx_pcs_rx_true_b2b),
+ .hssi_10g_rx_pcs_rxfifo_empty (hssi_10g_rx_pcs_rxfifo_empty),
+ .hssi_10g_rx_pcs_rxfifo_full (hssi_10g_rx_pcs_rxfifo_full),
+ .hssi_10g_rx_pcs_rxfifo_mode (hssi_10g_rx_pcs_rxfifo_mode),
+ .hssi_10g_rx_pcs_rxfifo_pempty (hssi_10g_rx_pcs_rxfifo_pempty),
+ .hssi_10g_rx_pcs_rxfifo_pfull (hssi_10g_rx_pcs_rxfifo_pfull),
+ .hssi_10g_rx_pcs_stretch_num_stages (hssi_10g_rx_pcs_stretch_num_stages),
+ .hssi_10g_rx_pcs_test_mode (hssi_10g_rx_pcs_test_mode),
+ .hssi_10g_rx_pcs_wrfifo_clken (hssi_10g_rx_pcs_wrfifo_clken),
+ // parameters for twentynm_hssi_10g_tx_pcs
+ .hssi_10g_tx_pcs_advanced_user_mode (hssi_10g_tx_pcs_advanced_user_mode),
+ .hssi_10g_tx_pcs_bitslip_en (hssi_10g_tx_pcs_bitslip_en),
+ .hssi_10g_tx_pcs_bonding_dft_en (hssi_10g_tx_pcs_bonding_dft_en),
+ .hssi_10g_tx_pcs_bonding_dft_val (hssi_10g_tx_pcs_bonding_dft_val),
+ .hssi_10g_tx_pcs_crcgen_bypass (hssi_10g_tx_pcs_crcgen_bypass),
+ .hssi_10g_tx_pcs_crcgen_clken (hssi_10g_tx_pcs_crcgen_clken),
+ .hssi_10g_tx_pcs_crcgen_err (hssi_10g_tx_pcs_crcgen_err),
+ .hssi_10g_tx_pcs_crcgen_inv (hssi_10g_tx_pcs_crcgen_inv),
+ .hssi_10g_tx_pcs_ctrl_bit_reverse (hssi_10g_tx_pcs_ctrl_bit_reverse),
+ .hssi_10g_tx_pcs_data_bit_reverse (hssi_10g_tx_pcs_data_bit_reverse),
+ .hssi_10g_tx_pcs_dft_clk_out_sel (hssi_10g_tx_pcs_dft_clk_out_sel),
+ .hssi_10g_tx_pcs_dispgen_bypass (hssi_10g_tx_pcs_dispgen_bypass),
+ .hssi_10g_tx_pcs_dispgen_clken (hssi_10g_tx_pcs_dispgen_clken),
+ .hssi_10g_tx_pcs_dispgen_err (hssi_10g_tx_pcs_dispgen_err),
+ .hssi_10g_tx_pcs_dispgen_pipeln (hssi_10g_tx_pcs_dispgen_pipeln),
+ .hssi_10g_tx_pcs_empty_flag_type (hssi_10g_tx_pcs_empty_flag_type),
+ .hssi_10g_tx_pcs_enc64b66b_txsm_clken (hssi_10g_tx_pcs_enc64b66b_txsm_clken),
+ .hssi_10g_tx_pcs_enc_64b66b_txsm_bypass (hssi_10g_tx_pcs_enc_64b66b_txsm_bypass),
+ .hssi_10g_tx_pcs_fastpath (hssi_10g_tx_pcs_fastpath),
+ .hssi_10g_tx_pcs_fec_clken (hssi_10g_tx_pcs_fec_clken),
+ .hssi_10g_tx_pcs_fec_enable (hssi_10g_tx_pcs_fec_enable),
+ .hssi_10g_tx_pcs_fifo_double_write (hssi_10g_tx_pcs_fifo_double_write),
+ .hssi_10g_tx_pcs_fifo_reg_fast (hssi_10g_tx_pcs_fifo_reg_fast),
+ .hssi_10g_tx_pcs_fifo_stop_rd (hssi_10g_tx_pcs_fifo_stop_rd),
+ .hssi_10g_tx_pcs_fifo_stop_wr (hssi_10g_tx_pcs_fifo_stop_wr),
+ .hssi_10g_tx_pcs_frmgen_burst (hssi_10g_tx_pcs_frmgen_burst),
+ .hssi_10g_tx_pcs_frmgen_bypass (hssi_10g_tx_pcs_frmgen_bypass),
+ .hssi_10g_tx_pcs_frmgen_clken (hssi_10g_tx_pcs_frmgen_clken),
+ .hssi_10g_tx_pcs_frmgen_mfrm_length (hssi_10g_tx_pcs_frmgen_mfrm_length),
+ .hssi_10g_tx_pcs_frmgen_pipeln (hssi_10g_tx_pcs_frmgen_pipeln),
+ .hssi_10g_tx_pcs_frmgen_pyld_ins (hssi_10g_tx_pcs_frmgen_pyld_ins),
+ .hssi_10g_tx_pcs_frmgen_wordslip (hssi_10g_tx_pcs_frmgen_wordslip),
+ .hssi_10g_tx_pcs_full_flag_type (hssi_10g_tx_pcs_full_flag_type),
+ .hssi_10g_tx_pcs_gb_pipeln_bypass (hssi_10g_tx_pcs_gb_pipeln_bypass),
+ .hssi_10g_tx_pcs_gb_tx_idwidth (hssi_10g_tx_pcs_gb_tx_idwidth),
+ .hssi_10g_tx_pcs_gb_tx_odwidth (hssi_10g_tx_pcs_gb_tx_odwidth),
+ .hssi_10g_tx_pcs_gbred_clken (hssi_10g_tx_pcs_gbred_clken),
+ .hssi_10g_tx_pcs_low_latency_en (hssi_10g_tx_pcs_low_latency_en),
+ .hssi_10g_tx_pcs_master_clk_sel (hssi_10g_tx_pcs_master_clk_sel),
+ .hssi_10g_tx_pcs_pempty_flag_type (hssi_10g_tx_pcs_pempty_flag_type),
+ .hssi_10g_tx_pcs_pfull_flag_type (hssi_10g_tx_pcs_pfull_flag_type),
+ .hssi_10g_tx_pcs_phcomp_rd_del (hssi_10g_tx_pcs_phcomp_rd_del),
+ .hssi_10g_tx_pcs_pld_if_type (hssi_10g_tx_pcs_pld_if_type),
+ .hssi_10g_tx_pcs_pseudo_random (hssi_10g_tx_pcs_pseudo_random),
+ .hssi_10g_tx_pcs_pseudo_seed_a (lcl_hssi_10g_tx_pcs_pseudo_seed_a), // String to bin conversion
+ .hssi_10g_tx_pcs_pseudo_seed_b (lcl_hssi_10g_tx_pcs_pseudo_seed_b), // String to bin conversion
+ .hssi_10g_tx_pcs_random_disp (hssi_10g_tx_pcs_random_disp),
+ .hssi_10g_tx_pcs_rdfifo_clken (hssi_10g_tx_pcs_rdfifo_clken),
+ .hssi_10g_tx_pcs_scrm_bypass (hssi_10g_tx_pcs_scrm_bypass),
+ .hssi_10g_tx_pcs_scrm_clken (hssi_10g_tx_pcs_scrm_clken),
+ .hssi_10g_tx_pcs_scrm_mode (hssi_10g_tx_pcs_scrm_mode),
+ .hssi_10g_tx_pcs_scrm_pipeln (hssi_10g_tx_pcs_scrm_pipeln),
+ .hssi_10g_tx_pcs_sh_err (hssi_10g_tx_pcs_sh_err),
+ .hssi_10g_tx_pcs_sop_mark (hssi_10g_tx_pcs_sop_mark),
+ .hssi_10g_tx_pcs_stretch_num_stages (hssi_10g_tx_pcs_stretch_num_stages),
+ .hssi_10g_tx_pcs_test_mode (hssi_10g_tx_pcs_test_mode),
+ .hssi_10g_tx_pcs_tx_scrm_err (hssi_10g_tx_pcs_tx_scrm_err),
+ .hssi_10g_tx_pcs_tx_scrm_width (hssi_10g_tx_pcs_tx_scrm_width),
+ .hssi_10g_tx_pcs_tx_sh_location (hssi_10g_tx_pcs_tx_sh_location),
+ .hssi_10g_tx_pcs_tx_sm_bypass (hssi_10g_tx_pcs_tx_sm_bypass),
+ .hssi_10g_tx_pcs_tx_sm_pipeln (hssi_10g_tx_pcs_tx_sm_pipeln),
+ .hssi_10g_tx_pcs_tx_testbus_sel (hssi_10g_tx_pcs_tx_testbus_sel),
+ .hssi_10g_tx_pcs_txfifo_empty (hssi_10g_tx_pcs_txfifo_empty),
+ .hssi_10g_tx_pcs_txfifo_full (hssi_10g_tx_pcs_txfifo_full),
+ .hssi_10g_tx_pcs_txfifo_mode (hssi_10g_tx_pcs_txfifo_mode),
+ .hssi_10g_tx_pcs_txfifo_pempty (hssi_10g_tx_pcs_txfifo_pempty),
+ .hssi_10g_tx_pcs_txfifo_pfull (hssi_10g_tx_pcs_txfifo_pfull),
+ .hssi_10g_tx_pcs_wr_clk_sel (hssi_10g_tx_pcs_wr_clk_sel),
+ .hssi_10g_tx_pcs_wrfifo_clken (hssi_10g_tx_pcs_wrfifo_clken),
+ // parameters for twentynm_hssi_8g_rx_pcs
+ .hssi_8g_rx_pcs_auto_error_replacement (hssi_8g_rx_pcs_auto_error_replacement),
+ .hssi_8g_rx_pcs_bit_reversal (hssi_8g_rx_pcs_bit_reversal),
+ .hssi_8g_rx_pcs_bonding_dft_en (hssi_8g_rx_pcs_bonding_dft_en),
+ .hssi_8g_rx_pcs_bonding_dft_val (hssi_8g_rx_pcs_bonding_dft_val),
+ .hssi_8g_rx_pcs_bypass_pipeline_reg (hssi_8g_rx_pcs_bypass_pipeline_reg),
+ .hssi_8g_rx_pcs_byte_deserializer (hssi_8g_rx_pcs_byte_deserializer),
+ .hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask (hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask),
+ .hssi_8g_rx_pcs_clkcmp_pattern_n (hssi_8g_rx_pcs_clkcmp_pattern_n),
+ .hssi_8g_rx_pcs_clkcmp_pattern_p (hssi_8g_rx_pcs_clkcmp_pattern_p),
+ .hssi_8g_rx_pcs_clock_gate_bds_dec_asn (hssi_8g_rx_pcs_clock_gate_bds_dec_asn),
+ .hssi_8g_rx_pcs_clock_gate_cdr_eidle (hssi_8g_rx_pcs_clock_gate_cdr_eidle),
+ .hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk (hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk),
+ .hssi_8g_rx_pcs_clock_gate_dw_rm_rd (hssi_8g_rx_pcs_clock_gate_dw_rm_rd),
+ .hssi_8g_rx_pcs_clock_gate_dw_rm_wr (hssi_8g_rx_pcs_clock_gate_dw_rm_wr),
+ .hssi_8g_rx_pcs_clock_gate_dw_wa (hssi_8g_rx_pcs_clock_gate_dw_wa),
+ .hssi_8g_rx_pcs_clock_gate_pc_rdclk (hssi_8g_rx_pcs_clock_gate_pc_rdclk),
+ .hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk (hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk),
+ .hssi_8g_rx_pcs_clock_gate_sw_rm_rd (hssi_8g_rx_pcs_clock_gate_sw_rm_rd),
+ .hssi_8g_rx_pcs_clock_gate_sw_rm_wr (hssi_8g_rx_pcs_clock_gate_sw_rm_wr),
+ .hssi_8g_rx_pcs_clock_gate_sw_wa (hssi_8g_rx_pcs_clock_gate_sw_wa),
+ .hssi_8g_rx_pcs_clock_observation_in_pld_core (hssi_8g_rx_pcs_clock_observation_in_pld_core),
+ .hssi_8g_rx_pcs_eidle_entry_eios (hssi_8g_rx_pcs_eidle_entry_eios),
+ .hssi_8g_rx_pcs_eidle_entry_iei (hssi_8g_rx_pcs_eidle_entry_iei),
+ .hssi_8g_rx_pcs_eidle_entry_sd (hssi_8g_rx_pcs_eidle_entry_sd),
+ .hssi_8g_rx_pcs_eightb_tenb_decoder (hssi_8g_rx_pcs_eightb_tenb_decoder),
+ .hssi_8g_rx_pcs_err_flags_sel (hssi_8g_rx_pcs_err_flags_sel),
+ .hssi_8g_rx_pcs_fixed_pat_det (hssi_8g_rx_pcs_fixed_pat_det),
+ .hssi_8g_rx_pcs_fixed_pat_num (hssi_8g_rx_pcs_fixed_pat_num),
+ .hssi_8g_rx_pcs_force_signal_detect (hssi_8g_rx_pcs_force_signal_detect),
+ .hssi_8g_rx_pcs_gen3_clk_en (hssi_8g_rx_pcs_gen3_clk_en),
+ .hssi_8g_rx_pcs_gen3_rx_clk_sel (hssi_8g_rx_pcs_gen3_rx_clk_sel),
+ .hssi_8g_rx_pcs_gen3_tx_clk_sel (hssi_8g_rx_pcs_gen3_tx_clk_sel),
+ .hssi_8g_rx_pcs_hip_mode (hssi_8g_rx_pcs_hip_mode),
+ .hssi_8g_rx_pcs_ibm_invalid_code (hssi_8g_rx_pcs_ibm_invalid_code),
+ .hssi_8g_rx_pcs_invalid_code_flag_only (hssi_8g_rx_pcs_invalid_code_flag_only),
+ .hssi_8g_rx_pcs_pad_or_edb_error_replace (hssi_8g_rx_pcs_pad_or_edb_error_replace),
+ .hssi_8g_rx_pcs_pcs_bypass (hssi_8g_rx_pcs_pcs_bypass),
+ .hssi_8g_rx_pcs_phase_comp_rdptr (hssi_8g_rx_pcs_phase_comp_rdptr),
+ .hssi_8g_rx_pcs_phase_compensation_fifo (hssi_8g_rx_pcs_phase_compensation_fifo),
+ .hssi_8g_rx_pcs_pipe_if_enable (hssi_8g_rx_pcs_pipe_if_enable),
+ .hssi_8g_rx_pcs_pma_dw (hssi_8g_rx_pcs_pma_dw),
+ .hssi_8g_rx_pcs_polinv_8b10b_dec (hssi_8g_rx_pcs_polinv_8b10b_dec),
+ .hssi_8g_rx_pcs_rate_match (hssi_8g_rx_pcs_rate_match),
+ .hssi_8g_rx_pcs_rate_match_del_thres (hssi_8g_rx_pcs_rate_match_del_thres),
+ .hssi_8g_rx_pcs_rate_match_empty_thres (hssi_8g_rx_pcs_rate_match_empty_thres),
+ .hssi_8g_rx_pcs_rate_match_full_thres (hssi_8g_rx_pcs_rate_match_full_thres),
+ .hssi_8g_rx_pcs_rate_match_ins_thres (hssi_8g_rx_pcs_rate_match_ins_thres),
+ .hssi_8g_rx_pcs_rate_match_start_thres (hssi_8g_rx_pcs_rate_match_start_thres),
+ .hssi_8g_rx_pcs_rx_clk2 (hssi_8g_rx_pcs_rx_clk2),
+ .hssi_8g_rx_pcs_rx_clk_free_running (hssi_8g_rx_pcs_rx_clk_free_running),
+ .hssi_8g_rx_pcs_rx_pcs_urst (hssi_8g_rx_pcs_rx_pcs_urst),
+ .hssi_8g_rx_pcs_rx_rcvd_clk (hssi_8g_rx_pcs_rx_rcvd_clk),
+ .hssi_8g_rx_pcs_rx_rd_clk (hssi_8g_rx_pcs_rx_rd_clk),
+ .hssi_8g_rx_pcs_rx_refclk (hssi_8g_rx_pcs_rx_refclk),
+ .hssi_8g_rx_pcs_rx_wr_clk (hssi_8g_rx_pcs_rx_wr_clk),
+ .hssi_8g_rx_pcs_symbol_swap (hssi_8g_rx_pcs_symbol_swap),
+ .hssi_8g_rx_pcs_sync_sm_idle_eios (hssi_8g_rx_pcs_sync_sm_idle_eios),
+ .hssi_8g_rx_pcs_test_bus_sel (hssi_8g_rx_pcs_test_bus_sel),
+ .hssi_8g_rx_pcs_tx_rx_parallel_loopback (hssi_8g_rx_pcs_tx_rx_parallel_loopback),
+ .hssi_8g_rx_pcs_wa_boundary_lock_ctrl (hssi_8g_rx_pcs_wa_boundary_lock_ctrl),
+ .hssi_8g_rx_pcs_wa_clk_slip_spacing (hssi_8g_rx_pcs_wa_clk_slip_spacing),
+ .hssi_8g_rx_pcs_wa_det_latency_sync_status_beh (hssi_8g_rx_pcs_wa_det_latency_sync_status_beh),
+ .hssi_8g_rx_pcs_wa_disp_err_flag (hssi_8g_rx_pcs_wa_disp_err_flag),
+ .hssi_8g_rx_pcs_wa_kchar (hssi_8g_rx_pcs_wa_kchar),
+ .hssi_8g_rx_pcs_wa_pd (hssi_8g_rx_pcs_wa_pd),
+ .hssi_8g_rx_pcs_wa_pd_data (lcl_hssi_8g_rx_pcs_wa_pd_data),
+ .hssi_8g_rx_pcs_wa_pd_polarity (hssi_8g_rx_pcs_wa_pd_polarity),
+ .hssi_8g_rx_pcs_wa_pld_controlled (hssi_8g_rx_pcs_wa_pld_controlled),
+ .hssi_8g_rx_pcs_wa_renumber_data (hssi_8g_rx_pcs_wa_renumber_data),
+ .hssi_8g_rx_pcs_wa_rgnumber_data (hssi_8g_rx_pcs_wa_rgnumber_data),
+ .hssi_8g_rx_pcs_wa_rknumber_data (hssi_8g_rx_pcs_wa_rknumber_data),
+ .hssi_8g_rx_pcs_wa_rosnumber_data (hssi_8g_rx_pcs_wa_rosnumber_data),
+ .hssi_8g_rx_pcs_wa_rvnumber_data (hssi_8g_rx_pcs_wa_rvnumber_data),
+ .hssi_8g_rx_pcs_wa_sync_sm_ctrl (hssi_8g_rx_pcs_wa_sync_sm_ctrl),
+ .hssi_8g_rx_pcs_wait_cnt (hssi_8g_rx_pcs_wait_cnt),
+ // parameters for twentynm_hssi_8g_tx_pcs
+ .hssi_8g_tx_pcs_bit_reversal (hssi_8g_tx_pcs_bit_reversal),
+ .hssi_8g_tx_pcs_bonding_dft_en (hssi_8g_tx_pcs_bonding_dft_en),
+ .hssi_8g_tx_pcs_bonding_dft_val (hssi_8g_tx_pcs_bonding_dft_val),
+ .hssi_8g_tx_pcs_bypass_pipeline_reg (hssi_8g_tx_pcs_bypass_pipeline_reg),
+ .hssi_8g_tx_pcs_byte_serializer (hssi_8g_tx_pcs_byte_serializer),
+ .hssi_8g_tx_pcs_clock_gate_bs_enc (hssi_8g_tx_pcs_clock_gate_bs_enc),
+ .hssi_8g_tx_pcs_clock_gate_dw_fifowr (hssi_8g_tx_pcs_clock_gate_dw_fifowr),
+ .hssi_8g_tx_pcs_clock_gate_fiford (hssi_8g_tx_pcs_clock_gate_fiford),
+ .hssi_8g_tx_pcs_clock_gate_sw_fifowr (hssi_8g_tx_pcs_clock_gate_sw_fifowr),
+ .hssi_8g_tx_pcs_clock_observation_in_pld_core (hssi_8g_tx_pcs_clock_observation_in_pld_core),
+ .hssi_8g_tx_pcs_data_selection_8b10b_encoder_input (hssi_8g_tx_pcs_data_selection_8b10b_encoder_input),
+ .hssi_8g_tx_pcs_dynamic_clk_switch (hssi_8g_tx_pcs_dynamic_clk_switch),
+ .hssi_8g_tx_pcs_eightb_tenb_disp_ctrl (hssi_8g_tx_pcs_eightb_tenb_disp_ctrl),
+ .hssi_8g_tx_pcs_eightb_tenb_encoder (hssi_8g_tx_pcs_eightb_tenb_encoder),
+ .hssi_8g_tx_pcs_force_echar (hssi_8g_tx_pcs_force_echar),
+ .hssi_8g_tx_pcs_force_kchar (hssi_8g_tx_pcs_force_kchar),
+ .hssi_8g_tx_pcs_gen3_tx_clk_sel (hssi_8g_tx_pcs_gen3_tx_clk_sel),
+ .hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel (hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel),
+ .hssi_8g_tx_pcs_hip_mode (hssi_8g_tx_pcs_hip_mode),
+ .hssi_8g_tx_pcs_pcs_bypass (hssi_8g_tx_pcs_pcs_bypass),
+ .hssi_8g_tx_pcs_phase_comp_rdptr (hssi_8g_tx_pcs_phase_comp_rdptr),
+ .hssi_8g_tx_pcs_phase_compensation_fifo (hssi_8g_tx_pcs_phase_compensation_fifo),
+ .hssi_8g_tx_pcs_phfifo_write_clk_sel (hssi_8g_tx_pcs_phfifo_write_clk_sel),
+ .hssi_8g_tx_pcs_pma_dw (hssi_8g_tx_pcs_pma_dw),
+ .hssi_8g_tx_pcs_refclk_b_clk_sel (hssi_8g_tx_pcs_refclk_b_clk_sel),
+ .hssi_8g_tx_pcs_revloop_back_rm (hssi_8g_tx_pcs_revloop_back_rm),
+ .hssi_8g_tx_pcs_symbol_swap (hssi_8g_tx_pcs_symbol_swap),
+ .hssi_8g_tx_pcs_tx_bitslip (hssi_8g_tx_pcs_tx_bitslip),
+ .hssi_8g_tx_pcs_tx_compliance_controlled_disparity (hssi_8g_tx_pcs_tx_compliance_controlled_disparity),
+ .hssi_8g_tx_pcs_tx_fast_pld_reg (hssi_8g_tx_pcs_tx_fast_pld_reg),
+ .hssi_8g_tx_pcs_txclk_freerun (hssi_8g_tx_pcs_txclk_freerun),
+ .hssi_8g_tx_pcs_txpcs_urst (hssi_8g_tx_pcs_txpcs_urst),
+ // parameters for twentynm_hssi_common_pcs_pma_interface
+ .hssi_common_pcs_pma_interface_asn_clk_enable (hssi_common_pcs_pma_interface_asn_clk_enable),
+ .hssi_common_pcs_pma_interface_asn_enable (hssi_common_pcs_pma_interface_asn_enable),
+ .hssi_common_pcs_pma_interface_block_sel (hssi_common_pcs_pma_interface_block_sel),
+ .hssi_common_pcs_pma_interface_bypass_early_eios (hssi_common_pcs_pma_interface_bypass_early_eios),
+ .hssi_common_pcs_pma_interface_bypass_pcie_switch (hssi_common_pcs_pma_interface_bypass_pcie_switch),
+ .hssi_common_pcs_pma_interface_bypass_pma_ltr (hssi_common_pcs_pma_interface_bypass_pma_ltr),
+ .hssi_common_pcs_pma_interface_bypass_pma_sw_done (lcl_hssi_common_pcs_pma_interface_bypass_pma_sw_done),
+ .hssi_common_pcs_pma_interface_bypass_ppm_lock (hssi_common_pcs_pma_interface_bypass_ppm_lock),
+ .hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp (hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp),
+ .hssi_common_pcs_pma_interface_bypass_txdetectrx (hssi_common_pcs_pma_interface_bypass_txdetectrx),
+ .hssi_common_pcs_pma_interface_cdr_control (hssi_common_pcs_pma_interface_cdr_control),
+ .hssi_common_pcs_pma_interface_cid_enable (hssi_common_pcs_pma_interface_cid_enable),
+ .hssi_common_pcs_pma_interface_data_mask_count (hssi_common_pcs_pma_interface_data_mask_count),
+ .hssi_common_pcs_pma_interface_data_mask_count_multi (hssi_common_pcs_pma_interface_data_mask_count_multi),
+ .hssi_common_pcs_pma_interface_dft_observation_clock_selection (hssi_common_pcs_pma_interface_dft_observation_clock_selection),
+ .hssi_common_pcs_pma_interface_early_eios_counter (hssi_common_pcs_pma_interface_early_eios_counter),
+ .hssi_common_pcs_pma_interface_force_freqdet (hssi_common_pcs_pma_interface_force_freqdet),
+ .hssi_common_pcs_pma_interface_free_run_clk_enable (hssi_common_pcs_pma_interface_free_run_clk_enable),
+ .hssi_common_pcs_pma_interface_ignore_sigdet_g23 (hssi_common_pcs_pma_interface_ignore_sigdet_g23),
+ .hssi_common_pcs_pma_interface_pc_en_counter (hssi_common_pcs_pma_interface_pc_en_counter),
+ .hssi_common_pcs_pma_interface_pc_rst_counter (hssi_common_pcs_pma_interface_pc_rst_counter),
+ .hssi_common_pcs_pma_interface_pcie_hip_mode (hssi_common_pcs_pma_interface_pcie_hip_mode),
+ .hssi_common_pcs_pma_interface_ph_fifo_reg_mode (hssi_common_pcs_pma_interface_ph_fifo_reg_mode),
+ .hssi_common_pcs_pma_interface_phfifo_flush_wait (hssi_common_pcs_pma_interface_phfifo_flush_wait),
+ .hssi_common_pcs_pma_interface_pipe_if_g3pcs (hssi_common_pcs_pma_interface_pipe_if_g3pcs),
+ .hssi_common_pcs_pma_interface_pma_done_counter (hssi_common_pcs_pma_interface_pma_done_counter),
+ .hssi_common_pcs_pma_interface_pma_if_dft_en (hssi_common_pcs_pma_interface_pma_if_dft_en),
+ .hssi_common_pcs_pma_interface_pma_if_dft_val (hssi_common_pcs_pma_interface_pma_if_dft_val),
+ .hssi_common_pcs_pma_interface_ppm_cnt_rst (hssi_common_pcs_pma_interface_ppm_cnt_rst),
+ .hssi_common_pcs_pma_interface_ppm_deassert_early (hssi_common_pcs_pma_interface_ppm_deassert_early),
+ .hssi_common_pcs_pma_interface_ppm_gen1_2_cnt (hssi_common_pcs_pma_interface_ppm_gen1_2_cnt),
+ .hssi_common_pcs_pma_interface_ppm_post_eidle_delay (hssi_common_pcs_pma_interface_ppm_post_eidle_delay),
+ .hssi_common_pcs_pma_interface_ppmsel (hssi_common_pcs_pma_interface_ppmsel),
+ .hssi_common_pcs_pma_interface_rxvalid_mask (hssi_common_pcs_pma_interface_rxvalid_mask),
+ .hssi_common_pcs_pma_interface_sigdet_wait_counter (hssi_common_pcs_pma_interface_sigdet_wait_counter),
+ .hssi_common_pcs_pma_interface_sigdet_wait_counter_multi (hssi_common_pcs_pma_interface_sigdet_wait_counter_multi),
+ .hssi_common_pcs_pma_interface_sim_mode (hssi_common_pcs_pma_interface_sim_mode),
+ .hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en (hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en),
+ .hssi_common_pcs_pma_interface_testout_sel (hssi_common_pcs_pma_interface_testout_sel),
+ .hssi_common_pcs_pma_interface_wait_clk_on_off_timer (hssi_common_pcs_pma_interface_wait_clk_on_off_timer),
+ .hssi_common_pcs_pma_interface_wait_pipe_synchronizing (hssi_common_pcs_pma_interface_wait_pipe_synchronizing),
+ .hssi_common_pcs_pma_interface_wait_send_syncp_fbkp (hssi_common_pcs_pma_interface_wait_send_syncp_fbkp),
+ .hssi_common_pcs_pma_interface_ppm_det_buckets(hssi_common_pcs_pma_interface_ppm_det_buckets),
+ // parameters for twentynm_hssi_common_pld_pcs_interface
+ .hssi_common_pld_pcs_interface_dft_clk_out_en (hssi_common_pld_pcs_interface_dft_clk_out_en),
+ .hssi_common_pld_pcs_interface_dft_clk_out_sel (hssi_common_pld_pcs_interface_dft_clk_out_sel),
+ .hssi_common_pld_pcs_interface_hrdrstctrl_en (hssi_common_pld_pcs_interface_hrdrstctrl_en),
+ .hssi_common_pld_pcs_interface_pcs_testbus_block_sel (hssi_common_pld_pcs_interface_pcs_testbus_block_sel),
+ // parameters for twentynm_hssi_fifo_rx_pcs
+ .hssi_fifo_rx_pcs_double_read_mode (hssi_fifo_rx_pcs_double_read_mode),
+ // parameters for twentynm_hssi_fifo_tx_pcs
+ .hssi_fifo_tx_pcs_double_write_mode (hssi_fifo_tx_pcs_double_write_mode),
+ // parameters for twentynm_hssi_gen3_rx_pcs
+ .hssi_gen3_rx_pcs_block_sync (hssi_gen3_rx_pcs_block_sync),
+ .hssi_gen3_rx_pcs_block_sync_sm (hssi_gen3_rx_pcs_block_sync_sm),
+ .hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn (hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn),
+ .hssi_gen3_rx_pcs_lpbk_force (hssi_gen3_rx_pcs_lpbk_force),
+ .hssi_gen3_rx_pcs_mode (hssi_gen3_rx_pcs_mode),
+ .hssi_gen3_rx_pcs_rate_match_fifo (hssi_gen3_rx_pcs_rate_match_fifo),
+ .hssi_gen3_rx_pcs_rate_match_fifo_latency (hssi_gen3_rx_pcs_rate_match_fifo_latency),
+ .hssi_gen3_rx_pcs_reverse_lpbk (hssi_gen3_rx_pcs_reverse_lpbk),
+ .hssi_gen3_rx_pcs_rx_b4gb_par_lpbk (hssi_gen3_rx_pcs_rx_b4gb_par_lpbk),
+ .hssi_gen3_rx_pcs_rx_force_balign (hssi_gen3_rx_pcs_rx_force_balign),
+ .hssi_gen3_rx_pcs_rx_ins_del_one_skip (hssi_gen3_rx_pcs_rx_ins_del_one_skip),
+ .hssi_gen3_rx_pcs_rx_num_fixed_pat (hssi_gen3_rx_pcs_rx_num_fixed_pat),
+ .hssi_gen3_rx_pcs_rx_test_out_sel (hssi_gen3_rx_pcs_rx_test_out_sel),
+ // parameters for twentynm_hssi_gen3_tx_pcs
+ .hssi_gen3_tx_pcs_mode (hssi_gen3_tx_pcs_mode),
+ .hssi_gen3_tx_pcs_reverse_lpbk (hssi_gen3_tx_pcs_reverse_lpbk),
+ .hssi_gen3_tx_pcs_tx_bitslip (hssi_gen3_tx_pcs_tx_bitslip),
+ .hssi_gen3_tx_pcs_tx_gbox_byp (hssi_gen3_tx_pcs_tx_gbox_byp),
+ // parameters for twentynm_hssi_krfec_rx_pcs
+ .hssi_krfec_rx_pcs_blksync_cor_en (hssi_krfec_rx_pcs_blksync_cor_en),
+ .hssi_krfec_rx_pcs_bypass_gb (hssi_krfec_rx_pcs_bypass_gb),
+ .hssi_krfec_rx_pcs_clr_ctrl (hssi_krfec_rx_pcs_clr_ctrl),
+ .hssi_krfec_rx_pcs_ctrl_bit_reverse (hssi_krfec_rx_pcs_ctrl_bit_reverse),
+ .hssi_krfec_rx_pcs_data_bit_reverse (hssi_krfec_rx_pcs_data_bit_reverse),
+ .hssi_krfec_rx_pcs_dv_start (hssi_krfec_rx_pcs_dv_start),
+ .hssi_krfec_rx_pcs_err_mark_type (hssi_krfec_rx_pcs_err_mark_type),
+ .hssi_krfec_rx_pcs_error_marking_en (hssi_krfec_rx_pcs_error_marking_en),
+ .hssi_krfec_rx_pcs_low_latency_en (hssi_krfec_rx_pcs_low_latency_en),
+ .hssi_krfec_rx_pcs_lpbk_mode (hssi_krfec_rx_pcs_lpbk_mode),
+ .hssi_krfec_rx_pcs_parity_invalid_enum (hssi_krfec_rx_pcs_parity_invalid_enum),
+ .hssi_krfec_rx_pcs_parity_valid_num (hssi_krfec_rx_pcs_parity_valid_num),
+ .hssi_krfec_rx_pcs_pipeln_blksync (hssi_krfec_rx_pcs_pipeln_blksync),
+ .hssi_krfec_rx_pcs_pipeln_descrm (hssi_krfec_rx_pcs_pipeln_descrm),
+ .hssi_krfec_rx_pcs_pipeln_errcorrect (hssi_krfec_rx_pcs_pipeln_errcorrect),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_ind (hssi_krfec_rx_pcs_pipeln_errtrap_ind),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_lfsr (hssi_krfec_rx_pcs_pipeln_errtrap_lfsr),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_loc (hssi_krfec_rx_pcs_pipeln_errtrap_loc),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_pat (hssi_krfec_rx_pcs_pipeln_errtrap_pat),
+ .hssi_krfec_rx_pcs_pipeln_gearbox (hssi_krfec_rx_pcs_pipeln_gearbox),
+ .hssi_krfec_rx_pcs_pipeln_syndrm (hssi_krfec_rx_pcs_pipeln_syndrm),
+ .hssi_krfec_rx_pcs_pipeln_trans_dec (hssi_krfec_rx_pcs_pipeln_trans_dec),
+ .hssi_krfec_rx_pcs_receive_order (hssi_krfec_rx_pcs_receive_order),
+ .hssi_krfec_rx_pcs_rx_testbus_sel (hssi_krfec_rx_pcs_rx_testbus_sel),
+ .hssi_krfec_rx_pcs_signal_ok_en (hssi_krfec_rx_pcs_signal_ok_en),
+ // parameters for twentynm_hssi_krfec_tx_pcs
+ .hssi_krfec_tx_pcs_burst_err (hssi_krfec_tx_pcs_burst_err),
+ .hssi_krfec_tx_pcs_burst_err_len (hssi_krfec_tx_pcs_burst_err_len),
+ .hssi_krfec_tx_pcs_ctrl_bit_reverse (hssi_krfec_tx_pcs_ctrl_bit_reverse),
+ .hssi_krfec_tx_pcs_data_bit_reverse (hssi_krfec_tx_pcs_data_bit_reverse),
+ .hssi_krfec_tx_pcs_enc_frame_query (hssi_krfec_tx_pcs_enc_frame_query),
+ .hssi_krfec_tx_pcs_low_latency_en (hssi_krfec_tx_pcs_low_latency_en),
+ .hssi_krfec_tx_pcs_pipeln_encoder (hssi_krfec_tx_pcs_pipeln_encoder),
+ .hssi_krfec_tx_pcs_pipeln_scrambler (hssi_krfec_tx_pcs_pipeln_scrambler),
+ .hssi_krfec_tx_pcs_transcode_err (hssi_krfec_tx_pcs_transcode_err),
+ .hssi_krfec_tx_pcs_transmit_order (hssi_krfec_tx_pcs_transmit_order),
+ .hssi_krfec_tx_pcs_tx_testbus_sel (hssi_krfec_tx_pcs_tx_testbus_sel),
+ // parameters for twentynm_hssi_pipe_gen1_2
+ .hssi_pipe_gen1_2_elec_idle_delay_val (hssi_pipe_gen1_2_elec_idle_delay_val),
+ .hssi_pipe_gen1_2_error_replace_pad (hssi_pipe_gen1_2_error_replace_pad),
+ .hssi_pipe_gen1_2_hip_mode (hssi_pipe_gen1_2_hip_mode),
+ .hssi_pipe_gen1_2_ind_error_reporting (hssi_pipe_gen1_2_ind_error_reporting),
+ .hssi_pipe_gen1_2_phystatus_delay_val (hssi_pipe_gen1_2_phystatus_delay_val),
+ .hssi_pipe_gen1_2_phystatus_rst_toggle (hssi_pipe_gen1_2_phystatus_rst_toggle),
+ .hssi_pipe_gen1_2_pipe_byte_de_serializer_en (hssi_pipe_gen1_2_pipe_byte_de_serializer_en),
+ .hssi_pipe_gen1_2_rx_pipe_enable (hssi_pipe_gen1_2_rx_pipe_enable),
+ .hssi_pipe_gen1_2_rxdetect_bypass (hssi_pipe_gen1_2_rxdetect_bypass),
+ .hssi_pipe_gen1_2_tx_pipe_enable (hssi_pipe_gen1_2_tx_pipe_enable),
+ .hssi_pipe_gen1_2_txswing (hssi_pipe_gen1_2_txswing),
+ // parameters for twentynm_hssi_pipe_gen3
+ .hssi_pipe_gen3_bypass_rx_detection_enable (hssi_pipe_gen3_bypass_rx_detection_enable),
+ .hssi_pipe_gen3_bypass_rx_preset (hssi_pipe_gen3_bypass_rx_preset),
+ .hssi_pipe_gen3_bypass_rx_preset_enable (hssi_pipe_gen3_bypass_rx_preset_enable),
+ .hssi_pipe_gen3_bypass_tx_coefficent (hssi_pipe_gen3_bypass_tx_coefficent),
+ .hssi_pipe_gen3_bypass_tx_coefficent_enable (hssi_pipe_gen3_bypass_tx_coefficent_enable),
+ .hssi_pipe_gen3_elecidle_delay_g3 (hssi_pipe_gen3_elecidle_delay_g3),
+ .hssi_pipe_gen3_ind_error_reporting (hssi_pipe_gen3_ind_error_reporting),
+ .hssi_pipe_gen3_mode (hssi_pipe_gen3_mode),
+ .hssi_pipe_gen3_phy_status_delay_g12 (hssi_pipe_gen3_phy_status_delay_g12),
+ .hssi_pipe_gen3_phy_status_delay_g3 (hssi_pipe_gen3_phy_status_delay_g3),
+ .hssi_pipe_gen3_phystatus_rst_toggle_g12 (hssi_pipe_gen3_phystatus_rst_toggle_g12),
+ .hssi_pipe_gen3_phystatus_rst_toggle_g3 (hssi_pipe_gen3_phystatus_rst_toggle_g3),
+ .hssi_pipe_gen3_rate_match_pad_insertion (hssi_pipe_gen3_rate_match_pad_insertion),
+ .hssi_pipe_gen3_test_out_sel (hssi_pipe_gen3_test_out_sel),
+ // parameters for twentynm_hssi_rx_pcs_pma_interface
+ .hssi_rx_pcs_pma_interface_block_sel (hssi_rx_pcs_pma_interface_block_sel),
+ .hssi_rx_pcs_pma_interface_channel_operation_mode (hssi_rx_pcs_pma_interface_channel_operation_mode),
+ .hssi_rx_pcs_pma_interface_clkslip_sel (hssi_rx_pcs_pma_interface_clkslip_sel),
+ .hssi_rx_pcs_pma_interface_lpbk_en (hssi_rx_pcs_pma_interface_lpbk_en),
+ .hssi_rx_pcs_pma_interface_master_clk_sel (hssi_rx_pcs_pma_interface_master_clk_sel),
+ .hssi_rx_pcs_pma_interface_pldif_datawidth_mode (hssi_rx_pcs_pma_interface_pldif_datawidth_mode),
+ .hssi_rx_pcs_pma_interface_pma_dw_rx (hssi_rx_pcs_pma_interface_pma_dw_rx),
+ .hssi_rx_pcs_pma_interface_pma_if_dft_en (hssi_rx_pcs_pma_interface_pma_if_dft_en),
+ .hssi_rx_pcs_pma_interface_pma_if_dft_val (hssi_rx_pcs_pma_interface_pma_if_dft_val),
+ .hssi_rx_pcs_pma_interface_prbs9_dwidth (hssi_rx_pcs_pma_interface_prbs9_dwidth),
+ .hssi_rx_pcs_pma_interface_prbs_clken (hssi_rx_pcs_pma_interface_prbs_clken),
+ .hssi_rx_pcs_pma_interface_prbs_ver (hssi_rx_pcs_pma_interface_prbs_ver),
+ .hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion (hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion),
+ .hssi_rx_pcs_pma_interface_rx_lpbk_en (hssi_rx_pcs_pma_interface_rx_lpbk_en),
+ .hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok (hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok),
+ .hssi_rx_pcs_pma_interface_rx_prbs_mask (hssi_rx_pcs_pma_interface_rx_prbs_mask),
+ .hssi_rx_pcs_pma_interface_rx_prbs_mode (hssi_rx_pcs_pma_interface_rx_prbs_mode),
+ .hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel (hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel),
+ .hssi_rx_pcs_pma_interface_rx_static_polarity_inversion (hssi_rx_pcs_pma_interface_rx_static_polarity_inversion),
+ .hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en (hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en),
+ // parameters for twentynm_hssi_rx_pld_pcs_interface
+ .hssi_rx_pld_pcs_interface_pcs_rx_block_sel (hssi_rx_pld_pcs_interface_pcs_rx_block_sel),
+ .hssi_rx_pld_pcs_interface_pcs_rx_clk_sel (hssi_rx_pld_pcs_interface_pcs_rx_clk_sel),
+ .hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en (hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en),
+ .hssi_rx_pld_pcs_interface_pcs_rx_output_sel (hssi_rx_pld_pcs_interface_pcs_rx_output_sel),
+ .hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel (hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel),
+ // parameters for twentynm_hssi_tx_pcs_pma_interface
+ .hssi_tx_pcs_pma_interface_bypass_pma_txelecidle (hssi_tx_pcs_pma_interface_bypass_pma_txelecidle),
+ .hssi_tx_pcs_pma_interface_channel_operation_mode (hssi_tx_pcs_pma_interface_channel_operation_mode),
+ .hssi_tx_pcs_pma_interface_lpbk_en (hssi_tx_pcs_pma_interface_lpbk_en),
+ .hssi_tx_pcs_pma_interface_master_clk_sel (hssi_tx_pcs_pma_interface_master_clk_sel),
+ .hssi_tx_pcs_pma_interface_pldif_datawidth_mode (hssi_tx_pcs_pma_interface_pldif_datawidth_mode),
+ .hssi_tx_pcs_pma_interface_pma_dw_tx (hssi_tx_pcs_pma_interface_pma_dw_tx),
+ .hssi_tx_pcs_pma_interface_pmagate_en (hssi_tx_pcs_pma_interface_pmagate_en),
+ .hssi_tx_pcs_pma_interface_prbs9_dwidth (hssi_tx_pcs_pma_interface_prbs9_dwidth),
+ .hssi_tx_pcs_pma_interface_prbs_clken (hssi_tx_pcs_pma_interface_prbs_clken),
+ .hssi_tx_pcs_pma_interface_prbs_gen_pat (hssi_tx_pcs_pma_interface_prbs_gen_pat),
+ .hssi_tx_pcs_pma_interface_sq_wave_num (hssi_tx_pcs_pma_interface_sq_wave_num),
+ .hssi_tx_pcs_pma_interface_sqwgen_clken (hssi_tx_pcs_pma_interface_sqwgen_clken),
+ .hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion (hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion),
+ .hssi_tx_pcs_pma_interface_tx_pma_data_sel (hssi_tx_pcs_pma_interface_tx_pma_data_sel),
+ .hssi_tx_pcs_pma_interface_tx_static_polarity_inversion (hssi_tx_pcs_pma_interface_tx_static_polarity_inversion),
+ .hssi_tx_pcs_pma_interface_pma_if_dft_en (hssi_tx_pcs_pma_interface_pma_if_dft_en),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock (hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value (hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock (hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock),
+ .hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period (hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period),
+ .hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable (hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh (hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable (hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window (hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size (hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel (hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin (hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value (hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value),
+ .hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control (hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control),
+ .hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control (hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control),
+ .hssi_tx_pcs_pma_interface_uhsif_enable (hssi_tx_pcs_pma_interface_uhsif_enable),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock (hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock (hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value (hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value (hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value (hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value (hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value),
+ // parameters for twentynm_hssi_tx_pld_pcs_interface
+ .hssi_tx_pld_pcs_interface_hd_10g_advanced_user_mode_tx (hssi_tx_pld_pcs_interface_hd_10g_advanced_user_mode_tx),
+ .hssi_rx_pld_pcs_interface_hd_10g_advanced_user_mode_rx (hssi_rx_pld_pcs_interface_hd_10g_advanced_user_mode_rx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_transparent_pcs_rx (hssi_rx_pld_pcs_interface_hd_chnl_transparent_pcs_rx),
+ .hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel (hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel),
+ .hssi_tx_pld_pcs_interface_pcs_tx_clk_source (hssi_tx_pld_pcs_interface_pcs_tx_clk_source),
+ .hssi_tx_pld_pcs_interface_pcs_tx_data_source (hssi_tx_pld_pcs_interface_pcs_tx_data_source),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en (hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel (hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl (hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel (hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en (hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl (hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl),
+ .hssi_tx_pld_pcs_interface_pcs_tx_output_sel (hssi_tx_pld_pcs_interface_pcs_tx_output_sel),
+ .hssi_rx_pld_pcs_interface_hd_10g_lpbk_en (hssi_rx_pld_pcs_interface_hd_10g_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_chnl_frequency_rules_en (hssi_rx_pld_pcs_interface_hd_chnl_frequency_rules_en),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pma_tx_clk_hz (hssi_tx_pld_pcs_interface_hd_chnl_pma_tx_clk_hz),
+ .hssi_tx_pld_pcs_interface_hd_chnl_shared_fifo_width_tx (hssi_tx_pld_pcs_interface_hd_chnl_shared_fifo_width_tx),
+ .hssi_rx_pld_pcs_interface_hd_10g_pma_dw_rx (hssi_rx_pld_pcs_interface_hd_10g_pma_dw_rx),
+ .hssi_tx_pld_pcs_interface_hd_fifo_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_fifo_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_8g_lpbk_en (hssi_rx_pld_pcs_interface_hd_8g_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_chnl_func_mode (hssi_rx_pld_pcs_interface_hd_chnl_func_mode),
+ .hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx (hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx),
+ .hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx (hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx),
+ .hssi_rx_pld_pcs_interface_hd_pldif_hrdrstctl_en (hssi_rx_pld_pcs_interface_hd_pldif_hrdrstctl_en),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_pmaif_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en (hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en),
+ .hssi_tx_pld_pcs_interface_hd_8g_fifo_mode_tx (hssi_tx_pld_pcs_interface_hd_8g_fifo_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en (hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_lpbk_en (hssi_tx_pld_pcs_interface_hd_pmaif_lpbk_en),
+ .hssi_tx_pld_pcs_interface_hd_chnl_frequency_rules_en (hssi_tx_pld_pcs_interface_hd_chnl_frequency_rules_en),
+ .hssi_tx_pld_pcs_interface_hd_chnl_lpbk_en (hssi_tx_pld_pcs_interface_hd_chnl_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_sim_mode (hssi_rx_pld_pcs_interface_hd_pmaif_sim_mode),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pma_rx_clk_hz (hssi_rx_pld_pcs_interface_hd_chnl_pma_rx_clk_hz),
+ .hssi_rx_pld_pcs_interface_hd_fifo_shared_fifo_width_rx (hssi_rx_pld_pcs_interface_hd_fifo_shared_fifo_width_rx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_chnl_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_8g_pma_dw_rx (hssi_rx_pld_pcs_interface_hd_8g_pma_dw_rx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pld_fifo_mode_rx (hssi_rx_pld_pcs_interface_hd_chnl_pld_fifo_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_func_mode (hssi_tx_pld_pcs_interface_hd_chnl_func_mode),
+ .hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode (hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode),
+ .hssi_rx_pld_pcs_interface_hd_chnl_shared_fifo_width_rx (hssi_rx_pld_pcs_interface_hd_chnl_shared_fifo_width_rx),
+ .hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_pma_dw_rx (hssi_rx_pld_pcs_interface_hd_pmaif_pma_dw_rx),
+ .hssi_tx_pld_pcs_interface_hd_10g_shared_fifo_width_tx (hssi_tx_pld_pcs_interface_hd_10g_shared_fifo_width_tx),
+ .hssi_tx_pld_pcs_interface_hd_10g_fifo_mode_tx (hssi_tx_pld_pcs_interface_hd_10g_fifo_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_pma_dw_tx (hssi_tx_pld_pcs_interface_hd_pmaif_pma_dw_tx),
+ .hssi_rx_pld_pcs_interface_hd_10g_test_bus_mode (hssi_rx_pld_pcs_interface_hd_10g_test_bus_mode),
+ .hssi_rx_pld_pcs_interface_hd_10g_low_latency_en_rx (hssi_rx_pld_pcs_interface_hd_10g_low_latency_en_rx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_clklow_clk_hz (hssi_rx_pld_pcs_interface_hd_chnl_clklow_clk_hz),
+ .hssi_tx_pld_pcs_interface_hd_pldif_hrdrstctl_en (hssi_tx_pld_pcs_interface_hd_pldif_hrdrstctl_en),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_lpbk_en (hssi_rx_pld_pcs_interface_hd_pmaif_lpbk_en),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_sim_mode (hssi_tx_pld_pcs_interface_hd_pmaif_sim_mode),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_uhsif_tx_clk_hz (hssi_tx_pld_pcs_interface_hd_chnl_pld_uhsif_tx_clk_hz),
+ .hssi_rx_pld_pcs_interface_hd_8g_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_8g_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_chnl_hrdrstctl_en (hssi_rx_pld_pcs_interface_hd_chnl_hrdrstctl_en),
+ .hssi_rx_pld_pcs_interface_hd_chnl_fref_clk_hz (hssi_rx_pld_pcs_interface_hd_chnl_fref_clk_hz),
+ .hssi_tx_pld_pcs_interface_hd_fifo_shared_fifo_width_tx (hssi_tx_pld_pcs_interface_hd_fifo_shared_fifo_width_tx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pma_dw_tx (hssi_tx_pld_pcs_interface_hd_chnl_pma_dw_tx),
+ .hssi_tx_pld_pcs_interface_hd_8g_hip_mode (hssi_tx_pld_pcs_interface_hd_8g_hip_mode),
+ .hssi_tx_pld_pcs_interface_hd_8g_lpbk_en (hssi_tx_pld_pcs_interface_hd_8g_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_chnl_low_latency_en_rx (hssi_rx_pld_pcs_interface_hd_chnl_low_latency_en_rx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_tx_clk_hz (hssi_tx_pld_pcs_interface_hd_chnl_pld_tx_clk_hz),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pld_rx_clk_hz (hssi_rx_pld_pcs_interface_hd_chnl_pld_rx_clk_hz),
+ .hssi_tx_pld_pcs_interface_hd_10g_lpbk_en (hssi_tx_pld_pcs_interface_hd_10g_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_8g_fifo_mode_rx (hssi_rx_pld_pcs_interface_hd_8g_fifo_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_10g_pma_dw_tx (hssi_tx_pld_pcs_interface_hd_10g_pma_dw_tx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pma_dw_rx (hssi_rx_pld_pcs_interface_hd_chnl_pma_dw_rx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_fifo_mode_tx (hssi_tx_pld_pcs_interface_hd_chnl_pld_fifo_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_hrdrstctl_en (hssi_tx_pld_pcs_interface_hd_chnl_hrdrstctl_en),
+ .hssi_rx_pld_pcs_interface_hd_10g_fifo_mode_rx (hssi_rx_pld_pcs_interface_hd_10g_fifo_mode_rx),
+ .hssi_rx_pld_pcs_interface_hd_8g_hip_mode (hssi_rx_pld_pcs_interface_hd_8g_hip_mode),
+ .hssi_tx_pld_pcs_interface_hd_chnl_low_latency_en_tx (hssi_tx_pld_pcs_interface_hd_chnl_low_latency_en_tx),
+ .hssi_rx_pld_pcs_interface_hd_10g_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_10g_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_chnl_hip_en (hssi_tx_pld_pcs_interface_hd_chnl_hip_en),
+ .hssi_rx_pld_pcs_interface_hd_fifo_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_fifo_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_8g_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_8g_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_8g_pma_dw_tx (hssi_tx_pld_pcs_interface_hd_8g_pma_dw_tx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_lpbk_en (hssi_rx_pld_pcs_interface_hd_chnl_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_pmaif_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_10g_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_10g_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_10g_shared_fifo_width_rx (hssi_rx_pld_pcs_interface_hd_10g_shared_fifo_width_rx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_chnl_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_10g_low_latency_en_tx (hssi_tx_pld_pcs_interface_hd_10g_low_latency_en_tx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_hip_en (hssi_rx_pld_pcs_interface_hd_chnl_hip_en),
+
+ // prot_mode
+ .cdr_pll_prot_mode (cdr_pll_prot_mode),
+ .cdr_pll_tx_pll_prot_mode (cdr_pll_tx_pll_prot_mode),
+ .pma_adapt_prot_mode (pma_adapt_prot_mode),
+ .pma_rx_odi_prot_mode (pma_rx_odi_prot_mode),
+ .pma_rx_buf_prot_mode (pma_rx_buf_prot_mode),
+ .pma_rx_buf_xrx_path_prot_mode (pma_rx_buf_xrx_path_prot_mode),
+ .pma_rx_dfe_prot_mode (pma_rx_dfe_prot_mode),
+ .pma_rx_deser_prot_mode (pma_rx_deser_prot_mode),
+ .pma_rx_sd_prot_mode (pma_rx_sd_prot_mode),
+ .pma_tx_buf_prot_mode (pma_tx_buf_prot_mode),
+ .pma_tx_buf_xtx_path_prot_mode (pma_tx_buf_xtx_path_prot_mode),
+ .pma_tx_ser_prot_mode (pma_tx_ser_prot_mode),
+ .pma_cgb_prot_mode (pma_cgb_prot_mode),
+ .hssi_rx_pld_pcs_interface_hd_8g_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_8g_prot_mode_rx),
+ .hssi_rx_pld_pcs_interface_hd_g3_prot_mode (hssi_rx_pld_pcs_interface_hd_g3_prot_mode),
+ .hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_fifo_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_fifo_prot_mode_tx),
+ .hssi_rx_pld_pcs_interface_hd_pldif_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_pldif_prot_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx),
+ .hssi_rx_pld_pcs_interface_hd_fifo_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_fifo_prot_mode_rx),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_pmaif_prot_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_10g_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_10g_prot_mode_tx),
+ .hssi_tx_pcs_pma_interface_prot_mode_tx (hssi_tx_pcs_pma_interface_prot_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_pldif_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_pldif_prot_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_chnl_prot_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_pmaif_prot_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_g3_prot_mode (hssi_tx_pld_pcs_interface_hd_g3_prot_mode),
+ .hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx),
+ .hssi_rx_pld_pcs_interface_hd_10g_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_10g_prot_mode_rx),
+ .hssi_10g_rx_pcs_prot_mode (hssi_10g_rx_pcs_prot_mode),
+ .hssi_10g_tx_pcs_prot_mode (hssi_10g_tx_pcs_prot_mode),
+ .hssi_8g_rx_pcs_prot_mode (hssi_8g_rx_pcs_prot_mode),
+ .hssi_8g_tx_pcs_prot_mode (hssi_8g_tx_pcs_prot_mode),
+ .hssi_common_pcs_pma_interface_prot_mode (hssi_common_pcs_pma_interface_prot_mode),
+ .hssi_fifo_rx_pcs_prot_mode (hssi_fifo_rx_pcs_prot_mode),
+ .hssi_fifo_tx_pcs_prot_mode (hssi_fifo_tx_pcs_prot_mode),
+ .hssi_krfec_rx_pcs_prot_mode (hssi_krfec_rx_pcs_prot_mode),
+ .hssi_krfec_tx_pcs_prot_mode (hssi_krfec_tx_pcs_prot_mode),
+ .hssi_pipe_gen1_2_prot_mode (hssi_pipe_gen1_2_prot_mode),
+ .hssi_rx_pcs_pma_interface_prot_mode_rx (hssi_rx_pcs_pma_interface_prot_mode_rx),
+ .hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx (hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx),
+ // datarate
+ .cdr_pll_datarate (cdr_pll_datarate),
+ .pma_adapt_datarate (pma_adapt_datarate),
+ .pma_rx_buf_datarate (pma_rx_buf_datarate),
+ .pma_rx_buf_xrx_path_datarate (pma_rx_buf_xrx_path_datarate),
+ .pma_rx_deser_datarate (pma_rx_deser_datarate),
+ .pma_rx_dfe_datarate (pma_rx_dfe_datarate),
+ .pma_rx_odi_datarate (pma_rx_odi_datarate),
+ .pma_tx_buf_datarate (pma_tx_buf_datarate),
+ .pma_tx_buf_xtx_path_datarate(pma_tx_buf_xtx_path_datarate),
+ .pma_cgb_datarate (pma_cgb_datarate),
+ // sup_mode
+ .cdr_pll_sup_mode (cdr_pll_sup_mode),
+ .hssi_8g_rx_pcs_sup_mode (hssi_8g_rx_pcs_sup_mode),
+ .hssi_8g_tx_pcs_sup_mode (hssi_8g_tx_pcs_sup_mode),
+ .hssi_10g_rx_pcs_sup_mode (hssi_10g_rx_pcs_sup_mode),
+ .hssi_10g_tx_pcs_sup_mode (hssi_10g_tx_pcs_sup_mode),
+ .hssi_common_pcs_pma_interface_sup_mode (hssi_common_pcs_pma_interface_sup_mode),
+ .hssi_gen3_rx_pcs_sup_mode (hssi_gen3_rx_pcs_sup_mode),
+ .hssi_gen3_tx_pcs_sup_mode (hssi_gen3_tx_pcs_sup_mode),
+ .hssi_krfec_rx_pcs_sup_mode (hssi_krfec_rx_pcs_sup_mode),
+ .hssi_krfec_tx_pcs_sup_mode (hssi_krfec_tx_pcs_sup_mode),
+ .hssi_pipe_gen1_2_sup_mode (hssi_pipe_gen1_2_sup_mode),
+ .hssi_pipe_gen3_sup_mode (hssi_pipe_gen3_sup_mode),
+ .hssi_rx_pcs_pma_interface_sup_mode (hssi_rx_pcs_pma_interface_sup_mode),
+ .hssi_tx_pcs_pma_interface_sup_mode (hssi_tx_pcs_pma_interface_sup_mode),
+ .pma_adapt_sup_mode (pma_adapt_sup_mode),
+ .pma_cgb_sup_mode (pma_cgb_sup_mode),
+ .pma_rx_buf_sup_mode (pma_rx_buf_sup_mode),
+ .pma_rx_buf_xrx_path_sup_mode (pma_rx_buf_xrx_path_sup_mode),
+ .pma_rx_deser_sup_mode (pma_rx_deser_sup_mode),
+ .pma_rx_dfe_sup_mode (pma_rx_dfe_sup_mode),
+ .pma_rx_odi_sup_mode (pma_rx_odi_sup_mode),
+ .pma_rx_sd_sup_mode (pma_rx_sd_sup_mode),
+ .pma_tx_buf_sup_mode (pma_tx_buf_sup_mode),
+ .pma_tx_buf_xtx_path_sup_mode (pma_tx_buf_xtx_path_sup_mode),
+ .pma_tx_ser_sup_mode (pma_tx_ser_sup_mode)
+ ) twentynm_xcvr_native_inst (
+ // nf_pma ports
+ /*input [bonded_lanes - 1:0] */.in_clk_cdr_b (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clk_cdr_t (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clk_fpll_b (tx_serial_clk0[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clk_fpll_t (tx_serial_clk2[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clk_lc_b (tx_serial_clk1[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clk_lc_hs (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clk_lc_t (tx_serial_clk3[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clkb_cdr_b (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clkb_cdr_t (1'b0),
+`ifndef ALTERA_RESERVED_QIS
+ /*input [bonded_lanes - 1:0] */.in_clkb_fpll_b (~tx_serial_clk0[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clkb_fpll_t (~tx_serial_clk2[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clkb_lc_b (~tx_serial_clk1[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clkb_lc_t (~tx_serial_clk3[ig]),
+`else
+ /*input [bonded_lanes - 1:0] */.in_clkb_fpll_b (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clkb_fpll_t (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clkb_lc_b (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clkb_lc_t (1'b0),
+`endif
+ /*input [bonded_lanes - 1:0] */.in_clkb_lc_hs (1'b0),
+ /*input [bonded_lanes * 6 - 1 : 0] */.in_cpulse_x6_dn_bus (tx_bonding_clocks[ig*6+:6]),
+ /*input [bonded_lanes * 6 - 1 : 0] */.in_cpulse_x6_up_bus (tx_bonding_clocks1[ig*6+:6]),
+ /*input [bonded_lanes * 6 - 1 : 0] */.in_cpulse_xn_dn_bus (tx_bonding_clocks2[ig*6+:6]),
+ /*input [bonded_lanes * 6 - 1 : 0] */.in_cpulse_xn_up_bus (tx_bonding_clocks3[ig*6+:6]),
+`ifndef ALTERA_RESERVED_QIS
+ /*input [bonded_lanes - 1:0] */.in_rx_n (~rx_serial_data[ig]),
+`else
+ /*input [bonded_lanes - 1:0] */.in_rx_n (1'b0),
+`endif
+ /*input [bonded_lanes - 1:0] */.in_rx_p (rx_serial_data[ig]),
+ /*output [bonded_lanes - 1:0] */.out_tx_n (/*unused*/ ),
+ /*output [bonded_lanes - 1:0] */.out_tx_p (tx_serial_data[ig]),
+ /*input [bonded_lanes * 12 - 1 : 0] */.in_ref_iqclk ({7'd0,rx_cdr_refclk4,rx_cdr_refclk3,rx_cdr_refclk2,rx_cdr_refclk1,rx_cdr_refclk0}),
+
+ // nf_pcs ports
+ // HIP
+ /*input [bonded_lanes * 64 - 1 : 0] */.in_hip_tx_data (tx_hip_data [ig*64+:64] ),
+ /*output [bonded_lanes * 51 - 1 : 0] */.out_hip_rx_data (rx_hip_data [ig*51+:51] ),
+ /*output [bonded_lanes * 3 - 1 : 0] */.out_hip_clk_out ({hip_frefclk[ig],int_hip_fixedclk,int_hip_pipe_pclk}),
+ /*output [bonded_lanes * 8 - 1 : 0] */.out_hip_ctrl_out (hip_ctrl [ig*8+:8] ),
+
+
+ // Standard datapath inputs
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_a1a2_size (rx_std_wa_a1a2size [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_bitloc_rev_en (rx_std_bitrev_ena [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_byte_rev_en (rx_std_byterev_ena [ig] ),
+ /*input [bonded_lanes * 3 - 1 : 0] */.in_pld_8g_eidleinfersel (pipe_rx_eidleinfersel [ig*3+:3]),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_encdt (rx_std_wa_patternalign [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_g3_rx_pld_rst_n (int_in_pld_8g_g3_rx_pld_rst_n ),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_g3_tx_pld_rst_n (int_in_pld_8g_g3_tx_pld_rst_n ),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_rddisable_tx (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_rdenable_rx (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_refclk_dig2 (1'b0), //TODO
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_rxpolarity (pipe_rx_polarity [ig] ),
+ /*input [bonded_lanes * 5 - 1 : 0] */.in_pld_8g_tx_boundary_sel (tx_std_bitslipboundarysel[ig*5+:5]),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_wrdisable_rx (1'b0), // unused in Si
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_wrenable_tx (1'b0), // unused in Si
+
+ // Standard datapath outputs
+ /*output [bonded_lanes * 4 - 1 : 0] */.out_pld_8g_a1a2_k1k2_flag (/*TODO*/),
+
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_empty_rmf (rx_std_rmfifo_empty [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_empty_rx (rx_std_pcfifo_empty [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_empty_tx (tx_std_pcfifo_empty [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_full_rmf (rx_std_rmfifo_full [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_full_rx (rx_std_pcfifo_full [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_full_tx (tx_std_pcfifo_full [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_rxelecidle (pipe_rx_elecidle [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_signal_detect_out (rx_std_signaldetect [ig] ),
+ /*output [bonded_lanes * 5 - 1 : 0] */.out_pld_8g_wa_boundary (rx_std_bitslipboundarysel[ig*5+:5]),
+
+ // Enhanced datapath bonding
+ /*input [bonded_lanes * 5 - 1 : 0] */.in_bond_pcs10g_in_bot (bond_pcs10g_in_bot [ig] ),
+ /*input [bonded_lanes * 5 - 1 : 0] */.in_bond_pcs10g_in_top (bond_pcs10g_in_top [ig] ),
+ /*input [bonded_lanes * 13 - 1 : 0] */.in_bond_pcs8g_in_bot (bond_pcs8g_in_bot [ig] ),
+ /*input [bonded_lanes * 13 - 1 : 0] */.in_bond_pcs8g_in_top (bond_pcs8g_in_top [ig] ),
+ /*input [bonded_lanes * 12 - 1 : 0] */.in_bond_pmaif_in_bot (bond_pmaif_in_bot [ig] ),
+ /*input [bonded_lanes * 12 - 1 : 0] */.in_bond_pmaif_in_top (bond_pmaif_in_top [ig] ),
+
+ /*output [bonded_lanes * 5 - 1 : 0] */.out_bond_pcs10g_out_bot (bond_pcs10g_out_bot [ig] ),
+ /*output [bonded_lanes * 5 - 1 : 0] */.out_bond_pcs10g_out_top (bond_pcs10g_out_top [ig] ),
+ /*output [bonded_lanes * 13 - 1 : 0] */.out_bond_pcs8g_out_bot (bond_pcs8g_out_bot [ig] ),
+ /*output [bonded_lanes * 13 - 1 : 0] */.out_bond_pcs8g_out_top (bond_pcs8g_out_top [ig] ),
+ /*output [bonded_lanes * 12 - 1 : 0] */.out_bond_pmaif_out_bot (bond_pmaif_out_bot [ig] ),
+ /*output [bonded_lanes * 12 - 1 : 0] */.out_bond_pmaif_out_top (bond_pmaif_out_top [ig] ),
+
+ // Enhanced datapath inputs
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_krfec_rx_pld_rst_n (int_in_pld_10g_krfec_rx_pld_rst_n),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_krfec_tx_pld_rst_n (int_in_pld_10g_krfec_tx_pld_rst_n),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_rx_align_clr (rx_enh_fifo_align_clr [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_rx_clr_ber_count (rx_enh_highber_clr_cnt [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_krfec_rx_clr_errblk_cnt (rx_enh_clr_errblk_count [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_rx_rd_en (rx_enh_fifo_rd_en [ig] ),
+ /*input [bonded_lanes * 7 - 1 : 0] */.in_pld_10g_tx_bitslip (tx_enh_bitslip [ig*7+:7]),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_tx_burst_en (tx_enh_frame_burst_en [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_tx_data_valid (tx_enh_data_valid [ig] ),
+ /*input [bonded_lanes * 2 - 1 : 0] */.in_pld_10g_tx_diag_status (tx_enh_frame_diag_status [ig*2+:2]),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_tx_wordslip (1'b0), // engineering mode only
+ // Enhanced datapath outputs
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_align_val (rx_enh_fifo_align_val[ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_krfec_rx_blk_lock (rx_enh_blk_lock [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_crc32_err (rx_enh_crc32_err [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_data_valid (rx_enh_data_valid [ig]),
+ /*output [bonded_lanes * 2 - 1 : 0] */.out_pld_10g_krfec_rx_diag_data_status (rx_enh_frame_diag_status[ig*2+:2]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_empty (rx_enh_fifo_empty [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_fifo_del (rx_enh_fifo_del [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_fifo_insert (rx_enh_fifo_insert [ig]),
+ /*output [bonded_lanes * 5 - 1 : 0] */.out_pld_10g_rx_fifo_num (rx_enh_fifo_cnt [ig*5+:5]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_frame_lock (rx_enh_frame_lock [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_hi_ber (rx_enh_highber [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_oflw_err (rx_enh_fifo_full [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_pempty (rx_enh_fifo_pempty [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_pfull (rx_enh_fifo_pfull [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_krfec_rx_frame (rx_enh_frame [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_burst_en_exe (/*TODO*/),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_empty (tx_enh_fifo_empty [ig]),
+ /*output [bonded_lanes * 4 - 1 : 0] */.out_pld_10g_tx_fifo_num (tx_enh_fifo_cnt [ig*4+:4]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_krfec_tx_frame (tx_enh_frame [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_full (tx_enh_fifo_full [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_pempty (tx_enh_fifo_pempty [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_pfull (tx_enh_fifo_pfull [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_wordslip_exe (/*unused*/ ), // engineering mode only
+
+ // Common interface inputs
+ /*input [bonded_lanes - 1:0] */.in_pld_bitslip (rx_bitslip [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_polinv_rx (rx_polinv [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_polinv_tx (tx_polinv [ig]),
+
+
+ /*input [bonded_lanes * 2 - 1 : 0] */.in_pld_rate (int_pipe_rate ),
+ /*input [bonded_lanes * 10 - 1 : 0] */.in_pld_reserved_in (10'd0),
+ /*input [bonded_lanes - 1:0] */.in_pld_rx_clk (rx_coreclkin [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_rx_prbs_err_clr (int_rx_prbs_err_clr[ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_syncsm_en (1'b1),
+ /*input [bonded_lanes - 1:0] */.in_pld_tx_clk (tx_coreclkin [ig] ),
+ /*input [bonded_lanes * 18 - 1 : 0] */.in_pld_tx_control (tx_control [ig*18+:18] ),
+ /*input [bonded_lanes * 128 - 1 : 0] */.in_pld_tx_data (tx_parallel_data [ig*128+:128] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_txelecidle (tx_pma_elecidle [ig] ),
+ /*output [bonded_lanes * 20 - 1 : 0] */.out_pld_rx_control (rx_control [ig*20+:20] ),
+ /*output [bonded_lanes * 128 - 1 : 0] */.out_pld_rx_data (rx_parallel_data [ig*128+:128] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_rx_prbs_done (rx_prbs_done [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_rx_prbs_err (rx_prbs_err [ig] ),
+ // Ultra high-speed interface
+ /*input [bonded_lanes - 1:0] */.in_pld_uhsif_tx_clk (tx_uhsif_clk [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_uhsif_lock (tx_uhsif_lock [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_uhsif_tx_clk_out (tx_uhsif_clkout [ig] ),
+ // KRFEC
+ /*input [bonded_lanes - 1:0] */.in_pld_mem_krfec_atpg_rst_n (1'b1),
+ /*input [bonded_lanes - 1:0] */.in_pld_atpg_los_en_n (1'b1),
+ /*output [bonded_lanes - 1:0] */.out_pld_krfec_tx_alignment (/*unused*/), // engineering mode only
+ // Gen 3 PCIe datapath
+ /*input [bonded_lanes * 18 - 1 : 0] */.in_pld_g3_current_coeff (pipe_g3_txdeemph [ig*18+:18] ),
+ /*input [bonded_lanes * 3 - 1 : 0] */.in_pld_g3_current_rxpreset (pipe_g3_rxpresethint[ig*3+:3] ),
+
+
+ /*input [bonded_lanes - 1:0] */.in_pld_ltr (int_rx_set_locktoref [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_partial_reconfig (1'b1),
+ /*input [bonded_lanes - 1:0] */.in_pld_pcs_refclk_dig (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_adapt_start (rx_adapt_start [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_early_eios (1'b0),
+ /*input [bonded_lanes * 6 - 1 : 0] */.in_pld_pma_eye_monitor (/*TODO*/),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_ltd_b (~int_rx_set_locktodata [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_ppm_lock (1'b1), //TODO - Temporary until PPM detector enabled
+ /*input [bonded_lanes * 5 - 1 : 0] */.in_pld_pma_reserved_out ({~rx_adapt_reset[ig],4'd0}),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_rs_lpbk_b (~int_rx_seriallpbken [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_rx_qpi_pullup (~rx_pma_qpipulldn [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_rxpma_rstb (~rx_analogreset_to_pma[ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_tx_bonding_rstb (1'b0), // x1 bonding reset unused
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_tx_qpi_pulldn (~tx_pma_qpipulldn [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_tx_qpi_pullup (~tx_pma_qpipullup [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_txdetectrx (tx_pma_txdetectrx [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_txpma_rstb (~tx_analogreset_to_pma[ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_tx_bitslip (1'b0), // TODO - deprecated
+ /*input [bonded_lanes * 2 - 1 : 0] */.in_pld_pma_pcie_switch (2'd0),
+ /*input [bonded_lanes - 1:0] */.in_pld_pmaif_rxclkslip (rx_pma_clkslip [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pmaif_rx_pld_rst_n (int_in_pld_pmaif_rx_pld_rst_n),
+ /*input [bonded_lanes - 1:0] */.in_pld_pmaif_tx_pld_rst_n (int_in_pld_pmaif_tx_pld_rst_n),
+ /*input [bonded_lanes - 1:0] */.in_pma_hclk (pipe_hclk_in ),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_clklow (rx_clklow [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_fref (rx_fref [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pcs_rx_clk_out (rx_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pcs_tx_clk_out (tx_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_adapt_done (/*unused*/),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_clkdiv_rx_user (rx_pma_div_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_clkdiv_tx_user (tx_pma_div_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_clk_divtx_iqtxrx (tx_pma_iqtxrx_clkout [ig]), // Needed for cascading
+ /*output [bonded_lanes - 1:0] */.out_clk_divrx_iqtxrx (rx_pma_iqtxrx_clkout [ig]), // Needed for cascading
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_hclk (int_pipe_hclk_out ),
+
+ /*output [bonded_lanes * 2 - 1 : 0] */.out_pld_pma_pcie_sw_done (/*unused*/),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_pfdmode_lock (rx_is_lockedtoref [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_rx_clk_out (rx_pma_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_rx_detect_valid (/*TODO*/),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_rx_found (tx_pma_rxfound [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_rxpll_lock (rx_is_lockedtodata [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_signal_ok (/*TODO*/),
+ /*output [bonded_lanes * 8 - 1 : 0] */.out_pld_pma_testbus (/*unused*/),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_tx_clk_out (tx_pma_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pmaif_mask_tx_pll (/*unused*/),
+ /*output [bonded_lanes * 10 - 1 : 0] */.out_pld_reserved_out (/*unused*/),
+ /*output [bonded_lanes * 20 - 1 : 0] */.out_pld_test_data (pld_testbus_for_rate[ig*20+:20]),
+ // PCIe
+ /*input [bonded_lanes * 2 - 1 : 0] */.in_pcie_sw_done_master_in (int_pipe_sw_done ),
+ /*output [bonded_lanes * 2 - 1 : 0] */.out_pcie_sw_master (int_pipe_sw ),
+
+ // TODO
+ /*input [bonded_lanes * 3 - 1 : 0] */.in_i_rxpreset (3'd0),
+ /*input [bonded_lanes - 1:0] */.in_adapt_start (1'b0),
+
+
+
+ // nf_xcvr_avmm ports
+ // AVMM slave interface signals (user)
+ /*input wire [avmm_interfaces-1 :0] */.avmm_clk (avmm_clk [ig] ),
+ /*input wire [avmm_interfaces-1 :0] */.avmm_reset (avmm_reset [ig] ),
+ /*input wire [avmm_interfaces*32-1 :0] */.avmm_writedata (avmm_writedata [ig*8+:8] ),
+ /*input wire [avmm_interfaces*9-1 :0] */.avmm_address (avmm_address [ig*RCFG_ADDR_BITS+:9]), // Only lowest 9 bits drive hardware
+ /*input wire [avmm_interfaces-1 :0] */.avmm_write (avmm_write [ig] ),
+ /*input wire [avmm_interfaces-1 :0] */.avmm_read (avmm_read [ig] ),
+ /*output wire [avmm_interfaces*32-1 :0] */.avmm_readdata (avmm_readdata [ig*8+:8] ),
+ /*output wire [avmm_interfaces-1 :0] */.avmm_waitrequest (avmm_waitrequest [ig] ),
+ /*output wire [avmm_interfaces-1 :0] */.avmm_busy (avmm_busy [ig] ),
+ /*output wire [avmm_interfaces-1 :0] */.pld_cal_done (pld_cal_done [ig] ),
+ /*output wire [avmm_interfaces-1 :0] */.hip_cal_done (hip_cal_done [ig] ),
+
+// TO BE REMOVED
+ .out_hip_npor()
+ );
+
+
+
+end
+endgenerate
+
+endmodule // altera_xcvr_native_a10
+
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/arria10_hps_altera_xcvr_native_a10_221_sfv7jkq.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/arria10_hps_altera_xcvr_native_a10_221_sfv7jkq.sv
new file mode 100644
index 0000000000000000000000000000000000000000..f56b58147f093749f0bf3600ec03aef55c007f01
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/arria10_hps_altera_xcvr_native_a10_221_sfv7jkq.sv
@@ -0,0 +1,2691 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1 ps/1 ps
+
+
+
+module arria10_hps_altera_xcvr_native_a10_221_sfv7jkq
+ #(
+ //---------------------
+ // Common parameters
+ //---------------------
+ parameter device_revision = "20nm5es", // (20nm5es, 20nm5es2, 20nm4, 20nm3, 20nm4qor,20nm2, 20nm1)
+
+ parameter duplex_mode = "duplex", // (tx,rx,duplex)
+ parameter channels = 1, // legal values 1+
+
+ parameter enable_calibration = 1, // (0,1)
+ // 0 - Disable transceiver calibration
+ // 1 - Enable transceiver calibration
+
+ parameter enable_analog_resets = 1, // (0,1)
+ // 0 - Disable tx_analog and rx_analog reset input connections. Still allows soft register override
+ // 1 - Enable tx_analog and rx_analog reset input connections
+
+ parameter enable_reset_sequence = 1, // (0,1)
+ // 0 - Disable reset sequencing
+ // 1 - Enable reset sequencing
+
+ // TX PMA
+ parameter bonded_mode = "not_bonded", // (not_bonded,pma_only,pma_pcs) not_bonded-Disable bonding,
+ // pma_only - Enable PMA only bonding
+ // pma_pcs - Enable PMA and PCS bonding
+ parameter pcs_bonding_master = 0, // (0:channels-1), Specifies PCS bonding master
+ parameter plls = 1, // (1,2,3,4)
+ parameter number_physical_bonding_clocks = 1, // (1,2,3,4)
+ parameter cdr_refclk_cnt = 1, // (1,2,3,4,5)
+ parameter enable_hip = 0, // (0,1) 0 - Not PCIe HIP, 1 - PCIe HIP
+
+ //----------------------
+ // Reconfiguration options
+ //----------------------
+ parameter rcfg_enable = 0, // (0,1)
+ // 0 - Disable the AVMM reconfiguration interface.
+ // 1 - Enable the AVMM reconfiguration interface.
+
+ parameter rcfg_shared = 0, // (0,1)
+ // 0 - Present separate AVMM interface for each channel,
+ // 1 - Present shared AVMM interface for all channels using address decoding.
+ // Bits [n:10] of "reconfig_address" select the channel to address.
+ // Bit [9] selects between soft registers (1) and HSSI channel registers (0)
+ // Bits [8:0] of "reconfig_address" provide the register offset within soft or hard register space.
+
+ parameter rcfg_jtag_enable = 0, // (0,1)
+ // 0 - Disable embedded debug master
+ // 1 - Enable embedded JTAG master. Requires "rcfg_shared==1".
+
+ parameter rcfg_separate_avmm_busy = 0, // (0,1)
+ // 0 - AVMM busy is reflected on the waitrequest
+ // 1 - AVMM busy must be read from a soft CSR
+ // Atom parameters
+ parameter dbg_embedded_debug_enable = 0, // enables embedded debug blocks
+ parameter dbg_capability_reg_enable = 0, // enables capability registers to describe the debug endpoint
+ parameter dbg_user_identifier = 0, // user-assigned value to either define phy_ip or to link associated ip
+ parameter dbg_stat_soft_logic_enable = 0, // enables soft logic to read status signals through avmm
+ parameter dbg_ctrl_soft_logic_enable = 0, // enables soft logic to write control signals through avmm
+ parameter dbg_prbs_soft_logic_enable = 0, // enables soft logic for prbs err accumulation
+ parameter dbg_odi_soft_logic_enable = 0,
+
+ parameter rcfg_emb_strm_enable = 0, // (0,1)
+ // 0 - Disable embedded reconfiguration streamer
+ // 1 - Enable embedded reconfiguration streamer
+
+ parameter rcfg_profile_cnt = 2, //Number of configuration profiles for embedded reconfiguration streamer
+
+ // ADME Parameters
+ parameter adme_prot_mode = "basic_tx",
+ parameter adme_data_rate = "5000000000",
+
+ // Parameters for the PCIe DFE IP
+ parameter enable_pcie_dfe_ip = 0,
+ parameter sim_reduced_counters = 0,
+ parameter disable_continuous_dfe = 0,
+
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_hip_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_hrdrstctl_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_prot_mode_rx = "disabled_prot_mode_rx" ,//basic_10gpcs_krfec_rx basic_10gpcs_rx basic_8gpcs_rm_disable_rx basic_8gpcs_rm_enable_rx cpri_8b10b_rx disabled_prot_mode_rx fortyg_basekr_krfec_rx gige_1588_rx gige_rx interlaken_rx pcie_g1_capable_rx pcie_g2_capable_rx pcie_g3_capable_rx pcs_direct_rx prbs_rx prp_krfec_rx prp_rx sfis_rx teng_1588_basekr_krfec_rx teng_1588_baser_rx teng_basekr_krfec_rx teng_baser_rx teng_sdi_rx
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx = "individual_rx" ,//ctrl_master_rx ctrl_slave_abv_rx ctrl_slave_blw_rx individual_rx
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_pma_dw_rx = "pma_8b_rx" ,//pcie_g3_dyn_dw_rx pma_10b_rx pma_16b_rx pma_20b_rx pma_32b_rx pma_40b_rx pma_64b_rx pma_8b_rx
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_pld_fifo_mode_rx = "fifo_rx" ,//fifo_rx reg_rx
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_shared_fifo_width_rx = "single_rx" ,//double_rx single_rx
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_low_latency_en_rx = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_func_mode = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_frequency_rules_en = "disable" ,//disable enable
+ parameter [29:0] hssi_rx_pld_pcs_interface_hd_chnl_pma_rx_clk_hz = 30'd0 ,//0:1073741823
+ parameter [29:0] hssi_rx_pld_pcs_interface_hd_chnl_pld_rx_clk_hz = 30'd0 ,//0:1073741823
+ parameter [29:0] hssi_rx_pld_pcs_interface_hd_chnl_fref_clk_hz = 30'd0 ,//0:1073741823
+ parameter [29:0] hssi_rx_pld_pcs_interface_hd_chnl_clklow_clk_hz = 30'd0 ,//0:1073741823
+ parameter hssi_rx_pld_pcs_interface_hd_fifo_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_fifo_prot_mode_rx = "teng_mode_rx" ,//non_teng_mode_rx teng_mode_rx
+ parameter hssi_rx_pld_pcs_interface_hd_fifo_shared_fifo_width_rx = "single_rx" ,//double_rx single_rx
+ parameter hssi_rx_pld_pcs_interface_hd_10g_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_10g_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_10g_pma_dw_rx = "pma_64b_rx" ,//pma_32b_rx pma_40b_rx pma_64b_rx
+ parameter hssi_rx_pld_pcs_interface_hd_10g_fifo_mode_rx = "fifo_rx" ,//fifo_rx reg_rx
+ parameter hssi_rx_pld_pcs_interface_hd_10g_prot_mode_rx = "disabled_prot_mode_rx" ,//basic_krfec_mode_rx basic_mode_rx disabled_prot_mode_rx interlaken_mode_rx sfis_mode_rx teng_1588_krfec_mode_rx teng_1588_mode_rx teng_baser_krfec_mode_rx teng_baser_mode_rx teng_sdi_mode_rx test_prp_krfec_mode_rx test_prp_mode_rx
+ parameter hssi_rx_pld_pcs_interface_hd_10g_low_latency_en_rx = "enable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_10g_shared_fifo_width_rx = "single_rx" ,//double_rx single_rx
+ parameter hssi_rx_pld_pcs_interface_hd_10g_test_bus_mode = "tx" ,//rx tx
+ parameter hssi_rx_pld_pcs_interface_hd_8g_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_8g_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_8g_prot_mode_rx = "disabled_prot_mode_rx" ,//basic_rm_disable_rx basic_rm_enable_rx cpri_rx cpri_rx_tx_rx disabled_prot_mode_rx gige_1588_rx gige_rx pipe_g1_rx pipe_g2_rx pipe_g3_rx
+ parameter hssi_rx_pld_pcs_interface_hd_8g_hip_mode = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_8g_pma_dw_rx = "pma_8b_rx" ,//pma_10b_rx pma_16b_rx pma_20b_rx pma_8b_rx
+ parameter hssi_rx_pld_pcs_interface_hd_8g_fifo_mode_rx = "fifo_rx" ,//fifo_rx reg_rx
+ parameter hssi_rx_pld_pcs_interface_hd_g3_prot_mode = "disabled_prot_mode" ,//disabled_prot_mode pipe_g1 pipe_g2 pipe_g3
+ parameter hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx = "disabled_prot_mode_rx" ,//basic_mode_rx disabled_prot_mode_rx fortyg_basekr_mode_rx teng_1588_basekr_mode_rx teng_basekr_mode_rx
+ parameter hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode = "tx" ,//rx tx
+ parameter hssi_rx_pld_pcs_interface_hd_pmaif_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_pmaif_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pld_pcs_interface_hd_pmaif_sim_mode = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_pmaif_prot_mode_rx = "disabled_prot_mode_rx" ,//disabled_prot_mode_rx eightg_basic_mode_rx eightg_g3_pcie_g3_hip_mode_rx eightg_g3_pcie_g3_pld_mode_rx eightg_only_pld_mode_rx eightg_pcie_g12_hip_mode_rx eightg_pcie_g12_pld_mode_rx pcs_direct_mode_rx prbs_mode_rx teng_basic_mode_rx teng_krfec_mode_rx teng_sfis_sdi_mode_rx
+ parameter hssi_rx_pld_pcs_interface_hd_pmaif_pma_dw_rx = "pma_8b_rx" ,//pcie_g3_dyn_dw_rx pma_10b_rx pma_16b_rx pma_20b_rx pma_32b_rx pma_40b_rx pma_64b_rx pma_8b_rx
+ parameter hssi_rx_pld_pcs_interface_hd_pldif_prot_mode_rx = "disabled_prot_mode_rx" ,//disabled_prot_mode_rx eightg_and_g3_pld_fifo_mode_rx eightg_and_g3_reg_mode_hip_rx eightg_and_g3_reg_mode_rx pcs_direct_reg_mode_rx teng_and_krfec_pld_fifo_mode_rx teng_and_krfec_reg_mode_rx teng_pld_fifo_mode_rx teng_reg_mode_rx
+ parameter hssi_rx_pld_pcs_interface_hd_pldif_hrdrstctl_en = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_pcs_rx_block_sel = "pcs_direct" ,//eightg pcs_direct teng
+ parameter hssi_rx_pld_pcs_interface_pcs_rx_clk_sel = "pld_rx_clk" ,//pcs_rx_clk pld_rx_clk
+ parameter hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en = "hip_rx_enable" ,//hip_rx_disable hip_rx_enable
+ parameter hssi_rx_pld_pcs_interface_pcs_rx_output_sel = "teng_output" ,//krfec_output teng_output
+ parameter hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel = "teng_clk_out" ,//eightg_clk_out pma_rx_clk pma_rx_clk_user teng_clk_out
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_hip_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_hrdrstctl_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx = "disabled_prot_mode_tx" ,//basic_10gpcs_krfec_tx basic_10gpcs_tx basic_8gpcs_tx cpri_8b10b_tx disabled_prot_mode_tx fortyg_basekr_krfec_tx gige_1588_tx gige_tx interlaken_tx pcie_g1_capable_tx pcie_g2_capable_tx pcie_g3_capable_tx pcs_direct_tx prbs_tx prp_krfec_tx prp_tx sfis_tx sqwave_tx teng_1588_basekr_krfec_tx teng_1588_baser_tx teng_basekr_krfec_tx teng_baser_tx teng_sdi_tx uhsif_tx
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx = "individual_tx" ,//ctrl_master_tx ctrl_slave_abv_tx ctrl_slave_blw_tx individual_tx
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_pma_dw_tx = "pma_8b_tx" ,//pcie_g3_dyn_dw_tx pma_10b_tx pma_16b_tx pma_20b_tx pma_32b_tx pma_40b_tx pma_64b_tx pma_8b_tx
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_pld_fifo_mode_tx = "fifo_tx" ,//fastreg_tx fifo_tx reg_tx
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_shared_fifo_width_tx = "single_tx" ,//double_tx single_tx
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_low_latency_en_tx = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_func_mode = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_chnl_frequency_rules_en = "disable" ,//disable enable
+ parameter [29:0] hssi_tx_pld_pcs_interface_hd_chnl_pma_tx_clk_hz = 30'd0 ,//0:1073741823
+ parameter [29:0] hssi_tx_pld_pcs_interface_hd_chnl_pld_tx_clk_hz = 30'd0 ,//0:1073741823
+ parameter [29:0] hssi_tx_pld_pcs_interface_hd_chnl_pld_uhsif_tx_clk_hz = 30'd0 ,//0:1073741823
+ parameter hssi_tx_pld_pcs_interface_hd_fifo_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_fifo_prot_mode_tx = "teng_mode_tx" ,//non_teng_mode_tx teng_mode_tx
+ parameter hssi_tx_pld_pcs_interface_hd_fifo_shared_fifo_width_tx = "single_tx" ,//double_tx single_tx
+ parameter hssi_tx_pld_pcs_interface_hd_10g_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_10g_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_10g_pma_dw_tx = "pma_64b_tx" ,//pma_32b_tx pma_40b_tx pma_64b_tx
+ parameter hssi_tx_pld_pcs_interface_hd_10g_fifo_mode_tx = "fifo_tx" ,//fastreg_tx fifo_tx reg_tx
+ parameter hssi_tx_pld_pcs_interface_hd_10g_prot_mode_tx = "disabled_prot_mode_tx" ,//basic_krfec_mode_tx basic_mode_tx disabled_prot_mode_tx interlaken_mode_tx sfis_mode_tx teng_1588_krfec_mode_tx teng_1588_mode_tx teng_baser_krfec_mode_tx teng_baser_mode_tx teng_sdi_mode_tx test_prp_krfec_mode_tx test_prp_mode_tx
+ parameter hssi_tx_pld_pcs_interface_hd_10g_low_latency_en_tx = "enable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_10g_shared_fifo_width_tx = "single_tx" ,//double_tx single_tx
+ parameter hssi_tx_pld_pcs_interface_hd_8g_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_8g_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx = "disabled_prot_mode_tx" ,//basic_tx cpri_rx_tx_tx cpri_tx disabled_prot_mode_tx gige_1588_tx gige_tx pipe_g1_tx pipe_g2_tx pipe_g3_tx
+ parameter hssi_tx_pld_pcs_interface_hd_8g_hip_mode = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_8g_pma_dw_tx = "pma_8b_tx" ,//pma_10b_tx pma_16b_tx pma_20b_tx pma_8b_tx
+ parameter hssi_tx_pld_pcs_interface_hd_8g_fifo_mode_tx = "fifo_tx" ,//fastreg_tx fifo_tx reg_tx
+ parameter hssi_tx_pld_pcs_interface_hd_g3_prot_mode = "disabled_prot_mode" ,//disabled_prot_mode pipe_g1 pipe_g2 pipe_g3
+ parameter hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx = "disabled_prot_mode_tx" ,//basic_mode_tx disabled_prot_mode_tx fortyg_basekr_mode_tx teng_1588_basekr_mode_tx teng_basekr_mode_tx
+ parameter hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_pmaif_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_pmaif_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pld_pcs_interface_hd_pmaif_sim_mode = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_pmaif_prot_mode_tx = "disabled_prot_mode_tx" ,//disabled_prot_mode_tx eightg_basic_mode_tx eightg_g3_pcie_g3_hip_mode_tx eightg_g3_pcie_g3_pld_mode_tx eightg_only_pld_mode_tx eightg_pcie_g12_hip_mode_tx eightg_pcie_g12_pld_mode_tx pcs_direct_mode_tx prbs_mode_tx sqwave_mode_tx teng_basic_mode_tx teng_krfec_mode_tx teng_sfis_sdi_mode_tx uhsif_direct_mode_tx uhsif_reg_mode_tx
+ parameter hssi_tx_pld_pcs_interface_hd_pmaif_pma_dw_tx = "pma_8b_tx" ,//pcie_g3_dyn_dw_tx pma_10b_tx pma_16b_tx pma_20b_tx pma_32b_tx pma_40b_tx pma_64b_tx pma_8b_tx
+ parameter hssi_tx_pld_pcs_interface_hd_pldif_prot_mode_tx = "disabled_prot_mode_tx" ,//disabled_prot_mode_tx eightg_and_g3_fastreg_mode_tx eightg_and_g3_pld_fifo_mode_tx eightg_and_g3_reg_mode_hip_tx eightg_and_g3_reg_mode_tx pcs_direct_fastreg_mode_tx teng_and_krfec_fastreg_mode_tx teng_and_krfec_pld_fifo_mode_tx teng_and_krfec_reg_mode_tx teng_fastreg_mode_tx teng_pld_fifo_mode_tx teng_reg_mode_tx uhsif_mode_tx
+ parameter hssi_tx_pld_pcs_interface_hd_pldif_hrdrstctl_en = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_clk_source = "teng" ,//eightg pma_clk teng
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_data_source = "hip_disable" ,//hip_disable hip_enable
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en = "delay1_clk_disable" ,//delay1_clk_disable delay1_clk_enable
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel = "pld_tx_clk" ,//pcs_tx_clk pld_tx_clk
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl = "delay1_path0" ,//delay1_path0 delay1_path1 delay1_path2 delay1_path3 delay1_path4
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel = "one_ff_delay" ,//one_ff_delay two_ff_delay
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en = "delay2_clk_disable" ,//delay2_clk_disable delay2_clk_enable
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl = "delay2_path0" ,//delay2_path0 delay2_path1 delay2_path2 delay2_path3 delay2_path4
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_output_sel = "teng_output" ,//krfec_output teng_output
+ parameter hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel = "teng_clk_out" ,//eightg_clk_out pma_tx_clk pma_tx_clk_user teng_clk_out
+ parameter hssi_krfec_tx_pcs_burst_err = "burst_err_dis" ,//burst_err_dis burst_err_en
+ parameter hssi_krfec_tx_pcs_burst_err_len = "burst_err_len1" ,//burst_err_len1 burst_err_len10 burst_err_len11 burst_err_len12 burst_err_len13 burst_err_len14 burst_err_len15 burst_err_len16 burst_err_len2 burst_err_len3 burst_err_len4 burst_err_len5 burst_err_len6 burst_err_len7 burst_err_len8 burst_err_len9
+ parameter hssi_krfec_tx_pcs_ctrl_bit_reverse = "ctrl_bit_reverse_dis" ,//ctrl_bit_reverse_dis ctrl_bit_reverse_en
+ parameter hssi_krfec_tx_pcs_data_bit_reverse = "data_bit_reverse_dis" ,//data_bit_reverse_dis data_bit_reverse_en
+ parameter hssi_krfec_tx_pcs_enc_frame_query = "enc_query_dis" ,//enc_query_dis enc_query_en
+ parameter hssi_krfec_tx_pcs_low_latency_en = "disable" ,//disable enable
+ parameter hssi_krfec_tx_pcs_pipeln_encoder = "enable" ,//disable enable
+ parameter hssi_krfec_tx_pcs_pipeln_scrambler = "enable" ,//disable enable
+ parameter hssi_krfec_tx_pcs_prot_mode = "disable_mode" ,//basic_mode disable_mode fortyg_basekr_mode teng_1588_basekr_mode teng_basekr_mode
+ parameter hssi_krfec_tx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_krfec_tx_pcs_transcode_err = "trans_err_dis" ,//trans_err_dis trans_err_en
+ parameter hssi_krfec_tx_pcs_transmit_order = "transmit_lsb" ,//transmit_lsb transmit_msb
+ parameter hssi_krfec_tx_pcs_tx_testbus_sel = "overall" ,//encoder1 encoder2 gearbox overall scramble1 scramble2 scramble3
+ parameter hssi_10g_rx_pcs_align_del = "align_del_en" ,//align_del_dis align_del_en
+ parameter hssi_10g_rx_pcs_ber_bit_err_total_cnt = "bit_err_total_cnt_10g" ,//bit_err_total_cnt_10g
+ parameter hssi_10g_rx_pcs_ber_clken = "ber_clk_dis" ,//ber_clk_dis ber_clk_en
+ parameter [20:0] hssi_10g_rx_pcs_ber_xus_timer_window = 21'd19530 ,//0:2097151
+ parameter hssi_10g_rx_pcs_bitslip_mode = "bitslip_dis" ,//bitslip_dis bitslip_en
+ parameter hssi_10g_rx_pcs_blksync_bitslip_type = "bitslip_comb" ,//bitslip_comb bitslip_reg
+ parameter [2:0] hssi_10g_rx_pcs_blksync_bitslip_wait_cnt = 3'd1 ,//0:7
+ parameter hssi_10g_rx_pcs_blksync_bitslip_wait_type = "bitslip_match" ,//bitslip_cnt bitslip_match
+ parameter hssi_10g_rx_pcs_blksync_bypass = "blksync_bypass_dis" ,//blksync_bypass_dis blksync_bypass_en
+ parameter hssi_10g_rx_pcs_blksync_clken = "blksync_clk_dis" ,//blksync_clk_dis blksync_clk_en
+ parameter hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt = "enum_invalid_sh_cnt_10g" ,//enum_invalid_sh_cnt_10g
+ parameter hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock = "knum_sh_cnt_postlock_10g" ,//knum_sh_cnt_postlock_10g
+ parameter hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock = "knum_sh_cnt_prelock_10g" ,//knum_sh_cnt_prelock_10g
+ parameter hssi_10g_rx_pcs_blksync_pipeln = "blksync_pipeln_dis" ,//blksync_pipeln_dis blksync_pipeln_en
+ parameter hssi_10g_rx_pcs_clr_errblk_cnt_en = "disable" ,//disable enable
+ parameter hssi_10g_rx_pcs_control_del = "control_del_all" ,//control_del_all control_del_none
+ parameter hssi_10g_rx_pcs_crcchk_bypass = "crcchk_bypass_dis" ,//crcchk_bypass_dis crcchk_bypass_en
+ parameter hssi_10g_rx_pcs_crcchk_clken = "crcchk_clk_dis" ,//crcchk_clk_dis crcchk_clk_en
+ parameter hssi_10g_rx_pcs_crcchk_inv = "crcchk_inv_dis" ,//crcchk_inv_dis crcchk_inv_en
+ parameter hssi_10g_rx_pcs_crcchk_pipeln = "crcchk_pipeln_dis" ,//crcchk_pipeln_dis crcchk_pipeln_en
+ parameter hssi_10g_rx_pcs_crcflag_pipeln = "crcflag_pipeln_dis" ,//crcflag_pipeln_dis crcflag_pipeln_en
+ parameter hssi_10g_rx_pcs_ctrl_bit_reverse = "ctrl_bit_reverse_dis" ,//ctrl_bit_reverse_dis ctrl_bit_reverse_en
+ parameter hssi_10g_rx_pcs_data_bit_reverse = "data_bit_reverse_dis" ,//data_bit_reverse_dis data_bit_reverse_en
+ parameter hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass = "dec_64b66b_rxsm_bypass_dis" ,//dec_64b66b_rxsm_bypass_dis dec_64b66b_rxsm_bypass_en
+ parameter hssi_10g_rx_pcs_dec64b66b_clken = "dec64b66b_clk_dis" ,//dec64b66b_clk_dis dec64b66b_clk_en
+ parameter hssi_10g_rx_pcs_descrm_bypass = "descrm_bypass_en" ,//descrm_bypass_dis descrm_bypass_en
+ parameter hssi_10g_rx_pcs_descrm_clken = "descrm_clk_dis" ,//descrm_clk_dis descrm_clk_en
+ parameter hssi_10g_rx_pcs_descrm_mode = "async" ,//async sync
+ parameter hssi_10g_rx_pcs_descrm_pipeln = "enable" ,//disable enable
+ parameter hssi_10g_rx_pcs_dft_clk_out_sel = "rx_master_clk" ,//rx_64b66bdec_clk rx_ber_clk rx_blksync_clk rx_crcchk_clk rx_descrm_clk rx_fec_clk rx_frmsync_clk rx_gbexp_clk rx_master_clk rx_rand_clk rx_rdfifo_clk rx_wrfifo_clk
+ parameter hssi_10g_rx_pcs_dis_signal_ok = "dis_signal_ok_dis" ,//dis_signal_ok_dis dis_signal_ok_en
+ parameter hssi_10g_rx_pcs_dispchk_bypass = "dispchk_bypass_dis" ,//dispchk_bypass_dis dispchk_bypass_en
+ parameter hssi_10g_rx_pcs_empty_flag_type = "empty_rd_side" ,//empty_rd_side empty_wr_side
+ parameter hssi_10g_rx_pcs_fast_path = "fast_path_dis" ,//fast_path_dis fast_path_en
+ parameter hssi_10g_rx_pcs_fec_clken = "fec_clk_dis" ,//fec_clk_dis fec_clk_en
+ parameter hssi_10g_rx_pcs_fec_enable = "fec_dis" ,//fec_dis fec_en
+ parameter hssi_10g_rx_pcs_fifo_double_read = "fifo_double_read_dis" ,//fifo_double_read_dis fifo_double_read_en
+ parameter hssi_10g_rx_pcs_fifo_stop_rd = "n_rd_empty" ,//n_rd_empty rd_empty
+ parameter hssi_10g_rx_pcs_fifo_stop_wr = "n_wr_full" ,//n_wr_full wr_full
+ parameter hssi_10g_rx_pcs_force_align = "force_align_dis" ,//force_align_dis force_align_en
+ parameter hssi_10g_rx_pcs_frmsync_bypass = "frmsync_bypass_dis" ,//frmsync_bypass_dis frmsync_bypass_en
+ parameter hssi_10g_rx_pcs_frmsync_clken = "frmsync_clk_dis" ,//frmsync_clk_dis frmsync_clk_en
+ parameter hssi_10g_rx_pcs_frmsync_enum_scrm = "enum_scrm_default" ,//enum_scrm_default
+ parameter hssi_10g_rx_pcs_frmsync_enum_sync = "enum_sync_default" ,//enum_sync_default
+ parameter hssi_10g_rx_pcs_frmsync_flag_type = "all_framing_words" ,//all_framing_words location_only
+ parameter hssi_10g_rx_pcs_frmsync_knum_sync = "knum_sync_default" ,//knum_sync_default
+ parameter [15:0] hssi_10g_rx_pcs_frmsync_mfrm_length = 16'd2048 ,//0:65535
+ parameter hssi_10g_rx_pcs_frmsync_pipeln = "frmsync_pipeln_dis" ,//frmsync_pipeln_dis frmsync_pipeln_en
+ parameter hssi_10g_rx_pcs_full_flag_type = "full_wr_side" ,//full_rd_side full_wr_side
+ parameter hssi_10g_rx_pcs_gb_rx_idwidth = "width_32" ,//width_32 width_40 width_64
+ parameter hssi_10g_rx_pcs_gb_rx_odwidth = "width_66" ,//width_32 width_40 width_50 width_64 width_66 width_67
+ parameter hssi_10g_rx_pcs_gbexp_clken = "gbexp_clk_dis" ,//gbexp_clk_dis gbexp_clk_en
+ parameter hssi_10g_rx_pcs_low_latency_en = "enable" ,//disable enable
+ parameter hssi_10g_rx_pcs_lpbk_mode = "lpbk_dis" ,//lpbk_dis lpbk_en
+ parameter hssi_10g_rx_pcs_master_clk_sel = "master_rx_pma_clk" ,//master_refclk_dig master_rx_pma_clk master_tx_pma_clk
+ parameter hssi_10g_rx_pcs_pempty_flag_type = "pempty_rd_side" ,//pempty_rd_side pempty_wr_side
+ parameter hssi_10g_rx_pcs_pfull_flag_type = "pfull_wr_side" ,//pfull_rd_side pfull_wr_side
+ parameter hssi_10g_rx_pcs_phcomp_rd_del = "phcomp_rd_del2" ,//phcomp_rd_del2 phcomp_rd_del3 phcomp_rd_del4
+ parameter hssi_10g_rx_pcs_pld_if_type = "fifo" ,//fifo reg
+ parameter hssi_10g_rx_pcs_prot_mode = "disable_mode" ,//basic_krfec_mode basic_mode disable_mode interlaken_mode sfis_mode teng_1588_krfec_mode teng_1588_mode teng_baser_krfec_mode teng_baser_mode teng_sdi_mode test_prp_krfec_mode test_prp_mode
+ parameter hssi_10g_rx_pcs_rand_clken = "rand_clk_dis" ,//rand_clk_dis rand_clk_en
+ parameter hssi_10g_rx_pcs_rd_clk_sel = "rd_rx_pma_clk" ,//rd_refclk_dig rd_rx_pld_clk rd_rx_pma_clk
+ parameter hssi_10g_rx_pcs_rdfifo_clken = "rdfifo_clk_dis" ,//rdfifo_clk_dis rdfifo_clk_en
+ parameter hssi_10g_rx_pcs_rx_fifo_write_ctrl = "blklock_stops" ,//blklock_ignore blklock_stops
+ parameter hssi_10g_rx_pcs_rx_scrm_width = "bit64" ,//bit64 bit66 bit67
+ parameter hssi_10g_rx_pcs_rx_sh_location = "lsb" ,//lsb msb
+ parameter hssi_10g_rx_pcs_rx_signal_ok_sel = "synchronized_ver" ,//nonsync_ver synchronized_ver
+ parameter hssi_10g_rx_pcs_rx_sm_bypass = "rx_sm_bypass_dis" ,//rx_sm_bypass_dis rx_sm_bypass_en
+ parameter hssi_10g_rx_pcs_rx_sm_hiber = "rx_sm_hiber_en" ,//rx_sm_hiber_dis rx_sm_hiber_en
+ parameter hssi_10g_rx_pcs_rx_sm_pipeln = "rx_sm_pipeln_dis" ,//rx_sm_pipeln_dis rx_sm_pipeln_en
+ parameter hssi_10g_rx_pcs_rx_testbus_sel = "crc32_chk_testbus1" ,//ber_testbus blank_testbus blksync_testbus1 blksync_testbus2 crc32_chk_testbus1 crc32_chk_testbus2 dec64b66b_testbus descramble_testbus frame_sync_testbus1 frame_sync_testbus2 gearbox_exp_testbus random_ver_testbus rxsm_testbus rx_fifo_testbus1 rx_fifo_testbus2
+ parameter hssi_10g_rx_pcs_rx_true_b2b = "b2b" ,//b2b single
+ parameter hssi_10g_rx_pcs_rxfifo_empty = "empty_default" ,//empty_default
+ parameter hssi_10g_rx_pcs_rxfifo_full = "full_default" ,//full_default
+ parameter hssi_10g_rx_pcs_rxfifo_mode = "phase_comp" ,//clk_comp_10g generic_basic generic_interlaken phase_comp phase_comp_dv register_mode
+ parameter [4:0] hssi_10g_rx_pcs_rxfifo_pempty = 5'd2 ,//0:31
+ parameter [4:0] hssi_10g_rx_pcs_rxfifo_pfull = 5'd23 ,//0:31
+ parameter hssi_10g_rx_pcs_stretch_num_stages = "zero_stage" ,//one_stage three_stage two_stage zero_stage
+ parameter hssi_10g_rx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_10g_rx_pcs_test_mode = "test_off" ,//pseudo_random test_off
+ parameter hssi_10g_rx_pcs_wrfifo_clken = "wrfifo_clk_dis" ,//wrfifo_clk_dis wrfifo_clk_en
+ parameter hssi_10g_tx_pcs_bitslip_en = "bitslip_dis" ,//bitslip_dis bitslip_en
+ parameter hssi_10g_tx_pcs_bonding_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_10g_tx_pcs_bonding_dft_val = "dft_0" ,//dft_0 dft_1
+ parameter hssi_10g_tx_pcs_crcgen_bypass = "crcgen_bypass_dis" ,//crcgen_bypass_dis crcgen_bypass_en
+ parameter hssi_10g_tx_pcs_crcgen_clken = "crcgen_clk_dis" ,//crcgen_clk_dis crcgen_clk_en
+ parameter hssi_10g_tx_pcs_crcgen_err = "crcgen_err_dis" ,//crcgen_err_dis crcgen_err_en
+ parameter hssi_10g_tx_pcs_crcgen_inv = "crcgen_inv_dis" ,//crcgen_inv_dis crcgen_inv_en
+ parameter hssi_10g_tx_pcs_ctrl_bit_reverse = "ctrl_bit_reverse_dis" ,//ctrl_bit_reverse_dis ctrl_bit_reverse_en
+ parameter hssi_10g_tx_pcs_data_bit_reverse = "data_bit_reverse_dis" ,//data_bit_reverse_dis data_bit_reverse_en
+ parameter hssi_10g_tx_pcs_dft_clk_out_sel = "tx_master_clk" ,//tx_64b66benc_txsm_clk tx_crcgen_clk tx_dispgen_clk tx_fec_clk tx_frmgen_clk tx_gbred_clk tx_master_clk tx_rdfifo_clk tx_scrm_clk tx_wrfifo_clk
+ parameter hssi_10g_tx_pcs_dispgen_bypass = "dispgen_bypass_dis" ,//dispgen_bypass_dis dispgen_bypass_en
+ parameter hssi_10g_tx_pcs_dispgen_clken = "dispgen_clk_dis" ,//dispgen_clk_dis dispgen_clk_en
+ parameter hssi_10g_tx_pcs_dispgen_err = "dispgen_err_dis" ,//dispgen_err_dis dispgen_err_en
+ parameter hssi_10g_tx_pcs_dispgen_pipeln = "dispgen_pipeln_dis" ,//dispgen_pipeln_dis dispgen_pipeln_en
+ parameter hssi_10g_tx_pcs_empty_flag_type = "empty_rd_side" ,//empty_rd_side empty_wr_side
+ parameter hssi_10g_tx_pcs_enc_64b66b_txsm_bypass = "enc_64b66b_txsm_bypass_dis" ,//enc_64b66b_txsm_bypass_dis enc_64b66b_txsm_bypass_en
+ parameter hssi_10g_tx_pcs_enc64b66b_txsm_clken = "enc64b66b_txsm_clk_dis" ,//enc64b66b_txsm_clk_dis enc64b66b_txsm_clk_en
+ parameter hssi_10g_tx_pcs_fastpath = "fastpath_dis" ,//fastpath_dis fastpath_en
+ parameter hssi_10g_tx_pcs_fec_clken = "fec_clk_dis" ,//fec_clk_dis fec_clk_en
+ parameter hssi_10g_tx_pcs_fec_enable = "fec_dis" ,//fec_dis fec_en
+ parameter hssi_10g_tx_pcs_fifo_double_write = "fifo_double_write_dis" ,//fifo_double_write_dis fifo_double_write_en
+ parameter hssi_10g_tx_pcs_fifo_reg_fast = "fifo_reg_fast_dis" ,//fifo_reg_fast_dis fifo_reg_fast_en
+ parameter hssi_10g_tx_pcs_fifo_stop_rd = "n_rd_empty" ,//n_rd_empty rd_empty
+ parameter hssi_10g_tx_pcs_fifo_stop_wr = "n_wr_full" ,//n_wr_full wr_full
+ parameter hssi_10g_tx_pcs_frmgen_burst = "frmgen_burst_dis" ,//frmgen_burst_dis frmgen_burst_en
+ parameter hssi_10g_tx_pcs_frmgen_bypass = "frmgen_bypass_dis" ,//frmgen_bypass_dis frmgen_bypass_en
+ parameter hssi_10g_tx_pcs_frmgen_clken = "frmgen_clk_dis" ,//frmgen_clk_dis frmgen_clk_en
+ parameter [15:0] hssi_10g_tx_pcs_frmgen_mfrm_length = 16'd2048 ,//0:65535
+ parameter hssi_10g_tx_pcs_frmgen_pipeln = "frmgen_pipeln_dis" ,//frmgen_pipeln_dis frmgen_pipeln_en
+ parameter hssi_10g_tx_pcs_frmgen_pyld_ins = "frmgen_pyld_ins_dis" ,//frmgen_pyld_ins_dis frmgen_pyld_ins_en
+ parameter hssi_10g_tx_pcs_frmgen_wordslip = "frmgen_wordslip_dis" ,//frmgen_wordslip_dis frmgen_wordslip_en
+ parameter hssi_10g_tx_pcs_full_flag_type = "full_wr_side" ,//full_rd_side full_wr_side
+ parameter hssi_10g_tx_pcs_gb_pipeln_bypass = "enable" ,//disable enable
+ parameter hssi_10g_tx_pcs_gb_tx_idwidth = "width_50" ,//width_32 width_40 width_50 width_64 width_66 width_67
+ parameter hssi_10g_tx_pcs_gb_tx_odwidth = "width_32" ,//width_32 width_40 width_64
+ parameter hssi_10g_tx_pcs_gbred_clken = "gbred_clk_dis" ,//gbred_clk_dis gbred_clk_en
+ parameter hssi_10g_tx_pcs_low_latency_en = "enable" ,//disable enable
+ parameter hssi_10g_tx_pcs_master_clk_sel = "master_tx_pma_clk" ,//master_refclk_dig master_tx_pma_clk
+ parameter hssi_10g_tx_pcs_pempty_flag_type = "pempty_rd_side" ,//pempty_rd_side pempty_wr_side
+ parameter hssi_10g_tx_pcs_pfull_flag_type = "pfull_wr_side" ,//pfull_rd_side pfull_wr_side
+ parameter hssi_10g_tx_pcs_phcomp_rd_del = "phcomp_rd_del2" ,//phcomp_rd_del2 phcomp_rd_del3 phcomp_rd_del4
+ parameter hssi_10g_tx_pcs_pld_if_type = "fifo" ,//fastreg fifo reg
+ parameter hssi_10g_tx_pcs_prot_mode = "disable_mode" ,//basic_krfec_mode basic_mode disable_mode interlaken_mode sfis_mode teng_1588_krfec_mode teng_1588_mode teng_baser_krfec_mode teng_baser_mode teng_sdi_mode test_prp_krfec_mode test_prp_mode
+ parameter hssi_10g_tx_pcs_pseudo_random = "all_0" ,//all_0 two_lf
+ parameter hssi_10g_tx_pcs_pseudo_seed_a = "288230376151711743" ,//NOVAL
+ parameter hssi_10g_tx_pcs_pseudo_seed_b = "288230376151711743" ,//NOVAL
+ parameter hssi_10g_tx_pcs_random_disp = "disable" ,//disable enable
+ parameter hssi_10g_tx_pcs_rdfifo_clken = "rdfifo_clk_dis" ,//rdfifo_clk_dis rdfifo_clk_en
+ parameter hssi_10g_tx_pcs_scrm_bypass = "scrm_bypass_dis" ,//scrm_bypass_dis scrm_bypass_en
+ parameter hssi_10g_tx_pcs_scrm_clken = "scrm_clk_dis" ,//scrm_clk_dis scrm_clk_en
+ parameter hssi_10g_tx_pcs_scrm_mode = "async" ,//async sync
+ parameter hssi_10g_tx_pcs_scrm_pipeln = "enable" ,//disable enable
+ parameter hssi_10g_tx_pcs_sh_err = "sh_err_dis" ,//sh_err_dis sh_err_en
+ parameter hssi_10g_tx_pcs_sop_mark = "sop_mark_dis" ,//sop_mark_dis sop_mark_en
+ parameter hssi_10g_tx_pcs_stretch_num_stages = "zero_stage" ,//one_stage three_stage two_stage zero_stage
+ parameter hssi_10g_tx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_10g_tx_pcs_test_mode = "test_off" ,//pseudo_random test_off
+ parameter hssi_10g_tx_pcs_tx_scrm_err = "scrm_err_dis" ,//scrm_err_dis scrm_err_en
+ parameter hssi_10g_tx_pcs_tx_scrm_width = "bit64" ,//bit64 bit66 bit67
+ parameter hssi_10g_tx_pcs_tx_sh_location = "lsb" ,//lsb msb
+ parameter hssi_10g_tx_pcs_tx_sm_bypass = "tx_sm_bypass_dis" ,//tx_sm_bypass_dis tx_sm_bypass_en
+ parameter hssi_10g_tx_pcs_tx_sm_pipeln = "tx_sm_pipeln_dis" ,//tx_sm_pipeln_dis tx_sm_pipeln_en
+ parameter hssi_10g_tx_pcs_tx_testbus_sel = "crc32_gen_testbus1" ,//blank_testbus crc32_gen_testbus1 crc32_gen_testbus2 disp_gen_testbus1 disp_gen_testbus2 enc64b66b_testbus frame_gen_testbus1 frame_gen_testbus2 gearbox_red_testbus scramble_testbus txsm_testbus tx_cp_bond_testbus tx_fifo_testbus1 tx_fifo_testbus2
+ parameter hssi_10g_tx_pcs_txfifo_empty = "empty_default" ,//empty_default
+ parameter hssi_10g_tx_pcs_txfifo_full = "full_default" ,//full_default
+ parameter hssi_10g_tx_pcs_txfifo_mode = "phase_comp" ,//basic_generic interlaken_generic phase_comp register_mode
+ parameter [3:0] hssi_10g_tx_pcs_txfifo_pempty = 4'd2 ,//0:15
+ parameter [3:0] hssi_10g_tx_pcs_txfifo_pfull = 4'd11 ,//0:15
+ parameter hssi_10g_tx_pcs_wr_clk_sel = "wr_tx_pma_clk" ,//wr_refclk_dig wr_tx_pld_clk wr_tx_pma_clk
+ parameter hssi_10g_tx_pcs_wrfifo_clken = "wrfifo_clk_dis" ,//wrfifo_clk_dis wrfifo_clk_en
+ parameter hssi_8g_rx_pcs_auto_error_replacement = "dis_err_replace" ,//dis_err_replace en_err_replace
+ parameter hssi_8g_rx_pcs_bit_reversal = "dis_bit_reversal" ,//dis_bit_reversal en_bit_reversal
+ parameter hssi_8g_rx_pcs_bonding_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_8g_rx_pcs_bonding_dft_val = "dft_0" ,//dft_0 dft_1
+ parameter hssi_8g_rx_pcs_bypass_pipeline_reg = "dis_bypass_pipeline" ,//dis_bypass_pipeline en_bypass_pipeline
+ parameter hssi_8g_rx_pcs_byte_deserializer = "dis_bds" ,//dis_bds en_bds_by_2 en_bds_by_2_det en_bds_by_4
+ parameter hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask = "dis_rxvalid_mask" ,//dis_rxvalid_mask en_rxvalid_mask
+ parameter [19:0] hssi_8g_rx_pcs_clkcmp_pattern_n = 20'd0 ,//0:1048575
+ parameter [19:0] hssi_8g_rx_pcs_clkcmp_pattern_p = 20'd0 ,//0:1048575
+ parameter hssi_8g_rx_pcs_clock_gate_bds_dec_asn = "dis_bds_dec_asn_clk_gating" ,//dis_bds_dec_asn_clk_gating en_bds_dec_asn_clk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_cdr_eidle = "dis_cdr_eidle_clk_gating" ,//dis_cdr_eidle_clk_gating en_cdr_eidle_clk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk = "dis_dw_pc_wrclk_gating" ,//dis_dw_pc_wrclk_gating en_dw_pc_wrclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_dw_rm_rd = "dis_dw_rm_rdclk_gating" ,//dis_dw_rm_rdclk_gating en_dw_rm_rdclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_dw_rm_wr = "dis_dw_rm_wrclk_gating" ,//dis_dw_rm_wrclk_gating en_dw_rm_wrclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_dw_wa = "dis_dw_wa_clk_gating" ,//dis_dw_wa_clk_gating en_dw_wa_clk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_pc_rdclk = "dis_pc_rdclk_gating" ,//dis_pc_rdclk_gating en_pc_rdclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk = "dis_sw_pc_wrclk_gating" ,//dis_sw_pc_wrclk_gating en_sw_pc_wrclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_sw_rm_rd = "dis_sw_rm_rdclk_gating" ,//dis_sw_rm_rdclk_gating en_sw_rm_rdclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_sw_rm_wr = "dis_sw_rm_wrclk_gating" ,//dis_sw_rm_wrclk_gating en_sw_rm_wrclk_gating
+ parameter hssi_8g_rx_pcs_clock_gate_sw_wa = "dis_sw_wa_clk_gating" ,//dis_sw_wa_clk_gating en_sw_wa_clk_gating
+ parameter hssi_8g_rx_pcs_clock_observation_in_pld_core = "internal_sw_wa_clk" ,//internal_cdr_eidle_clk internal_clk_2_b internal_dw_rm_rd_clk internal_dw_rm_wr_clk internal_dw_rx_wr_clk internal_dw_wa_clk internal_rx_pma_clk_gen3 internal_rx_rcvd_clk_gen3 internal_rx_rd_clk internal_sm_rm_wr_clk internal_sw_rm_rd_clk internal_sw_rx_wr_clk internal_sw_wa_clk
+ parameter hssi_8g_rx_pcs_eidle_entry_eios = "dis_eidle_eios" ,//dis_eidle_eios en_eidle_eios
+ parameter hssi_8g_rx_pcs_eidle_entry_iei = "dis_eidle_iei" ,//dis_eidle_iei en_eidle_iei
+ parameter hssi_8g_rx_pcs_eidle_entry_sd = "dis_eidle_sd" ,//dis_eidle_sd en_eidle_sd
+ parameter hssi_8g_rx_pcs_eightb_tenb_decoder = "dis_8b10b" ,//dis_8b10b en_8b10b_ibm en_8b10b_sgx
+ parameter hssi_8g_rx_pcs_err_flags_sel = "err_flags_wa" ,//err_flags_8b10b err_flags_wa
+ parameter hssi_8g_rx_pcs_fixed_pat_det = "dis_fixed_patdet" ,//dis_fixed_patdet en_fixed_patdet
+ parameter [3:0] hssi_8g_rx_pcs_fixed_pat_num = 4'd15 ,//0:15
+ parameter hssi_8g_rx_pcs_force_signal_detect = "en_force_signal_detect" ,//dis_force_signal_detect en_force_signal_detect
+ parameter hssi_8g_rx_pcs_gen3_clk_en = "disable_clk" ,//disable_clk enable_clk
+ parameter hssi_8g_rx_pcs_gen3_rx_clk_sel = "rcvd_clk" ,//en_dig_clk1_8g rcvd_clk
+ parameter hssi_8g_rx_pcs_gen3_tx_clk_sel = "tx_pma_clk" ,//en_dig_clk2_8g tx_pma_clk
+ parameter hssi_8g_rx_pcs_hip_mode = "dis_hip" ,//dis_hip en_hip
+ parameter hssi_8g_rx_pcs_ibm_invalid_code = "dis_ibm_invalid_code" ,//dis_ibm_invalid_code en_ibm_invalid_code
+ parameter hssi_8g_rx_pcs_invalid_code_flag_only = "dis_invalid_code_only" ,//dis_invalid_code_only en_invalid_code_only
+ parameter hssi_8g_rx_pcs_pad_or_edb_error_replace = "replace_edb" ,//replace_edb replace_edb_dynamic replace_pad
+ parameter hssi_8g_rx_pcs_pcs_bypass = "dis_pcs_bypass" ,//dis_pcs_bypass en_pcs_bypass
+ parameter hssi_8g_rx_pcs_phase_comp_rdptr = "enable_rdptr" ,//disable_rdptr enable_rdptr
+ parameter hssi_8g_rx_pcs_phase_compensation_fifo = "low_latency" ,//low_latency normal_latency pld_ctrl_low_latency pld_ctrl_normal_latency register_fifo
+ parameter hssi_8g_rx_pcs_pipe_if_enable = "dis_pipe_rx" ,//dis_pipe_rx en_pipe3_rx en_pipe_rx
+ parameter hssi_8g_rx_pcs_pma_dw = "eight_bit" ,//eight_bit sixteen_bit ten_bit twenty_bit
+ parameter hssi_8g_rx_pcs_polinv_8b10b_dec = "dis_polinv_8b10b_dec" ,//dis_polinv_8b10b_dec en_polinv_8b10b_dec
+ parameter hssi_8g_rx_pcs_prot_mode = "gige" ,//basic_rm_disable basic_rm_enable cpri cpri_rx_tx disabled_prot_mode gige gige_1588 pipe_g1 pipe_g2 pipe_g3
+ parameter hssi_8g_rx_pcs_rate_match = "dis_rm" ,//dis_rm dw_basic_rm gige_rm pipe_rm pipe_rm_0ppm sw_basic_rm
+ parameter hssi_8g_rx_pcs_rate_match_del_thres = "dis_rm_del_thres" ,//dis_rm_del_thres dw_basic_rm_del_thres gige_rm_del_thres pipe_rm_0ppm_del_thres pipe_rm_del_thres sw_basic_rm_del_thres
+ parameter hssi_8g_rx_pcs_rate_match_empty_thres = "dis_rm_empty_thres" ,//dis_rm_empty_thres dw_basic_rm_empty_thres gige_rm_empty_thres pipe_rm_0ppm_empty_thres pipe_rm_empty_thres sw_basic_rm_empty_thres
+ parameter hssi_8g_rx_pcs_rate_match_full_thres = "dis_rm_full_thres" ,//dis_rm_full_thres dw_basic_rm_full_thres gige_rm_full_thres pipe_rm_0ppm_full_thres pipe_rm_full_thres sw_basic_rm_full_thres
+ parameter hssi_8g_rx_pcs_rate_match_ins_thres = "dis_rm_ins_thres" ,//dis_rm_ins_thres dw_basic_rm_ins_thres gige_rm_ins_thres pipe_rm_0ppm_ins_thres pipe_rm_ins_thres sw_basic_rm_ins_thres
+ parameter hssi_8g_rx_pcs_rate_match_start_thres = "dis_rm_start_thres" ,//dis_rm_start_thres dw_basic_rm_start_thres gige_rm_start_thres pipe_rm_0ppm_start_thres pipe_rm_start_thres sw_basic_rm_start_thres
+ parameter hssi_8g_rx_pcs_rx_clk_free_running = "en_rx_clk_free_run" ,//dis_rx_clk_free_run en_rx_clk_free_run
+ parameter hssi_8g_rx_pcs_rx_clk2 = "rcvd_clk_clk2" ,//rcvd_clk_clk2 refclk_dig2_clk2 tx_pma_clock_clk2
+ parameter hssi_8g_rx_pcs_rx_pcs_urst = "en_rx_pcs_urst" ,//dis_rx_pcs_urst en_rx_pcs_urst
+ parameter hssi_8g_rx_pcs_rx_rcvd_clk = "rcvd_clk_rcvd_clk" ,//rcvd_clk_rcvd_clk tx_pma_clock_rcvd_clk
+ parameter hssi_8g_rx_pcs_rx_rd_clk = "pld_rx_clk" ,//pld_rx_clk rx_clk
+ parameter hssi_8g_rx_pcs_rx_refclk = "dis_refclk_sel" ,//dis_refclk_sel en_refclk_sel
+ parameter hssi_8g_rx_pcs_rx_wr_clk = "rx_clk2_div_1_2_4" ,//rx_clk2_div_1_2_4 txfifo_rd_clk
+ parameter hssi_8g_rx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_8g_rx_pcs_symbol_swap = "dis_symbol_swap" ,//dis_symbol_swap en_symbol_swap
+ parameter hssi_8g_rx_pcs_sync_sm_idle_eios = "dis_syncsm_idle" ,//dis_syncsm_idle en_syncsm_idle
+ parameter hssi_8g_rx_pcs_test_bus_sel = "tx_testbus" ,//pcie_ctrl_testbus rm_testbus rx_ctrl_plane_testbus rx_ctrl_testbus tx_ctrl_plane_testbus tx_testbus wa_testbus
+ parameter hssi_8g_rx_pcs_tx_rx_parallel_loopback = "dis_plpbk" ,//dis_plpbk en_plpbk
+ parameter hssi_8g_rx_pcs_wa_boundary_lock_ctrl = "bit_slip" ,//auto_align_pld_ctrl bit_slip deterministic_latency sync_sm
+ parameter [9:0] hssi_8g_rx_pcs_wa_clk_slip_spacing = 10'd16 ,//0:1023
+ parameter hssi_8g_rx_pcs_wa_det_latency_sync_status_beh = "assert_sync_status_non_imm" ,//assert_sync_status_imm assert_sync_status_non_imm dont_care_assert_sync
+ parameter hssi_8g_rx_pcs_wa_disp_err_flag = "dis_disp_err_flag" ,//dis_disp_err_flag en_disp_err_flag
+ parameter hssi_8g_rx_pcs_wa_kchar = "dis_kchar" ,//dis_kchar en_kchar
+ parameter hssi_8g_rx_pcs_wa_pd = "wa_pd_10" ,//wa_pd_10 wa_pd_16_dw wa_pd_16_sw wa_pd_20 wa_pd_32 wa_pd_40 wa_pd_7 wa_pd_8_dw wa_pd_8_sw
+ parameter hssi_8g_rx_pcs_wa_pd_data = "0" ,//NOVAL
+ parameter hssi_8g_rx_pcs_wa_pd_polarity = "dis_pd_both_pol" ,//dis_pd_both_pol dont_care_both_pol en_pd_both_pol
+ parameter hssi_8g_rx_pcs_wa_pld_controlled = "dis_pld_ctrl" ,//dis_pld_ctrl level_sensitive_dw pld_ctrl_sw rising_edge_sensitive_dw
+ parameter [5:0] hssi_8g_rx_pcs_wa_renumber_data = 6'd0 ,//0:63
+ parameter [7:0] hssi_8g_rx_pcs_wa_rgnumber_data = 8'd0 ,//0:255
+ parameter [7:0] hssi_8g_rx_pcs_wa_rknumber_data = 8'd0 ,//0:255
+ parameter [1:0] hssi_8g_rx_pcs_wa_rosnumber_data = 2'd0 ,//0:3
+ parameter [12:0] hssi_8g_rx_pcs_wa_rvnumber_data = 13'd0 ,//0:8191
+ parameter hssi_8g_rx_pcs_wa_sync_sm_ctrl = "gige_sync_sm" ,//dw_basic_sync_sm fibre_channel_sync_sm gige_sync_sm pipe_sync_sm sw_basic_sync_sm
+ parameter [11:0] hssi_8g_rx_pcs_wait_cnt = 12'd0 ,//0:4095
+ parameter hssi_8g_tx_pcs_bit_reversal = "dis_bit_reversal" ,//dis_bit_reversal en_bit_reversal
+ parameter hssi_8g_tx_pcs_bonding_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_8g_tx_pcs_bonding_dft_val = "dft_0" ,//dft_0 dft_1
+ parameter hssi_8g_tx_pcs_bypass_pipeline_reg = "dis_bypass_pipeline" ,//dis_bypass_pipeline en_bypass_pipeline
+ parameter hssi_8g_tx_pcs_byte_serializer = "dis_bs" ,//dis_bs en_bs_by_2 en_bs_by_4
+ parameter hssi_8g_tx_pcs_clock_gate_bs_enc = "dis_bs_enc_clk_gating" ,//dis_bs_enc_clk_gating en_bs_enc_clk_gating
+ parameter hssi_8g_tx_pcs_clock_gate_dw_fifowr = "dis_dw_fifowr_clk_gating" ,//dis_dw_fifowr_clk_gating en_dw_fifowr_clk_gating
+ parameter hssi_8g_tx_pcs_clock_gate_fiford = "dis_fiford_clk_gating" ,//dis_fiford_clk_gating en_fiford_clk_gating
+ parameter hssi_8g_tx_pcs_clock_gate_sw_fifowr = "dis_sw_fifowr_clk_gating" ,//dis_sw_fifowr_clk_gating en_sw_fifowr_clk_gating
+ parameter hssi_8g_tx_pcs_clock_observation_in_pld_core = "internal_refclk_b" ,//internal_dw_fifo_wr_clk internal_fifo_rd_clk internal_pipe_tx_clk_out_gen3 internal_refclk_b internal_sw_fifo_wr_clk internal_tx_clk_out_gen3
+ parameter hssi_8g_tx_pcs_data_selection_8b10b_encoder_input = "normal_data_path" ,//gige_idle_conversion normal_data_path
+ parameter hssi_8g_tx_pcs_dynamic_clk_switch = "dis_dyn_clk_switch" ,//dis_dyn_clk_switch en_dyn_clk_switch
+ parameter hssi_8g_tx_pcs_eightb_tenb_disp_ctrl = "dis_disp_ctrl" ,//dis_disp_ctrl en_disp_ctrl en_ib_disp_ctrl
+ parameter hssi_8g_tx_pcs_eightb_tenb_encoder = "dis_8b10b" ,//dis_8b10b en_8b10b_ibm en_8b10b_sgx
+ parameter hssi_8g_tx_pcs_force_echar = "dis_force_echar" ,//dis_force_echar en_force_echar
+ parameter hssi_8g_tx_pcs_force_kchar = "dis_force_kchar" ,//dis_force_kchar en_force_kchar
+ parameter hssi_8g_tx_pcs_gen3_tx_clk_sel = "tx_pma_clk" ,//dis_tx_clk tx_pma_clk
+ parameter hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel = "func_clk" ,//dis_tx_pipe_clk func_clk
+ parameter hssi_8g_tx_pcs_hip_mode = "dis_hip" ,//dis_hip en_hip
+ parameter hssi_8g_tx_pcs_pcs_bypass = "dis_pcs_bypass" ,//dis_pcs_bypass en_pcs_bypass
+ parameter hssi_8g_tx_pcs_phase_comp_rdptr = "enable_rdptr" ,//disable_rdptr enable_rdptr
+ parameter hssi_8g_tx_pcs_phase_compensation_fifo = "low_latency" ,//low_latency normal_latency pld_ctrl_low_latency pld_ctrl_normal_latency register_fifo
+ parameter hssi_8g_tx_pcs_phfifo_write_clk_sel = "pld_tx_clk" ,//pld_tx_clk tx_clk
+ parameter hssi_8g_tx_pcs_pma_dw = "eight_bit" ,//eight_bit sixteen_bit ten_bit twenty_bit
+ parameter hssi_8g_tx_pcs_prot_mode = "basic" ,//basic cpri cpri_rx_tx disabled_prot_mode gige gige_1588 pipe_g1 pipe_g2 pipe_g3
+ parameter hssi_8g_tx_pcs_refclk_b_clk_sel = "tx_pma_clock" ,//refclk_dig tx_pma_clock
+ parameter hssi_8g_tx_pcs_revloop_back_rm = "dis_rev_loopback_rx_rm" ,//dis_rev_loopback_rx_rm en_rev_loopback_rx_rm
+ parameter hssi_8g_tx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_8g_tx_pcs_symbol_swap = "dis_symbol_swap" ,//dis_symbol_swap en_symbol_swap
+ parameter hssi_8g_tx_pcs_tx_bitslip = "dis_tx_bitslip" ,//dis_tx_bitslip en_tx_bitslip
+ parameter hssi_8g_tx_pcs_tx_compliance_controlled_disparity = "dis_txcompliance" ,//dis_txcompliance en_txcompliance_pipe2p0 en_txcompliance_pipe3p0
+ parameter hssi_8g_tx_pcs_tx_fast_pld_reg = "dis_tx_fast_pld_reg" ,//dis_tx_fast_pld_reg en_tx_fast_pld_reg
+ parameter hssi_8g_tx_pcs_txclk_freerun = "dis_freerun_tx" ,//dis_freerun_tx en_freerun_tx
+ parameter hssi_8g_tx_pcs_txpcs_urst = "en_txpcs_urst" ,//dis_txpcs_urst en_txpcs_urst
+ parameter cdr_pll_pma_width = 8 ,//8 10 16 20 32 40 64
+ parameter cdr_pll_cgb_div = 1 ,//1:2 4 8
+ parameter cdr_pll_is_cascaded_pll = "false" ,//false true
+ parameter cdr_pll_datarate = "0 bps" ,//NOVAL
+ parameter [4:0] cdr_pll_lpd_counter = 5'd1 ,//0:31
+ parameter [4:0] cdr_pll_lpfd_counter = 5'd1 ,//0:31
+ parameter [5:0] cdr_pll_n_counter_scratch = 6'd1 ,//0:63
+ parameter cdr_pll_output_clock_frequency = "0 hz" ,//NOVAL
+ parameter cdr_pll_reference_clock_frequency = "0 hz" ,//NOVAL
+ parameter [4:0] cdr_pll_set_cdr_vco_speed = 5'd1 ,//0:31
+ parameter [7:0] cdr_pll_set_cdr_vco_speed_fix = 8'd0 ,//0:255
+ parameter cdr_pll_vco_freq = "0 hz" ,//NOVAL
+ parameter cdr_pll_atb_select_control = "atb_off" ,//atb_off atb_select_tp_1 atb_select_tp_10 atb_select_tp_11 atb_select_tp_12 atb_select_tp_13 atb_select_tp_14 atb_select_tp_15 atb_select_tp_2 atb_select_tp_3 atb_select_tp_4 atb_select_tp_5 atb_select_tp_6 atb_select_tp_7 atb_select_tp_8 atb_select_tp_9
+ parameter cdr_pll_auto_reset_on = "auto_reset_on" ,//auto_reset_off auto_reset_on
+ parameter cdr_pll_bbpd_data_pattern_filter_select = "bbpd_data_pat_off" ,//bbpd_data_pat_1 bbpd_data_pat_2 bbpd_data_pat_3 bbpd_data_pat_off
+ parameter cdr_pll_bw_sel = "low" ,//high low medium
+ parameter cdr_pll_cdr_odi_select = "sel_cdr" ,//sel_cdr sel_odi
+ parameter cdr_pll_cdr_phaselock_mode = "no_ignore_lock" ,//ignore_lock no_ignore_lock
+ parameter cdr_pll_cdr_powerdown_mode = "power_down" ,//power_down power_up
+ parameter cdr_pll_chgpmp_current_pd = "cp_current_pd_setting0" ,//cp_current_pd_setting0 cp_current_pd_setting1 cp_current_pd_setting2 cp_current_pd_setting3 cp_current_pd_setting4
+ parameter cdr_pll_chgpmp_current_pfd = "cp_current_pfd_setting0" ,//cp_current_pfd_setting0 cp_current_pfd_setting1 cp_current_pfd_setting2 cp_current_pfd_setting3 cp_current_pfd_setting4
+ parameter cdr_pll_chgpmp_replicate = "true" ,//false true
+ parameter cdr_pll_chgpmp_testmode = "cp_test_disable" ,//cp_test_disable cp_test_dn cp_test_up cp_tristate
+ parameter cdr_pll_clklow_mux_select = "clklow_mux_cdr_fbclk" ,//clklow_mux_cdr_fbclk clklow_mux_dfe_test clklow_mux_fpll_test1 clklow_mux_reserved_1 clklow_mux_reserved_2 clklow_mux_reserved_3 clklow_mux_reserved_4 clklow_mux_rx_deser_pclk_test
+ parameter cdr_pll_diag_loopback_enable = "false" ,//false true
+ parameter cdr_pll_disable_up_dn = "true" ,//false true
+ parameter cdr_pll_fref_clklow_div = 1 ,//1:2 4 8
+ parameter cdr_pll_fref_mux_select = "fref_mux_cdr_refclk" ,//fref_mux_cdr_refclk fref_mux_fpll_test0 fref_mux_reserved_1 fref_mux_reserved_2 fref_mux_reserved_3 fref_mux_reserved_4 fref_mux_reserved_5 fref_mux_tx_ser_pclk_test
+ parameter cdr_pll_gpon_lck2ref_control = "gpon_lck2ref_off" ,//gpon_lck2ref_off gpon_lck2ref_on
+ parameter cdr_pll_initial_settings = "false" ,//false true
+ parameter cdr_pll_lck2ref_delay_control = "lck2ref_delay_off" ,//lck2ref_delay_1 lck2ref_delay_2 lck2ref_delay_3 lck2ref_delay_4 lck2ref_delay_5 lck2ref_delay_6 lck2ref_delay_7 lck2ref_delay_off
+ parameter cdr_pll_lf_resistor_pd = "lf_pd_setting0" ,//lf_pd_setting0 lf_pd_setting1 lf_pd_setting2 lf_pd_setting3
+ parameter cdr_pll_lf_resistor_pfd = "lf_pfd_setting0" ,//lf_pfd_setting0 lf_pfd_setting1 lf_pfd_setting2 lf_pfd_setting3
+ parameter cdr_pll_lf_ripple_cap = "lf_no_ripple" ,//lf_no_ripple lf_ripple_cap1
+ parameter cdr_pll_loop_filter_bias_select = "lpflt_bias_off" ,//lpflt_bias_1 lpflt_bias_2 lpflt_bias_3 lpflt_bias_4 lpflt_bias_5 lpflt_bias_6 lpflt_bias_7 lpflt_bias_off
+ parameter cdr_pll_loopback_mode = "loopback_disabled" ,//loopback_disabled loopback_received_data loopback_recovered_data
+ parameter cdr_pll_ltd_ltr_micro_controller_select = "ltd_ltr_pcs" ,//ltd_ltr_pcs ltd_ucontroller ltr_ucontroller
+ parameter cdr_pll_m_counter = 1 ,//1:6 8:10 12 15:16 18 20 24:25 30 32:33 36 40 48 50 60 64 80 100
+ parameter cdr_pll_n_counter = 1 ,//1:2 4 8
+ parameter cdr_pll_pd_fastlock_mode = "false" ,//false true
+ parameter cdr_pll_pd_l_counter = 1 ,//0:2 4 8 16
+ parameter cdr_pll_pfd_l_counter = 1 ,//0:2 4 8 16 100
+ parameter cdr_pll_primary_use = "cmu" ,//cdr cmu
+ parameter cdr_pll_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter cdr_pll_requires_gt_capable_channel = "false" ,//false true
+ parameter cdr_pll_reverse_serial_loopback = "no_loopback" ,//loopback_data_0_1 loopback_data_no_posttap loopback_data_with_posttap no_loopback
+ parameter cdr_pll_set_cdr_v2i_enable = "true" ,//false true
+ parameter cdr_pll_set_cdr_vco_reset = "false" ,//false true
+ parameter cdr_pll_set_cdr_vco_speed_pciegen3 = "cdr_vco_max_speedbin_pciegen3" ,//cdr_vco_max_speedbin_pciegen3 cdr_vco_min_speedbin_pciegen3
+ parameter cdr_pll_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter cdr_pll_tx_pll_prot_mode = "txpll_unused" ,//txpll_enable txpll_enable_pcie txpll_unused
+ parameter cdr_pll_txpll_hclk_driver_enable = "false" ,//false true
+ parameter cdr_pll_vco_overrange_voltage = "vco_overrange_off" ,// new
+ parameter cdr_pll_vco_underrange_voltage = "vco_underrange_off" ,// new
+ parameter cdr_pll_fb_select = "direct_fb" ,//direct_fb iqtxrxclk_fb
+ parameter cdr_pll_uc_ro_cal = "uc_ro_cal_off" ,//uc_ro_cal_off uc_ro_cal_on
+ parameter cdr_pll_iqclk_mux_sel = "power_down" ,//iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 power_down
+ parameter cdr_pll_pcie_gen = "non_pcie" ,//non_pcie pcie_gen1_100mhzref pcie_gen1_125mhzref pcie_gen2_100mhzref pcie_gen2_125mhzref pcie_gen3_100mhzref pcie_gen3_125mhzref
+ parameter [7:0] cdr_pll_set_cdr_input_freq_range = 8'b11111111 ,
+ parameter cdr_pll_chgpmp_current_dn_trim = "cp_current_trimming_dn_setting0" ,
+ parameter cdr_pll_chgpmp_up_pd_trim_double = "normal_up_trim_current" ,
+ parameter cdr_pll_chgpmp_current_up_pd = "cp_current_pd_up_setting0" ,
+ parameter cdr_pll_chgpmp_current_up_trim = "cp_current_trimming_up_setting0" ,
+ parameter cdr_pll_chgpmp_dn_pd_trim_double = "normal_dn_trim_current" ,
+ parameter cdr_pll_cal_vco_count_length = "sel_8b_count" ,// new
+ parameter cdr_pll_chgpmp_current_dn_pd = "cp_current_pd_dn_setting0" ,
+ parameter pma_rx_odi_datarate = "0 bps" ,//NOVAL
+ parameter pma_rx_odi_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_rx_odi_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_rx_buf_bypass_eqz_stages_234 = "bypass_off" ,//bypass_off byypass_stages_234
+ parameter pma_rx_buf_datarate = "0 bps" ,//NOVAL
+ parameter pma_rx_buf_diag_lp_en = "dlp_off" ,//dlp_off dlp_on
+ parameter pma_rx_buf_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_rx_buf_qpi_enable = "non_qpi_mode" ,//non_qpi_mode qpi_mode
+ parameter pma_rx_buf_rx_refclk_divider = "bypass_divider" ,//bypass_divider divide_by_2
+ parameter pma_rx_buf_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_rx_buf_loopback_modes = "lpbk_disable" ,//lpbk_disable post_cdr pre_cdr
+ parameter pma_rx_buf_refclk_en = "disable" ,//disable enable
+ parameter pma_rx_buf_pm_tx_rx_pcie_gen = "non_pcie" ,//non_pcie pcie_gen1_100mhzref pcie_gen1_125mhzref pcie_gen2_100mhzref pcie_gen2_125mhzref pcie_gen3_100mhzref pcie_gen3_125mhzref
+ parameter pma_rx_buf_pm_tx_rx_pcie_gen_bitwidth = "pcie_gen3_32b" ,//pcie_gen3_16b pcie_gen3_32b
+ parameter pma_rx_buf_pm_tx_rx_cvp_mode = "cvp_off" ,//cvp_off cvp_on
+ parameter pma_rx_buf_xrx_path_uc_cal_enable = "rx_cal_off" ,//rx_cal_off rx_cal_on
+ parameter pma_rx_buf_xrx_path_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_rx_buf_xrx_path_prot_mode = "unused" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_rx_buf_xrx_path_datarate = "0 bps" ,//NOVAL
+ parameter [7:0] pma_rx_buf_xrx_path_datawidth = 8'd0 ,//0:255
+ parameter pma_rx_buf_xrx_path_pma_rx_divclk_hz = "0" ,//NOVAL
+ parameter pma_tx_buf_datarate = "0 bps" ,//NOVAL
+ parameter pma_tx_buf_prot_mode = "basic_tx" ,//basic_kr_tx basic_tx cei_tx cpri_tx fc_tx gige_tx gpon_tx higig_tx obsai_tx pcie_gen1_tx pcie_gen2_tx pcie_gen3_tx pcie_gen4_tx qpi_tx sata_tx sdi_tx sfi_tx sfp_tx sonet_tx srio_tx unused xaui_tx xfp_tx
+ parameter pma_tx_buf_rx_det = "mode_0" ,//mode_0 mode_1 mode_10 mode_11 mode_12 mode_13 mode_14 mode_15 mode_2 mode_3 mode_4 mode_5 mode_6 mode_7 mode_8 mode_9
+ parameter pma_tx_buf_rx_det_output_sel = "rx_det_pcie_out" ,//rx_det_pcie_out rx_det_qpi_out
+ parameter pma_tx_buf_rx_det_pdb = "rx_det_off" ,//rx_det_off rx_det_on
+ parameter pma_tx_buf_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_tx_buf_user_fir_coeff_ctrl_sel = "ram_ctl" ,//dynamic_ctl ram_ctl
+ parameter pma_tx_buf_xtx_path_prot_mode = "basic_tx" ,//basic_kr_tx basic_tx cei_tx cpri_tx fc_tx gige_tx gpon_tx higig_tx obsai_tx pcie_gen1_tx pcie_gen2_tx pcie_gen3_tx pcie_gen4_tx qpi_tx sata_tx sdi_tx sfi_tx sfp_tx sonet_tx srio_tx unused xaui_tx xfp_tx
+ parameter pma_tx_buf_xtx_path_datarate = "0 bps" ,//NOVAL
+ parameter [7:0] pma_tx_buf_xtx_path_datawidth = 8'd0 ,//0:255
+ parameter [3:0] pma_tx_buf_xtx_path_clock_divider_ratio = 4'd0 ,//0:15
+ parameter pma_tx_buf_xtx_path_pma_tx_divclk_hz = "0" ,//NOVAL
+ parameter pma_tx_buf_xtx_path_tx_pll_clk_hz = "0 hz" ,//NOVAL
+ parameter pma_tx_buf_xtx_path_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_adapt_datarate = "0 bps" ,//NOVAL
+ parameter pma_adapt_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_adapt_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_adapt_adapt_mode = "dfe_vga" ,//ctle ctle_vga ctle_vga_dfe dfe_vga manual
+ parameter pma_cdr_refclk_powerdown_mode = "powerdown" ,//powerdown powerup
+ parameter pma_cdr_refclk_receiver_detect_src = "core_refclk_src" ,//core_refclk_src iqclk_src
+ parameter pma_cdr_refclk_refclk_select = "ref_iqclk0" ,//adj_pll_clk coreclk fixed_clk iqtxrxclk0 iqtxrxclk1 iqtxrxclk2 iqtxrxclk3 iqtxrxclk4 iqtxrxclk5 lvpecl power_down ref_iqclk0 ref_iqclk1 ref_iqclk10 ref_iqclk11 ref_iqclk2 ref_iqclk3 ref_iqclk4 ref_iqclk5 ref_iqclk6 ref_iqclk7 ref_iqclk8 ref_iqclk9
+ parameter pma_rx_deser_clkdiv_source = "vco_bypass_normal" ,//clklow_to_clkdivrx fref_to_clkdivrx vco_bypass_normal
+ parameter pma_rx_deser_clkdivrx_user_mode = "clkdivrx_user_disabled" ,//clkdivrx_user_disabled clkdivrx_user_clkdiv clkdivrx_user_clkdiv_div2 clkdivrx_user_div33 clkdivrx_user_div40 clkdivrx_user_div66
+ parameter pma_rx_deser_pcie_gen = "non_pcie" ,// pcie_gen1_100mhzref|pcie_gen2_100mhzref|pcie_gen3_100mhzref|pcie_gen1_125mhzref|pcie_gen2_125mhzref|pcie_gen3_125mhzref|non_pcie
+ parameter pma_rx_deser_pcie_gen_bitwidth = "pcie_gen3_32b" ,// pcie_gen3_32b|pcie_gen3_16b
+
+ parameter pma_rx_deser_datarate = "0 bps" ,//NOVAL
+ parameter pma_rx_deser_deser_factor = 8 ,//8 10 16 20 32 40 64
+ parameter pma_rx_deser_force_clkdiv_for_testing = "normal_clkdiv" ,//forced_0 forced_1 normal_clkdiv
+ parameter pma_rx_deser_sdclk_enable = "false" ,//false true
+ parameter pma_rx_deser_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_rx_deser_rst_n_adapt_odi = "no_rst_adapt_odi" ,//no_rst_adapt_odi yes_rst_adapt_odi
+ parameter pma_rx_deser_bitslip_bypass = "bs_bypass_no" ,//bs_bypass_no bs_bypass_yes
+ parameter pma_rx_deser_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_cgb_bitslip_enable = "enable_bitslip" ,//disable_bitslip enable_bitslip
+ parameter pma_cgb_bonding_reset_enable = "allow_bonding_reset" ,//allow_bonding_reset disallow_bonding_reset
+ parameter pma_cgb_datarate = "0 bps" ,//NOVAL
+ parameter pma_cgb_pcie_gen3_bitwidth = "pciegen3_wide" ,//pciegen3_narrow pciegen3_wide
+ parameter pma_cgb_prot_mode = "basic_tx" ,//basic_kr_tx basic_tx cei_tx cpri_tx fc_tx gige_tx gpon_tx higig_tx obsai_tx pcie_gen1_tx pcie_gen2_tx pcie_gen3_tx pcie_gen4_tx qpi_tx sata_tx sdi_tx sfi_tx sfp_tx sonet_tx srio_tx unused xaui_tx xfp_tx
+ parameter pma_cgb_ser_mode = "eight_bit" ,//eight_bit forty_bit sixteen_bit sixty_four_bit ten_bit thirty_two_bit twenty_bit
+ parameter pma_cgb_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_cgb_x1_div_m_sel = "divbypass" ,//divby2 divby4 divby8 divbypass
+ parameter pma_cgb_input_select_x1 = "unused" ,//cdr_txpll_b cdr_txpll_t fpll_bot fpll_top hfclk_x6_dn hfclk_x6_up hfclk_xn_dn hfclk_xn_up lcpll_bot lcpll_hs lcpll_top same_ch_txpll unused
+ parameter pma_cgb_input_select_gen3 = "unused" ,//cdr_txpll_b cdr_txpll_t fpll_bot fpll_top hfclk_x6_dn hfclk_x6_up hfclk_xn_dn hfclk_xn_up lcpll_bot lcpll_hs lcpll_top same_ch_txpll unused
+ parameter pma_cgb_input_select_xn = "unused" ,//sel_cgb_loc sel_x6_dn sel_x6_up sel_xn_dn sel_xn_up unused
+ parameter pma_cgb_tx_ucontrol_en = "disable" ,//disable enable
+ parameter pma_rx_dfe_datarate = "0 bps" ,//NOVAL
+ parameter pma_rx_dfe_pdb = "dfe_enable" ,//dfe_enable dfe_powerdown dfe_reset
+ parameter pma_rx_dfe_pdb_fixedtap = "fixtap_dfe_powerdown" ,//fixtap_dfe_enable fixtap_dfe_powerdown
+ parameter pma_rx_dfe_pdb_floattap = "floattap_dfe_powerdown" ,//floattap_dfe_enable floattap_dfe_powerdown
+ parameter pma_rx_dfe_pdb_fxtap4t7 = "fxtap4t7_powerdown" ,//fxtap4t7_enable fxtap4t7_powerdown
+ parameter pma_rx_dfe_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_rx_dfe_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_rx_sd_prot_mode = "basic_rx" ,//basic_kr_rx basic_rx cpri_rx gpon_rx pcie_gen1_rx pcie_gen2_rx pcie_gen3_rx pcie_gen4_rx qpi_rx sata_rx unused
+ parameter pma_rx_sd_sd_output_off = 1 ,//0:28
+ parameter pma_rx_sd_sd_output_on = 1 ,//0:15
+ parameter pma_rx_sd_sd_pdb = "sd_off" ,//sd_off sd_on
+ parameter pma_rx_sd_sd_threshold = 3 ,//0:15
+ parameter pma_rx_sd_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_tx_ser_ser_clk_divtx_user_sel = "divtx_user_33" ,//divtx_user_1 divtx_user_2 divtx_user_33 divtx_user_40 divtx_user_66 divtx_user_off
+ parameter pma_tx_ser_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter pma_tx_ser_prot_mode = "basic_tx" ,//basic_kr_tx basic_tx cei_tx cpri_tx fc_tx gige_tx gpon_tx higig_tx obsai_tx pcie_gen1_tx pcie_gen2_tx pcie_gen3_tx pcie_gen4_tx qpi_tx sata_tx sdi_tx sfi_tx sfp_tx sonet_tx srio_tx unused xaui_tx xfp_tx
+ parameter [2:0] hssi_pipe_gen1_2_elec_idle_delay_val = 3'd0 ,//0:7
+ parameter hssi_pipe_gen1_2_error_replace_pad = "replace_edb" ,//replace_edb replace_pad
+ parameter hssi_pipe_gen1_2_hip_mode = "dis_hip" ,//dis_hip en_hip
+ parameter hssi_pipe_gen1_2_ind_error_reporting = "dis_ind_error_reporting" ,//dis_ind_error_reporting en_ind_error_reporting
+ parameter [2:0] hssi_pipe_gen1_2_phystatus_delay_val = 3'd0 ,//0:7
+ parameter hssi_pipe_gen1_2_phystatus_rst_toggle = "dis_phystatus_rst_toggle" ,//dis_phystatus_rst_toggle en_phystatus_rst_toggle
+ parameter hssi_pipe_gen1_2_pipe_byte_de_serializer_en = "dont_care_bds" ,//dis_bds dont_care_bds en_bds_by_2
+ parameter hssi_pipe_gen1_2_prot_mode = "pipe_g1" ,//basic disabled_prot_mode pipe_g1 pipe_g2 pipe_g3
+ parameter hssi_pipe_gen1_2_rx_pipe_enable = "dis_pipe_rx" ,//dis_pipe_rx en_pipe3_rx en_pipe_rx
+ parameter hssi_pipe_gen1_2_rxdetect_bypass = "dis_rxdetect_bypass" ,//dis_rxdetect_bypass en_rxdetect_bypass
+ parameter hssi_pipe_gen1_2_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_pipe_gen1_2_tx_pipe_enable = "dis_pipe_tx" ,//dis_pipe_tx en_pipe3_tx en_pipe_tx
+ parameter hssi_pipe_gen1_2_txswing = "dis_txswing" ,//dis_txswing en_txswing
+ parameter hssi_common_pld_pcs_interface_dft_clk_out_en = "dft_clk_out_disable" ,//dft_clk_out_disable dft_clk_out_enable
+ parameter hssi_common_pld_pcs_interface_dft_clk_out_sel = "teng_rx_dft_clk" ,//eightg_rx_dft_clk eightg_tx_dft_clk pmaif_dft_clk teng_rx_dft_clk teng_tx_dft_clk
+ parameter hssi_common_pld_pcs_interface_hrdrstctrl_en = "hrst_dis" ,//hrst_dis hrst_en
+ parameter hssi_common_pld_pcs_interface_pcs_testbus_block_sel = "eightg" ,//eightg g3pcs krfec pma_if teng
+ parameter hssi_common_pcs_pma_interface_asn_clk_enable = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_asn_enable = "dis_asn" ,//dis_asn en_asn
+ parameter hssi_common_pcs_pma_interface_block_sel = "eight_g_pcs" ,//eight_g_pcs pcie_gen3
+ parameter hssi_common_pcs_pma_interface_bypass_early_eios = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_pcie_switch = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_pma_ltr = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_pma_sw_done = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_ppm_lock = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_bypass_txdetectrx = "false" ,//false true
+ parameter hssi_common_pcs_pma_interface_cdr_control = "en_cdr_ctrl" ,//dis_cdr_ctrl en_cdr_ctrl
+ parameter hssi_common_pcs_pma_interface_cid_enable = "en_cid_mode" ,//dis_cid_mode en_cid_mode
+ parameter [15:0] hssi_common_pcs_pma_interface_data_mask_count = 16'd2500 ,//0:65535
+ parameter [2:0] hssi_common_pcs_pma_interface_data_mask_count_multi = 3'd1 ,//0:7
+ parameter hssi_common_pcs_pma_interface_dft_observation_clock_selection = "dft_clk_obsrv_tx0" ,//dft_clk_obsrv_asn0 dft_clk_obsrv_asn1 dft_clk_obsrv_clklow dft_clk_obsrv_fref dft_clk_obsrv_hclk dft_clk_obsrv_rx dft_clk_obsrv_tx0 dft_clk_obsrv_tx1 dft_clk_obsrv_tx2 dft_clk_obsrv_tx3 dft_clk_obsrv_tx4
+ parameter [7:0] hssi_common_pcs_pma_interface_early_eios_counter = 8'd50 ,//0:255
+ parameter hssi_common_pcs_pma_interface_force_freqdet = "force_freqdet_dis" ,//force0_freqdet_en force1_freqdet_en force_freqdet_dis
+ parameter hssi_common_pcs_pma_interface_free_run_clk_enable = "true" ,//false true
+ parameter hssi_common_pcs_pma_interface_ignore_sigdet_g23 = "false" ,//false true
+ parameter [6:0] hssi_common_pcs_pma_interface_pc_en_counter = 7'd55 ,//0:127
+ parameter [4:0] hssi_common_pcs_pma_interface_pc_rst_counter = 5'd23 ,//0:31
+ parameter hssi_common_pcs_pma_interface_pcie_hip_mode = "hip_disable" ,//hip_disable hip_enable
+ parameter hssi_common_pcs_pma_interface_ph_fifo_reg_mode = "phfifo_reg_mode_dis" ,//phfifo_reg_mode_dis phfifo_reg_mode_en
+ parameter [5:0] hssi_common_pcs_pma_interface_phfifo_flush_wait = 6'd36 ,//0:63
+ parameter hssi_common_pcs_pma_interface_pipe_if_g3pcs = "pipe_if_8gpcs" ,//pipe_if_8gpcs pipe_if_g3pcs
+ parameter [17:0] hssi_common_pcs_pma_interface_pma_done_counter = 18'd175000 ,//0:262143
+ parameter hssi_common_pcs_pma_interface_pma_if_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_common_pcs_pma_interface_pma_if_dft_val = "dft_0" ,//dft_0 dft_1
+ parameter hssi_common_pcs_pma_interface_ppm_cnt_rst = "ppm_cnt_rst_dis" ,//ppm_cnt_rst_dis ppm_cnt_rst_en
+ parameter hssi_common_pcs_pma_interface_ppm_deassert_early = "deassert_early_dis" ,//deassert_early_dis deassert_early_en
+ parameter hssi_common_pcs_pma_interface_ppm_gen1_2_cnt = "cnt_32k" ,//cnt_32k cnt_64k
+ parameter hssi_common_pcs_pma_interface_ppm_post_eidle_delay = "cnt_200_cycles" ,//cnt_200_cycles cnt_400_cycles
+ parameter hssi_common_pcs_pma_interface_ppmsel = "ppmsel_300" ,//ppmsel_100 ppmsel_1000 ppmsel_125 ppmsel_200 ppmsel_250 ppmsel_2500 ppmsel_300 ppmsel_500 ppmsel_5000 ppmsel_62p5 ppmsel_disable ppm_other
+ parameter hssi_common_pcs_pma_interface_prot_mode = "disable_prot_mode" ,//disable_prot_mode other_protocols pipe_g12 pipe_g3
+ parameter hssi_common_pcs_pma_interface_rxvalid_mask = "rxvalid_mask_en" ,//rxvalid_mask_dis rxvalid_mask_en
+ parameter [11:0] hssi_common_pcs_pma_interface_sigdet_wait_counter = 12'd2500 ,//0:4095
+ parameter [2:0] hssi_common_pcs_pma_interface_sigdet_wait_counter_multi = 3'd1 ,//0:7
+ parameter hssi_common_pcs_pma_interface_sim_mode = "disable" ,//disable enable
+ parameter hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en = "true" ,//false true
+ parameter hssi_common_pcs_pma_interface_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_common_pcs_pma_interface_testout_sel = "ppm_det_test" ,//asn_test pma_pll_test ppm_det_test prbs_gen_test prbs_ver_test rxpmaif_test uhsif_1_test uhsif_2_test uhsif_3_test
+ parameter [3:0] hssi_common_pcs_pma_interface_wait_clk_on_off_timer = 4'd4 ,//0:15
+ parameter [4:0] hssi_common_pcs_pma_interface_wait_pipe_synchronizing = 5'd23 ,//0:31
+ parameter [10:0] hssi_common_pcs_pma_interface_wait_send_syncp_fbkp = 11'd250 ,//0:2047
+ parameter hssi_common_pcs_pma_interface_ppm_det_buckets = "ppm_100_bucket" ,//disable_prot ppm_100_bucket ppm_300_100_bucket ppm_300_bucket
+ parameter hssi_tx_pcs_pma_interface_bypass_pma_txelecidle = "false" ,//false true
+ parameter hssi_tx_pcs_pma_interface_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_tx_pcs_pma_interface_lpbk_en = "disable" ,//disable enable
+ parameter hssi_tx_pcs_pma_interface_master_clk_sel = "master_tx_pma_clk" ,//master_refclk_dig master_tx_pma_clk
+ parameter hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx = "other_prot_mode" ,//other_prot_mode pipe_g12 pipe_g3
+ parameter hssi_tx_pcs_pma_interface_pldif_datawidth_mode = "pldif_data_10bit" ,//pldif_data_10bit pldif_data_8bit
+ parameter hssi_tx_pcs_pma_interface_pma_dw_tx = "pma_8b_tx" ,//pcie_g3_dyn_dw_tx pma_10b_tx pma_16b_tx pma_20b_tx pma_32b_tx pma_40b_tx pma_64b_tx pma_8b_tx
+ parameter hssi_tx_pcs_pma_interface_pma_if_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_tx_pcs_pma_interface_pmagate_en = "pmagate_dis" ,//pmagate_dis pmagate_en
+ parameter hssi_tx_pcs_pma_interface_prbs_clken = "prbs_clk_dis" ,//prbs_clk_dis prbs_clk_en
+ parameter hssi_tx_pcs_pma_interface_prbs_gen_pat = "prbs_gen_dis" ,//prbs_15 prbs_23 prbs_31 prbs_9 prbs_gen_dis
+ parameter hssi_tx_pcs_pma_interface_prbs9_dwidth = "prbs9_64b" ,//prbs9_10b prbs9_64b
+ parameter hssi_tx_pcs_pma_interface_prot_mode_tx = "disabled_prot_mode_tx" ,//disabled_prot_mode_tx eightg_basic_mode_tx eightg_g3_pcie_g3_hip_mode_tx eightg_g3_pcie_g3_pld_mode_tx eightg_only_pld_mode_tx eightg_pcie_g12_hip_mode_tx eightg_pcie_g12_pld_mode_tx pcs_direct_mode_tx prbs_mode_tx sqwave_mode_tx teng_basic_mode_tx teng_krfec_mode_tx teng_sfis_sdi_mode_tx uhsif_direct_mode_tx uhsif_reg_mode_tx
+ parameter hssi_tx_pcs_pma_interface_sq_wave_num = "sq_wave_4" ,//sq_wave_1 sq_wave_4 sq_wave_6 sq_wave_8 sq_wave_default
+ parameter hssi_tx_pcs_pma_interface_sqwgen_clken = "sqwgen_clk_dis" ,//sqwgen_clk_dis sqwgen_clk_en
+ parameter hssi_tx_pcs_pma_interface_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion = "tx_dyn_polinv_dis" ,//tx_dyn_polinv_dis tx_dyn_polinv_en
+ parameter hssi_tx_pcs_pma_interface_tx_pma_data_sel = "pld_dir" ,//block_sel_default directed_uhsif_dat eight_g_pcs pcie_gen3 pld_dir prbs_pat registered_uhsif_dat sq_wave_pat ten_g_pcs
+ parameter hssi_tx_pcs_pma_interface_tx_static_polarity_inversion = "tx_stat_polinv_dis" ,//tx_stat_polinv_dis tx_stat_polinv_en
+ parameter hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock = "uhsif_filt_stepsz_b4lock_4" ,//uhsif_filt_stepsz_b4lock_2 uhsif_filt_stepsz_b4lock_4 uhsif_filt_stepsz_b4lock_6 uhsif_filt_stepsz_b4lock_8
+ parameter [3:0] hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value = 4'd11 ,//0:15
+ parameter hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock = "uhsif_filt_cntthr_b4lock_16" ,//uhsif_filt_cntthr_b4lock_16 uhsif_filt_cntthr_b4lock_24 uhsif_filt_cntthr_b4lock_32 uhsif_filt_cntthr_b4lock_8
+ parameter hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period = "uhsif_dcn_test_period_4" ,//uhsif_dcn_test_period_12 uhsif_dcn_test_period_16 uhsif_dcn_test_period_4 uhsif_dcn_test_period_8
+ parameter hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable = "uhsif_dcn_test_mode_disable" ,//uhsif_dcn_test_mode_disable uhsif_dcn_test_mode_enable
+ parameter hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh = "uhsif_dzt_cnt_thr_4" ,//uhsif_dzt_cnt_thr_2 uhsif_dzt_cnt_thr_4 uhsif_dzt_cnt_thr_6 uhsif_dzt_cnt_thr_8
+ parameter hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable = "uhsif_dzt_enable" ,//uhsif_dzt_disable uhsif_dzt_enable
+ parameter hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window = "uhsif_dzt_obr_win_32" ,//uhsif_dzt_obr_win_16 uhsif_dzt_obr_win_32 uhsif_dzt_obr_win_48 uhsif_dzt_obr_win_64
+ parameter hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size = "uhsif_dzt_skipsz_8" ,//uhsif_dzt_skipsz_12 uhsif_dzt_skipsz_16 uhsif_dzt_skipsz_4 uhsif_dzt_skipsz_8
+ parameter hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel = "uhsif_index_internal" ,//uhsif_index_cram uhsif_index_internal
+ parameter hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin = "uhsif_dcn_margin_4" ,//uhsif_dcn_margin_2 uhsif_dcn_margin_3 uhsif_dcn_margin_4 uhsif_dcn_margin_5
+ parameter [7:0] hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value = 8'd128 ,//0:255
+ parameter hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control = "uhsif_dft_dz_det_val_0" ,//uhsif_dft_dz_det_val_0 uhsif_dft_dz_det_val_1
+ parameter hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control = "uhsif_dft_up_val_0" ,//uhsif_dft_up_val_0 uhsif_dft_up_val_1
+ parameter hssi_tx_pcs_pma_interface_uhsif_enable = "uhsif_disable" ,//uhsif_disable uhsif_enable
+ parameter hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock = "uhsif_lkd_segsz_aflock_2048" ,//uhsif_lkd_segsz_aflock_1024 uhsif_lkd_segsz_aflock_2048 uhsif_lkd_segsz_aflock_4096 uhsif_lkd_segsz_aflock_512
+ parameter hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock = "uhsif_lkd_segsz_b4lock_32" ,//uhsif_lkd_segsz_b4lock_128 uhsif_lkd_segsz_b4lock_16 uhsif_lkd_segsz_b4lock_32 uhsif_lkd_segsz_b4lock_64
+ parameter [3:0] hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value = 4'd8 ,//0:15
+ parameter [3:0] hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value = 4'd8 ,//0:15
+ parameter [3:0] hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value = 4'd3 ,//0:15
+ parameter [3:0] hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value = 4'd3 ,//0:15
+ parameter hssi_rx_pcs_pma_interface_block_sel = "eight_g_pcs" ,//direct_pld eight_g_pcs ten_g_pcs
+ parameter hssi_rx_pcs_pma_interface_channel_operation_mode = "tx_rx_pair_enabled" ,//tx_rx_independent tx_rx_pair_enabled
+ parameter hssi_rx_pcs_pma_interface_clkslip_sel = "pld" ,//pld slip_eight_g_pcs
+ parameter hssi_rx_pcs_pma_interface_lpbk_en = "disable" ,//disable enable
+ parameter hssi_rx_pcs_pma_interface_master_clk_sel = "master_rx_pma_clk" ,//master_refclk_dig master_rx_pma_clk master_tx_pma_clk
+ parameter hssi_rx_pcs_pma_interface_pldif_datawidth_mode = "pldif_data_10bit" ,//pldif_data_10bit pldif_data_8bit
+ parameter hssi_rx_pcs_pma_interface_pma_dw_rx = "pma_8b_rx" ,//pcie_g3_dyn_dw_rx pma_10b_rx pma_16b_rx pma_20b_rx pma_32b_rx pma_40b_rx pma_64b_rx pma_8b_rx
+ parameter hssi_rx_pcs_pma_interface_pma_if_dft_en = "dft_dis" ,//dft_dis dft_en
+ parameter hssi_rx_pcs_pma_interface_pma_if_dft_val = "dft_0" ,//dft_0 dft_1
+ parameter hssi_rx_pcs_pma_interface_prbs_clken = "prbs_clk_dis" ,//prbs_clk_dis prbs_clk_en
+ parameter hssi_rx_pcs_pma_interface_prbs_ver = "prbs_off" ,//prbs_15 prbs_23 prbs_31 prbs_9 prbs_off
+ parameter hssi_rx_pcs_pma_interface_prbs9_dwidth = "prbs9_64b" ,//prbs9_10b prbs9_64b
+ parameter hssi_rx_pcs_pma_interface_prot_mode_rx = "disabled_prot_mode_rx" ,//disabled_prot_mode_rx eightg_basic_mode_rx eightg_g3_pcie_g3_hip_mode_rx eightg_g3_pcie_g3_pld_mode_rx eightg_only_pld_mode_rx eightg_pcie_g12_hip_mode_rx eightg_pcie_g12_pld_mode_rx pcs_direct_mode_rx prbs_mode_rx teng_basic_mode_rx teng_krfec_mode_rx teng_sfis_sdi_mode_rx
+ parameter hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion = "rx_dyn_polinv_dis" ,//rx_dyn_polinv_dis rx_dyn_polinv_en
+ parameter hssi_rx_pcs_pma_interface_rx_lpbk_en = "lpbk_dis" ,//lpbk_dis lpbk_en
+ parameter hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok = "unforce_sig_ok" ,//force_sig_ok unforce_sig_ok
+ parameter hssi_rx_pcs_pma_interface_rx_prbs_mask = "prbsmask128" ,//prbsmask1024 prbsmask128 prbsmask256 prbsmask512
+ parameter hssi_rx_pcs_pma_interface_rx_prbs_mode = "teng_mode" ,//eightg_mode teng_mode
+ parameter hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel = "sel_sig_det" ,//sel_sig_det sel_sig_ok
+ parameter hssi_rx_pcs_pma_interface_rx_static_polarity_inversion = "rx_stat_polinv_dis" ,//rx_stat_polinv_dis rx_stat_polinv_en
+ parameter hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en = "uhsif_lpbk_dis" ,//uhsif_lpbk_dis uhsif_lpbk_en
+ parameter hssi_rx_pcs_pma_interface_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_fifo_tx_pcs_double_write_mode = "double_write_dis" ,//double_write_dis double_write_en
+ parameter hssi_fifo_tx_pcs_prot_mode = "teng_mode" ,//non_teng_mode teng_mode
+ parameter hssi_fifo_rx_pcs_double_read_mode = "double_read_dis" ,//double_read_dis double_read_en
+ parameter hssi_fifo_rx_pcs_prot_mode = "teng_mode" ,//non_teng_mode teng_mode
+ parameter hssi_krfec_rx_pcs_blksync_cor_en = "detect" ,//correct detect
+ parameter hssi_krfec_rx_pcs_bypass_gb = "bypass_dis" ,//bypass_dis bypass_en
+ parameter hssi_krfec_rx_pcs_clr_ctrl = "both_enabled" ,//both_enabled corr_cnt_only uncorr_cnt_only
+ parameter hssi_krfec_rx_pcs_ctrl_bit_reverse = "ctrl_bit_reverse_dis" ,//ctrl_bit_reverse_dis ctrl_bit_reverse_en
+ parameter hssi_krfec_rx_pcs_data_bit_reverse = "data_bit_reverse_dis" ,//data_bit_reverse_dis data_bit_reverse_en
+ parameter hssi_krfec_rx_pcs_dv_start = "with_blklock" ,//with_blklock with_blksync
+ parameter hssi_krfec_rx_pcs_err_mark_type = "err_mark_10g" ,//err_mark_10g err_mark_40g
+ parameter hssi_krfec_rx_pcs_error_marking_en = "err_mark_dis" ,//err_mark_dis err_mark_en
+ parameter hssi_krfec_rx_pcs_low_latency_en = "disable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_lpbk_mode = "lpbk_dis" ,//lpbk_dis lpbk_en
+ parameter [7:0] hssi_krfec_rx_pcs_parity_invalid_enum = 8'd8 ,//0:255
+ parameter [3:0] hssi_krfec_rx_pcs_parity_valid_num = 4'd4 ,//0:15
+ parameter hssi_krfec_rx_pcs_pipeln_blksync = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_descrm = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_errcorrect = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_errtrap_ind = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_errtrap_lfsr = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_errtrap_loc = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_errtrap_pat = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_gearbox = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_syndrm = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_pipeln_trans_dec = "enable" ,//disable enable
+ parameter hssi_krfec_rx_pcs_prot_mode = "disable_mode" ,//basic_mode disable_mode fortyg_basekr_mode teng_1588_basekr_mode teng_basekr_mode
+ parameter hssi_krfec_rx_pcs_receive_order = "receive_lsb" ,//receive_lsb receive_msb
+ parameter hssi_krfec_rx_pcs_rx_testbus_sel = "overall" ,//blksync blksync_cntrs decoder_master_sm decoder_master_sm_cntrs decoder_rd_sm errtrap_ind1 errtrap_ind2 errtrap_ind3 errtrap_ind4 errtrap_ind5 errtrap_loc errtrap_pat1 errtrap_pat2 errtrap_pat3 errtrap_pat4 errtrap_sm fast_search fast_search_cntrs gb_and_trans overall syndrm1 syndrm2 syndrm_sm
+ parameter hssi_krfec_rx_pcs_signal_ok_en = "sig_ok_dis" ,//sig_ok_dis sig_ok_en
+ parameter hssi_krfec_rx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_pipe_gen3_bypass_rx_detection_enable = "false" ,//false true
+ parameter [2:0] hssi_pipe_gen3_bypass_rx_preset = 3'd0 ,//0:7
+ parameter hssi_pipe_gen3_bypass_rx_preset_enable = "false" ,//false true
+ parameter [17:0] hssi_pipe_gen3_bypass_tx_coefficent = 18'd0 ,//0:262143
+ parameter hssi_pipe_gen3_bypass_tx_coefficent_enable = "false" ,//false true
+ parameter [2:0] hssi_pipe_gen3_elecidle_delay_g3 = 3'd6 ,//0:7
+ parameter hssi_pipe_gen3_ind_error_reporting = "dis_ind_error_reporting" ,//dis_ind_error_reporting en_ind_error_reporting
+ parameter hssi_pipe_gen3_mode = "pipe_g1" ,//disable_pcs pipe_g1 pipe_g2 pipe_g3
+ parameter [2:0] hssi_pipe_gen3_phy_status_delay_g12 = 3'd5 ,//0:7
+ parameter [2:0] hssi_pipe_gen3_phy_status_delay_g3 = 3'd5 ,//0:7
+ parameter hssi_pipe_gen3_phystatus_rst_toggle_g12 = "dis_phystatus_rst_toggle" ,//dis_phystatus_rst_toggle en_phystatus_rst_toggle
+ parameter hssi_pipe_gen3_phystatus_rst_toggle_g3 = "dis_phystatus_rst_toggle_g3" ,//dis_phystatus_rst_toggle_g3 en_phystatus_rst_toggle_g3
+ parameter hssi_pipe_gen3_rate_match_pad_insertion = "dis_rm_fifo_pad_ins" ,//dis_rm_fifo_pad_ins en_rm_fifo_pad_ins
+ parameter hssi_pipe_gen3_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_pipe_gen3_test_out_sel = "disable_test_out" ,//disable_test_out pipe_ctrl_test_out pipe_test_out1 pipe_test_out2 pipe_test_out3 rx_test_out tx_test_out
+ parameter hssi_gen3_tx_pcs_mode = "gen3_func" ,//disable_pcs gen3_func
+ parameter hssi_gen3_tx_pcs_reverse_lpbk = "rev_lpbk_en" ,//rev_lpbk_dis rev_lpbk_en
+ parameter hssi_gen3_tx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter [4:0] hssi_gen3_tx_pcs_tx_bitslip = 5'd0 ,//0:31
+ parameter hssi_gen3_tx_pcs_tx_gbox_byp = "bypass_gbox" ,//bypass_gbox enable_gbox
+ parameter hssi_gen3_rx_pcs_block_sync = "enable_block_sync" ,//bypass_block_sync enable_block_sync
+ parameter hssi_gen3_rx_pcs_block_sync_sm = "enable_blk_sync_sm" ,//disable_blk_sync_sm enable_blk_sync_sm
+ parameter hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn = "enable" ,//disable enable
+ parameter hssi_gen3_rx_pcs_lpbk_force = "lpbk_frce_dis" ,//lpbk_frce_dis lpbk_frce_en
+ parameter hssi_gen3_rx_pcs_mode = "gen3_func" ,//disable_pcs gen3_func
+ parameter hssi_gen3_rx_pcs_rate_match_fifo = "enable_rm_fifo_600ppm" ,//bypass_rm_fifo enable_rm_fifo_0ppm enable_rm_fifo_600ppm
+ parameter hssi_gen3_rx_pcs_rate_match_fifo_latency = "regular_latency" ,//low_latency regular_latency
+ parameter hssi_gen3_rx_pcs_reverse_lpbk = "rev_lpbk_en" ,//rev_lpbk_dis rev_lpbk_en
+ parameter hssi_gen3_rx_pcs_rx_b4gb_par_lpbk = "b4gb_par_lpbk_dis" ,//b4gb_par_lpbk_dis b4gb_par_lpbk_en
+ parameter hssi_gen3_rx_pcs_rx_force_balign = "en_force_balign" ,//dis_force_balign en_force_balign
+ parameter hssi_gen3_rx_pcs_rx_ins_del_one_skip = "ins_del_one_skip_en" ,//ins_del_one_skip_dis ins_del_one_skip_en
+ parameter [3:0] hssi_gen3_rx_pcs_rx_num_fixed_pat = 4'd8 ,//0:15
+ parameter hssi_gen3_rx_pcs_rx_test_out_sel = "rx_test_out0" ,//rx_test_out0 rx_test_out1
+ parameter hssi_gen3_rx_pcs_sup_mode = "user_mode" ,//engineering_mode user_mode
+ parameter hssi_10g_rx_pcs_advanced_user_mode = "disable" ,//disable enable
+ parameter hssi_10g_tx_pcs_advanced_user_mode = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_10g_advanced_user_mode_rx = "disable" ,//disable enable
+ parameter hssi_rx_pld_pcs_interface_hd_chnl_transparent_pcs_rx = "disable" ,//disable enable
+ parameter hssi_tx_pld_pcs_interface_hd_10g_advanced_user_mode_tx = "disable" ,//disable enable
+ parameter pma_adapt_adp_1s_ctle_bypass = "radp_1s_ctle_bypass_0" ,//radp_1s_ctle_bypass_0|radp_1s_ctle_bypass_1
+ parameter pma_adapt_adp_4s_ctle_bypass = "radp_4s_ctle_bypass_0" ,//radp_4s_ctle_bypass_0|radp_4s_ctle_bypass_1
+ parameter pma_adapt_adp_ctle_adapt_cycle_window = "radp_ctle_adapt_cycle_window_6" ,//radp_ctle_adapt_cycle_window_0|radp_ctle_adapt_cycle_window_1|radp_ctle_adapt_cycle_window_2|radp_ctle_adapt_cycle_window_3|radp_ctle_adapt_cycle_window_4|radp_ctle_adapt_cycle_window_5|radp_ctle_adapt_cycle_window_6|radp_ctle_adapt_cycle_window_7
+ parameter pma_adapt_adp_ctle_en = "radp_ctle_disable" ,//radp_ctle_disable|radp_ctle_enable
+ parameter pma_adapt_adp_dfe_fltap_bypass = "radp_dfe_fltap_bypass_0" ,//radp_dfe_fltap_bypass_0|radp_dfe_fltap_bypass_1
+ parameter pma_adapt_adp_dfe_fltap_en = "radp_dfe_fltap_disable" ,//radp_dfe_fltap_disable|radp_dfe_fltap_enable
+ parameter pma_adapt_adp_dfe_fxtap_bypass = "radp_dfe_fxtap_bypass_0" ,//radp_dfe_fxtap_bypass_0|radp_dfe_fxtap_bypass_1
+ parameter pma_adapt_adp_dfe_fxtap_en = "radp_dfe_fxtap_disable" ,//radp_dfe_fxtap_disable|radp_dfe_fxtap_enable
+ parameter pma_adapt_adp_dfe_fxtap_hold_en = "radp_dfe_fxtap_not_held" ,//radp_dfe_fxtap_not_held|radp_dfe_fxtap_hold
+ parameter pma_adapt_adp_dfe_mode = "radp_dfe_mode_0" ,//radp_dfe_mode_0|radp_dfe_mode_1|radp_dfe_mode_2|radp_dfe_mode_3|radp_dfe_mode_4|radp_dfe_mode_5|radp_dfe_mode_6|radp_dfe_mode_7
+ parameter pma_adapt_adp_mode = "radp_mode_0" ,//radp_mode_0|radp_mode_1|radp_mode_2|radp_mode_3|radp_mode_4|radp_mode_5|radp_mode_6|radp_mode_7|radp_mode_8|radp_mode_9|radp_mode_10|radp_mode_11|radp_mode_12|radp_mode_13|radp_mode_14|radp_mode_15
+ parameter pma_adapt_adp_onetime_dfe = "radp_onetime_dfe_0" ,//radp_onetime_dfe_0|radp_onetime_dfe_1
+ parameter pma_adapt_adp_vga_bypass = "radp_vga_bypass_0" ,//radp_vga_bypass_0|radp_vga_bypass_1
+ parameter pma_adapt_adp_vga_en = "radp_vga_disable" ,//radp_vga_disable|radp_vga_enable
+ parameter pma_adapt_adp_vref_bypass = "radp_vref_bypass_0" ,//radp_vref_bypass_0|radp_vref_bypass_1
+ parameter pma_adapt_adp_vref_en = "radp_vref_disable" ,//radp_vref_disable|radp_vref_enable
+ parameter pma_adapt_odi_dfe_spec_en = "rodi_dfe_spec_en_0" ,//rodi_dfe_spec_en_0|rodi_dfe_spec_en_1
+ parameter pma_rx_dfe_dft_en = "dft_disable" ,//dft_disable|dft_enalbe
+ parameter pma_rx_odi_step_ctrl_sel = "feedback_mode" ,//dprio_mode|feedback_mode|jm_mode
+
+ parameter hip_cal_en = "disable" //Indicates whether HIP is enabled or not. Valid values: disable, enable
+ ) (
+ //------------------------
+ // Common Ports
+ //------------------------
+ // Resets
+ input wire [channels-1:0] tx_analogreset, // TX PMA reset
+ input wire [channels-1:0] tx_digitalreset, // TX PCS reset
+ input wire [channels-1:0] rx_analogreset, // RX PMA reset
+ input wire [channels-1:0] rx_digitalreset, // RX PCS reset
+
+ output wire [channels-1:0] tx_cal_busy, // TX calibration in progress
+ output wire [channels-1:0] rx_cal_busy, // RX calibration in progress
+ output wire [channels-1:0] avmm_busy,
+
+ // TX serial clocks
+ input wire [channels-1:0] tx_serial_clk0, // clkout from external PLL
+ input wire [channels-1:0] tx_serial_clk1, // clkout from external PLL
+ input wire [channels-1:0] tx_serial_clk2, // clkout from external PLL
+ input wire [channels-1:0] tx_serial_clk3, // clkout from external PLL
+ // Bonding clocks
+ input wire [channels*6-1:0] tx_bonding_clocks, // Bonding clock bundle from Master CGB
+ input wire [channels*6-1:0] tx_bonding_clocks1, // Bonding clock bundle from Master CGB
+ input wire [channels*6-1:0] tx_bonding_clocks2, // Bonding clock bundle from Master CGB
+ input wire [channels*6-1:0] tx_bonding_clocks3, // Bonding clock bundle from Master CGB
+ // CDR reference clocks
+ input wire rx_cdr_refclk0, // RX PLL reference clock 0
+ input wire rx_cdr_refclk1, // RX PLL reference clock 1
+ input wire rx_cdr_refclk2, // RX PLL reference clock 2
+ input wire rx_cdr_refclk3, // RX PLL reference clock 3
+ input wire rx_cdr_refclk4, // RX PLL reference clock 4
+ // TX and RX serial ports
+ output wire [channels-1:0] tx_serial_data, // TX serial data output to HSSI pin
+ input wire [channels-1:0] rx_serial_data, // RX serial data input from HSSI pin
+ // PMA control ports
+ input wire [channels-1:0] rx_pma_clkslip, // Slip RX PMA by one clock cycle
+ input wire [channels-1:0] rx_seriallpbken, // Enable TX-to-RX loopback
+ input wire [channels-1:0] rx_set_locktodata,// Set CDR to manual lock to data mode
+ input wire [channels-1:0] rx_set_locktoref, // Set CDR to manual lock to reference mode
+ // PMA status ports
+ output wire [channels-1:0] rx_is_lockedtoref, // CDR is in lock to reference mode
+ output wire [channels-1:0] rx_is_lockedtodata, // CDR is in lock to data mode
+
+ // QPI specific ports
+ input wire [channels-1:0] rx_pma_qpipulldn,
+ input wire [channels-1:0] tx_pma_qpipulldn,
+ input wire [channels-1:0] tx_pma_qpipullup,
+ input wire [channels-1:0] tx_pma_txdetectrx,
+ input wire [channels-1:0] tx_pma_elecidle, // TX electrical idle
+ output wire [channels-1:0] tx_pma_rxfound,
+
+ // Common ports
+ //PPM detector clocks
+ output wire [channels-1:0] rx_clklow, // RX Low freq recovered clock, PPM detector specific
+ output wire [channels-1:0] rx_fref, // RX PFD reference clock, PPM detector specific
+
+ //-------------------------
+ // Common datapath ports
+ //-------------------------
+ // Clock ports
+ input wire [channels-1:0] tx_coreclkin, // TX parallel clock input
+ input wire [channels-1:0] rx_coreclkin, // RX parallel clock input
+ output wire [channels-1:0] tx_clkout, // TX Parallel clock output
+ output wire [channels-1:0] rx_clkout, // RX parallel clock output
+ output wire [channels-1:0] tx_pma_clkout, // TX clock output from PMA
+ output wire [channels-1:0] rx_pma_clkout, // RX clock output from PMA
+ output wire [channels-1:0] tx_pma_div_clkout, // TX clock output from PMA (programmable divider)
+ output wire [channels-1:0] rx_pma_div_clkout, // RX clock output from PMA (programmable divider)
+ output wire [channels-1:0] tx_pma_iqtxrx_clkout, // TX clock output from PMA to iqtxrx lines (for cascading)
+ output wire [channels-1:0] rx_pma_iqtxrx_clkout, // RX clock output from PMA to iqtxrx lines (for cascading)
+ // parallel data ports
+ input wire [channels*128-1:0] tx_parallel_data, // PCS TX parallel data interface
+ output wire [channels*128-1:0] rx_parallel_data, // PCS RX parallel data interface
+ input wire [channels*18-1:0] tx_control, // PCS TX control data
+ output wire [channels*20-1:0] rx_control, // PCS RX control data
+ // Polarity inversion
+ input wire [channels-1:0] tx_polinv, // TX polarity inversion
+ input wire [channels-1:0] rx_polinv, // RX polarity inversion
+ // Bitslip
+ input wire [channels-1:0] rx_bitslip, // RX bitslip (Standard and Enhanced PCS). Asynchronous. Rising edge triggers single bit slip.
+ // Adaptation
+ input wire [channels-1:0] rx_adapt_reset, // For adaptation engine control: user needs to apply reset first
+ input wire [channels-1:0] rx_adapt_start, // For adaptation engine control: user, after releasing reset, needs to apply start
+ // PRBS
+ input wire [channels-1:0] rx_prbs_err_clr,
+ output wire [channels-1:0] rx_prbs_done,
+ output wire [channels-1:0] rx_prbs_err,
+ // Ultra high-speed interface
+ input wire [channels-1:0] tx_uhsif_clk, // Ultra high-speed interface clock input
+ output wire [channels-1:0] tx_uhsif_clkout, // Ultra high-speed interface clock output
+ output wire [channels-1:0] tx_uhsif_lock, // Ultra high-speed interface status
+
+ //-------------------------
+ // Standard datapath ports
+ //-------------------------
+ // Phase compensation FIFOs
+ output wire [channels-1:0] tx_std_pcfifo_full, //Phase comp. FIFO full
+ output wire [channels-1:0] tx_std_pcfifo_empty, //Phase comp. FIFO empty
+ output wire [channels-1:0] rx_std_pcfifo_full, //Phase comp. FIFO full
+ output wire [channels-1:0] rx_std_pcfifo_empty, //Phase comp. FIFO empty
+ // Bit reversal
+ input wire [channels-1:0] rx_std_bitrev_ena,
+ // Byte (de)serializer
+ input wire [channels-1:0] rx_std_byterev_ena,
+ // Bit slip
+ input wire [channels*5-1:0] tx_std_bitslipboundarysel,
+ output wire [channels*5-1:0] rx_std_bitslipboundarysel,
+ // Word align/Deterministic SM
+ input wire [channels-1:0] rx_std_wa_patternalign,
+ input wire [channels-1:0] rx_std_wa_a1a2size,
+ // Rate Match FIFO
+ output wire [channels-1:0] rx_std_rmfifo_full, //Rate Match FIFO full
+ output wire [channels-1:0] rx_std_rmfifo_empty, //Rate Match FIFO empty
+ // PCIe
+ output wire [channels-1:0] rx_std_signaldetect,
+
+ //-------------------------
+ // Enhanced datapath ports
+ //-------------------------
+ // TxFIFO/RxFIFO
+ input wire [channels-1:0] tx_enh_data_valid,
+//input wire [channels-1:0] tx_enh_wordslip, // Engg mode feature so not enabled
+ output wire [channels-1:0] tx_enh_fifo_full,
+ output wire [channels-1:0] tx_enh_fifo_pfull,
+ output wire [channels-1:0] tx_enh_fifo_empty,
+ output wire [channels-1:0] tx_enh_fifo_pempty,
+ output wire [channels*4-1:0] tx_enh_fifo_cnt,
+
+ input wire [channels-1:0] rx_enh_fifo_rd_en,
+ output wire [channels-1:0] rx_enh_data_valid,
+ output wire [channels-1:0] rx_enh_fifo_full,
+ output wire [channels-1:0] rx_enh_fifo_pfull,
+ output wire [channels-1:0] rx_enh_fifo_empty,
+ output wire [channels-1:0] rx_enh_fifo_pempty,
+ output wire [channels-1:0] rx_enh_fifo_del,
+ output wire [channels-1:0] rx_enh_fifo_insert,
+ output wire [channels*5-1:0] rx_enh_fifo_cnt,
+ output wire [channels-1:0] rx_enh_fifo_align_val,
+ input wire [channels-1:0] rx_enh_fifo_align_clr, // Active high. User Align clear signal for RX FIFO when it's used as a deskew FIFO in Interlaken mode. When it asserts, FIFO is reset and it looks for new alignment pattern. It's don't care for non-Interlaken mode
+
+ // Frame generator/sync
+ output wire [channels-1:0] tx_enh_frame,
+ input wire [channels-1:0] tx_enh_frame_burst_en,
+ input wire [channels*2-1:0] tx_enh_frame_diag_status,
+
+ output wire [channels-1:0] rx_enh_frame,
+ output wire [channels-1:0] rx_enh_frame_lock,
+ output wire [channels*2-1:0] rx_enh_frame_diag_status,
+
+ // CRC chk
+ output wire [channels-1:0] rx_enh_crc32_err,
+
+ // BER
+ output wire [channels-1:0] rx_enh_highber,
+ input wire [channels-1:0] rx_enh_highber_clr_cnt,
+
+ // 64B/66B specific 10GBASER signal
+ input wire [channels-1:0] rx_enh_clr_errblk_count,
+
+ // Block sync
+ output wire [channels-1:0] rx_enh_blk_lock,
+
+ // Bit slip
+ input wire [channels*7-1:0] tx_enh_bitslip,
+
+ //-------------------------
+ // HIP ports
+ //-------------------------
+ input wire [channels*64-1:0] tx_hip_data,
+ output wire [channels*51-1:0] rx_hip_data,
+ output wire hip_pipe_pclk,
+ output wire hip_fixedclk,
+ output wire [channels -1:0] hip_frefclk,
+ output wire [channels*8 -1:0] hip_ctrl,
+ output wire [channels -1:0] hip_cal_done,
+
+ //-----
+ // PCIe/PIPE
+ //-----
+ input wire ltssm_detect_quiet,
+ input wire ltssm_detect_active,
+ input wire ltssm_rcvr_phase_two,
+ input wire hip_reduce_counters,
+ input wire [1:0] pcie_rate,
+ input wire [(enable_hip?channels*2:2)-1:0] pipe_rate,
+ input wire [1:0] pipe_sw_done,
+ output wire [1:0] pipe_sw,
+ input wire pipe_hclk_in,
+ output wire pipe_hclk_out,
+ input wire [channels*18-1:0] pipe_g3_txdeemph,
+ input wire [channels*3 -1:0] pipe_g3_rxpresethint,
+ input wire [channels*3 -1:0] pipe_rx_eidleinfersel,
+ output wire [channels -1:0] pipe_rx_elecidle,
+ input wire [channels -1:0] pipe_rx_polarity,
+
+ // -----
+ // optional reset ack
+ // -----
+ output reg [channels - 1:0] tx_analogreset_ack,
+ output reg [channels - 1:0] rx_analogreset_ack,
+
+ //--------------------------
+ // Reconfiguration interface
+ //--------------------------
+ input wire [(rcfg_enable&&rcfg_shared ? 1 : channels)-1:0] reconfig_clk,
+ input wire [(rcfg_enable&&rcfg_shared ? 1 : channels)-1:0] reconfig_reset,
+ input wire [(rcfg_enable&&rcfg_shared ? 1 : channels)-1:0] reconfig_write,
+ input wire [(rcfg_enable&&rcfg_shared ? 1 : channels)-1:0] reconfig_read,
+ input wire [(rcfg_enable&&rcfg_shared ? (10+altera_xcvr_native_a10_functions_h::clogb2_alt_xcvr_native_a10(channels-1)) : (10*channels))-1:0] reconfig_address,
+ input wire [(rcfg_enable&&rcfg_shared ? 1 : channels)*32-1:0] reconfig_writedata,
+ output wire [(rcfg_enable&&rcfg_shared ? 1 : channels)*32-1:0] reconfig_readdata,
+ output wire [(rcfg_enable&&rcfg_shared ? 1 : channels)-1:0] reconfig_waitrequest
+);
+
+localparam RCFG_ADDR_BITS = 10;
+
+localparam xcvr_native_mode = (duplex_mode == "duplex") ? "mode_duplex"
+ : (duplex_mode == "tx") ? "mode_tx_only"
+ : "mode_rx_only";
+localparam calibration_en = enable_calibration ? "enable" : "disable";
+localparam arbiter_ctrl = enable_calibration ? "uc" : "pld";
+localparam cal_done = enable_calibration ? "cal_done_deassert" : "cal_done_assert";
+localparam avmm_busy_en = rcfg_separate_avmm_busy ? "enable" : "disable";
+
+localparam enable_pcs_bonding = (bonded_mode == "pma_pcs") ? 1 : 0;
+localparam lcl_pcs_bonding_master = enable_pcs_bonding ? pcs_bonding_master : channels / 2;
+localparam lcl_adme_assgn_map = {" assignments {dataRate ",adme_data_rate," protMode ",adme_prot_mode," device_revision ",device_revision,"}"};
+
+
+// Use model
+// 1. By default, PHY will connect analog resets and enable sequencing
+// lcl_enable_analog_resets = 1; lcl_enable_reset_sequence = 1
+// 2. Users have to use option in the GUI to disconnect analog resets for a PHY configuration or
+// Users have to use ALTERA_XCVR_A10_DISCONNECT_ANALOG_RESETS to disconnect resets for the entire design
+// lcl_enable_analog_resets = enable_analog_resets (0); lcl_enable_reset_sequence = enable_reset_sequence (0)
+// 3. Users have to use ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS to restore old behavior of resets
+// lcl_enable_analog_resets = 1; lcl_enable_reset_sequence = 0
+
+localparam lcl_enable_analog_resets =
+`ifdef ALTERA_RESERVED_QIS
+ `ifdef ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS
+ 1; // MACRO override for quartus synthesis. Connect resets
+ `else
+ `ifdef ALTERA_XCVR_A10_DISCONNECT_ANALOG_RESETS
+ 0;
+ `else
+ enable_analog_resets;
+ `endif
+ `endif
+`else
+ 1; // not synthesis. Connect resets
+`endif // (NOT ALTERA_RESERVED_QIS)
+
+localparam lcl_enable_reset_sequence =
+`ifdef ALTERA_RESERVED_QIS
+ `ifdef ALTERA_XCVR_A10_ENABLE_ANALOG_RESETS
+ 0; // MACRO override for quartus synthesis
+ `else
+ `ifdef ALTERA_XCVR_A10_DISCONNECT_ANALOG_RESETS
+ 0;
+ `else
+ enable_reset_sequence;
+ `endif
+ `endif
+`else
+ 0; // not synthesis
+`endif // (NOT ALTERA_RESERVED_QIS)
+
+localparam lcl_disable_pipe_rate_retry =
+`ifdef ALTERA_XCVR_A10_PIPE_RATE_RETRY_BYPASS
+ 1 ; //MACRO override to disable the retry circuit
+`else
+ 0 ; //default, enable retry
+`endif
+
+// AVMM reconfiguration interface signals
+wire [channels-1:0] avmm_clk;
+wire [channels-1:0] avmm_reset;
+wire [channels-1:0] avmm_write;
+wire [channels-1:0] avmm_read;
+wire [channels*RCFG_ADDR_BITS-1:0] avmm_address;
+wire [channels*8-1:0] avmm_writedata;
+wire [channels*8-1:0] avmm_readdata;
+wire [channels-1:0] avmm_waitrequest;
+
+// wires for control signals from embedded debug
+wire [channels-1:0] int_rx_prbs_err_clr;
+wire [channels-1:0] int_rx_set_locktoref;
+wire [channels-1:0] int_rx_set_locktodata;
+wire [channels-1:0] int_rx_seriallpbken;
+wire [channels-1:0] int_tx_analogreset;
+wire [channels-1:0] tx_analogreset_to_pma;
+wire [channels-1:0] int_tx_digitalreset;
+wire [channels-1:0] int_rx_analogreset;
+wire [channels-1:0] rx_analogreset_to_pma;
+wire [channels-1:0] int_rx_digitalreset;
+
+// Wires for disconnecting tx_analogreset and rx_analogreset
+wire [channels-1:0] tx_analogreset_input;
+wire [channels-1:0] rx_analogreset_input;
+
+wire [channels-1:0] int_tx_cal_busy_mask; // TX calibration in progress
+wire [channels-1:0] int_rx_cal_busy_mask; // RX calibration in progress
+
+wire [channels-1:0] pld_cal_done;
+
+wire [1:0] int_pcie_rate_sw;
+
+assign tx_cal_busy = ~pld_cal_done & int_tx_cal_busy_mask;
+assign rx_cal_busy = ~pld_cal_done & int_rx_cal_busy_mask;
+assign int_pcie_rate_sw = (enable_hip) ? pcie_rate : pipe_rate;
+
+//***************************************************************************
+//************* Embedded JTAG, AVMM and Embedded Streamer Expansion *********
+alt_xcvr_native_rcfg_opt_logic_sfv7jkq #(
+ .dbg_user_identifier ( dbg_user_identifier ),
+ .duplex_mode ( duplex_mode ),
+ .dbg_embedded_debug_enable ( dbg_embedded_debug_enable ),
+ .dbg_capability_reg_enable ( dbg_capability_reg_enable ),
+ .dbg_prbs_soft_logic_enable ( dbg_prbs_soft_logic_enable ),
+ .dbg_odi_soft_logic_enable ( dbg_odi_soft_logic_enable ),
+ .dbg_stat_soft_logic_enable ( dbg_stat_soft_logic_enable ),
+ .dbg_ctrl_soft_logic_enable ( dbg_ctrl_soft_logic_enable ),
+ .enable_pcie_dfe_ip ( enable_pcie_dfe_ip ),
+ .disable_continuous_dfe ( disable_continuous_dfe ),
+ .sim_reduced_counters ( sim_reduced_counters ),
+ .enable_hip ( enable_hip ),
+ .CHANNELS ( channels ),
+ .ADDR_BITS ( RCFG_ADDR_BITS ),
+ .ADME_SLAVE_MAP ( "altera_xcvr_native_a10" ),
+ .ADME_ASSGN_MAP ( lcl_adme_assgn_map ),
+ .RECONFIG_SHARED ( rcfg_enable && rcfg_shared ),
+ .JTAG_ENABLED ( rcfg_enable && rcfg_jtag_enable ),
+ .RCFG_EMB_STRM_ENABLED ( rcfg_enable && rcfg_emb_strm_enable ),
+ .RCFG_PROFILE_CNT ( rcfg_profile_cnt )
+) alt_xcvr_native_optional_rcfg_logic (
+ // User reconfig interface ports
+ .reconfig_clk ( reconfig_clk ),
+ .reconfig_reset ( reconfig_reset ),
+ .reconfig_write ( reconfig_write ),
+ .reconfig_read ( reconfig_read ),
+ .reconfig_address ( reconfig_address ),
+ .reconfig_writedata ( reconfig_writedata ),
+ .reconfig_readdata ( reconfig_readdata ),
+ .reconfig_waitrequest ( reconfig_waitrequest ),
+
+ // AVMM ports to transceiver
+ .avmm_clk ( avmm_clk ),
+ .avmm_reset ( avmm_reset ),
+ .avmm_write ( avmm_write ),
+ .avmm_read ( avmm_read ),
+ .avmm_address ( avmm_address ),
+ .avmm_writedata ( avmm_writedata ),
+ .avmm_readdata ( avmm_readdata ),
+ .avmm_waitrequest ( avmm_waitrequest ),
+
+ // input signals for PCIe DFE IP
+ .ltssm_detect_quiet ( ltssm_detect_quiet ),
+ .ltssm_detect_active ( ltssm_detect_active ),
+ .ltssm_rcvr_phase_two ( ltssm_rcvr_phase_two ),
+ .pcie_rate ( int_pcie_rate_sw ),
+ .hip_reduce_counters ( hip_reduce_counters ),
+
+ // input signals from the PHYfor PRBS error accumulation
+ .prbs_err_signal ( rx_prbs_err ),
+ .prbs_done_signal ( rx_prbs_done ),
+
+ // input rx_clkout for PRBS
+ .in_rx_clkout ( rx_clkout ),
+
+ // input status signals from the transceiver
+ .in_rx_is_lockedtoref ( rx_is_lockedtoref ),
+ .in_rx_is_lockedtodata ( rx_is_lockedtodata ),
+ .in_tx_cal_busy ( tx_cal_busy ),
+ .in_rx_cal_busy ( rx_cal_busy ),
+ .in_avmm_busy ( avmm_busy ),
+
+ // input control signals from the core
+ .in_rx_prbs_err_clr ( rx_prbs_err_clr ),
+ .in_set_rx_locktoref ( rx_set_locktoref ),
+ .in_set_rx_locktodata ( rx_set_locktodata ),
+ .in_en_serial_lpbk ( rx_seriallpbken ),
+ .in_rx_analogreset ( rx_analogreset_input ),
+ .in_rx_digitalreset ( rx_digitalreset ),
+ .in_tx_analogreset ( tx_analogreset_input ),
+ .in_tx_digitalreset ( tx_digitalreset ),
+
+ // output control signals to the phy
+ .out_prbs_err_clr ( int_rx_prbs_err_clr ),
+ .out_set_rx_locktoref ( int_rx_set_locktoref ),
+ .out_set_rx_locktodata ( int_rx_set_locktodata ),
+ .out_en_serial_lpbk ( int_rx_seriallpbken ),
+ .out_rx_analogreset ( int_rx_analogreset ),
+ .out_rx_digitalreset ( int_rx_digitalreset ),
+ .out_tx_analogreset ( int_tx_analogreset ),
+ .out_tx_digitalreset ( int_tx_digitalreset ),
+ .out_tx_cal_busy_mask ( int_tx_cal_busy_mask ),
+ .out_rx_cal_busy_mask ( int_rx_cal_busy_mask )
+);
+
+//***************** End Embedded JTAG and AVMM Expansion ********************
+//***************************************************************************
+
+
+// Bonding wires
+wire [4:0] bond_pcs10g_in_bot [channels-1:0];
+wire [4:0] bond_pcs10g_in_top [channels-1:0];
+wire [4:0] bond_pcs10g_out_bot [channels-1:0];
+wire [4:0] bond_pcs10g_out_top [channels-1:0];
+
+wire [12:0] bond_pcs8g_in_bot [channels-1:0];
+wire [12:0] bond_pcs8g_in_top [channels-1:0];
+wire [12:0] bond_pcs8g_out_bot [channels-1:0];
+wire [12:0] bond_pcs8g_out_top [channels-1:0];
+
+wire [11:0] bond_pmaif_in_bot [channels-1:0];
+wire [11:0] bond_pmaif_in_top [channels-1:0];
+wire [11:0] bond_pmaif_out_bot [channels-1:0];
+wire [11:0] bond_pmaif_out_top [channels-1:0];
+
+wire [channels*20-1:0] pld_testbus_for_rate;
+genvar ig;
+
+generate
+ for(ig=0;ig<channels;ig=ig+1) begin : g_xcvr_native_insts
+ wire [1:0] int_pipe_sw_done;
+ wire [1:0] int_pipe_sw;
+ wire int_pipe_hclk_out;
+ wire int_hip_pipe_pclk;
+ wire int_hip_fixedclk;
+ wire [1:0] int_pipe_rate;
+
+ wire int_in_pld_8g_g3_rx_pld_rst_n;
+ wire int_in_pld_8g_g3_tx_pld_rst_n;
+ wire int_in_pld_10g_krfec_rx_pld_rst_n;
+ wire int_in_pld_10g_krfec_tx_pld_rst_n;
+ wire int_in_pld_pmaif_rx_pld_rst_n;
+ wire int_in_pld_pmaif_tx_pld_rst_n;
+
+ assign int_in_pld_8g_g3_rx_pld_rst_n = ~int_rx_digitalreset[ig];
+ assign int_in_pld_8g_g3_tx_pld_rst_n = ~int_tx_digitalreset[ig];
+
+ // If we are in HIP
+ if(enable_hip) begin
+ assign int_pipe_rate = pipe_rate[ig*2+:2];
+ assign int_in_pld_10g_krfec_rx_pld_rst_n = 1'b0;
+ assign int_in_pld_10g_krfec_tx_pld_rst_n = 1'b0;
+ assign int_in_pld_pmaif_rx_pld_rst_n = 1'b0;
+ assign int_in_pld_pmaif_tx_pld_rst_n = 1'b0;
+ end else begin
+
+
+ // If its the master channel, assign the pld_rate
+ if(ig == lcl_pcs_bonding_master) begin: g_pipe_pld_rate_master_channel
+
+ // Use a macro to bypass the retry circuit
+ if(hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx == "pipe_g2_tx" && lcl_disable_pipe_rate_retry == 0) begin: g_alt_xcvr_native_pipe_retry_g2
+
+ alt_xcvr_native_pipe_retry alt_xcvr_native_pipe_retry_inst (
+ /*input */ .pipe_pclk (tx_coreclkin[ig]),
+ /*input */ .tx_digitalreset (tx_digitalreset[ig]),
+ /*input [1:0] */ .pld_rate (pipe_rate),
+ /*input [19:0] */ .pld_testbus (pld_testbus_for_rate[20*ig+:20]),
+ /*output reg [1:0] */ .rate_retry (int_pipe_rate)
+ );
+
+ end else if (hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx == "pipe_g3_tx") begin: g_pipe_rate_g3
+
+ (* altera_attribute = " -name MAX_WIRES_FOR_CORE_PERIPHERY_TRANSFER 2; -name GLOBAL_SIGNAL OFF -from \"twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interface_pld_pcs_tx_clk_out\" " *)
+ reg [1:0] int_pipe_rate_reg = 2'b0;
+
+ (* altera_attribute = " -name GLOBAL_SIGNAL OFF -from \"twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interface_pld_pcs_tx_clk_out\" " *)
+ reg [7:0] int_pipe_rate_sync = 8'b0;
+
+ (* altera_attribute = " -name GLOBAL_SIGNAL OFF -from \"twentynm_xcvr_native:g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5:inst_twentynm_pcs|w_hssi_tx_pld_pcs_interface_pld_pcs_tx_clk_out\" " *)
+ reg [2:0] int_pipe_rate_delay = 3'b0;
+
+ assign int_pipe_rate = int_pipe_rate_reg;
+ always@(posedge tx_clkout[ig]) begin
+ // shift register to set a synchronizer
+ int_pipe_rate_sync[5:0] <= {int_pipe_rate_sync[3:0], pipe_rate};
+
+ // if the last stage of the synchronizer is not the same as the
+ // one before it, run a counter then udpate the final register stage
+ if(int_pipe_rate_sync[7:6] == int_pipe_rate_sync[5:4]) begin
+ int_pipe_rate_delay <= 3'b0;
+ end else begin
+
+ // if the counter is full (7-bit count) update the final stage
+ if(&int_pipe_rate_delay) begin
+ int_pipe_rate_sync[7:6] <= int_pipe_rate_sync[5:4];
+ end else begin
+ int_pipe_rate_delay <= int_pipe_rate_delay + 3'b1;
+ end
+ end
+
+ int_pipe_rate_reg <= int_pipe_rate_sync[7:6];
+ end
+ end else begin: g_no_pipe_rate
+ assign int_pipe_rate = pipe_rate;
+ end
+
+ end else begin: g_pipe_pld_rate_non_master
+ assign int_pipe_rate = 2'b0;
+ end
+
+ assign int_in_pld_10g_krfec_rx_pld_rst_n = ~int_rx_digitalreset[ig];
+ assign int_in_pld_10g_krfec_tx_pld_rst_n = ~int_tx_digitalreset[ig];
+ assign int_in_pld_pmaif_rx_pld_rst_n = ~int_rx_digitalreset[ig];
+ assign int_in_pld_pmaif_tx_pld_rst_n = ~int_tx_digitalreset[ig];
+ end
+
+ // Option 1: enable reset sequencing and analog resets, insert reset endpoint for TX and RX
+ if(lcl_enable_analog_resets == 1 && lcl_enable_reset_sequence == 1 && !enable_hip) begin: g_analog_resets_default
+ // connect resets
+ assign tx_analogreset_input[ig] = tx_analogreset[ig];
+ assign rx_analogreset_input[ig] = rx_analogreset[ig];
+
+ if(duplex_mode == "duplex" || duplex_mode == "tx") begin: g_tre_tx_endpoint
+ altera_transceiver_reset_endpoint reset_endpoint_tx (
+ .tre_reset_req(int_tx_analogreset[ig]),
+ .tre_reset_in(tx_analogreset_to_pma[ig])
+ );
+
+ always @(*) begin
+ tx_analogreset_ack[ig] = tx_analogreset_to_pma[ig];
+ end
+
+ end else begin: g_tre_tx_no_endpoint
+ assign tx_analogreset_to_pma[ig] = 1'b0;
+
+ always @(*) begin
+ tx_analogreset_ack[ig] = 1'b0;
+ end
+
+ end
+
+ if(duplex_mode == "duplex" || duplex_mode == "rx") begin: g_tre_rx_endpoint
+ altera_transceiver_reset_endpoint reset_endpoint_rx (
+ .tre_reset_req(int_rx_analogreset[ig]),
+ .tre_reset_in(rx_analogreset_to_pma[ig])
+ );
+
+ always @(*) begin
+ rx_analogreset_ack[ig] = rx_analogreset_to_pma[ig];
+ end
+
+ end else begin: g_tre_rx_no_end_point
+ assign rx_analogreset_to_pma[ig] = 1'b0;
+
+ always @(*) begin
+ rx_analogreset_ack[ig] = 1'b0;
+ end
+
+ end
+
+ end else if(lcl_enable_analog_resets == 0 && lcl_enable_reset_sequence == 0 && !enable_hip) begin: g_analog_resets_disconnect // Option 2: disconnect analog resets
+ assign tx_analogreset_input[ig] = 1'b0;
+ assign rx_analogreset_input[ig] = 1'b0;
+ assign tx_analogreset_to_pma[ig] = int_tx_analogreset[ig];
+ assign rx_analogreset_to_pma[ig] = int_rx_analogreset[ig];
+
+ always @(*) begin
+ tx_analogreset_ack[ig] = 1'b0;
+ rx_analogreset_ack[ig] = 1'b0;
+ end
+
+ end else begin: g_analog_resets_connect // Option 3: restore old style reset connection
+ assign tx_analogreset_input[ig] = tx_analogreset[ig];
+ assign rx_analogreset_input[ig] = rx_analogreset[ig];
+ assign tx_analogreset_to_pma[ig] = int_tx_analogreset[ig];
+ assign rx_analogreset_to_pma[ig] = int_rx_analogreset[ig];
+
+ `ifdef ALTERA_RESERVED_QIS
+ always @(*) begin
+ tx_analogreset_ack[ig] = tx_analogreset_to_pma[ig];
+ rx_analogreset_ack[ig] = rx_analogreset_to_pma[ig];
+ end
+ `else
+ initial begin
+ tx_analogreset_ack[ig] = 1'b0;
+ rx_analogreset_ack[ig] = 1'b0;
+ end
+
+ always @(*) begin
+ #70000;
+ tx_analogreset_ack[ig] = tx_analogreset_to_pma[ig];
+ rx_analogreset_ack[ig] = rx_analogreset_to_pma[ig];
+ end
+ `endif
+ end
+
+ // PCIe HIP clock selections
+ if((ig == 0 && enable_hip && channels == 2) ||
+ (ig == 3 && enable_hip && (channels == 4 || channels == 8)) ||
+ (ig == 0 && (!enable_hip || channels == 1))) begin
+ assign hip_pipe_pclk = int_hip_pipe_pclk;
+ assign hip_fixedclk = int_hip_fixedclk;
+ end
+
+ // PCIe rate switch signals
+ if(ig == lcl_pcs_bonding_master) begin
+ assign int_pipe_sw_done = pipe_sw_done;
+ assign pipe_sw = int_pipe_sw;
+ assign pipe_hclk_out = int_pipe_hclk_out;
+ end else begin
+ assign int_pipe_sw_done = 2'b00;
+ end
+ // Bonding connections
+ if(enable_pcs_bonding) begin : g_bonding_connections
+ if(ig == (channels-1)) begin
+ assign bond_pcs10g_in_top[ig] = 5'd0;
+ assign bond_pcs8g_in_top[ig] = 13'd0;
+ assign bond_pmaif_in_top[ig] = 12'd0;
+ end else begin
+ assign bond_pcs10g_in_top[ig] = bond_pcs10g_out_bot[ig+1];
+ assign bond_pcs8g_in_top[ig] = bond_pcs8g_out_bot[ig+1];
+ assign bond_pmaif_in_top[ig] = bond_pmaif_out_bot[ig+1];
+ end
+
+ if(ig == 0) begin
+ assign bond_pcs10g_in_bot[ig] = 5'd0;
+ assign bond_pcs8g_in_bot[ig] = 13'd0;
+ assign bond_pmaif_in_bot[ig] = 12'd0;
+ end else begin
+ assign bond_pcs10g_in_bot[ig] = bond_pcs10g_out_top[ig-1];
+ assign bond_pcs8g_in_bot[ig] = bond_pcs8g_out_top[ig-1];
+ assign bond_pmaif_in_bot[ig] = bond_pmaif_out_top[ig-1];
+ end
+ end else begin : g_no_bonding_connections
+ assign bond_pcs10g_in_top[ig] = 5'd0;
+ assign bond_pcs10g_in_bot[ig] = 5'd0;
+ assign bond_pcs8g_in_top[ig] = 13'd0;
+ assign bond_pcs8g_in_bot[ig] = 13'd0;
+ assign bond_pmaif_in_top[ig] = 12'd0;
+ assign bond_pmaif_in_bot[ig] = 12'd0;
+ end
+ // End bonding connections
+
+ localparam [3:0] lcl_pma_tx_buf_mcgb_location_for_pcie = altera_xcvr_native_a10_functions_h::get_mcgb_location_alt_xcvr_native_a10(lcl_pcs_bonding_master, ig);
+
+ // Channel level bonding parameters
+ localparam lcl_hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx =
+ (hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx == "individual_tx") ? "individual_tx"
+ : (ig < lcl_pcs_bonding_master) ? "ctrl_slave_blw_tx"
+ : (ig > lcl_pcs_bonding_master) ? "ctrl_slave_abv_tx"
+ : "ctrl_master_tx";
+
+ localparam lcl_hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx =
+ (hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx == "individual_rx") ? "individual_rx"
+ : (ig < lcl_pcs_bonding_master) ? "ctrl_slave_blw_rx"
+ : (ig > lcl_pcs_bonding_master) ? "ctrl_slave_abv_rx"
+ : "ctrl_master_rx";
+
+ localparam lcl_hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding =
+ (hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx != "pcie_g1_capable_tx" && hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx != "pcie_g2_capable_tx" && hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx != "pcie_g3_capable_tx") ? "individual"
+ : (hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx == "individual_tx") ? "individual"
+ : (ig < lcl_pcs_bonding_master) ? "ctrl_slave_blw"
+ : (ig > lcl_pcs_bonding_master) ? "ctrl_slave_abv"
+ : "ctrl_master";
+ localparam lcl_hssi_common_pcs_pma_interface_bypass_pma_sw_done =
+ (hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx == "pcie_g1_capable_tx" || hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx == "pcie_g2_capable_tx" || hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx == "pcie_g3_capable_tx") ?
+ ((lcl_hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding == "ctrl_slave_blw" || lcl_hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding == "ctrl_slave_abv") ? "true"
+ : "false") : "false";
+
+ // PCS level bonding parameters
+ localparam lcl_hssi_tx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_tx = lcl_hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx;
+ localparam lcl_hssi_rx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_rx = lcl_hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx;
+ localparam lcl_hssi_tx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_tx = lcl_hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx;
+ localparam lcl_hssi_rx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_rx = lcl_hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx;
+ localparam lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding = lcl_hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding;
+
+
+ localparam lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_consumption = enable_pcs_bonding ?
+ (ig < lcl_pcs_bonding_master) ? "bundled_slave_below"
+ : (ig > lcl_pcs_bonding_master) ? "bundled_slave_above"
+ : "bundled_master"
+ : "individual";
+ localparam lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption = (lcl_hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx == "individual_rx")? "individual"
+ : (ig < lcl_pcs_bonding_master) ? "bundled_slave_below"
+ : (ig > lcl_pcs_bonding_master) ? "bundled_slave_above"
+ : "bundled_master";
+
+ localparam lcl_hssi_10g_tx_pcs_ctrl_plane_bonding = enable_pcs_bonding ?
+ (ig < lcl_pcs_bonding_master) ? "ctrl_slave_blw"
+ : (ig > lcl_pcs_bonding_master) ? "ctrl_slave_abv"
+ : "ctrl_master"
+ : "individual";
+ localparam [7:0] lcl_hssi_10g_tx_pcs_comp_cnt = enable_pcs_bonding ? altera_xcvr_native_a10_functions_h::get_comp_cnt_alt_xcvr_native_a10(channels, lcl_pcs_bonding_master, ig)
+ : 8'd0;
+
+ localparam lcl_pma_cgb_select_done_master_or_slave = enable_pcs_bonding ? "choose_master_pcie_sw_done" : "choose_slave_pcie_sw_done";
+
+ // following parameters were assigned auto_single before wrapper files were removed
+ localparam lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_compensation = (hssi_8g_rx_pcs_byte_deserializer=="en_bds_by_4") ? "en_compensation" : "dis_compensation";
+ localparam lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_distribution = (lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_consumption=="bundled_master") ? "master_chnl_distr" : "not_master_chnl_distr";
+ localparam lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_distribution = (lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption=="bundled_master") ? "master_chnl_distr" : "not_master_chnl_distr";
+ localparam lcl_hssi_8g_rx_pcs_auto_speed_nego = (((hssi_8g_rx_pcs_prot_mode=="pipe_g3")&&((lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption=="individual")||(lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption=="bundled_master")))) ?
+ "en_asn_g2_freq_scal" :
+ (((hssi_8g_rx_pcs_prot_mode=="pipe_g2")&&((lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption=="individual")||(lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption=="bundled_master")))) ?
+ "en_asn_g2_freq_scal" :
+ "dis_asn";
+
+ localparam lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_compensation = ((hssi_8g_tx_pcs_byte_serializer=="en_bs_by_4")) ? "en_compensation" : "dis_compensation";
+ localparam lcl_hssi_8g_tx_pcs_auto_speed_nego_gen2 = (((hssi_8g_tx_pcs_prot_mode=="pipe_g2")&&((lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_consumption=="individual")||(lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_consumption=="bundled_master")))) ?
+ "en_asn_g2_freq_scal" :
+ "dis_asn_g2";
+
+ localparam lcl_hssi_10g_tx_pcs_compin_sel = ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="individual")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_master")) ?
+ "compin_master" :
+ ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_blw")) ?
+ "compin_slave_bot" :
+ ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "compin_slave_top" :
+ "compin_default";
+ localparam lcl_hssi_10g_tx_pcs_distdwn_master = ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="individual")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_master")) ?
+ "distdwn_master_en" :
+ ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_blw")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "distdwn_master_dis" :
+ "distdwn_master_dis";
+ localparam lcl_hssi_10g_tx_pcs_distup_master = ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="individual")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_master")) ?
+ "distup_master_en" :
+ ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_blw")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "distup_master_dis" :
+ "distup_master_dis";
+ localparam lcl_hssi_10g_tx_pcs_indv = ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="individual")) ?
+ "indv_en" :
+ ((lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_blw")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_master")||(lcl_hssi_10g_tx_pcs_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "indv_dis" :
+ "indv_dis";
+ localparam lcl_hssi_10g_tx_pcs_dv_bond = ((lcl_hssi_10g_tx_pcs_indv=="indv_dis")) ? "dv_bond_en" : "dv_bond_dis";
+
+ localparam lcl_hssi_common_pcs_pma_interface_cp_cons_sel = ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="individual")||(lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_master")) ?
+ "cp_cons_master" :
+ ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_blw")) ?
+ "cp_cons_slave_blw" :
+ ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "cp_cons_slave_abv" :
+ "cp_cons_default";
+ localparam lcl_hssi_common_pcs_pma_interface_cp_dwn_mstr = ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="individual")||(lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_master")) ?
+ "true" :
+ ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_blw")||(lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "false" :
+ "true";
+ localparam lcl_hssi_common_pcs_pma_interface_cp_up_mstr = ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="individual")||(lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_master")) ?
+ "true" :
+ ((lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_blw")||(lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding=="ctrl_slave_abv")) ?
+ "false" :
+ "true";
+
+ // String to binary conversions
+ localparam [127:0] temp_lcl_hssi_10g_tx_pcs_pseudo_seed_a = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(hssi_10g_tx_pcs_pseudo_seed_a);
+ localparam [127:0] temp_lcl_hssi_10g_tx_pcs_pseudo_seed_b = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(hssi_10g_tx_pcs_pseudo_seed_b);
+ localparam [127:0] temp_lcl_hssi_8g_rx_pcs_wa_pd_data = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(hssi_8g_rx_pcs_wa_pd_data);
+ localparam [127:0] temp_lcl_pma_tx_buf_xtx_path_pma_tx_divclk_hz = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(pma_tx_buf_xtx_path_pma_tx_divclk_hz);
+ localparam [127:0] temp_lcl_pma_rx_buf_xrx_path_pma_rx_divclk_hz = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(pma_rx_buf_xrx_path_pma_rx_divclk_hz);
+ localparam [127:0] temp_lcl_pma_tx_buf_xtx_path_tx_pll_clk_hz = altera_xcvr_native_a10_functions_h::str_2_bin_alt_xcvr_native_a10(pma_tx_buf_xtx_path_tx_pll_clk_hz);
+ localparam [57:0] lcl_hssi_10g_tx_pcs_pseudo_seed_a = altera_xcvr_native_a10_functions_h::set_10g_scrm_seed_user_alt_xcvr_native_a10(hssi_10g_tx_pcs_prot_mode,temp_lcl_hssi_10g_tx_pcs_pseudo_seed_a [57:0],ig); // randomization per channel for interlaken
+ localparam [57:0] lcl_hssi_10g_tx_pcs_pseudo_seed_b = temp_lcl_hssi_10g_tx_pcs_pseudo_seed_b [57:0];
+ localparam [39:0] lcl_hssi_8g_rx_pcs_wa_pd_data = temp_lcl_hssi_8g_rx_pcs_wa_pd_data [39:0];
+ localparam [31:0] lcl_pma_tx_buf_xtx_path_pma_tx_divclk_hz = temp_lcl_pma_tx_buf_xtx_path_pma_tx_divclk_hz[31:0];
+ localparam [31:0] lcl_pma_rx_buf_xrx_path_pma_rx_divclk_hz = temp_lcl_pma_rx_buf_xrx_path_pma_rx_divclk_hz[31:0];
+ localparam [31:0] lcl_pma_tx_buf_xtx_path_tx_pll_clk_hz = temp_lcl_pma_tx_buf_xtx_path_tx_pll_clk_hz[31:0];
+
+
+ twentynm_xcvr_native #(
+
+ .device_revision(device_revision),
+
+ // nf_pcs parameters
+ .xcvr_native_mode (xcvr_native_mode),
+ .bonding_master_ch (0),
+ .bonded_lanes (1),
+ // nf_xcvr_avmm parameters
+ .avmm_interfaces (1),
+ .rcfg_enable (rcfg_enable),
+ .enable_avmm (1),
+ .arbiter_ctrl (arbiter_ctrl),
+ .calibration_en (calibration_en),
+ .avmm_busy_en (avmm_busy_en),
+ .hip_cal_en (hip_cal_en),
+ .cal_done (cal_done),
+
+
+ // Overridden parameters for pcie
+ .pma_tx_buf_mcgb_location_for_pcie(lcl_pma_tx_buf_mcgb_location_for_pcie),
+
+ // Overridden bonding parameters
+ .hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx(lcl_hssi_tx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_tx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx(lcl_hssi_rx_pld_pcs_interface_hd_chnl_ctrl_plane_bonding_rx),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding (lcl_hssi_tx_pld_pcs_interface_hd_pmaif_ctrl_plane_bonding ),
+ .hssi_tx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_tx (lcl_hssi_tx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_tx ),
+ .hssi_rx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_rx (lcl_hssi_rx_pld_pcs_interface_hd_10g_ctrl_plane_bonding_rx ),
+ .hssi_tx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_tx (lcl_hssi_tx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_tx ),
+ .hssi_rx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_rx (lcl_hssi_rx_pld_pcs_interface_hd_8g_ctrl_plane_bonding_rx ),
+
+ .hssi_8g_rx_pcs_ctrl_plane_bonding_compensation (lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_compensation),
+ .hssi_8g_rx_pcs_ctrl_plane_bonding_consumption (lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_consumption ),
+ .hssi_8g_rx_pcs_ctrl_plane_bonding_distribution (lcl_hssi_8g_rx_pcs_ctrl_plane_bonding_distribution),
+ .hssi_8g_rx_pcs_auto_speed_nego (lcl_hssi_8g_rx_pcs_auto_speed_nego ),
+
+ .hssi_8g_tx_pcs_ctrl_plane_bonding_compensation (lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_compensation),
+ .hssi_8g_tx_pcs_ctrl_plane_bonding_consumption (lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_consumption ),
+ .hssi_8g_tx_pcs_ctrl_plane_bonding_distribution (lcl_hssi_8g_tx_pcs_ctrl_plane_bonding_distribution),
+ .hssi_8g_tx_pcs_auto_speed_nego_gen2 (lcl_hssi_8g_tx_pcs_auto_speed_nego_gen2 ),
+
+ .hssi_10g_tx_pcs_ctrl_plane_bonding (lcl_hssi_10g_tx_pcs_ctrl_plane_bonding),
+ .hssi_10g_tx_pcs_comp_cnt (lcl_hssi_10g_tx_pcs_comp_cnt ),
+ .hssi_10g_tx_pcs_compin_sel (lcl_hssi_10g_tx_pcs_compin_sel ),
+ .hssi_10g_tx_pcs_distdwn_bypass_pipeln ("distdwn_bypass_pipeln_dis" ),
+ .hssi_10g_tx_pcs_distdwn_master (lcl_hssi_10g_tx_pcs_distdwn_master ),
+ .hssi_10g_tx_pcs_distup_bypass_pipeln ("distup_bypass_pipeln_dis" ),
+ .hssi_10g_tx_pcs_distup_master (lcl_hssi_10g_tx_pcs_distup_master ),
+ .hssi_10g_tx_pcs_dv_bond (lcl_hssi_10g_tx_pcs_dv_bond ),
+ .hssi_10g_tx_pcs_indv (lcl_hssi_10g_tx_pcs_indv ),
+
+ .hssi_common_pcs_pma_interface_ctrl_plane_bonding (lcl_hssi_common_pcs_pma_interface_ctrl_plane_bonding),
+ .hssi_common_pcs_pma_interface_cp_cons_sel (lcl_hssi_common_pcs_pma_interface_cp_cons_sel ),
+ .hssi_common_pcs_pma_interface_cp_dwn_mstr (lcl_hssi_common_pcs_pma_interface_cp_dwn_mstr ),
+ .hssi_common_pcs_pma_interface_cp_up_mstr (lcl_hssi_common_pcs_pma_interface_cp_up_mstr ),
+
+ // Overridden parameters for twentynm_hssi_pma_cdr_refclk_select_mux
+ .pma_cdr_refclk_inclk0_logical_to_physical_mapping ( "ref_iqclk0" ),
+ .pma_cdr_refclk_inclk1_logical_to_physical_mapping ( (cdr_refclk_cnt > 1) ? "ref_iqclk1" : "power_down"),
+ .pma_cdr_refclk_inclk2_logical_to_physical_mapping ( (cdr_refclk_cnt > 2) ? "ref_iqclk2" : "power_down"),
+ .pma_cdr_refclk_inclk3_logical_to_physical_mapping ( (cdr_refclk_cnt > 3) ? "ref_iqclk3" : "power_down"),
+ .pma_cdr_refclk_inclk4_logical_to_physical_mapping ( (cdr_refclk_cnt > 4) ? "ref_iqclk4" : "power_down"),
+ .pma_cgb_scratch0_x1_clock_src( (bonded_mode == "not_bonded") ? "fpll_bot" : "unused"),
+ .pma_cgb_scratch1_x1_clock_src(((bonded_mode == "not_bonded") && (plls > 1)) ? "lcpll_bot" : "unused"),
+ .pma_cgb_scratch2_x1_clock_src(((bonded_mode == "not_bonded") && (plls > 2)) ? "fpll_top" : "unused"),
+ .pma_cgb_scratch3_x1_clock_src(((bonded_mode == "not_bonded") && (plls > 3)) ? "lcpll_top" : "unused"),
+ //.pma_cgb_scratch0_bonded_clock_src( ((bonded_mode == "pma_only") || (bonded_mode == "pma_pcs"))?
+ // "fpll_bot" : "unused"),
+ //.pma_cgb_scratch1_bonded_clock_src((((bonded_mode == "pma_only") || (bonded_mode == "pma_pcs")) && (number_physical_bonding_clocks > 1)) ?
+ // "lcpll_bot" : "unused"),
+ //.pma_cgb_scratch2_bonded_clock_src((((bonded_mode == "pma_only") || (bonded_mode == "pma_pcs")) && (number_physical_bonding_clocks > 2)) ?
+ // "fpll_top" : "unused"),
+ //.pma_cgb_scratch3_bonded_clock_src((((bonded_mode == "pma_only") || (bonded_mode == "pma_pcs")) && (number_physical_bonding_clocks > 3)) ?
+ // "lcpll_top" : "unused"),
+
+ // parameters for twentynm_hssi_pma_adaptation
+ // parameters for twentynm_hssi_pma_cdr_refclk_select_mux
+ //.pma_cdr_refclk_receiver_detect_src (pma_cdr_refclk_receiver_detect_src),
+ .pma_cdr_refclk_refclk_select (pma_cdr_refclk_refclk_select),
+ .pma_cdr_refclk_powerdown_mode (pma_cdr_refclk_powerdown_mode),
+ // parameters for twentynm_hssi_pma_channel_pll
+ .cdr_pll_atb_select_control (cdr_pll_atb_select_control),
+ .cdr_pll_bbpd_data_pattern_filter_select (cdr_pll_bbpd_data_pattern_filter_select),
+ .cdr_pll_bw_sel (cdr_pll_bw_sel),
+ .cdr_pll_cdr_odi_select (cdr_pll_cdr_odi_select),
+ .cdr_pll_cgb_div (cdr_pll_cgb_div),
+ .cdr_pll_chgpmp_current_pd (cdr_pll_chgpmp_current_pd),
+ .cdr_pll_chgpmp_current_pfd (cdr_pll_chgpmp_current_pfd),
+ .cdr_pll_chgpmp_replicate (cdr_pll_chgpmp_replicate),
+ .cdr_pll_chgpmp_testmode (cdr_pll_chgpmp_testmode),
+ .cdr_pll_clklow_mux_select (cdr_pll_clklow_mux_select),
+ .cdr_pll_diag_loopback_enable (cdr_pll_diag_loopback_enable),
+ .cdr_pll_disable_up_dn (cdr_pll_disable_up_dn),
+ .cdr_pll_fb_select (cdr_pll_fb_select),
+ .cdr_pll_fref_clklow_div (cdr_pll_fref_clklow_div),
+ .cdr_pll_fref_mux_select (cdr_pll_fref_mux_select),
+ .cdr_pll_gpon_lck2ref_control (cdr_pll_gpon_lck2ref_control),
+ .cdr_pll_iqclk_mux_sel (cdr_pll_iqclk_mux_sel),
+ .cdr_pll_is_cascaded_pll (cdr_pll_is_cascaded_pll),
+ .cdr_pll_lck2ref_delay_control (cdr_pll_lck2ref_delay_control),
+ .cdr_pll_lpd_counter (cdr_pll_lpd_counter),
+ .cdr_pll_lpfd_counter (cdr_pll_lpfd_counter),
+ .cdr_pll_lf_resistor_pd (cdr_pll_lf_resistor_pd),
+ .cdr_pll_lf_resistor_pfd (cdr_pll_lf_resistor_pfd),
+ .cdr_pll_lf_ripple_cap (cdr_pll_lf_ripple_cap),
+ .cdr_pll_loop_filter_bias_select (cdr_pll_loop_filter_bias_select),
+ .cdr_pll_loopback_mode (cdr_pll_loopback_mode),
+ .cdr_pll_ltd_ltr_micro_controller_select (cdr_pll_ltd_ltr_micro_controller_select),
+ .cdr_pll_m_counter (cdr_pll_m_counter),
+ .cdr_pll_n_counter (cdr_pll_n_counter),
+ .cdr_pll_n_counter_scratch (cdr_pll_n_counter_scratch),
+ .cdr_pll_output_clock_frequency (cdr_pll_output_clock_frequency),
+ .cdr_pll_pcie_gen (cdr_pll_pcie_gen),
+ .cdr_pll_set_cdr_input_freq_range (cdr_pll_set_cdr_input_freq_range),
+ .cdr_pll_chgpmp_current_dn_trim (cdr_pll_chgpmp_current_dn_trim),
+ .cdr_pll_chgpmp_up_pd_trim_double (cdr_pll_chgpmp_up_pd_trim_double),
+ .cdr_pll_chgpmp_current_up_pd (cdr_pll_chgpmp_current_up_pd),
+ .cdr_pll_chgpmp_current_up_trim (cdr_pll_chgpmp_current_up_trim),
+ .cdr_pll_chgpmp_dn_pd_trim_double (cdr_pll_chgpmp_dn_pd_trim_double),
+ .cdr_pll_cal_vco_count_length (cdr_pll_cal_vco_count_length),
+ .cdr_pll_chgpmp_current_dn_pd (cdr_pll_chgpmp_current_dn_pd),
+ .cdr_pll_pd_fastlock_mode (cdr_pll_pd_fastlock_mode),
+ .cdr_pll_pd_l_counter (cdr_pll_pd_l_counter),
+ .cdr_pll_pfd_l_counter (cdr_pll_pfd_l_counter),
+ .cdr_pll_pma_width (cdr_pll_pma_width),
+ .cdr_pll_primary_use (cdr_pll_primary_use),
+ .cdr_pll_reference_clock_frequency (cdr_pll_reference_clock_frequency),
+// .cdr_pll_requires_gt_capable_channel (cdr_pll_requires_gt_capable_channel ),
+ .cdr_pll_reverse_serial_loopback (cdr_pll_reverse_serial_loopback),
+ .cdr_pll_set_cdr_vco_reset (cdr_pll_set_cdr_vco_reset),
+ .cdr_pll_set_cdr_vco_speed (cdr_pll_set_cdr_vco_speed),
+ .cdr_pll_set_cdr_vco_speed_pciegen3 (cdr_pll_set_cdr_vco_speed_pciegen3),
+ .cdr_pll_set_cdr_v2i_enable (cdr_pll_set_cdr_v2i_enable),
+ .cdr_pll_txpll_hclk_driver_enable (cdr_pll_txpll_hclk_driver_enable),
+ .cdr_pll_vco_overrange_voltage (cdr_pll_vco_overrange_voltage),
+ .cdr_pll_vco_underrange_voltage (cdr_pll_vco_underrange_voltage),
+ .cdr_pll_uc_ro_cal (cdr_pll_uc_ro_cal),
+ .cdr_pll_vco_freq (cdr_pll_vco_freq),
+ .cdr_pll_set_cdr_vco_speed_fix (cdr_pll_set_cdr_vco_speed_fix),
+ .cdr_pll_auto_reset_on (cdr_pll_auto_reset_on),
+ .cdr_pll_cdr_phaselock_mode (cdr_pll_cdr_phaselock_mode),
+ .cdr_pll_cdr_powerdown_mode (cdr_pll_cdr_powerdown_mode),
+ .cdr_pll_initial_settings (cdr_pll_initial_settings),
+ // parameters for pma_adapt
+ .pma_adapt_adapt_mode (pma_adapt_adapt_mode),
+ .pma_adapt_adp_1s_ctle_bypass (pma_adapt_adp_1s_ctle_bypass),
+ .pma_adapt_adp_4s_ctle_bypass (pma_adapt_adp_4s_ctle_bypass),
+ .pma_adapt_adp_ctle_adapt_cycle_window (pma_adapt_adp_ctle_adapt_cycle_window),
+ .pma_adapt_adp_ctle_en (pma_adapt_adp_ctle_en),
+ .pma_adapt_adp_dfe_fltap_bypass (pma_adapt_adp_dfe_fltap_bypass),
+ .pma_adapt_adp_dfe_fltap_en (pma_adapt_adp_dfe_fltap_en),
+ .pma_adapt_adp_dfe_fxtap_bypass (pma_adapt_adp_dfe_fxtap_bypass),
+ .pma_adapt_adp_dfe_fxtap_en (pma_adapt_adp_dfe_fxtap_en),
+ .pma_adapt_adp_dfe_fxtap_hold_en (pma_adapt_adp_dfe_fxtap_hold_en),
+ .pma_adapt_adp_dfe_mode (pma_adapt_adp_dfe_mode),
+ .pma_adapt_adp_mode (pma_adapt_adp_mode),
+ .pma_adapt_adp_onetime_dfe (pma_adapt_adp_onetime_dfe),
+ .pma_adapt_adp_vga_bypass (pma_adapt_adp_vga_bypass),
+ .pma_adapt_adp_vga_en (pma_adapt_adp_vga_en),
+ .pma_adapt_adp_vref_bypass (pma_adapt_adp_vref_bypass),
+ .pma_adapt_adp_vref_en (pma_adapt_adp_vref_en),
+ .pma_adapt_odi_dfe_spec_en (pma_adapt_odi_dfe_spec_en),
+ // parameters for twentynm_hssi_pma_rx_buf
+ .pma_rx_buf_bypass_eqz_stages_234 (pma_rx_buf_bypass_eqz_stages_234),
+ .pma_rx_buf_diag_lp_en (pma_rx_buf_diag_lp_en),
+ .pma_rx_buf_qpi_enable (pma_rx_buf_qpi_enable),
+ .pma_rx_buf_rx_refclk_divider (pma_rx_buf_rx_refclk_divider),
+ .pma_rx_buf_loopback_modes (pma_rx_buf_loopback_modes),
+ .pma_rx_buf_refclk_en (pma_rx_buf_refclk_en),
+ .pma_rx_buf_pm_tx_rx_pcie_gen (pma_rx_buf_pm_tx_rx_pcie_gen),
+ .pma_rx_buf_pm_tx_rx_pcie_gen_bitwidth (pma_rx_buf_pm_tx_rx_pcie_gen_bitwidth),
+ .pma_rx_buf_pm_tx_rx_cvp_mode (pma_rx_buf_pm_tx_rx_cvp_mode),
+ .pma_rx_buf_xrx_path_uc_cal_enable (pma_rx_buf_xrx_path_uc_cal_enable),
+ .pma_rx_buf_xrx_path_datawidth (pma_rx_buf_xrx_path_datawidth),
+ .pma_rx_buf_xrx_path_pma_rx_divclk_hz (lcl_pma_rx_buf_xrx_path_pma_rx_divclk_hz), // String to bin conversion
+ // parameters for twentynm_hssi_pma_rx_deser
+ .pma_rx_deser_clkdivrx_user_mode (pma_rx_deser_clkdivrx_user_mode),
+ .pma_rx_deser_pcie_gen (pma_rx_deser_pcie_gen),
+ .pma_rx_deser_pcie_gen_bitwidth (pma_rx_deser_pcie_gen_bitwidth),
+ .pma_rx_deser_deser_factor (pma_rx_deser_deser_factor),
+ .pma_rx_deser_sdclk_enable (pma_rx_deser_sdclk_enable),
+ .pma_rx_deser_clkdiv_source (pma_rx_deser_clkdiv_source),
+ .pma_rx_deser_force_clkdiv_for_testing (pma_rx_deser_force_clkdiv_for_testing),
+ .pma_rx_deser_rst_n_adapt_odi (pma_rx_deser_rst_n_adapt_odi),
+ .pma_rx_deser_bitslip_bypass (pma_rx_deser_bitslip_bypass),
+ // parameters for twentynm_hssi_pma_rx_dfe
+ .pma_rx_dfe_pdb (pma_rx_dfe_pdb),
+ .pma_rx_dfe_pdb_fixedtap (pma_rx_dfe_pdb_fixedtap),
+ .pma_rx_dfe_pdb_floattap (pma_rx_dfe_pdb_floattap),
+ .pma_rx_dfe_pdb_fxtap4t7 (pma_rx_dfe_pdb_fxtap4t7),
+ .pma_rx_dfe_dft_en (pma_rx_dfe_dft_en),
+ // parameters for twentynm_hssi_pma_rx_odi
+ .pma_rx_odi_step_ctrl_sel (pma_rx_odi_step_ctrl_sel),
+ // parameters for twentynm_hssi_pma_rx_sd
+ .pma_rx_sd_sd_output_off (pma_rx_sd_sd_output_off),
+ .pma_rx_sd_sd_output_on (pma_rx_sd_sd_output_on),
+ .pma_rx_sd_sd_pdb (pma_rx_sd_sd_pdb),
+ //.pma_rx_sd_sd_threshold (pma_rx_sd_sd_threshold),
+ // parameters for twentynm_hssi_pma_tx_buf
+ .pma_tx_buf_rx_det (pma_tx_buf_rx_det),
+ .pma_tx_buf_rx_det_output_sel (pma_tx_buf_rx_det_output_sel),
+ .pma_tx_buf_rx_det_pdb (pma_tx_buf_rx_det_pdb),
+ .pma_tx_buf_user_fir_coeff_ctrl_sel (pma_tx_buf_user_fir_coeff_ctrl_sel),
+ .pma_tx_buf_xtx_path_datawidth (pma_tx_buf_xtx_path_datawidth),
+ .pma_tx_buf_xtx_path_clock_divider_ratio (pma_tx_buf_xtx_path_clock_divider_ratio),
+ .pma_tx_buf_xtx_path_pma_tx_divclk_hz (lcl_pma_tx_buf_xtx_path_pma_tx_divclk_hz), // String to bin conversion
+ //.pma_tx_buf_xtx_path_tx_pll_clk_hz (lcl_pma_tx_buf_xtx_path_tx_pll_clk_hz), // String to bin conversion
+ .pma_tx_buf_xtx_path_tx_pll_clk_hz (pma_tx_buf_xtx_path_tx_pll_clk_hz),
+ // parameters for twentynm_hssi_pma_tx_cgb
+ .pma_cgb_bitslip_enable (pma_cgb_bitslip_enable),
+ .pma_cgb_bonding_reset_enable (pma_cgb_bonding_reset_enable),
+ .pma_cgb_input_select_xn (pma_cgb_input_select_xn),
+ .pma_cgb_input_select_gen3 (pma_cgb_input_select_gen3),
+ .pma_cgb_input_select_x1 (pma_cgb_input_select_x1),
+ .pma_cgb_pcie_gen3_bitwidth (pma_cgb_pcie_gen3_bitwidth),
+ .pma_cgb_select_done_master_or_slave (lcl_pma_cgb_select_done_master_or_slave),
+ .pma_cgb_ser_mode (pma_cgb_ser_mode),
+ .pma_cgb_x1_div_m_sel (pma_cgb_x1_div_m_sel),
+ .pma_cgb_tx_ucontrol_en (pma_cgb_tx_ucontrol_en),
+ // parameters for twentynm_hssi_pma_tx_ser
+ .pma_tx_ser_ser_clk_divtx_user_sel (pma_tx_ser_ser_clk_divtx_user_sel),
+
+ // twentynm_pcs parameters
+ // parameters for twentynm_hssi_10g_rx_pcs
+ .hssi_10g_rx_pcs_advanced_user_mode (hssi_10g_rx_pcs_advanced_user_mode),
+ .hssi_10g_rx_pcs_align_del (hssi_10g_rx_pcs_align_del),
+ .hssi_10g_rx_pcs_ber_bit_err_total_cnt (hssi_10g_rx_pcs_ber_bit_err_total_cnt),
+ .hssi_10g_rx_pcs_ber_clken (hssi_10g_rx_pcs_ber_clken),
+ .hssi_10g_rx_pcs_ber_xus_timer_window (hssi_10g_rx_pcs_ber_xus_timer_window),
+ .hssi_10g_rx_pcs_bitslip_mode (hssi_10g_rx_pcs_bitslip_mode),
+ .hssi_10g_rx_pcs_blksync_bitslip_type (hssi_10g_rx_pcs_blksync_bitslip_type),
+ .hssi_10g_rx_pcs_blksync_bitslip_wait_cnt (hssi_10g_rx_pcs_blksync_bitslip_wait_cnt),
+ .hssi_10g_rx_pcs_blksync_bitslip_wait_type (hssi_10g_rx_pcs_blksync_bitslip_wait_type),
+ .hssi_10g_rx_pcs_blksync_bypass (hssi_10g_rx_pcs_blksync_bypass),
+ .hssi_10g_rx_pcs_blksync_clken (hssi_10g_rx_pcs_blksync_clken),
+ .hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt (hssi_10g_rx_pcs_blksync_enum_invalid_sh_cnt),
+ .hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock (hssi_10g_rx_pcs_blksync_knum_sh_cnt_postlock),
+ .hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock (hssi_10g_rx_pcs_blksync_knum_sh_cnt_prelock),
+ .hssi_10g_rx_pcs_blksync_pipeln (hssi_10g_rx_pcs_blksync_pipeln),
+ .hssi_10g_rx_pcs_clr_errblk_cnt_en (hssi_10g_rx_pcs_clr_errblk_cnt_en),
+ .hssi_10g_rx_pcs_control_del (hssi_10g_rx_pcs_control_del),
+ .hssi_10g_rx_pcs_crcchk_bypass (hssi_10g_rx_pcs_crcchk_bypass),
+ .hssi_10g_rx_pcs_crcchk_clken (hssi_10g_rx_pcs_crcchk_clken),
+ .hssi_10g_rx_pcs_crcchk_inv (hssi_10g_rx_pcs_crcchk_inv),
+ .hssi_10g_rx_pcs_crcchk_pipeln (hssi_10g_rx_pcs_crcchk_pipeln),
+ .hssi_10g_rx_pcs_crcflag_pipeln (hssi_10g_rx_pcs_crcflag_pipeln),
+ .hssi_10g_rx_pcs_ctrl_bit_reverse (hssi_10g_rx_pcs_ctrl_bit_reverse),
+ .hssi_10g_rx_pcs_data_bit_reverse (hssi_10g_rx_pcs_data_bit_reverse),
+ .hssi_10g_rx_pcs_dec64b66b_clken (hssi_10g_rx_pcs_dec64b66b_clken),
+ .hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass (hssi_10g_rx_pcs_dec_64b66b_rxsm_bypass),
+ .hssi_10g_rx_pcs_descrm_bypass (hssi_10g_rx_pcs_descrm_bypass),
+ .hssi_10g_rx_pcs_descrm_clken (hssi_10g_rx_pcs_descrm_clken),
+ .hssi_10g_rx_pcs_descrm_mode (hssi_10g_rx_pcs_descrm_mode),
+ .hssi_10g_rx_pcs_descrm_pipeln (hssi_10g_rx_pcs_descrm_pipeln),
+ .hssi_10g_rx_pcs_dft_clk_out_sel (hssi_10g_rx_pcs_dft_clk_out_sel),
+ .hssi_10g_rx_pcs_dis_signal_ok (hssi_10g_rx_pcs_dis_signal_ok),
+ .hssi_10g_rx_pcs_dispchk_bypass (hssi_10g_rx_pcs_dispchk_bypass),
+ .hssi_10g_rx_pcs_empty_flag_type (hssi_10g_rx_pcs_empty_flag_type),
+ .hssi_10g_rx_pcs_fast_path (hssi_10g_rx_pcs_fast_path),
+ .hssi_10g_rx_pcs_fec_clken (hssi_10g_rx_pcs_fec_clken),
+ .hssi_10g_rx_pcs_fec_enable (hssi_10g_rx_pcs_fec_enable),
+ .hssi_10g_rx_pcs_fifo_double_read (hssi_10g_rx_pcs_fifo_double_read),
+ .hssi_10g_rx_pcs_fifo_stop_rd (hssi_10g_rx_pcs_fifo_stop_rd),
+ .hssi_10g_rx_pcs_fifo_stop_wr (hssi_10g_rx_pcs_fifo_stop_wr),
+ .hssi_10g_rx_pcs_force_align (hssi_10g_rx_pcs_force_align),
+ .hssi_10g_rx_pcs_frmsync_bypass (hssi_10g_rx_pcs_frmsync_bypass),
+ .hssi_10g_rx_pcs_frmsync_clken (hssi_10g_rx_pcs_frmsync_clken),
+ .hssi_10g_rx_pcs_frmsync_enum_scrm (hssi_10g_rx_pcs_frmsync_enum_scrm),
+ .hssi_10g_rx_pcs_frmsync_enum_sync (hssi_10g_rx_pcs_frmsync_enum_sync),
+ .hssi_10g_rx_pcs_frmsync_flag_type (hssi_10g_rx_pcs_frmsync_flag_type),
+ .hssi_10g_rx_pcs_frmsync_knum_sync (hssi_10g_rx_pcs_frmsync_knum_sync),
+ .hssi_10g_rx_pcs_frmsync_mfrm_length (hssi_10g_rx_pcs_frmsync_mfrm_length),
+ .hssi_10g_rx_pcs_frmsync_pipeln (hssi_10g_rx_pcs_frmsync_pipeln),
+ .hssi_10g_rx_pcs_full_flag_type (hssi_10g_rx_pcs_full_flag_type),
+ .hssi_10g_rx_pcs_gb_rx_idwidth (hssi_10g_rx_pcs_gb_rx_idwidth),
+ .hssi_10g_rx_pcs_gb_rx_odwidth (hssi_10g_rx_pcs_gb_rx_odwidth),
+ .hssi_10g_rx_pcs_gbexp_clken (hssi_10g_rx_pcs_gbexp_clken),
+ .hssi_10g_rx_pcs_low_latency_en (hssi_10g_rx_pcs_low_latency_en),
+ .hssi_10g_rx_pcs_lpbk_mode (hssi_10g_rx_pcs_lpbk_mode),
+ .hssi_10g_rx_pcs_master_clk_sel (hssi_10g_rx_pcs_master_clk_sel),
+ .hssi_10g_rx_pcs_pempty_flag_type (hssi_10g_rx_pcs_pempty_flag_type),
+ .hssi_10g_rx_pcs_pfull_flag_type (hssi_10g_rx_pcs_pfull_flag_type),
+ .hssi_10g_rx_pcs_phcomp_rd_del (hssi_10g_rx_pcs_phcomp_rd_del),
+ .hssi_10g_rx_pcs_pld_if_type (hssi_10g_rx_pcs_pld_if_type),
+ .hssi_10g_rx_pcs_rand_clken (hssi_10g_rx_pcs_rand_clken),
+ .hssi_10g_rx_pcs_rd_clk_sel (hssi_10g_rx_pcs_rd_clk_sel),
+ .hssi_10g_rx_pcs_rdfifo_clken (hssi_10g_rx_pcs_rdfifo_clken),
+ .hssi_10g_rx_pcs_rx_fifo_write_ctrl (hssi_10g_rx_pcs_rx_fifo_write_ctrl),
+ .hssi_10g_rx_pcs_rx_scrm_width (hssi_10g_rx_pcs_rx_scrm_width),
+ .hssi_10g_rx_pcs_rx_sh_location (hssi_10g_rx_pcs_rx_sh_location),
+ .hssi_10g_rx_pcs_rx_signal_ok_sel (hssi_10g_rx_pcs_rx_signal_ok_sel),
+ .hssi_10g_rx_pcs_rx_sm_bypass (hssi_10g_rx_pcs_rx_sm_bypass),
+ .hssi_10g_rx_pcs_rx_sm_hiber (hssi_10g_rx_pcs_rx_sm_hiber),
+ .hssi_10g_rx_pcs_rx_sm_pipeln (hssi_10g_rx_pcs_rx_sm_pipeln),
+ .hssi_10g_rx_pcs_rx_testbus_sel (hssi_10g_rx_pcs_rx_testbus_sel),
+ .hssi_10g_rx_pcs_rx_true_b2b (hssi_10g_rx_pcs_rx_true_b2b),
+ .hssi_10g_rx_pcs_rxfifo_empty (hssi_10g_rx_pcs_rxfifo_empty),
+ .hssi_10g_rx_pcs_rxfifo_full (hssi_10g_rx_pcs_rxfifo_full),
+ .hssi_10g_rx_pcs_rxfifo_mode (hssi_10g_rx_pcs_rxfifo_mode),
+ .hssi_10g_rx_pcs_rxfifo_pempty (hssi_10g_rx_pcs_rxfifo_pempty),
+ .hssi_10g_rx_pcs_rxfifo_pfull (hssi_10g_rx_pcs_rxfifo_pfull),
+ .hssi_10g_rx_pcs_stretch_num_stages (hssi_10g_rx_pcs_stretch_num_stages),
+ .hssi_10g_rx_pcs_test_mode (hssi_10g_rx_pcs_test_mode),
+ .hssi_10g_rx_pcs_wrfifo_clken (hssi_10g_rx_pcs_wrfifo_clken),
+ // parameters for twentynm_hssi_10g_tx_pcs
+ .hssi_10g_tx_pcs_advanced_user_mode (hssi_10g_tx_pcs_advanced_user_mode),
+ .hssi_10g_tx_pcs_bitslip_en (hssi_10g_tx_pcs_bitslip_en),
+ .hssi_10g_tx_pcs_bonding_dft_en (hssi_10g_tx_pcs_bonding_dft_en),
+ .hssi_10g_tx_pcs_bonding_dft_val (hssi_10g_tx_pcs_bonding_dft_val),
+ .hssi_10g_tx_pcs_crcgen_bypass (hssi_10g_tx_pcs_crcgen_bypass),
+ .hssi_10g_tx_pcs_crcgen_clken (hssi_10g_tx_pcs_crcgen_clken),
+ .hssi_10g_tx_pcs_crcgen_err (hssi_10g_tx_pcs_crcgen_err),
+ .hssi_10g_tx_pcs_crcgen_inv (hssi_10g_tx_pcs_crcgen_inv),
+ .hssi_10g_tx_pcs_ctrl_bit_reverse (hssi_10g_tx_pcs_ctrl_bit_reverse),
+ .hssi_10g_tx_pcs_data_bit_reverse (hssi_10g_tx_pcs_data_bit_reverse),
+ .hssi_10g_tx_pcs_dft_clk_out_sel (hssi_10g_tx_pcs_dft_clk_out_sel),
+ .hssi_10g_tx_pcs_dispgen_bypass (hssi_10g_tx_pcs_dispgen_bypass),
+ .hssi_10g_tx_pcs_dispgen_clken (hssi_10g_tx_pcs_dispgen_clken),
+ .hssi_10g_tx_pcs_dispgen_err (hssi_10g_tx_pcs_dispgen_err),
+ .hssi_10g_tx_pcs_dispgen_pipeln (hssi_10g_tx_pcs_dispgen_pipeln),
+ .hssi_10g_tx_pcs_empty_flag_type (hssi_10g_tx_pcs_empty_flag_type),
+ .hssi_10g_tx_pcs_enc64b66b_txsm_clken (hssi_10g_tx_pcs_enc64b66b_txsm_clken),
+ .hssi_10g_tx_pcs_enc_64b66b_txsm_bypass (hssi_10g_tx_pcs_enc_64b66b_txsm_bypass),
+ .hssi_10g_tx_pcs_fastpath (hssi_10g_tx_pcs_fastpath),
+ .hssi_10g_tx_pcs_fec_clken (hssi_10g_tx_pcs_fec_clken),
+ .hssi_10g_tx_pcs_fec_enable (hssi_10g_tx_pcs_fec_enable),
+ .hssi_10g_tx_pcs_fifo_double_write (hssi_10g_tx_pcs_fifo_double_write),
+ .hssi_10g_tx_pcs_fifo_reg_fast (hssi_10g_tx_pcs_fifo_reg_fast),
+ .hssi_10g_tx_pcs_fifo_stop_rd (hssi_10g_tx_pcs_fifo_stop_rd),
+ .hssi_10g_tx_pcs_fifo_stop_wr (hssi_10g_tx_pcs_fifo_stop_wr),
+ .hssi_10g_tx_pcs_frmgen_burst (hssi_10g_tx_pcs_frmgen_burst),
+ .hssi_10g_tx_pcs_frmgen_bypass (hssi_10g_tx_pcs_frmgen_bypass),
+ .hssi_10g_tx_pcs_frmgen_clken (hssi_10g_tx_pcs_frmgen_clken),
+ .hssi_10g_tx_pcs_frmgen_mfrm_length (hssi_10g_tx_pcs_frmgen_mfrm_length),
+ .hssi_10g_tx_pcs_frmgen_pipeln (hssi_10g_tx_pcs_frmgen_pipeln),
+ .hssi_10g_tx_pcs_frmgen_pyld_ins (hssi_10g_tx_pcs_frmgen_pyld_ins),
+ .hssi_10g_tx_pcs_frmgen_wordslip (hssi_10g_tx_pcs_frmgen_wordslip),
+ .hssi_10g_tx_pcs_full_flag_type (hssi_10g_tx_pcs_full_flag_type),
+ .hssi_10g_tx_pcs_gb_pipeln_bypass (hssi_10g_tx_pcs_gb_pipeln_bypass),
+ .hssi_10g_tx_pcs_gb_tx_idwidth (hssi_10g_tx_pcs_gb_tx_idwidth),
+ .hssi_10g_tx_pcs_gb_tx_odwidth (hssi_10g_tx_pcs_gb_tx_odwidth),
+ .hssi_10g_tx_pcs_gbred_clken (hssi_10g_tx_pcs_gbred_clken),
+ .hssi_10g_tx_pcs_low_latency_en (hssi_10g_tx_pcs_low_latency_en),
+ .hssi_10g_tx_pcs_master_clk_sel (hssi_10g_tx_pcs_master_clk_sel),
+ .hssi_10g_tx_pcs_pempty_flag_type (hssi_10g_tx_pcs_pempty_flag_type),
+ .hssi_10g_tx_pcs_pfull_flag_type (hssi_10g_tx_pcs_pfull_flag_type),
+ .hssi_10g_tx_pcs_phcomp_rd_del (hssi_10g_tx_pcs_phcomp_rd_del),
+ .hssi_10g_tx_pcs_pld_if_type (hssi_10g_tx_pcs_pld_if_type),
+ .hssi_10g_tx_pcs_pseudo_random (hssi_10g_tx_pcs_pseudo_random),
+ .hssi_10g_tx_pcs_pseudo_seed_a (lcl_hssi_10g_tx_pcs_pseudo_seed_a), // String to bin conversion
+ .hssi_10g_tx_pcs_pseudo_seed_b (lcl_hssi_10g_tx_pcs_pseudo_seed_b), // String to bin conversion
+ .hssi_10g_tx_pcs_random_disp (hssi_10g_tx_pcs_random_disp),
+ .hssi_10g_tx_pcs_rdfifo_clken (hssi_10g_tx_pcs_rdfifo_clken),
+ .hssi_10g_tx_pcs_scrm_bypass (hssi_10g_tx_pcs_scrm_bypass),
+ .hssi_10g_tx_pcs_scrm_clken (hssi_10g_tx_pcs_scrm_clken),
+ .hssi_10g_tx_pcs_scrm_mode (hssi_10g_tx_pcs_scrm_mode),
+ .hssi_10g_tx_pcs_scrm_pipeln (hssi_10g_tx_pcs_scrm_pipeln),
+ .hssi_10g_tx_pcs_sh_err (hssi_10g_tx_pcs_sh_err),
+ .hssi_10g_tx_pcs_sop_mark (hssi_10g_tx_pcs_sop_mark),
+ .hssi_10g_tx_pcs_stretch_num_stages (hssi_10g_tx_pcs_stretch_num_stages),
+ .hssi_10g_tx_pcs_test_mode (hssi_10g_tx_pcs_test_mode),
+ .hssi_10g_tx_pcs_tx_scrm_err (hssi_10g_tx_pcs_tx_scrm_err),
+ .hssi_10g_tx_pcs_tx_scrm_width (hssi_10g_tx_pcs_tx_scrm_width),
+ .hssi_10g_tx_pcs_tx_sh_location (hssi_10g_tx_pcs_tx_sh_location),
+ .hssi_10g_tx_pcs_tx_sm_bypass (hssi_10g_tx_pcs_tx_sm_bypass),
+ .hssi_10g_tx_pcs_tx_sm_pipeln (hssi_10g_tx_pcs_tx_sm_pipeln),
+ .hssi_10g_tx_pcs_tx_testbus_sel (hssi_10g_tx_pcs_tx_testbus_sel),
+ .hssi_10g_tx_pcs_txfifo_empty (hssi_10g_tx_pcs_txfifo_empty),
+ .hssi_10g_tx_pcs_txfifo_full (hssi_10g_tx_pcs_txfifo_full),
+ .hssi_10g_tx_pcs_txfifo_mode (hssi_10g_tx_pcs_txfifo_mode),
+ .hssi_10g_tx_pcs_txfifo_pempty (hssi_10g_tx_pcs_txfifo_pempty),
+ .hssi_10g_tx_pcs_txfifo_pfull (hssi_10g_tx_pcs_txfifo_pfull),
+ .hssi_10g_tx_pcs_wr_clk_sel (hssi_10g_tx_pcs_wr_clk_sel),
+ .hssi_10g_tx_pcs_wrfifo_clken (hssi_10g_tx_pcs_wrfifo_clken),
+ // parameters for twentynm_hssi_8g_rx_pcs
+ .hssi_8g_rx_pcs_auto_error_replacement (hssi_8g_rx_pcs_auto_error_replacement),
+ .hssi_8g_rx_pcs_bit_reversal (hssi_8g_rx_pcs_bit_reversal),
+ .hssi_8g_rx_pcs_bonding_dft_en (hssi_8g_rx_pcs_bonding_dft_en),
+ .hssi_8g_rx_pcs_bonding_dft_val (hssi_8g_rx_pcs_bonding_dft_val),
+ .hssi_8g_rx_pcs_bypass_pipeline_reg (hssi_8g_rx_pcs_bypass_pipeline_reg),
+ .hssi_8g_rx_pcs_byte_deserializer (hssi_8g_rx_pcs_byte_deserializer),
+ .hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask (hssi_8g_rx_pcs_cdr_ctrl_rxvalid_mask),
+ .hssi_8g_rx_pcs_clkcmp_pattern_n (hssi_8g_rx_pcs_clkcmp_pattern_n),
+ .hssi_8g_rx_pcs_clkcmp_pattern_p (hssi_8g_rx_pcs_clkcmp_pattern_p),
+ .hssi_8g_rx_pcs_clock_gate_bds_dec_asn (hssi_8g_rx_pcs_clock_gate_bds_dec_asn),
+ .hssi_8g_rx_pcs_clock_gate_cdr_eidle (hssi_8g_rx_pcs_clock_gate_cdr_eidle),
+ .hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk (hssi_8g_rx_pcs_clock_gate_dw_pc_wrclk),
+ .hssi_8g_rx_pcs_clock_gate_dw_rm_rd (hssi_8g_rx_pcs_clock_gate_dw_rm_rd),
+ .hssi_8g_rx_pcs_clock_gate_dw_rm_wr (hssi_8g_rx_pcs_clock_gate_dw_rm_wr),
+ .hssi_8g_rx_pcs_clock_gate_dw_wa (hssi_8g_rx_pcs_clock_gate_dw_wa),
+ .hssi_8g_rx_pcs_clock_gate_pc_rdclk (hssi_8g_rx_pcs_clock_gate_pc_rdclk),
+ .hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk (hssi_8g_rx_pcs_clock_gate_sw_pc_wrclk),
+ .hssi_8g_rx_pcs_clock_gate_sw_rm_rd (hssi_8g_rx_pcs_clock_gate_sw_rm_rd),
+ .hssi_8g_rx_pcs_clock_gate_sw_rm_wr (hssi_8g_rx_pcs_clock_gate_sw_rm_wr),
+ .hssi_8g_rx_pcs_clock_gate_sw_wa (hssi_8g_rx_pcs_clock_gate_sw_wa),
+ .hssi_8g_rx_pcs_clock_observation_in_pld_core (hssi_8g_rx_pcs_clock_observation_in_pld_core),
+ .hssi_8g_rx_pcs_eidle_entry_eios (hssi_8g_rx_pcs_eidle_entry_eios),
+ .hssi_8g_rx_pcs_eidle_entry_iei (hssi_8g_rx_pcs_eidle_entry_iei),
+ .hssi_8g_rx_pcs_eidle_entry_sd (hssi_8g_rx_pcs_eidle_entry_sd),
+ .hssi_8g_rx_pcs_eightb_tenb_decoder (hssi_8g_rx_pcs_eightb_tenb_decoder),
+ .hssi_8g_rx_pcs_err_flags_sel (hssi_8g_rx_pcs_err_flags_sel),
+ .hssi_8g_rx_pcs_fixed_pat_det (hssi_8g_rx_pcs_fixed_pat_det),
+ .hssi_8g_rx_pcs_fixed_pat_num (hssi_8g_rx_pcs_fixed_pat_num),
+ .hssi_8g_rx_pcs_force_signal_detect (hssi_8g_rx_pcs_force_signal_detect),
+ .hssi_8g_rx_pcs_gen3_clk_en (hssi_8g_rx_pcs_gen3_clk_en),
+ .hssi_8g_rx_pcs_gen3_rx_clk_sel (hssi_8g_rx_pcs_gen3_rx_clk_sel),
+ .hssi_8g_rx_pcs_gen3_tx_clk_sel (hssi_8g_rx_pcs_gen3_tx_clk_sel),
+ .hssi_8g_rx_pcs_hip_mode (hssi_8g_rx_pcs_hip_mode),
+ .hssi_8g_rx_pcs_ibm_invalid_code (hssi_8g_rx_pcs_ibm_invalid_code),
+ .hssi_8g_rx_pcs_invalid_code_flag_only (hssi_8g_rx_pcs_invalid_code_flag_only),
+ .hssi_8g_rx_pcs_pad_or_edb_error_replace (hssi_8g_rx_pcs_pad_or_edb_error_replace),
+ .hssi_8g_rx_pcs_pcs_bypass (hssi_8g_rx_pcs_pcs_bypass),
+ .hssi_8g_rx_pcs_phase_comp_rdptr (hssi_8g_rx_pcs_phase_comp_rdptr),
+ .hssi_8g_rx_pcs_phase_compensation_fifo (hssi_8g_rx_pcs_phase_compensation_fifo),
+ .hssi_8g_rx_pcs_pipe_if_enable (hssi_8g_rx_pcs_pipe_if_enable),
+ .hssi_8g_rx_pcs_pma_dw (hssi_8g_rx_pcs_pma_dw),
+ .hssi_8g_rx_pcs_polinv_8b10b_dec (hssi_8g_rx_pcs_polinv_8b10b_dec),
+ .hssi_8g_rx_pcs_rate_match (hssi_8g_rx_pcs_rate_match),
+ .hssi_8g_rx_pcs_rate_match_del_thres (hssi_8g_rx_pcs_rate_match_del_thres),
+ .hssi_8g_rx_pcs_rate_match_empty_thres (hssi_8g_rx_pcs_rate_match_empty_thres),
+ .hssi_8g_rx_pcs_rate_match_full_thres (hssi_8g_rx_pcs_rate_match_full_thres),
+ .hssi_8g_rx_pcs_rate_match_ins_thres (hssi_8g_rx_pcs_rate_match_ins_thres),
+ .hssi_8g_rx_pcs_rate_match_start_thres (hssi_8g_rx_pcs_rate_match_start_thres),
+ .hssi_8g_rx_pcs_rx_clk2 (hssi_8g_rx_pcs_rx_clk2),
+ .hssi_8g_rx_pcs_rx_clk_free_running (hssi_8g_rx_pcs_rx_clk_free_running),
+ .hssi_8g_rx_pcs_rx_pcs_urst (hssi_8g_rx_pcs_rx_pcs_urst),
+ .hssi_8g_rx_pcs_rx_rcvd_clk (hssi_8g_rx_pcs_rx_rcvd_clk),
+ .hssi_8g_rx_pcs_rx_rd_clk (hssi_8g_rx_pcs_rx_rd_clk),
+ .hssi_8g_rx_pcs_rx_refclk (hssi_8g_rx_pcs_rx_refclk),
+ .hssi_8g_rx_pcs_rx_wr_clk (hssi_8g_rx_pcs_rx_wr_clk),
+ .hssi_8g_rx_pcs_symbol_swap (hssi_8g_rx_pcs_symbol_swap),
+ .hssi_8g_rx_pcs_sync_sm_idle_eios (hssi_8g_rx_pcs_sync_sm_idle_eios),
+ .hssi_8g_rx_pcs_test_bus_sel (hssi_8g_rx_pcs_test_bus_sel),
+ .hssi_8g_rx_pcs_tx_rx_parallel_loopback (hssi_8g_rx_pcs_tx_rx_parallel_loopback),
+ .hssi_8g_rx_pcs_wa_boundary_lock_ctrl (hssi_8g_rx_pcs_wa_boundary_lock_ctrl),
+ .hssi_8g_rx_pcs_wa_clk_slip_spacing (hssi_8g_rx_pcs_wa_clk_slip_spacing),
+ .hssi_8g_rx_pcs_wa_det_latency_sync_status_beh (hssi_8g_rx_pcs_wa_det_latency_sync_status_beh),
+ .hssi_8g_rx_pcs_wa_disp_err_flag (hssi_8g_rx_pcs_wa_disp_err_flag),
+ .hssi_8g_rx_pcs_wa_kchar (hssi_8g_rx_pcs_wa_kchar),
+ .hssi_8g_rx_pcs_wa_pd (hssi_8g_rx_pcs_wa_pd),
+ .hssi_8g_rx_pcs_wa_pd_data (lcl_hssi_8g_rx_pcs_wa_pd_data),
+ .hssi_8g_rx_pcs_wa_pd_polarity (hssi_8g_rx_pcs_wa_pd_polarity),
+ .hssi_8g_rx_pcs_wa_pld_controlled (hssi_8g_rx_pcs_wa_pld_controlled),
+ .hssi_8g_rx_pcs_wa_renumber_data (hssi_8g_rx_pcs_wa_renumber_data),
+ .hssi_8g_rx_pcs_wa_rgnumber_data (hssi_8g_rx_pcs_wa_rgnumber_data),
+ .hssi_8g_rx_pcs_wa_rknumber_data (hssi_8g_rx_pcs_wa_rknumber_data),
+ .hssi_8g_rx_pcs_wa_rosnumber_data (hssi_8g_rx_pcs_wa_rosnumber_data),
+ .hssi_8g_rx_pcs_wa_rvnumber_data (hssi_8g_rx_pcs_wa_rvnumber_data),
+ .hssi_8g_rx_pcs_wa_sync_sm_ctrl (hssi_8g_rx_pcs_wa_sync_sm_ctrl),
+ .hssi_8g_rx_pcs_wait_cnt (hssi_8g_rx_pcs_wait_cnt),
+ // parameters for twentynm_hssi_8g_tx_pcs
+ .hssi_8g_tx_pcs_bit_reversal (hssi_8g_tx_pcs_bit_reversal),
+ .hssi_8g_tx_pcs_bonding_dft_en (hssi_8g_tx_pcs_bonding_dft_en),
+ .hssi_8g_tx_pcs_bonding_dft_val (hssi_8g_tx_pcs_bonding_dft_val),
+ .hssi_8g_tx_pcs_bypass_pipeline_reg (hssi_8g_tx_pcs_bypass_pipeline_reg),
+ .hssi_8g_tx_pcs_byte_serializer (hssi_8g_tx_pcs_byte_serializer),
+ .hssi_8g_tx_pcs_clock_gate_bs_enc (hssi_8g_tx_pcs_clock_gate_bs_enc),
+ .hssi_8g_tx_pcs_clock_gate_dw_fifowr (hssi_8g_tx_pcs_clock_gate_dw_fifowr),
+ .hssi_8g_tx_pcs_clock_gate_fiford (hssi_8g_tx_pcs_clock_gate_fiford),
+ .hssi_8g_tx_pcs_clock_gate_sw_fifowr (hssi_8g_tx_pcs_clock_gate_sw_fifowr),
+ .hssi_8g_tx_pcs_clock_observation_in_pld_core (hssi_8g_tx_pcs_clock_observation_in_pld_core),
+ .hssi_8g_tx_pcs_data_selection_8b10b_encoder_input (hssi_8g_tx_pcs_data_selection_8b10b_encoder_input),
+ .hssi_8g_tx_pcs_dynamic_clk_switch (hssi_8g_tx_pcs_dynamic_clk_switch),
+ .hssi_8g_tx_pcs_eightb_tenb_disp_ctrl (hssi_8g_tx_pcs_eightb_tenb_disp_ctrl),
+ .hssi_8g_tx_pcs_eightb_tenb_encoder (hssi_8g_tx_pcs_eightb_tenb_encoder),
+ .hssi_8g_tx_pcs_force_echar (hssi_8g_tx_pcs_force_echar),
+ .hssi_8g_tx_pcs_force_kchar (hssi_8g_tx_pcs_force_kchar),
+ .hssi_8g_tx_pcs_gen3_tx_clk_sel (hssi_8g_tx_pcs_gen3_tx_clk_sel),
+ .hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel (hssi_8g_tx_pcs_gen3_tx_pipe_clk_sel),
+ .hssi_8g_tx_pcs_hip_mode (hssi_8g_tx_pcs_hip_mode),
+ .hssi_8g_tx_pcs_pcs_bypass (hssi_8g_tx_pcs_pcs_bypass),
+ .hssi_8g_tx_pcs_phase_comp_rdptr (hssi_8g_tx_pcs_phase_comp_rdptr),
+ .hssi_8g_tx_pcs_phase_compensation_fifo (hssi_8g_tx_pcs_phase_compensation_fifo),
+ .hssi_8g_tx_pcs_phfifo_write_clk_sel (hssi_8g_tx_pcs_phfifo_write_clk_sel),
+ .hssi_8g_tx_pcs_pma_dw (hssi_8g_tx_pcs_pma_dw),
+ .hssi_8g_tx_pcs_refclk_b_clk_sel (hssi_8g_tx_pcs_refclk_b_clk_sel),
+ .hssi_8g_tx_pcs_revloop_back_rm (hssi_8g_tx_pcs_revloop_back_rm),
+ .hssi_8g_tx_pcs_symbol_swap (hssi_8g_tx_pcs_symbol_swap),
+ .hssi_8g_tx_pcs_tx_bitslip (hssi_8g_tx_pcs_tx_bitslip),
+ .hssi_8g_tx_pcs_tx_compliance_controlled_disparity (hssi_8g_tx_pcs_tx_compliance_controlled_disparity),
+ .hssi_8g_tx_pcs_tx_fast_pld_reg (hssi_8g_tx_pcs_tx_fast_pld_reg),
+ .hssi_8g_tx_pcs_txclk_freerun (hssi_8g_tx_pcs_txclk_freerun),
+ .hssi_8g_tx_pcs_txpcs_urst (hssi_8g_tx_pcs_txpcs_urst),
+ // parameters for twentynm_hssi_common_pcs_pma_interface
+ .hssi_common_pcs_pma_interface_asn_clk_enable (hssi_common_pcs_pma_interface_asn_clk_enable),
+ .hssi_common_pcs_pma_interface_asn_enable (hssi_common_pcs_pma_interface_asn_enable),
+ .hssi_common_pcs_pma_interface_block_sel (hssi_common_pcs_pma_interface_block_sel),
+ .hssi_common_pcs_pma_interface_bypass_early_eios (hssi_common_pcs_pma_interface_bypass_early_eios),
+ .hssi_common_pcs_pma_interface_bypass_pcie_switch (hssi_common_pcs_pma_interface_bypass_pcie_switch),
+ .hssi_common_pcs_pma_interface_bypass_pma_ltr (hssi_common_pcs_pma_interface_bypass_pma_ltr),
+ .hssi_common_pcs_pma_interface_bypass_pma_sw_done (lcl_hssi_common_pcs_pma_interface_bypass_pma_sw_done),
+ .hssi_common_pcs_pma_interface_bypass_ppm_lock (hssi_common_pcs_pma_interface_bypass_ppm_lock),
+ .hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp (hssi_common_pcs_pma_interface_bypass_send_syncp_fbkp),
+ .hssi_common_pcs_pma_interface_bypass_txdetectrx (hssi_common_pcs_pma_interface_bypass_txdetectrx),
+ .hssi_common_pcs_pma_interface_cdr_control (hssi_common_pcs_pma_interface_cdr_control),
+ .hssi_common_pcs_pma_interface_cid_enable (hssi_common_pcs_pma_interface_cid_enable),
+ .hssi_common_pcs_pma_interface_data_mask_count (hssi_common_pcs_pma_interface_data_mask_count),
+ .hssi_common_pcs_pma_interface_data_mask_count_multi (hssi_common_pcs_pma_interface_data_mask_count_multi),
+ .hssi_common_pcs_pma_interface_dft_observation_clock_selection (hssi_common_pcs_pma_interface_dft_observation_clock_selection),
+ .hssi_common_pcs_pma_interface_early_eios_counter (hssi_common_pcs_pma_interface_early_eios_counter),
+ .hssi_common_pcs_pma_interface_force_freqdet (hssi_common_pcs_pma_interface_force_freqdet),
+ .hssi_common_pcs_pma_interface_free_run_clk_enable (hssi_common_pcs_pma_interface_free_run_clk_enable),
+ .hssi_common_pcs_pma_interface_ignore_sigdet_g23 (hssi_common_pcs_pma_interface_ignore_sigdet_g23),
+ .hssi_common_pcs_pma_interface_pc_en_counter (hssi_common_pcs_pma_interface_pc_en_counter),
+ .hssi_common_pcs_pma_interface_pc_rst_counter (hssi_common_pcs_pma_interface_pc_rst_counter),
+ .hssi_common_pcs_pma_interface_pcie_hip_mode (hssi_common_pcs_pma_interface_pcie_hip_mode),
+ .hssi_common_pcs_pma_interface_ph_fifo_reg_mode (hssi_common_pcs_pma_interface_ph_fifo_reg_mode),
+ .hssi_common_pcs_pma_interface_phfifo_flush_wait (hssi_common_pcs_pma_interface_phfifo_flush_wait),
+ .hssi_common_pcs_pma_interface_pipe_if_g3pcs (hssi_common_pcs_pma_interface_pipe_if_g3pcs),
+ .hssi_common_pcs_pma_interface_pma_done_counter (hssi_common_pcs_pma_interface_pma_done_counter),
+ .hssi_common_pcs_pma_interface_pma_if_dft_en (hssi_common_pcs_pma_interface_pma_if_dft_en),
+ .hssi_common_pcs_pma_interface_pma_if_dft_val (hssi_common_pcs_pma_interface_pma_if_dft_val),
+ .hssi_common_pcs_pma_interface_ppm_cnt_rst (hssi_common_pcs_pma_interface_ppm_cnt_rst),
+ .hssi_common_pcs_pma_interface_ppm_deassert_early (hssi_common_pcs_pma_interface_ppm_deassert_early),
+ .hssi_common_pcs_pma_interface_ppm_gen1_2_cnt (hssi_common_pcs_pma_interface_ppm_gen1_2_cnt),
+ .hssi_common_pcs_pma_interface_ppm_post_eidle_delay (hssi_common_pcs_pma_interface_ppm_post_eidle_delay),
+ .hssi_common_pcs_pma_interface_ppmsel (hssi_common_pcs_pma_interface_ppmsel),
+ .hssi_common_pcs_pma_interface_rxvalid_mask (hssi_common_pcs_pma_interface_rxvalid_mask),
+ .hssi_common_pcs_pma_interface_sigdet_wait_counter (hssi_common_pcs_pma_interface_sigdet_wait_counter),
+ .hssi_common_pcs_pma_interface_sigdet_wait_counter_multi (hssi_common_pcs_pma_interface_sigdet_wait_counter_multi),
+ .hssi_common_pcs_pma_interface_sim_mode (hssi_common_pcs_pma_interface_sim_mode),
+ .hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en (hssi_common_pcs_pma_interface_spd_chg_rst_wait_cnt_en),
+ .hssi_common_pcs_pma_interface_testout_sel (hssi_common_pcs_pma_interface_testout_sel),
+ .hssi_common_pcs_pma_interface_wait_clk_on_off_timer (hssi_common_pcs_pma_interface_wait_clk_on_off_timer),
+ .hssi_common_pcs_pma_interface_wait_pipe_synchronizing (hssi_common_pcs_pma_interface_wait_pipe_synchronizing),
+ .hssi_common_pcs_pma_interface_wait_send_syncp_fbkp (hssi_common_pcs_pma_interface_wait_send_syncp_fbkp),
+ .hssi_common_pcs_pma_interface_ppm_det_buckets(hssi_common_pcs_pma_interface_ppm_det_buckets),
+ // parameters for twentynm_hssi_common_pld_pcs_interface
+ .hssi_common_pld_pcs_interface_dft_clk_out_en (hssi_common_pld_pcs_interface_dft_clk_out_en),
+ .hssi_common_pld_pcs_interface_dft_clk_out_sel (hssi_common_pld_pcs_interface_dft_clk_out_sel),
+ .hssi_common_pld_pcs_interface_hrdrstctrl_en (hssi_common_pld_pcs_interface_hrdrstctrl_en),
+ .hssi_common_pld_pcs_interface_pcs_testbus_block_sel (hssi_common_pld_pcs_interface_pcs_testbus_block_sel),
+ // parameters for twentynm_hssi_fifo_rx_pcs
+ .hssi_fifo_rx_pcs_double_read_mode (hssi_fifo_rx_pcs_double_read_mode),
+ // parameters for twentynm_hssi_fifo_tx_pcs
+ .hssi_fifo_tx_pcs_double_write_mode (hssi_fifo_tx_pcs_double_write_mode),
+ // parameters for twentynm_hssi_gen3_rx_pcs
+ .hssi_gen3_rx_pcs_block_sync (hssi_gen3_rx_pcs_block_sync),
+ .hssi_gen3_rx_pcs_block_sync_sm (hssi_gen3_rx_pcs_block_sync_sm),
+ .hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn (hssi_gen3_rx_pcs_cdr_ctrl_force_unalgn),
+ .hssi_gen3_rx_pcs_lpbk_force (hssi_gen3_rx_pcs_lpbk_force),
+ .hssi_gen3_rx_pcs_mode (hssi_gen3_rx_pcs_mode),
+ .hssi_gen3_rx_pcs_rate_match_fifo (hssi_gen3_rx_pcs_rate_match_fifo),
+ .hssi_gen3_rx_pcs_rate_match_fifo_latency (hssi_gen3_rx_pcs_rate_match_fifo_latency),
+ .hssi_gen3_rx_pcs_reverse_lpbk (hssi_gen3_rx_pcs_reverse_lpbk),
+ .hssi_gen3_rx_pcs_rx_b4gb_par_lpbk (hssi_gen3_rx_pcs_rx_b4gb_par_lpbk),
+ .hssi_gen3_rx_pcs_rx_force_balign (hssi_gen3_rx_pcs_rx_force_balign),
+ .hssi_gen3_rx_pcs_rx_ins_del_one_skip (hssi_gen3_rx_pcs_rx_ins_del_one_skip),
+ .hssi_gen3_rx_pcs_rx_num_fixed_pat (hssi_gen3_rx_pcs_rx_num_fixed_pat),
+ .hssi_gen3_rx_pcs_rx_test_out_sel (hssi_gen3_rx_pcs_rx_test_out_sel),
+ // parameters for twentynm_hssi_gen3_tx_pcs
+ .hssi_gen3_tx_pcs_mode (hssi_gen3_tx_pcs_mode),
+ .hssi_gen3_tx_pcs_reverse_lpbk (hssi_gen3_tx_pcs_reverse_lpbk),
+ .hssi_gen3_tx_pcs_tx_bitslip (hssi_gen3_tx_pcs_tx_bitslip),
+ .hssi_gen3_tx_pcs_tx_gbox_byp (hssi_gen3_tx_pcs_tx_gbox_byp),
+ // parameters for twentynm_hssi_krfec_rx_pcs
+ .hssi_krfec_rx_pcs_blksync_cor_en (hssi_krfec_rx_pcs_blksync_cor_en),
+ .hssi_krfec_rx_pcs_bypass_gb (hssi_krfec_rx_pcs_bypass_gb),
+ .hssi_krfec_rx_pcs_clr_ctrl (hssi_krfec_rx_pcs_clr_ctrl),
+ .hssi_krfec_rx_pcs_ctrl_bit_reverse (hssi_krfec_rx_pcs_ctrl_bit_reverse),
+ .hssi_krfec_rx_pcs_data_bit_reverse (hssi_krfec_rx_pcs_data_bit_reverse),
+ .hssi_krfec_rx_pcs_dv_start (hssi_krfec_rx_pcs_dv_start),
+ .hssi_krfec_rx_pcs_err_mark_type (hssi_krfec_rx_pcs_err_mark_type),
+ .hssi_krfec_rx_pcs_error_marking_en (hssi_krfec_rx_pcs_error_marking_en),
+ .hssi_krfec_rx_pcs_low_latency_en (hssi_krfec_rx_pcs_low_latency_en),
+ .hssi_krfec_rx_pcs_lpbk_mode (hssi_krfec_rx_pcs_lpbk_mode),
+ .hssi_krfec_rx_pcs_parity_invalid_enum (hssi_krfec_rx_pcs_parity_invalid_enum),
+ .hssi_krfec_rx_pcs_parity_valid_num (hssi_krfec_rx_pcs_parity_valid_num),
+ .hssi_krfec_rx_pcs_pipeln_blksync (hssi_krfec_rx_pcs_pipeln_blksync),
+ .hssi_krfec_rx_pcs_pipeln_descrm (hssi_krfec_rx_pcs_pipeln_descrm),
+ .hssi_krfec_rx_pcs_pipeln_errcorrect (hssi_krfec_rx_pcs_pipeln_errcorrect),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_ind (hssi_krfec_rx_pcs_pipeln_errtrap_ind),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_lfsr (hssi_krfec_rx_pcs_pipeln_errtrap_lfsr),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_loc (hssi_krfec_rx_pcs_pipeln_errtrap_loc),
+ .hssi_krfec_rx_pcs_pipeln_errtrap_pat (hssi_krfec_rx_pcs_pipeln_errtrap_pat),
+ .hssi_krfec_rx_pcs_pipeln_gearbox (hssi_krfec_rx_pcs_pipeln_gearbox),
+ .hssi_krfec_rx_pcs_pipeln_syndrm (hssi_krfec_rx_pcs_pipeln_syndrm),
+ .hssi_krfec_rx_pcs_pipeln_trans_dec (hssi_krfec_rx_pcs_pipeln_trans_dec),
+ .hssi_krfec_rx_pcs_receive_order (hssi_krfec_rx_pcs_receive_order),
+ .hssi_krfec_rx_pcs_rx_testbus_sel (hssi_krfec_rx_pcs_rx_testbus_sel),
+ .hssi_krfec_rx_pcs_signal_ok_en (hssi_krfec_rx_pcs_signal_ok_en),
+ // parameters for twentynm_hssi_krfec_tx_pcs
+ .hssi_krfec_tx_pcs_burst_err (hssi_krfec_tx_pcs_burst_err),
+ .hssi_krfec_tx_pcs_burst_err_len (hssi_krfec_tx_pcs_burst_err_len),
+ .hssi_krfec_tx_pcs_ctrl_bit_reverse (hssi_krfec_tx_pcs_ctrl_bit_reverse),
+ .hssi_krfec_tx_pcs_data_bit_reverse (hssi_krfec_tx_pcs_data_bit_reverse),
+ .hssi_krfec_tx_pcs_enc_frame_query (hssi_krfec_tx_pcs_enc_frame_query),
+ .hssi_krfec_tx_pcs_low_latency_en (hssi_krfec_tx_pcs_low_latency_en),
+ .hssi_krfec_tx_pcs_pipeln_encoder (hssi_krfec_tx_pcs_pipeln_encoder),
+ .hssi_krfec_tx_pcs_pipeln_scrambler (hssi_krfec_tx_pcs_pipeln_scrambler),
+ .hssi_krfec_tx_pcs_transcode_err (hssi_krfec_tx_pcs_transcode_err),
+ .hssi_krfec_tx_pcs_transmit_order (hssi_krfec_tx_pcs_transmit_order),
+ .hssi_krfec_tx_pcs_tx_testbus_sel (hssi_krfec_tx_pcs_tx_testbus_sel),
+ // parameters for twentynm_hssi_pipe_gen1_2
+ .hssi_pipe_gen1_2_elec_idle_delay_val (hssi_pipe_gen1_2_elec_idle_delay_val),
+ .hssi_pipe_gen1_2_error_replace_pad (hssi_pipe_gen1_2_error_replace_pad),
+ .hssi_pipe_gen1_2_hip_mode (hssi_pipe_gen1_2_hip_mode),
+ .hssi_pipe_gen1_2_ind_error_reporting (hssi_pipe_gen1_2_ind_error_reporting),
+ .hssi_pipe_gen1_2_phystatus_delay_val (hssi_pipe_gen1_2_phystatus_delay_val),
+ .hssi_pipe_gen1_2_phystatus_rst_toggle (hssi_pipe_gen1_2_phystatus_rst_toggle),
+ .hssi_pipe_gen1_2_pipe_byte_de_serializer_en (hssi_pipe_gen1_2_pipe_byte_de_serializer_en),
+ .hssi_pipe_gen1_2_rx_pipe_enable (hssi_pipe_gen1_2_rx_pipe_enable),
+ .hssi_pipe_gen1_2_rxdetect_bypass (hssi_pipe_gen1_2_rxdetect_bypass),
+ .hssi_pipe_gen1_2_tx_pipe_enable (hssi_pipe_gen1_2_tx_pipe_enable),
+ .hssi_pipe_gen1_2_txswing (hssi_pipe_gen1_2_txswing),
+ // parameters for twentynm_hssi_pipe_gen3
+ .hssi_pipe_gen3_bypass_rx_detection_enable (hssi_pipe_gen3_bypass_rx_detection_enable),
+ .hssi_pipe_gen3_bypass_rx_preset (hssi_pipe_gen3_bypass_rx_preset),
+ .hssi_pipe_gen3_bypass_rx_preset_enable (hssi_pipe_gen3_bypass_rx_preset_enable),
+ .hssi_pipe_gen3_bypass_tx_coefficent (hssi_pipe_gen3_bypass_tx_coefficent),
+ .hssi_pipe_gen3_bypass_tx_coefficent_enable (hssi_pipe_gen3_bypass_tx_coefficent_enable),
+ .hssi_pipe_gen3_elecidle_delay_g3 (hssi_pipe_gen3_elecidle_delay_g3),
+ .hssi_pipe_gen3_ind_error_reporting (hssi_pipe_gen3_ind_error_reporting),
+ .hssi_pipe_gen3_mode (hssi_pipe_gen3_mode),
+ .hssi_pipe_gen3_phy_status_delay_g12 (hssi_pipe_gen3_phy_status_delay_g12),
+ .hssi_pipe_gen3_phy_status_delay_g3 (hssi_pipe_gen3_phy_status_delay_g3),
+ .hssi_pipe_gen3_phystatus_rst_toggle_g12 (hssi_pipe_gen3_phystatus_rst_toggle_g12),
+ .hssi_pipe_gen3_phystatus_rst_toggle_g3 (hssi_pipe_gen3_phystatus_rst_toggle_g3),
+ .hssi_pipe_gen3_rate_match_pad_insertion (hssi_pipe_gen3_rate_match_pad_insertion),
+ .hssi_pipe_gen3_test_out_sel (hssi_pipe_gen3_test_out_sel),
+ // parameters for twentynm_hssi_rx_pcs_pma_interface
+ .hssi_rx_pcs_pma_interface_block_sel (hssi_rx_pcs_pma_interface_block_sel),
+ .hssi_rx_pcs_pma_interface_channel_operation_mode (hssi_rx_pcs_pma_interface_channel_operation_mode),
+ .hssi_rx_pcs_pma_interface_clkslip_sel (hssi_rx_pcs_pma_interface_clkslip_sel),
+ .hssi_rx_pcs_pma_interface_lpbk_en (hssi_rx_pcs_pma_interface_lpbk_en),
+ .hssi_rx_pcs_pma_interface_master_clk_sel (hssi_rx_pcs_pma_interface_master_clk_sel),
+ .hssi_rx_pcs_pma_interface_pldif_datawidth_mode (hssi_rx_pcs_pma_interface_pldif_datawidth_mode),
+ .hssi_rx_pcs_pma_interface_pma_dw_rx (hssi_rx_pcs_pma_interface_pma_dw_rx),
+ .hssi_rx_pcs_pma_interface_pma_if_dft_en (hssi_rx_pcs_pma_interface_pma_if_dft_en),
+ .hssi_rx_pcs_pma_interface_pma_if_dft_val (hssi_rx_pcs_pma_interface_pma_if_dft_val),
+ .hssi_rx_pcs_pma_interface_prbs9_dwidth (hssi_rx_pcs_pma_interface_prbs9_dwidth),
+ .hssi_rx_pcs_pma_interface_prbs_clken (hssi_rx_pcs_pma_interface_prbs_clken),
+ .hssi_rx_pcs_pma_interface_prbs_ver (hssi_rx_pcs_pma_interface_prbs_ver),
+ .hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion (hssi_rx_pcs_pma_interface_rx_dyn_polarity_inversion),
+ .hssi_rx_pcs_pma_interface_rx_lpbk_en (hssi_rx_pcs_pma_interface_rx_lpbk_en),
+ .hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok (hssi_rx_pcs_pma_interface_rx_prbs_force_signal_ok),
+ .hssi_rx_pcs_pma_interface_rx_prbs_mask (hssi_rx_pcs_pma_interface_rx_prbs_mask),
+ .hssi_rx_pcs_pma_interface_rx_prbs_mode (hssi_rx_pcs_pma_interface_rx_prbs_mode),
+ .hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel (hssi_rx_pcs_pma_interface_rx_signalok_signaldet_sel),
+ .hssi_rx_pcs_pma_interface_rx_static_polarity_inversion (hssi_rx_pcs_pma_interface_rx_static_polarity_inversion),
+ .hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en (hssi_rx_pcs_pma_interface_rx_uhsif_lpbk_en),
+ // parameters for twentynm_hssi_rx_pld_pcs_interface
+ .hssi_rx_pld_pcs_interface_pcs_rx_block_sel (hssi_rx_pld_pcs_interface_pcs_rx_block_sel),
+ .hssi_rx_pld_pcs_interface_pcs_rx_clk_sel (hssi_rx_pld_pcs_interface_pcs_rx_clk_sel),
+ .hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en (hssi_rx_pld_pcs_interface_pcs_rx_hip_clk_en),
+ .hssi_rx_pld_pcs_interface_pcs_rx_output_sel (hssi_rx_pld_pcs_interface_pcs_rx_output_sel),
+ .hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel (hssi_rx_pld_pcs_interface_pcs_rx_clk_out_sel),
+ // parameters for twentynm_hssi_tx_pcs_pma_interface
+ .hssi_tx_pcs_pma_interface_bypass_pma_txelecidle (hssi_tx_pcs_pma_interface_bypass_pma_txelecidle),
+ .hssi_tx_pcs_pma_interface_channel_operation_mode (hssi_tx_pcs_pma_interface_channel_operation_mode),
+ .hssi_tx_pcs_pma_interface_lpbk_en (hssi_tx_pcs_pma_interface_lpbk_en),
+ .hssi_tx_pcs_pma_interface_master_clk_sel (hssi_tx_pcs_pma_interface_master_clk_sel),
+ .hssi_tx_pcs_pma_interface_pldif_datawidth_mode (hssi_tx_pcs_pma_interface_pldif_datawidth_mode),
+ .hssi_tx_pcs_pma_interface_pma_dw_tx (hssi_tx_pcs_pma_interface_pma_dw_tx),
+ .hssi_tx_pcs_pma_interface_pmagate_en (hssi_tx_pcs_pma_interface_pmagate_en),
+ .hssi_tx_pcs_pma_interface_prbs9_dwidth (hssi_tx_pcs_pma_interface_prbs9_dwidth),
+ .hssi_tx_pcs_pma_interface_prbs_clken (hssi_tx_pcs_pma_interface_prbs_clken),
+ .hssi_tx_pcs_pma_interface_prbs_gen_pat (hssi_tx_pcs_pma_interface_prbs_gen_pat),
+ .hssi_tx_pcs_pma_interface_sq_wave_num (hssi_tx_pcs_pma_interface_sq_wave_num),
+ .hssi_tx_pcs_pma_interface_sqwgen_clken (hssi_tx_pcs_pma_interface_sqwgen_clken),
+ .hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion (hssi_tx_pcs_pma_interface_tx_dyn_polarity_inversion),
+ .hssi_tx_pcs_pma_interface_tx_pma_data_sel (hssi_tx_pcs_pma_interface_tx_pma_data_sel),
+ .hssi_tx_pcs_pma_interface_tx_static_polarity_inversion (hssi_tx_pcs_pma_interface_tx_static_polarity_inversion),
+ .hssi_tx_pcs_pma_interface_pma_if_dft_en (hssi_tx_pcs_pma_interface_pma_if_dft_en),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock (hssi_tx_pcs_pma_interface_uhsif_cnt_step_filt_before_lock),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value (hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_after_lock_value),
+ .hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock (hssi_tx_pcs_pma_interface_uhsif_cnt_thresh_filt_before_lock),
+ .hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period (hssi_tx_pcs_pma_interface_uhsif_dcn_test_update_period),
+ .hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable (hssi_tx_pcs_pma_interface_uhsif_dcn_testmode_enable),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh (hssi_tx_pcs_pma_interface_uhsif_dead_zone_count_thresh),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable (hssi_tx_pcs_pma_interface_uhsif_dead_zone_detection_enable),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window (hssi_tx_pcs_pma_interface_uhsif_dead_zone_obser_window),
+ .hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size (hssi_tx_pcs_pma_interface_uhsif_dead_zone_skip_size),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel (hssi_tx_pcs_pma_interface_uhsif_delay_cell_index_sel),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin (hssi_tx_pcs_pma_interface_uhsif_delay_cell_margin),
+ .hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value (hssi_tx_pcs_pma_interface_uhsif_delay_cell_static_index_value),
+ .hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control (hssi_tx_pcs_pma_interface_uhsif_dft_dead_zone_control),
+ .hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control (hssi_tx_pcs_pma_interface_uhsif_dft_up_filt_control),
+ .hssi_tx_pcs_pma_interface_uhsif_enable (hssi_tx_pcs_pma_interface_uhsif_enable),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock (hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_after_lock),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock (hssi_tx_pcs_pma_interface_uhsif_lock_det_segsz_before_lock),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value (hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_after_lock_value),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value (hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_cnt_before_lock_value),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value (hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_after_lock_value),
+ .hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value (hssi_tx_pcs_pma_interface_uhsif_lock_det_thresh_diff_before_lock_value),
+ // parameters for twentynm_hssi_tx_pld_pcs_interface
+ .hssi_tx_pld_pcs_interface_hd_10g_advanced_user_mode_tx (hssi_tx_pld_pcs_interface_hd_10g_advanced_user_mode_tx),
+ .hssi_rx_pld_pcs_interface_hd_10g_advanced_user_mode_rx (hssi_rx_pld_pcs_interface_hd_10g_advanced_user_mode_rx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_transparent_pcs_rx (hssi_rx_pld_pcs_interface_hd_chnl_transparent_pcs_rx),
+ .hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel (hssi_tx_pld_pcs_interface_pcs_tx_clk_out_sel),
+ .hssi_tx_pld_pcs_interface_pcs_tx_clk_source (hssi_tx_pld_pcs_interface_pcs_tx_clk_source),
+ .hssi_tx_pld_pcs_interface_pcs_tx_data_source (hssi_tx_pld_pcs_interface_pcs_tx_data_source),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en (hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_en),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel (hssi_tx_pld_pcs_interface_pcs_tx_delay1_clk_sel),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl (hssi_tx_pld_pcs_interface_pcs_tx_delay1_ctrl),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel (hssi_tx_pld_pcs_interface_pcs_tx_delay1_data_sel),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en (hssi_tx_pld_pcs_interface_pcs_tx_delay2_clk_en),
+ .hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl (hssi_tx_pld_pcs_interface_pcs_tx_delay2_ctrl),
+ .hssi_tx_pld_pcs_interface_pcs_tx_output_sel (hssi_tx_pld_pcs_interface_pcs_tx_output_sel),
+ .hssi_rx_pld_pcs_interface_hd_10g_lpbk_en (hssi_rx_pld_pcs_interface_hd_10g_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_chnl_frequency_rules_en (hssi_rx_pld_pcs_interface_hd_chnl_frequency_rules_en),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pma_tx_clk_hz (hssi_tx_pld_pcs_interface_hd_chnl_pma_tx_clk_hz),
+ .hssi_tx_pld_pcs_interface_hd_chnl_shared_fifo_width_tx (hssi_tx_pld_pcs_interface_hd_chnl_shared_fifo_width_tx),
+ .hssi_rx_pld_pcs_interface_hd_10g_pma_dw_rx (hssi_rx_pld_pcs_interface_hd_10g_pma_dw_rx),
+ .hssi_tx_pld_pcs_interface_hd_fifo_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_fifo_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_8g_lpbk_en (hssi_rx_pld_pcs_interface_hd_8g_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_chnl_func_mode (hssi_rx_pld_pcs_interface_hd_chnl_func_mode),
+ .hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx (hssi_rx_pld_pcs_interface_hd_krfec_low_latency_en_rx),
+ .hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx (hssi_tx_pld_pcs_interface_hd_krfec_low_latency_en_tx),
+ .hssi_rx_pld_pcs_interface_hd_pldif_hrdrstctl_en (hssi_rx_pld_pcs_interface_hd_pldif_hrdrstctl_en),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_pmaif_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en (hssi_rx_pld_pcs_interface_hd_krfec_lpbk_en),
+ .hssi_tx_pld_pcs_interface_hd_8g_fifo_mode_tx (hssi_tx_pld_pcs_interface_hd_8g_fifo_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en (hssi_tx_pld_pcs_interface_hd_krfec_lpbk_en),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_lpbk_en (hssi_tx_pld_pcs_interface_hd_pmaif_lpbk_en),
+ .hssi_tx_pld_pcs_interface_hd_chnl_frequency_rules_en (hssi_tx_pld_pcs_interface_hd_chnl_frequency_rules_en),
+ .hssi_tx_pld_pcs_interface_hd_chnl_lpbk_en (hssi_tx_pld_pcs_interface_hd_chnl_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_sim_mode (hssi_rx_pld_pcs_interface_hd_pmaif_sim_mode),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pma_rx_clk_hz (hssi_rx_pld_pcs_interface_hd_chnl_pma_rx_clk_hz),
+ .hssi_rx_pld_pcs_interface_hd_fifo_shared_fifo_width_rx (hssi_rx_pld_pcs_interface_hd_fifo_shared_fifo_width_rx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_chnl_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_8g_pma_dw_rx (hssi_rx_pld_pcs_interface_hd_8g_pma_dw_rx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pld_fifo_mode_rx (hssi_rx_pld_pcs_interface_hd_chnl_pld_fifo_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_func_mode (hssi_tx_pld_pcs_interface_hd_chnl_func_mode),
+ .hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode (hssi_rx_pld_pcs_interface_hd_krfec_test_bus_mode),
+ .hssi_rx_pld_pcs_interface_hd_chnl_shared_fifo_width_rx (hssi_rx_pld_pcs_interface_hd_chnl_shared_fifo_width_rx),
+ .hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_krfec_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_pma_dw_rx (hssi_rx_pld_pcs_interface_hd_pmaif_pma_dw_rx),
+ .hssi_tx_pld_pcs_interface_hd_10g_shared_fifo_width_tx (hssi_tx_pld_pcs_interface_hd_10g_shared_fifo_width_tx),
+ .hssi_tx_pld_pcs_interface_hd_10g_fifo_mode_tx (hssi_tx_pld_pcs_interface_hd_10g_fifo_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_pma_dw_tx (hssi_tx_pld_pcs_interface_hd_pmaif_pma_dw_tx),
+ .hssi_rx_pld_pcs_interface_hd_10g_test_bus_mode (hssi_rx_pld_pcs_interface_hd_10g_test_bus_mode),
+ .hssi_rx_pld_pcs_interface_hd_10g_low_latency_en_rx (hssi_rx_pld_pcs_interface_hd_10g_low_latency_en_rx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_clklow_clk_hz (hssi_rx_pld_pcs_interface_hd_chnl_clklow_clk_hz),
+ .hssi_tx_pld_pcs_interface_hd_pldif_hrdrstctl_en (hssi_tx_pld_pcs_interface_hd_pldif_hrdrstctl_en),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_lpbk_en (hssi_rx_pld_pcs_interface_hd_pmaif_lpbk_en),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_sim_mode (hssi_tx_pld_pcs_interface_hd_pmaif_sim_mode),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_uhsif_tx_clk_hz (hssi_tx_pld_pcs_interface_hd_chnl_pld_uhsif_tx_clk_hz),
+ .hssi_rx_pld_pcs_interface_hd_8g_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_8g_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_chnl_hrdrstctl_en (hssi_rx_pld_pcs_interface_hd_chnl_hrdrstctl_en),
+ .hssi_rx_pld_pcs_interface_hd_chnl_fref_clk_hz (hssi_rx_pld_pcs_interface_hd_chnl_fref_clk_hz),
+ .hssi_tx_pld_pcs_interface_hd_fifo_shared_fifo_width_tx (hssi_tx_pld_pcs_interface_hd_fifo_shared_fifo_width_tx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pma_dw_tx (hssi_tx_pld_pcs_interface_hd_chnl_pma_dw_tx),
+ .hssi_tx_pld_pcs_interface_hd_8g_hip_mode (hssi_tx_pld_pcs_interface_hd_8g_hip_mode),
+ .hssi_tx_pld_pcs_interface_hd_8g_lpbk_en (hssi_tx_pld_pcs_interface_hd_8g_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_chnl_low_latency_en_rx (hssi_rx_pld_pcs_interface_hd_chnl_low_latency_en_rx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_tx_clk_hz (hssi_tx_pld_pcs_interface_hd_chnl_pld_tx_clk_hz),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pld_rx_clk_hz (hssi_rx_pld_pcs_interface_hd_chnl_pld_rx_clk_hz),
+ .hssi_tx_pld_pcs_interface_hd_10g_lpbk_en (hssi_tx_pld_pcs_interface_hd_10g_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_8g_fifo_mode_rx (hssi_rx_pld_pcs_interface_hd_8g_fifo_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_10g_pma_dw_tx (hssi_tx_pld_pcs_interface_hd_10g_pma_dw_tx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_pma_dw_rx (hssi_rx_pld_pcs_interface_hd_chnl_pma_dw_rx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_pld_fifo_mode_tx (hssi_tx_pld_pcs_interface_hd_chnl_pld_fifo_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_chnl_hrdrstctl_en (hssi_tx_pld_pcs_interface_hd_chnl_hrdrstctl_en),
+ .hssi_rx_pld_pcs_interface_hd_10g_fifo_mode_rx (hssi_rx_pld_pcs_interface_hd_10g_fifo_mode_rx),
+ .hssi_rx_pld_pcs_interface_hd_8g_hip_mode (hssi_rx_pld_pcs_interface_hd_8g_hip_mode),
+ .hssi_tx_pld_pcs_interface_hd_chnl_low_latency_en_tx (hssi_tx_pld_pcs_interface_hd_chnl_low_latency_en_tx),
+ .hssi_rx_pld_pcs_interface_hd_10g_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_10g_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_chnl_hip_en (hssi_tx_pld_pcs_interface_hd_chnl_hip_en),
+ .hssi_rx_pld_pcs_interface_hd_fifo_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_fifo_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_8g_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_8g_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_8g_pma_dw_tx (hssi_tx_pld_pcs_interface_hd_8g_pma_dw_tx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_lpbk_en (hssi_rx_pld_pcs_interface_hd_chnl_lpbk_en),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_pmaif_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_krfec_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_10g_channel_operation_mode (hssi_tx_pld_pcs_interface_hd_10g_channel_operation_mode),
+ .hssi_rx_pld_pcs_interface_hd_10g_shared_fifo_width_rx (hssi_rx_pld_pcs_interface_hd_10g_shared_fifo_width_rx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_channel_operation_mode (hssi_rx_pld_pcs_interface_hd_chnl_channel_operation_mode),
+ .hssi_tx_pld_pcs_interface_hd_10g_low_latency_en_tx (hssi_tx_pld_pcs_interface_hd_10g_low_latency_en_tx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_hip_en (hssi_rx_pld_pcs_interface_hd_chnl_hip_en),
+
+ // prot_mode
+ .cdr_pll_prot_mode (cdr_pll_prot_mode),
+ .cdr_pll_tx_pll_prot_mode (cdr_pll_tx_pll_prot_mode),
+ .pma_adapt_prot_mode (pma_adapt_prot_mode),
+ .pma_rx_odi_prot_mode (pma_rx_odi_prot_mode),
+ .pma_rx_buf_prot_mode (pma_rx_buf_prot_mode),
+ .pma_rx_buf_xrx_path_prot_mode (pma_rx_buf_xrx_path_prot_mode),
+ .pma_rx_dfe_prot_mode (pma_rx_dfe_prot_mode),
+ .pma_rx_deser_prot_mode (pma_rx_deser_prot_mode),
+ .pma_rx_sd_prot_mode (pma_rx_sd_prot_mode),
+ .pma_tx_buf_prot_mode (pma_tx_buf_prot_mode),
+ .pma_tx_buf_xtx_path_prot_mode (pma_tx_buf_xtx_path_prot_mode),
+ .pma_tx_ser_prot_mode (pma_tx_ser_prot_mode),
+ .pma_cgb_prot_mode (pma_cgb_prot_mode),
+ .hssi_rx_pld_pcs_interface_hd_8g_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_8g_prot_mode_rx),
+ .hssi_rx_pld_pcs_interface_hd_g3_prot_mode (hssi_rx_pld_pcs_interface_hd_g3_prot_mode),
+ .hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_krfec_prot_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_fifo_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_fifo_prot_mode_tx),
+ .hssi_rx_pld_pcs_interface_hd_pldif_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_pldif_prot_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_8g_prot_mode_tx),
+ .hssi_rx_pld_pcs_interface_hd_fifo_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_fifo_prot_mode_rx),
+ .hssi_rx_pld_pcs_interface_hd_pmaif_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_pmaif_prot_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_10g_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_10g_prot_mode_tx),
+ .hssi_tx_pcs_pma_interface_prot_mode_tx (hssi_tx_pcs_pma_interface_prot_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_pldif_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_pldif_prot_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_krfec_prot_mode_tx),
+ .hssi_rx_pld_pcs_interface_hd_chnl_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_chnl_prot_mode_rx),
+ .hssi_tx_pld_pcs_interface_hd_pmaif_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_pmaif_prot_mode_tx),
+ .hssi_tx_pld_pcs_interface_hd_g3_prot_mode (hssi_tx_pld_pcs_interface_hd_g3_prot_mode),
+ .hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx (hssi_tx_pld_pcs_interface_hd_chnl_prot_mode_tx),
+ .hssi_rx_pld_pcs_interface_hd_10g_prot_mode_rx (hssi_rx_pld_pcs_interface_hd_10g_prot_mode_rx),
+ .hssi_10g_rx_pcs_prot_mode (hssi_10g_rx_pcs_prot_mode),
+ .hssi_10g_tx_pcs_prot_mode (hssi_10g_tx_pcs_prot_mode),
+ .hssi_8g_rx_pcs_prot_mode (hssi_8g_rx_pcs_prot_mode),
+ .hssi_8g_tx_pcs_prot_mode (hssi_8g_tx_pcs_prot_mode),
+ .hssi_common_pcs_pma_interface_prot_mode (hssi_common_pcs_pma_interface_prot_mode),
+ .hssi_fifo_rx_pcs_prot_mode (hssi_fifo_rx_pcs_prot_mode),
+ .hssi_fifo_tx_pcs_prot_mode (hssi_fifo_tx_pcs_prot_mode),
+ .hssi_krfec_rx_pcs_prot_mode (hssi_krfec_rx_pcs_prot_mode),
+ .hssi_krfec_tx_pcs_prot_mode (hssi_krfec_tx_pcs_prot_mode),
+ .hssi_pipe_gen1_2_prot_mode (hssi_pipe_gen1_2_prot_mode),
+ .hssi_rx_pcs_pma_interface_prot_mode_rx (hssi_rx_pcs_pma_interface_prot_mode_rx),
+ .hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx (hssi_tx_pcs_pma_interface_pcie_sub_prot_mode_tx),
+ // datarate
+ .cdr_pll_datarate (cdr_pll_datarate),
+ .pma_adapt_datarate (pma_adapt_datarate),
+ .pma_rx_buf_datarate (pma_rx_buf_datarate),
+ .pma_rx_buf_xrx_path_datarate (pma_rx_buf_xrx_path_datarate),
+ .pma_rx_deser_datarate (pma_rx_deser_datarate),
+ .pma_rx_dfe_datarate (pma_rx_dfe_datarate),
+ .pma_rx_odi_datarate (pma_rx_odi_datarate),
+ .pma_tx_buf_datarate (pma_tx_buf_datarate),
+ .pma_tx_buf_xtx_path_datarate(pma_tx_buf_xtx_path_datarate),
+ .pma_cgb_datarate (pma_cgb_datarate),
+ // sup_mode
+ .cdr_pll_sup_mode (cdr_pll_sup_mode),
+ .hssi_8g_rx_pcs_sup_mode (hssi_8g_rx_pcs_sup_mode),
+ .hssi_8g_tx_pcs_sup_mode (hssi_8g_tx_pcs_sup_mode),
+ .hssi_10g_rx_pcs_sup_mode (hssi_10g_rx_pcs_sup_mode),
+ .hssi_10g_tx_pcs_sup_mode (hssi_10g_tx_pcs_sup_mode),
+ .hssi_common_pcs_pma_interface_sup_mode (hssi_common_pcs_pma_interface_sup_mode),
+ .hssi_gen3_rx_pcs_sup_mode (hssi_gen3_rx_pcs_sup_mode),
+ .hssi_gen3_tx_pcs_sup_mode (hssi_gen3_tx_pcs_sup_mode),
+ .hssi_krfec_rx_pcs_sup_mode (hssi_krfec_rx_pcs_sup_mode),
+ .hssi_krfec_tx_pcs_sup_mode (hssi_krfec_tx_pcs_sup_mode),
+ .hssi_pipe_gen1_2_sup_mode (hssi_pipe_gen1_2_sup_mode),
+ .hssi_pipe_gen3_sup_mode (hssi_pipe_gen3_sup_mode),
+ .hssi_rx_pcs_pma_interface_sup_mode (hssi_rx_pcs_pma_interface_sup_mode),
+ .hssi_tx_pcs_pma_interface_sup_mode (hssi_tx_pcs_pma_interface_sup_mode),
+ .pma_adapt_sup_mode (pma_adapt_sup_mode),
+ .pma_cgb_sup_mode (pma_cgb_sup_mode),
+ .pma_rx_buf_sup_mode (pma_rx_buf_sup_mode),
+ .pma_rx_buf_xrx_path_sup_mode (pma_rx_buf_xrx_path_sup_mode),
+ .pma_rx_deser_sup_mode (pma_rx_deser_sup_mode),
+ .pma_rx_dfe_sup_mode (pma_rx_dfe_sup_mode),
+ .pma_rx_odi_sup_mode (pma_rx_odi_sup_mode),
+ .pma_rx_sd_sup_mode (pma_rx_sd_sup_mode),
+ .pma_tx_buf_sup_mode (pma_tx_buf_sup_mode),
+ .pma_tx_buf_xtx_path_sup_mode (pma_tx_buf_xtx_path_sup_mode),
+ .pma_tx_ser_sup_mode (pma_tx_ser_sup_mode)
+ ) twentynm_xcvr_native_inst (
+ // nf_pma ports
+ /*input [bonded_lanes - 1:0] */.in_clk_cdr_b (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clk_cdr_t (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clk_fpll_b (tx_serial_clk0[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clk_fpll_t (tx_serial_clk2[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clk_lc_b (tx_serial_clk1[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clk_lc_hs (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clk_lc_t (tx_serial_clk3[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clkb_cdr_b (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clkb_cdr_t (1'b0),
+`ifndef ALTERA_RESERVED_QIS
+ /*input [bonded_lanes - 1:0] */.in_clkb_fpll_b (~tx_serial_clk0[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clkb_fpll_t (~tx_serial_clk2[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clkb_lc_b (~tx_serial_clk1[ig]),
+ /*input [bonded_lanes - 1:0] */.in_clkb_lc_t (~tx_serial_clk3[ig]),
+`else
+ /*input [bonded_lanes - 1:0] */.in_clkb_fpll_b (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clkb_fpll_t (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clkb_lc_b (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_clkb_lc_t (1'b0),
+`endif
+ /*input [bonded_lanes - 1:0] */.in_clkb_lc_hs (1'b0),
+ /*input [bonded_lanes * 6 - 1 : 0] */.in_cpulse_x6_dn_bus (tx_bonding_clocks[ig*6+:6]),
+ /*input [bonded_lanes * 6 - 1 : 0] */.in_cpulse_x6_up_bus (tx_bonding_clocks1[ig*6+:6]),
+ /*input [bonded_lanes * 6 - 1 : 0] */.in_cpulse_xn_dn_bus (tx_bonding_clocks2[ig*6+:6]),
+ /*input [bonded_lanes * 6 - 1 : 0] */.in_cpulse_xn_up_bus (tx_bonding_clocks3[ig*6+:6]),
+`ifndef ALTERA_RESERVED_QIS
+ /*input [bonded_lanes - 1:0] */.in_rx_n (~rx_serial_data[ig]),
+`else
+ /*input [bonded_lanes - 1:0] */.in_rx_n (1'b0),
+`endif
+ /*input [bonded_lanes - 1:0] */.in_rx_p (rx_serial_data[ig]),
+ /*output [bonded_lanes - 1:0] */.out_tx_n (/*unused*/ ),
+ /*output [bonded_lanes - 1:0] */.out_tx_p (tx_serial_data[ig]),
+ /*input [bonded_lanes * 12 - 1 : 0] */.in_ref_iqclk ({7'd0,rx_cdr_refclk4,rx_cdr_refclk3,rx_cdr_refclk2,rx_cdr_refclk1,rx_cdr_refclk0}),
+
+ // nf_pcs ports
+ // HIP
+ /*input [bonded_lanes * 64 - 1 : 0] */.in_hip_tx_data (tx_hip_data [ig*64+:64] ),
+ /*output [bonded_lanes * 51 - 1 : 0] */.out_hip_rx_data (rx_hip_data [ig*51+:51] ),
+ /*output [bonded_lanes * 3 - 1 : 0] */.out_hip_clk_out ({hip_frefclk[ig],int_hip_fixedclk,int_hip_pipe_pclk}),
+ /*output [bonded_lanes * 8 - 1 : 0] */.out_hip_ctrl_out (hip_ctrl [ig*8+:8] ),
+
+
+ // Standard datapath inputs
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_a1a2_size (rx_std_wa_a1a2size [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_bitloc_rev_en (rx_std_bitrev_ena [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_byte_rev_en (rx_std_byterev_ena [ig] ),
+ /*input [bonded_lanes * 3 - 1 : 0] */.in_pld_8g_eidleinfersel (pipe_rx_eidleinfersel [ig*3+:3]),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_encdt (rx_std_wa_patternalign [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_g3_rx_pld_rst_n (int_in_pld_8g_g3_rx_pld_rst_n ),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_g3_tx_pld_rst_n (int_in_pld_8g_g3_tx_pld_rst_n ),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_rddisable_tx (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_rdenable_rx (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_refclk_dig2 (1'b0), //TODO
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_rxpolarity (pipe_rx_polarity [ig] ),
+ /*input [bonded_lanes * 5 - 1 : 0] */.in_pld_8g_tx_boundary_sel (tx_std_bitslipboundarysel[ig*5+:5]),
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_wrdisable_rx (1'b0), // unused in Si
+ /*input [bonded_lanes - 1:0] */.in_pld_8g_wrenable_tx (1'b0), // unused in Si
+
+ // Standard datapath outputs
+ /*output [bonded_lanes * 4 - 1 : 0] */.out_pld_8g_a1a2_k1k2_flag (/*TODO*/),
+
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_empty_rmf (rx_std_rmfifo_empty [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_empty_rx (rx_std_pcfifo_empty [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_empty_tx (tx_std_pcfifo_empty [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_full_rmf (rx_std_rmfifo_full [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_full_rx (rx_std_pcfifo_full [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_full_tx (tx_std_pcfifo_full [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_rxelecidle (pipe_rx_elecidle [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_8g_signal_detect_out (rx_std_signaldetect [ig] ),
+ /*output [bonded_lanes * 5 - 1 : 0] */.out_pld_8g_wa_boundary (rx_std_bitslipboundarysel[ig*5+:5]),
+
+ // Enhanced datapath bonding
+ /*input [bonded_lanes * 5 - 1 : 0] */.in_bond_pcs10g_in_bot (bond_pcs10g_in_bot [ig] ),
+ /*input [bonded_lanes * 5 - 1 : 0] */.in_bond_pcs10g_in_top (bond_pcs10g_in_top [ig] ),
+ /*input [bonded_lanes * 13 - 1 : 0] */.in_bond_pcs8g_in_bot (bond_pcs8g_in_bot [ig] ),
+ /*input [bonded_lanes * 13 - 1 : 0] */.in_bond_pcs8g_in_top (bond_pcs8g_in_top [ig] ),
+ /*input [bonded_lanes * 12 - 1 : 0] */.in_bond_pmaif_in_bot (bond_pmaif_in_bot [ig] ),
+ /*input [bonded_lanes * 12 - 1 : 0] */.in_bond_pmaif_in_top (bond_pmaif_in_top [ig] ),
+
+ /*output [bonded_lanes * 5 - 1 : 0] */.out_bond_pcs10g_out_bot (bond_pcs10g_out_bot [ig] ),
+ /*output [bonded_lanes * 5 - 1 : 0] */.out_bond_pcs10g_out_top (bond_pcs10g_out_top [ig] ),
+ /*output [bonded_lanes * 13 - 1 : 0] */.out_bond_pcs8g_out_bot (bond_pcs8g_out_bot [ig] ),
+ /*output [bonded_lanes * 13 - 1 : 0] */.out_bond_pcs8g_out_top (bond_pcs8g_out_top [ig] ),
+ /*output [bonded_lanes * 12 - 1 : 0] */.out_bond_pmaif_out_bot (bond_pmaif_out_bot [ig] ),
+ /*output [bonded_lanes * 12 - 1 : 0] */.out_bond_pmaif_out_top (bond_pmaif_out_top [ig] ),
+
+ // Enhanced datapath inputs
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_krfec_rx_pld_rst_n (int_in_pld_10g_krfec_rx_pld_rst_n),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_krfec_tx_pld_rst_n (int_in_pld_10g_krfec_tx_pld_rst_n),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_rx_align_clr (rx_enh_fifo_align_clr [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_rx_clr_ber_count (rx_enh_highber_clr_cnt [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_krfec_rx_clr_errblk_cnt (rx_enh_clr_errblk_count [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_rx_rd_en (rx_enh_fifo_rd_en [ig] ),
+ /*input [bonded_lanes * 7 - 1 : 0] */.in_pld_10g_tx_bitslip (tx_enh_bitslip [ig*7+:7]),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_tx_burst_en (tx_enh_frame_burst_en [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_tx_data_valid (tx_enh_data_valid [ig] ),
+ /*input [bonded_lanes * 2 - 1 : 0] */.in_pld_10g_tx_diag_status (tx_enh_frame_diag_status [ig*2+:2]),
+ /*input [bonded_lanes - 1:0] */.in_pld_10g_tx_wordslip (1'b0), // engineering mode only
+ // Enhanced datapath outputs
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_align_val (rx_enh_fifo_align_val[ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_krfec_rx_blk_lock (rx_enh_blk_lock [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_crc32_err (rx_enh_crc32_err [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_data_valid (rx_enh_data_valid [ig]),
+ /*output [bonded_lanes * 2 - 1 : 0] */.out_pld_10g_krfec_rx_diag_data_status (rx_enh_frame_diag_status[ig*2+:2]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_empty (rx_enh_fifo_empty [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_fifo_del (rx_enh_fifo_del [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_fifo_insert (rx_enh_fifo_insert [ig]),
+ /*output [bonded_lanes * 5 - 1 : 0] */.out_pld_10g_rx_fifo_num (rx_enh_fifo_cnt [ig*5+:5]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_frame_lock (rx_enh_frame_lock [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_hi_ber (rx_enh_highber [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_oflw_err (rx_enh_fifo_full [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_pempty (rx_enh_fifo_pempty [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_rx_pfull (rx_enh_fifo_pfull [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_krfec_rx_frame (rx_enh_frame [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_burst_en_exe (/*TODO*/),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_empty (tx_enh_fifo_empty [ig]),
+ /*output [bonded_lanes * 4 - 1 : 0] */.out_pld_10g_tx_fifo_num (tx_enh_fifo_cnt [ig*4+:4]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_krfec_tx_frame (tx_enh_frame [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_full (tx_enh_fifo_full [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_pempty (tx_enh_fifo_pempty [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_pfull (tx_enh_fifo_pfull [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_10g_tx_wordslip_exe (/*unused*/ ), // engineering mode only
+
+ // Common interface inputs
+ /*input [bonded_lanes - 1:0] */.in_pld_bitslip (rx_bitslip [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_polinv_rx (rx_polinv [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_polinv_tx (tx_polinv [ig]),
+
+
+ /*input [bonded_lanes * 2 - 1 : 0] */.in_pld_rate (int_pipe_rate ),
+ /*input [bonded_lanes * 10 - 1 : 0] */.in_pld_reserved_in (10'd0),
+ /*input [bonded_lanes - 1:0] */.in_pld_rx_clk (rx_coreclkin [ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_rx_prbs_err_clr (int_rx_prbs_err_clr[ig] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_syncsm_en (1'b1),
+ /*input [bonded_lanes - 1:0] */.in_pld_tx_clk (tx_coreclkin [ig] ),
+ /*input [bonded_lanes * 18 - 1 : 0] */.in_pld_tx_control (tx_control [ig*18+:18] ),
+ /*input [bonded_lanes * 128 - 1 : 0] */.in_pld_tx_data (tx_parallel_data [ig*128+:128] ),
+ /*input [bonded_lanes - 1:0] */.in_pld_txelecidle (tx_pma_elecidle [ig] ),
+ /*output [bonded_lanes * 20 - 1 : 0] */.out_pld_rx_control (rx_control [ig*20+:20] ),
+ /*output [bonded_lanes * 128 - 1 : 0] */.out_pld_rx_data (rx_parallel_data [ig*128+:128] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_rx_prbs_done (rx_prbs_done [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_rx_prbs_err (rx_prbs_err [ig] ),
+ // Ultra high-speed interface
+ /*input [bonded_lanes - 1:0] */.in_pld_uhsif_tx_clk (tx_uhsif_clk [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_uhsif_lock (tx_uhsif_lock [ig] ),
+ /*output [bonded_lanes - 1:0] */.out_pld_uhsif_tx_clk_out (tx_uhsif_clkout [ig] ),
+ // KRFEC
+ /*input [bonded_lanes - 1:0] */.in_pld_mem_krfec_atpg_rst_n (1'b1),
+ /*input [bonded_lanes - 1:0] */.in_pld_atpg_los_en_n (1'b1),
+ /*output [bonded_lanes - 1:0] */.out_pld_krfec_tx_alignment (/*unused*/), // engineering mode only
+ // Gen 3 PCIe datapath
+ /*input [bonded_lanes * 18 - 1 : 0] */.in_pld_g3_current_coeff (pipe_g3_txdeemph [ig*18+:18] ),
+ /*input [bonded_lanes * 3 - 1 : 0] */.in_pld_g3_current_rxpreset (pipe_g3_rxpresethint[ig*3+:3] ),
+
+
+ /*input [bonded_lanes - 1:0] */.in_pld_ltr (int_rx_set_locktoref [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_partial_reconfig (1'b1),
+ /*input [bonded_lanes - 1:0] */.in_pld_pcs_refclk_dig (1'b0),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_adapt_start (rx_adapt_start [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_early_eios (1'b0),
+ /*input [bonded_lanes * 6 - 1 : 0] */.in_pld_pma_eye_monitor (/*TODO*/),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_ltd_b (~int_rx_set_locktodata [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_ppm_lock (1'b1), //TODO - Temporary until PPM detector enabled
+ /*input [bonded_lanes * 5 - 1 : 0] */.in_pld_pma_reserved_out ({~rx_adapt_reset[ig],4'd0}),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_rs_lpbk_b (~int_rx_seriallpbken [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_rx_qpi_pullup (~rx_pma_qpipulldn [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_rxpma_rstb (~rx_analogreset_to_pma[ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_tx_bonding_rstb (1'b0), // x1 bonding reset unused
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_tx_qpi_pulldn (~tx_pma_qpipulldn [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_tx_qpi_pullup (~tx_pma_qpipullup [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_txdetectrx (tx_pma_txdetectrx [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_txpma_rstb (~tx_analogreset_to_pma[ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pma_tx_bitslip (1'b0), // TODO - deprecated
+ /*input [bonded_lanes * 2 - 1 : 0] */.in_pld_pma_pcie_switch (2'd0),
+ /*input [bonded_lanes - 1:0] */.in_pld_pmaif_rxclkslip (rx_pma_clkslip [ig]),
+ /*input [bonded_lanes - 1:0] */.in_pld_pmaif_rx_pld_rst_n (int_in_pld_pmaif_rx_pld_rst_n),
+ /*input [bonded_lanes - 1:0] */.in_pld_pmaif_tx_pld_rst_n (int_in_pld_pmaif_tx_pld_rst_n),
+ /*input [bonded_lanes - 1:0] */.in_pma_hclk (pipe_hclk_in ),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_clklow (rx_clklow [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_fref (rx_fref [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pcs_rx_clk_out (rx_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pcs_tx_clk_out (tx_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_adapt_done (/*unused*/),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_clkdiv_rx_user (rx_pma_div_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_clkdiv_tx_user (tx_pma_div_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_clk_divtx_iqtxrx (tx_pma_iqtxrx_clkout [ig]), // Needed for cascading
+ /*output [bonded_lanes - 1:0] */.out_clk_divrx_iqtxrx (rx_pma_iqtxrx_clkout [ig]), // Needed for cascading
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_hclk (int_pipe_hclk_out ),
+
+ /*output [bonded_lanes * 2 - 1 : 0] */.out_pld_pma_pcie_sw_done (/*unused*/),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_pfdmode_lock (rx_is_lockedtoref [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_rx_clk_out (rx_pma_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_rx_detect_valid (/*TODO*/),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_rx_found (tx_pma_rxfound [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_rxpll_lock (rx_is_lockedtodata [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_signal_ok (/*TODO*/),
+ /*output [bonded_lanes * 8 - 1 : 0] */.out_pld_pma_testbus (/*unused*/),
+ /*output [bonded_lanes - 1:0] */.out_pld_pma_tx_clk_out (tx_pma_clkout [ig]),
+ /*output [bonded_lanes - 1:0] */.out_pld_pmaif_mask_tx_pll (/*unused*/),
+ /*output [bonded_lanes * 10 - 1 : 0] */.out_pld_reserved_out (/*unused*/),
+ /*output [bonded_lanes * 20 - 1 : 0] */.out_pld_test_data (pld_testbus_for_rate[ig*20+:20]),
+ // PCIe
+ /*input [bonded_lanes * 2 - 1 : 0] */.in_pcie_sw_done_master_in (int_pipe_sw_done ),
+ /*output [bonded_lanes * 2 - 1 : 0] */.out_pcie_sw_master (int_pipe_sw ),
+
+ // TODO
+ /*input [bonded_lanes * 3 - 1 : 0] */.in_i_rxpreset (3'd0),
+ /*input [bonded_lanes - 1:0] */.in_adapt_start (1'b0),
+
+
+
+ // nf_xcvr_avmm ports
+ // AVMM slave interface signals (user)
+ /*input wire [avmm_interfaces-1 :0] */.avmm_clk (avmm_clk [ig] ),
+ /*input wire [avmm_interfaces-1 :0] */.avmm_reset (avmm_reset [ig] ),
+ /*input wire [avmm_interfaces*32-1 :0] */.avmm_writedata (avmm_writedata [ig*8+:8] ),
+ /*input wire [avmm_interfaces*9-1 :0] */.avmm_address (avmm_address [ig*RCFG_ADDR_BITS+:9]), // Only lowest 9 bits drive hardware
+ /*input wire [avmm_interfaces-1 :0] */.avmm_write (avmm_write [ig] ),
+ /*input wire [avmm_interfaces-1 :0] */.avmm_read (avmm_read [ig] ),
+ /*output wire [avmm_interfaces*32-1 :0] */.avmm_readdata (avmm_readdata [ig*8+:8] ),
+ /*output wire [avmm_interfaces-1 :0] */.avmm_waitrequest (avmm_waitrequest [ig] ),
+ /*output wire [avmm_interfaces-1 :0] */.avmm_busy (avmm_busy [ig] ),
+ /*output wire [avmm_interfaces-1 :0] */.pld_cal_done (pld_cal_done [ig] ),
+ /*output wire [avmm_interfaces-1 :0] */.hip_cal_done (hip_cal_done [ig] ),
+
+// TO BE REMOVED
+ .out_hip_npor()
+ );
+
+
+
+end
+endgenerate
+
+endmodule // altera_xcvr_native_a10
+
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_commands_h.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_commands_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..af27c3d2eeff79cb76f00610a0e5dfbbb339d540
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_commands_h.sv
@@ -0,0 +1,411 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Revision 2.0
+package pcie_mgmt_commands_h;
+
+localparam CMD_SIZE = 5;
+localparam ARG1_SIZE = 32;
+
+localparam ROM_WIDTH = CMD_SIZE + ARG1_SIZE;
+
+// Define bit offsets within ROM word
+localparam ARG1_OFST = 0;
+localparam CMD_OFST = ARG1_OFST + ARG1_SIZE;
+
+// Bit field abstractions
+localparam WAIT_OFST = ARG1_OFST;
+localparam WAIT_SIZE = ARG1_SIZE;
+localparam REG_OFST = ARG1_OFST;
+localparam REG_SIZE = ARG1_SIZE;
+localparam REG_VAL_OFST = ARG1_OFST;
+localparam REG_VAL_SIZE = ARG1_SIZE;
+localparam BIT_INDEX_OFST = ARG1_OFST;
+localparam BIT_INDEX_SIZE = 5;
+localparam BIT_VAL_OFST = BIT_INDEX_OFST + BIT_INDEX_SIZE;
+localparam BIT_VAL_SIZE = 1;
+localparam BIT_INDEX2_OFST = BIT_VAL_OFST + BIT_VAL_SIZE;
+localparam CMP_VAL_OFST = ARG1_OFST;
+localparam CMP_VAL_SIZE = ARG1_SIZE;
+
+// Define all the commands
+localparam CMD_HALT = 5'd0,
+ CMD_WAIT = 5'd1,
+ // REG ops
+ CMD_LOAD_ADDR = 5'd2,
+ CMD_LOAD_RESULT = 5'd3,
+ CMD_WRITE_REG = 5'd4,
+ CMD_READ_REG = 5'd5,
+ CMD_READ_REG_BIT = 5'd6,
+ CMD_WAIT_REG = 5'd7,
+ CMD_WAIT_REG_BIT = 5'd8,
+ // PIO ops
+ CMD_WRITE_PIO_BIT_RES = 5'd9,
+ CMD_READ_PIO_BIT = 5'd10,
+ CMD_WAIT_PIO_BIT = 5'd11,
+ // Register ops
+ CMD_CMP_RESULT = 5'd12,
+ CMD_JNEZ = 5'd13,
+ //Commands for Read Modified Write
+ CMD_MOD = 5'd14,
+ CMD_MASK = 5'd15,
+ //Memory OPs
+ CMD_LD_MEM_ADDR = 5'd16,
+ CMD_ST_MEM_ADDR = 5'd17,
+ CMD_LD_REG_FROM_MEM = 5'd18,
+ CMD_LD_MOD_FROM_MEM = 5'd19,
+ CMD_ST_REG_TO_MEM = 5'd20,
+ CMD_INC_MEM_ADDR = 5'd21,
+ //ALU
+ CMD_ADD = 5'd22,
+ CMD_SUB = 5'd23,
+ CMD_CONVERT_CTLE = 5'd24;
+
+
+
+`define FUNC_PROTO function [ROM_WIDTH-1:0]
+
+// NOOP
+`FUNC_PROTO noop;
+ input unused;
+ begin
+ noop = sleep(0);
+ end
+endfunction
+
+
+// Halt function
+`FUNC_PROTO halt;
+ input unused;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_HALT;
+ halt = cmd;
+ end
+endfunction
+
+
+// Sleep function waits for the specified number of clocks
+`FUNC_PROTO sleep;
+ input [WAIT_SIZE-1:0] clock_cycle_count;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_WAIT;
+ cmd[WAIT_OFST+:WAIT_SIZE] = clock_cycle_count;
+ sleep = cmd;
+ end
+endfunction
+
+
+// Load a value into the address register
+`FUNC_PROTO load_address;
+ input [REG_SIZE-1:0] address;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_LOAD_ADDR;
+ cmd[REG_OFST+:REG_SIZE] = address;
+ load_address = cmd;
+ end
+endfunction
+
+
+// Load a value into the result register
+`FUNC_PROTO load_result;
+ input [REG_SIZE-1:0] result;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_LOAD_RESULT;
+ cmd[REG_OFST+:REG_SIZE] = result;
+ load_result = cmd;
+ end
+endfunction
+
+// Write the contents of the result register to the the register specified by
+// address.
+//
+// @writedata - Data to be written.
+`FUNC_PROTO write_reg;
+ input [REG_VAL_SIZE-1:0] unused;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_WRITE_REG;
+ write_reg = cmd;
+ end
+endfunction
+
+
+// Reads data from the register specified by address
+// and stores the read data into the result register
+//
+// @address - Address of the register to be read.
+`FUNC_PROTO read_reg;
+ input unused;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_READ_REG;
+ read_reg = cmd;
+ end
+endfunction
+
+//reads the data from the results register, and writes it to the local
+//register, using the mask to modify only the correct bits.
+//
+// @modify_data- data to be written into the scratch register.
+`FUNC_PROTO modify_reg;
+ input [REG_VAL_SIZE-1:0] modify_data;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_MOD;
+ cmd[REG_VAL_OFST+:REG_VAL_SIZE] = modify_data;
+ modify_reg = cmd;
+ end
+endfunction
+
+//Stores the mask value into a local register specifically for performing
+//RMW
+//
+// @mask_data - the mask for performing RMW
+`FUNC_PROTO mask_reg;
+ input [REG_VAL_SIZE-1:0] mask_data;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_MASK;
+ cmd[REG_VAL_OFST+:REG_VAL_SIZE] = mask_data;
+ mask_reg = cmd;
+ end
+endfunction
+
+
+// Reads a data bit from the register at the specified
+// address and stores it in the result register
+`FUNC_PROTO read_reg_bit;
+ input [BIT_INDEX_SIZE-1:0] bit_index;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_READ_REG_BIT;
+ cmd[BIT_INDEX_OFST+:BIT_INDEX_SIZE] = bit_index;
+ read_reg_bit = cmd;
+ end
+endfunction
+
+
+// Wait for register to equal value
+`FUNC_PROTO wait_for_reg;
+ input [REG_VAL_SIZE-1:0] expected_data;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_WAIT_REG;
+ cmd[REG_VAL_OFST+:REG_VAL_SIZE] = expected_data;
+ wait_for_reg = cmd;
+ end
+endfunction
+
+
+// Wait for a register bit to be 0 or 1
+`FUNC_PROTO wait_for_reg_bit;
+ input [BIT_INDEX_SIZE-1:0] bit_index;
+ input [REG_VAL_SIZE-1:0] expected_bit_value;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_WAIT_REG_BIT;
+ cmd[BIT_INDEX_OFST+:BIT_INDEX_SIZE] = bit_index;
+ cmd[BIT_VAL_OFST+:BIT_VAL_SIZE] = expected_bit_value;
+ wait_for_reg_bit = cmd;
+ end
+endfunction
+
+// Write bit from result register to PIO port bit
+`FUNC_PROTO write_result_bit_to_pio_bit;
+ input [BIT_INDEX_SIZE-1:0] result_bit_index;
+ input [BIT_INDEX_SIZE-1:0] pio_bit_index;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_WRITE_PIO_BIT_RES;
+ cmd[BIT_INDEX_OFST+:BIT_INDEX_SIZE] = pio_bit_index;
+ cmd[BIT_INDEX2_OFST+:BIT_INDEX_SIZE] = result_bit_index;
+ write_result_bit_to_pio_bit = cmd;
+ end
+endfunction
+
+
+// Read PIO bit and store value (0 or 1) to internal result register
+`FUNC_PROTO read_pio_bit;
+ input [BIT_INDEX_SIZE-1:0] bit_index;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_READ_PIO_BIT;
+ cmd[BIT_INDEX_OFST+:BIT_INDEX_SIZE] = bit_index;
+ read_pio_bit = cmd;
+ end
+endfunction
+
+
+// Wait for a bit on the PIO input to be 0 or 1
+`FUNC_PROTO wait_for_pio_bit;
+ input [BIT_INDEX_SIZE-1:0] bit_index;
+ input expected_bit_value;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_WAIT_PIO_BIT;
+ cmd[BIT_INDEX_OFST+:BIT_INDEX_SIZE] = bit_index;
+ cmd[BIT_VAL_OFST+:BIT_VAL_SIZE] = expected_bit_value;
+ wait_for_pio_bit = cmd;
+ end
+endfunction
+
+
+// Compare the value to the result register and staore the compare result
+// (0 or 1) in the result register
+`FUNC_PROTO compare_result;
+ input [CMP_VAL_SIZE-1:0] compare_value;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_CMP_RESULT;
+ cmd[CMP_VAL_OFST+:CMP_VAL_SIZE] = compare_value;
+ compare_result = cmd;
+ end
+endfunction
+
+
+// Compare the value in the result register to 0
+// If they are equal, continue execution, otherwise, jump to the
+// command previously stored by the set_jump_address command.
+`FUNC_PROTO jump_not_equal_zero;
+ input [CMP_VAL_SIZE-1:0] address;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_JNEZ;
+ cmd[REG_OFST+:REG_SIZE] = address;
+ jump_not_equal_zero = cmd;
+ end
+endfunction
+
+`FUNC_PROTO add_to_reg;
+ input [REG_SIZE-1:0] value;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_ADD;
+ cmd[REG_OFST+:REG_SIZE] = value;
+ add_to_reg = cmd;
+ end
+endfunction
+
+`FUNC_PROTO convert_ctle;
+ input [REG_SIZE-1:0] value;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_CONVERT_CTLE;
+ cmd[REG_OFST+:REG_SIZE] = value;
+ convert_ctle = cmd;
+ end
+endfunction
+
+`FUNC_PROTO sub_from_reg;
+ input [REG_SIZE-1:0] value;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_SUB;
+ cmd[REG_OFST+:REG_SIZE] = value;
+ sub_from_reg = cmd;
+ end
+endfunction
+
+`FUNC_PROTO inc_mem_address;
+ input unused;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_INC_MEM_ADDR;
+ inc_mem_address = cmd;
+ end
+endfunction
+
+`FUNC_PROTO load_mem_addr_to_reg;
+ input unused;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_LD_MEM_ADDR;
+ load_mem_addr_to_reg = cmd;
+ end
+endfunction
+
+`FUNC_PROTO store_reg_to_mem_addr;
+ input [REG_SIZE-1:0] address;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_ST_MEM_ADDR;
+ cmd[REG_OFST+:REG_SIZE] = address;
+ store_reg_to_mem_addr = cmd;
+ end
+endfunction
+
+`FUNC_PROTO wr_to_mem_address;
+ input unused;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_ST_REG_TO_MEM;
+ wr_to_mem_address = cmd;
+ end
+endfunction
+
+`FUNC_PROTO rd_from_mem_address;
+ input unused;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_LD_REG_FROM_MEM;
+ rd_from_mem_address = cmd;
+ end
+endfunction
+
+`FUNC_PROTO modify_reg_from_mem_address;
+ input [REG_SIZE-1:0] mask;
+ reg [ROM_WIDTH-1:0] cmd;
+ begin
+ cmd = {ROM_WIDTH{1'b0}};
+ cmd[REG_OFST+:REG_SIZE] = mask;
+ cmd[CMD_OFST+:CMD_SIZE] = CMD_LD_MOD_FROM_MEM;
+ modify_reg_from_mem_address = cmd;
+ end
+endfunction
+
+// Log base 2 function for calculating bus widths
+function integer clogb2;
+ input [31:0] value;
+ for (clogb2=0; value>0; clogb2=clogb2+1)
+ value = value>>1;
+endfunction
+
+endpackage
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_cpu.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_cpu.sv
new file mode 100644
index 0000000000000000000000000000000000000000..95b8c6d0150a3bf59c8f592821ef1e0219a258fe
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_cpu.sv
@@ -0,0 +1,329 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ps/1ps
+
+// Revision 2.1
+module pcie_mgmt_cpu #(
+ parameter PIO_OUT_SIZE = 8, // Width of PIO output port
+ parameter PIO_IN_SIZE = 8, // Width of PIO input port
+ parameter [PIO_OUT_SIZE-1:0] PIO_OUT_INIT_VALUE = 0, // Initial value for pio_out registers
+ parameter ROM_DEPTH = 512, // Depth of command ROM
+ parameter MEM_DEPTH = 8,
+ parameter ROM_WIDTH = pcie_mgmt_commands_h::ROM_WIDTH,
+ parameter ADDR_WIDTH = pcie_mgmt_commands_h::clogb2(ROM_DEPTH)
+ ) (
+ input clk,
+ input reset,
+
+ output reg av_write,
+ output reg av_read,
+ output reg [30:0] av_address,
+ output reg [31:0] av_writedata,
+ input [31:0] av_readdata,
+ input av_waitrequest,
+
+ // Instruction master (ROM interface)
+ output reg [ADDR_WIDTH-1:0] rom_address,
+ output rom_read,
+ input [ ROM_WIDTH-1:0] rom_data,
+
+ output reg [PIO_OUT_SIZE-1:0] pio_out,
+ input [ PIO_IN_SIZE-1:0] pio_in
+);
+
+import pcie_mgmt_commands_h::*; // Contains low-level instructions
+
+integer i;
+localparam ST_FETCH = 0, // Fetching and decoding command
+ ST_WAIT = 1, // Waiting for a number of clock cycles
+ ST_WRITE_REG = 2, // Writing to an avalon register
+ ST_READ_REG = 3, // Reading from an avalon register
+ ST_WAIT_PIO = 4, // Reading from the PIO input
+ ST_HALT = 5; // HALT, no more commands
+
+// State machine signals
+reg [ 2:0] state;
+reg [ 2:0] next_state;
+reg [31:0] wait_count;
+wire wait_done;
+wire read_reg_done;
+
+// ROM operands
+wire [CMD_SIZE-1:0] rom_cmd;
+wire [REG_VAL_SIZE-1:0] reg_val;
+wire [REG_VAL_SIZE-1:0] mask_val;
+wire [REG_SIZE-1:0] reg_addr;
+wire [BIT_INDEX_SIZE-1:0] bit_index;
+wire [BIT_INDEX_SIZE-1:0] bit_index2;
+wire bit_val;
+wire [WAIT_SIZE-1:0] wait_val;
+wire [CMP_VAL_SIZE-1:0] cmp_val;
+
+// Internal signals
+reg cmd_done;
+wire reg_match;
+wire reg_bit_match;
+wire pio_bit_match;
+wire [REG_VAL_SIZE-1:0] mem_data;
+reg [REG_VAL_SIZE-1:0] r0;
+reg [REG_VAL_SIZE-1:0] mem_addr;
+reg [REG_VAL_SIZE-1:0] mask = {REG_VAL_SIZE{1'b0}};
+reg [REG_VAL_SIZE-1:0] cpu_memory [0:MEM_DEPTH-1];
+
+//*********************************************************************
+//************************ Command ROM ********************************
+assign rom_read = cmd_done | reset;
+//********************** End Command ROM ******************************
+//*********************************************************************
+
+//*********************************************************************
+//**************** Extract Operands From ROM Data *********************
+assign rom_cmd = rom_data[CMD_OFST+:CMD_SIZE];
+assign reg_addr = rom_data[REG_OFST+:REG_SIZE];
+assign wait_val = rom_data[WAIT_OFST+:WAIT_SIZE];
+
+assign reg_val = rom_data[REG_VAL_OFST+:REG_VAL_SIZE];
+assign mask_val = rom_data[REG_VAL_OFST+:REG_VAL_SIZE];
+assign bit_index = rom_data[BIT_INDEX_OFST+:BIT_INDEX_SIZE];
+assign bit_index2= rom_data[BIT_INDEX2_OFST+:BIT_INDEX_SIZE];
+assign bit_val = rom_data[BIT_VAL_OFST+:BIT_VAL_SIZE];
+
+assign cmp_val = rom_data[CMP_VAL_OFST+:CMP_VAL_SIZE];
+//************** End Extract Operands From ROM Data *******************
+//*********************************************************************
+
+
+//*********************************************************************
+//************************ Internal Signals ***************************
+// Matches
+assign reg_match = (av_readdata == reg_val);
+assign reg_bit_match = (av_readdata[bit_index] == bit_val);
+assign pio_bit_match = (pio_in [bit_index] == bit_val);
+// Done flags
+assign wait_done = !wait_count;
+assign read_reg_done = (rom_cmd == CMD_WAIT_REG) ? reg_match :
+ (rom_cmd == CMD_WAIT_REG_BIT) ? reg_bit_match :
+ 1'b1;
+
+always @* begin
+ case(state)
+ ST_FETCH:
+ case(rom_cmd)
+ CMD_LOAD_ADDR,
+ CMD_LOAD_RESULT,
+ CMD_WRITE_PIO_BIT_RES,
+ CMD_READ_PIO_BIT,
+ //--self
+ CMD_MOD,
+ CMD_MASK,
+ CMD_LD_MEM_ADDR,
+ CMD_ST_MEM_ADDR,
+ CMD_ST_REG_TO_MEM,
+ CMD_LD_REG_FROM_MEM,
+ CMD_LD_MOD_FROM_MEM,
+ CMD_INC_MEM_ADDR,
+ CMD_ADD,
+ CMD_CONVERT_CTLE,
+ CMD_SUB,
+ CMD_CMP_RESULT:
+ cmd_done = 1'b1;
+ default: cmd_done = 1'b0;
+
+ endcase
+ ST_WAIT: cmd_done = wait_done;
+ ST_WRITE_REG: cmd_done = !av_waitrequest;
+ ST_READ_REG: cmd_done = !av_waitrequest & read_reg_done;
+ ST_WAIT_PIO: cmd_done = pio_bit_match;
+ default: cmd_done = 1'b0;
+ endcase
+end
+//************************ Internal Signals ***************************
+//*********************************************************************
+
+
+//*********************************************************************
+//************************ State Machine ******************************
+// State decoder
+always @(posedge clk or posedge reset)
+ if(reset) state <= ST_FETCH;
+ else if(state == ST_FETCH) state <= next_state;
+ else if(cmd_done) state <= next_state;
+
+always @*
+ begin
+ case(state)
+ // Get next command
+ ST_FETCH:
+ case(rom_cmd)
+ CMD_HALT: next_state = ST_HALT;
+
+ CMD_WRITE_REG: next_state = ST_WRITE_REG;
+
+ CMD_READ_REG,
+ CMD_READ_REG_BIT,
+ CMD_WAIT_REG,
+ CMD_WAIT_REG_BIT: next_state = ST_READ_REG;
+
+ CMD_WAIT_PIO_BIT: next_state = ST_WAIT_PIO;
+
+ CMD_JNEZ,
+ CMD_WAIT: next_state = ST_WAIT;
+ default: next_state = state;
+
+ endcase
+ // Wait
+ ST_WAIT: next_state = ST_FETCH;
+ // Write
+ ST_WRITE_REG: next_state = ST_FETCH;
+ // Read register
+ ST_READ_REG: next_state = ST_FETCH;
+ // Read the PIO port
+ ST_WAIT_PIO: next_state = ST_FETCH;
+ // HALT!(remain here)
+ ST_HALT: next_state = ST_HALT;
+ default: next_state = state;
+ endcase
+ end
+//********************** End State Machine ****************************
+//*********************************************************************
+
+
+//*********************************************************************
+//*********************** Output Encoders *****************************
+
+// Registers changing only on fetch
+always @(posedge clk or posedge reset)
+ if(reset)
+ rom_address <= {ADDR_WIDTH{1'b0}};
+ else if((state == ST_FETCH) & (rom_cmd == CMD_JNEZ) & |r0)
+ rom_address <= reg_addr[0+:ADDR_WIDTH];
+ else if(cmd_done)
+ rom_address <= rom_address + { {(ADDR_WIDTH-1){1'b0}}, 1'b1};
+
+
+// Avalon interface decoder
+always @(posedge clk or posedge reset)
+ if(reset) begin
+ av_write <= 1'b0;
+ av_read <= 1'b0;
+ av_address <= 31'd0;
+ av_writedata<= 32'd0;
+ end else begin
+ case(state)
+ // Get next command
+ ST_FETCH: begin
+ case(rom_cmd)
+ CMD_LOAD_ADDR:
+ av_address <= reg_addr[30:0];
+
+ CMD_WRITE_REG: begin
+ av_write <= 1'b1;
+ av_writedata<= r0;
+ end
+ CMD_READ_REG,
+ CMD_READ_REG_BIT,
+ CMD_WAIT_REG,
+ CMD_WAIT_REG_BIT:
+ av_read <= 1'b1;
+ endcase
+ end
+ // Write
+ ST_WRITE_REG: av_write <= ~cmd_done;
+ // Read register
+ ST_READ_REG: av_read <= ~cmd_done;
+ endcase
+ end
+
+
+// Wait counter
+always @(posedge clk or posedge reset)
+ if(reset) wait_count <= 32'd0;
+ else if((state == ST_FETCH) && (rom_cmd == CMD_WAIT))
+ wait_count <= wait_val;
+ else if((state == ST_WAIT) && !cmd_done)
+ wait_count <= wait_count + 32'hffffffff;
+
+
+// pio_out decoder
+always @(posedge clk or posedge reset)
+ if(reset) pio_out <= PIO_OUT_INIT_VALUE[0+:PIO_OUT_SIZE];
+ else if(state == ST_FETCH) begin
+ if(rom_cmd == CMD_WRITE_PIO_BIT_RES)
+ pio_out[bit_index] <= r0[bit_index2];
+ end
+
+// Error decoder
+assign mem_data = cpu_memory[mem_addr];
+always @(posedge clk or posedge reset)
+ if(reset) begin
+ r0 <= {REG_VAL_SIZE{1'b0}};
+ mask <= {REG_VAL_SIZE{1'b0}};
+ mem_addr <= {REG_VAL_SIZE{1'b0}};
+ for( i = 0; i < MEM_DEPTH; i = i + 1 ) begin
+ cpu_memory[i] <= 'd0;
+ end
+ end else begin
+ for( i = 0; i < MEM_DEPTH; i = i + 1 ) begin
+ cpu_memory[i] <= cpu_memory[i];
+ end
+
+ case(state)
+ ST_FETCH:
+ if(rom_cmd == CMD_CMP_RESULT) begin
+ r0 <= {CMP_VAL_SIZE{1'b0}};
+ r0[0] <= (r0 == cmp_val) ? 1'b0 : 1'b1;
+ end else if(rom_cmd == CMD_LOAD_RESULT) begin
+ r0 <= reg_val;
+ end else if(rom_cmd == CMD_READ_PIO_BIT) begin
+ r0 <= {{REG_VAL_SIZE-1{1'b0}},pio_in[bit_index]};
+ end else if(rom_cmd == CMD_MASK) begin
+ //Stores the mask in a local register.
+ mask <= mask_val;
+ end else if(rom_cmd == CMD_MOD) begin
+ r0 <= ((mask & reg_val) | (~mask & r0));
+ end else if(rom_cmd == CMD_ADD) begin
+ r0 <= r0+reg_val;
+ end else if(rom_cmd == CMD_CONVERT_CTLE) begin
+ r0 <= (mem_data[3:1] == 3'b111) ? {r0[REG_VAL_SIZE-1:6],5'b11100,r0[0]} : {r0[REG_VAL_SIZE-1:6],mem_data[3:0],1'b0,r0[0]};
+ end else if(rom_cmd == CMD_SUB) begin
+ r0 <= r0-reg_val;
+ end else if(rom_cmd == CMD_LD_MEM_ADDR) begin
+ r0 <= mem_addr;
+ end else if(rom_cmd == CMD_ST_MEM_ADDR) begin
+ mem_addr <= r0;
+ end else if(rom_cmd == CMD_INC_MEM_ADDR) begin
+ mem_addr <= mem_addr + 32'b1;
+ end else if(rom_cmd == CMD_LD_REG_FROM_MEM) begin
+ r0 <= mem_data;
+ end else if(rom_cmd == CMD_LD_MOD_FROM_MEM) begin
+ r0 <= ((mask_val & mem_data) | (~mask_val & r0));
+ end else if(rom_cmd == CMD_ST_REG_TO_MEM) begin
+ cpu_memory[mem_addr] <= r0;
+ end
+
+
+ ST_READ_REG:
+ if(cmd_done)
+ if(rom_cmd == CMD_READ_REG_BIT)
+ r0 <= {{REG_VAL_SIZE-1{1'b0}},av_readdata[bit_index]};
+ else
+ r0 <= av_readdata;
+ ST_WAIT_PIO:
+ r0 <= {{REG_VAL_SIZE-1{1'b0}},pio_in[bit_index]};
+ endcase
+ end
+//********************* End Output Encoders ***************************
+//*********************************************************************
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_functions_h.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_functions_h.sv
new file mode 100644
index 0000000000000000000000000000000000000000..512e09fc7c473e35c716ead611345bb39bbcb161
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_functions_h.sv
@@ -0,0 +1,447 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Revision 2.0
+package pcie_mgmt_functions_h;
+
+`define f_set_rom prog_rom[rom_i]=
+`define f_inc_rom rom_i=rom_i+1
+
+import pcie_mgmt_commands_h::*;
+
+localparam MAX_LABEL = 512;
+localparam MAX_DEPTH = 4096;
+
+// These should be synthesized away
+integer rom_labels[0:(MAX_LABEL-1)];
+reg [ROM_WIDTH-1:0] prog_rom [0:(MAX_DEPTH-1)]; // Command storage ROM
+integer rom_i;
+integer clocks_per_second; // Must be set from outside
+
+
+task set_clocks_per_second;
+ input integer new_clocks_per_second;
+ begin
+ clocks_per_second = new_clocks_per_second;
+ end
+endtask
+
+
+task f_noop;
+ begin
+ `f_set_rom sleep(0);
+ `f_inc_rom;
+ end
+endtask
+
+// Halt function
+// Required as last instruction in ROM. Instructs the command
+// processor to halt execution indefinitely.
+//
+// @param unused - An unused but required value.
+task f_halt;
+ begin
+ `f_set_rom halt(0);
+ `f_inc_rom;
+ end
+endtask
+
+// Sleep function
+// Pauses execution for the number of clock cycles specified
+// by the parameter "ticks"
+//
+// @param ticks - The number of clock cycles to sleep
+task f_sleep;
+ input [WAIT_SIZE-1:0] ticks;
+ begin
+ `f_set_rom sleep(ticks);
+ `f_inc_rom;
+ end
+endtask
+
+task f_convert_ctle;
+ begin
+ `f_set_rom convert_ctle(0);
+ `f_inc_rom;
+ end
+endtask
+
+task f_add_to_reg;
+ input [REG_SIZE-1:0] value;
+ begin
+ `f_set_rom add_to_reg(value);
+ `f_inc_rom;
+ end
+endtask
+
+task f_mod_mem_value;
+ input [REG_SIZE-1:0] mask;
+ begin
+ `f_set_rom modify_reg_from_mem_address(mask);
+ `f_inc_rom;
+ end
+endtask
+
+task f_sub_from_reg;
+ input [REG_SIZE-1:0] value;
+ begin
+ `f_set_rom sub_from_reg(value);
+ `f_inc_rom;
+ end
+endtask
+
+task f_inc_mem_address;
+ begin
+ `f_set_rom inc_mem_address(0);
+ `f_inc_rom;
+ end
+endtask
+
+task f_load_mem_address;
+ begin
+ `f_set_rom load_mem_addr_to_reg(0);
+ `f_inc_rom;
+ end
+endtask
+
+task f_store_mem_address;
+ begin
+ `f_set_rom store_reg_to_mem_addr(0);
+ `f_inc_rom;
+ end
+endtask
+
+task f_st_reg_to_address;
+ begin
+ `f_set_rom wr_to_mem_address(0);
+ `f_inc_rom;
+ end
+endtask
+
+task f_ld_address_to_reg;
+ begin
+ `f_set_rom rd_from_mem_address(0);
+ `f_inc_rom;
+ end
+endtask
+
+// Micro-sleep function
+// Pauses execution for the number of microseconds specified
+// by the parameter "usecs"
+//
+// @param usecs - The number of microseconds to sleep.
+task f_usleep;
+ input integer usecs;
+ reg [WAIT_SIZE-1:0] ticks;
+ begin
+ ticks = (clocks_per_second / 1000000) * usecs;
+ f_sleep(ticks);
+ end
+endtask
+
+
+// Load the internal result register with the value
+// specified.
+//
+// @param datain - The value to be loaded to the internal result
+// register
+task f_load_result;
+ input [REG_SIZE-1:0] datain;
+ begin
+ `f_set_rom load_result(datain);
+ `f_inc_rom;
+ end
+endtask
+
+// Write result to register function
+// Writes the data stored in the internal result register to the
+// register specified by the parameter "address".
+//
+// @param address - Address of the register to write
+task f_write_result_to_reg;
+ input [REG_SIZE-1:0] address;
+ begin
+ `f_set_rom load_address(address);
+ `f_inc_rom;
+ `f_set_rom write_reg(0);
+ `f_inc_rom;
+ end
+endtask
+
+
+// Write register function
+// Writes the data specified by the parameter "writedata" to the
+// register specified by the parameter "address". First stores
+// the writedata in the internal result register then writes it
+// to the the specified address.
+//
+// @param address - Address of the register to write
+// @param writedata - Data to be written to register
+task f_write_reg;
+ input [REG_SIZE-1:0] address;
+ input [REG_VAL_SIZE-1:0] writedata;
+ begin
+ f_load_result(writedata);
+ f_write_result_to_reg(address);
+ end
+endtask
+
+
+//Modifies the value of the results register with the value of the
+//you with to write to the address. Specify two values. The first
+//is used to mask the data register, and the second is the data value
+//itself. A 1 in the mask specifies that bit to be written from the data
+//value. A 0 in the mask specifies that bit to be igrored. ie recycled.
+//
+//@param mask_data - 32-bit mask for RMW
+//@param modify_data - 32-bt data value for the register
+//
+//Use: f_modify_reg(mask_data, modify_data);
+task f_modify_reg;
+ input [REG_VAL_SIZE-1:0] mask_data;
+ input [REG_VAL_SIZE-1:0] modify_data;
+ begin
+ `f_set_rom mask_reg(mask_data);
+ `f_inc_rom;
+ `f_set_rom modify_reg(modify_data);
+ `f_inc_rom;
+ end
+endtask
+
+
+// Read register function
+// Reads data from the register specified by the parameter "address"
+// and stores the value in the internal result register.
+//
+// @param address - Address of the register to read
+task f_read_reg;
+ input [REG_SIZE-1:0] address;
+ begin
+ `f_set_rom load_address(address);
+ `f_inc_rom;
+ `f_set_rom read_reg(0);
+ `f_inc_rom;
+ end
+endtask
+
+// Read register bit function
+// Reads data from the register specified by the parameter "address"
+// and stores the value of the bit within the register specified by
+// the parameter "bit_index" in the internal result register.
+//
+// @param address - Address of the register to read
+// @param bit_index - Index of the bit within the register to read
+task f_read_reg_bit;
+ input [REG_SIZE-1:0] address;
+ input [BIT_INDEX_SIZE-1:0] bit_index;
+ begin
+ `f_set_rom load_address(address);
+ `f_inc_rom;
+ `f_set_rom read_reg_bit(bit_index);
+ `f_inc_rom;
+ end
+endtask
+
+
+// Wait for register function
+// Continuously reads data from the register specified by the parameter
+// "address" and waits until the register's value equals the value
+// specified by parameter "expected_data" before continuing execution.
+// The value of the register is stored in the internal result register.
+//
+// @param address - Address of the register to read (and wait for)
+// @param expected_data - Value to wait for the register to equal.
+task f_wait_for_reg;
+ input [REG_SIZE-1:0] address;
+ input [REG_VAL_SIZE-1:0] expected_data;
+ begin
+ `f_set_rom load_address(address);
+ `f_inc_rom;
+ `f_set_rom wait_for_reg(expected_data);
+ `f_inc_rom;
+ end
+endtask
+
+// Wait for register bit function
+// Continuously reads data from the register specified by the parameter
+// "address" and waits until the value of the bit specified by "bit_index"
+// equals the value specified by the parameter "expected_data" (0 or 1).
+//
+// @param address - Address of the register to read (and wait for).
+// @param bit_index - Index of the bit within the register to read.
+task f_wait_for_reg_bit;
+ input [REG_SIZE-1:0] address;
+ input [BIT_INDEX_SIZE-1:0] bit_index;
+ input [REG_VAL_SIZE-1:0] expected_data;
+ begin
+ `f_set_rom load_address(address);
+ `f_inc_rom;
+ `f_set_rom wait_for_reg_bit(bit_index, expected_data);
+ `f_inc_rom;
+ end
+endtask
+
+
+// Write bit from result register to PIO output bit
+// Reads a bit specified by the parameter "result_bit_index" within the
+// internal result register and writes the value to the PIO output port bit
+// specified by the parameter "pio_bit_index".
+//
+// @param result_bit_index - Index of the bit within the internal result
+// register.
+// @param pio_bit_index - Index of the bit within the PIO output port to write
+// to.
+task f_write_result_bit_to_pio_bit;
+ input [BIT_INDEX_SIZE-1:0] result_bit_index;
+ input [BIT_INDEX_SIZE-1:0] pio_bit_index;
+ begin
+ `f_set_rom write_result_bit_to_pio_bit(result_bit_index, pio_bit_index);
+ `f_inc_rom;
+ end
+endtask
+
+
+// Write PIO bit function
+// Writes the value specified by the parameter "bit_value" (0 or 1) to
+// the PIO output bit specified by the parameter "bit_index". First
+// writes the value to the internal result register then writes it to the
+// PIO.
+//
+// @param bit_index - The bit within the PIO output port to write to.
+// @param bit_value - The value to write to the PIO output bit.
+task f_write_pio_bit;
+ input [BIT_INDEX_SIZE-1:0] bit_index;
+ input [BIT_VAL_SIZE-1:0] bit_value;
+ begin
+ f_load_result(bit_value);
+ f_write_result_bit_to_pio_bit(0, bit_index);
+ end
+endtask
+
+
+// Read PIO bit function
+// Reads a bit from the PIO input port and stores the value (0 or 1) into the
+// internal result register.
+//
+// @param bit_index - Index of bit within the PIO input port to read.
+task f_read_pio_bit;
+ input [BIT_INDEX_SIZE-1:0] bit_index;
+ begin
+ `f_set_rom read_pio_bit(bit_index);
+ `f_inc_rom;
+ end
+endtask
+
+// Wait for PIO bit function
+// Continuously reads the value of the bit specified by the parameter
+// "bit_index" within the PIO input port and waits for the value of the
+// bit to be equal to the value specified by the parameter
+// "expected_bit_value" before continuing execution.
+//
+// @param bit_index - Index of bit within the PIO input port to read.
+// @param expected_bit_value - Expected value of the bit on the PIO
+// input port
+task f_wait_for_pio_bit;
+ input [BIT_INDEX_SIZE-1:0] bit_index;
+ input [BIT_VAL_SIZE-1:0] expected_bit_value;
+ begin
+ `f_set_rom wait_for_pio_bit(bit_index, expected_bit_value);
+ `f_inc_rom;
+ end
+endtask
+
+// Compare result function
+// Compares the contents of the internal result register to the value
+// specified by the parameter "compare_value". Stores the result (1 for
+// no-match, 0 for match) in the internal result register.
+//
+// @param compare_value. The value to compare with the internal result
+// register.
+task f_compare_result;
+ input [CMP_VAL_SIZE-1:0] compare_value;
+ begin
+ `f_set_rom compare_result(compare_value);
+ `f_inc_rom;
+ end
+endtask
+
+
+// Set a label which can be subsequently jumped to.
+//
+// @param label - The integer label to assign as an identifier.
+task f_label;
+ input integer label;
+ begin
+ if(rom_labels[label] != -1)
+ $display("[f_label] ERROR - Duplicate label %0d! at address %0d", label, rom_i);
+ else if(label < MAX_LABEL && label >= 0)
+ rom_labels[label] = rom_i;
+ else
+ $display("[f_label] ERROR - Invalid label: %0d!, must be between 0<=MAX_LABEL", label);
+ end
+endtask
+
+// jump-not-equal-zero instruction
+// Compares the contents of the internal result register to 0. If the
+// contents are 0, program execution continues, otherwise the program
+// jumps to the indicated label which was set by a previous set_label command
+task f_jump_not_equal_zero;
+ input integer label;
+ begin
+ if(label > MAX_LABEL || label < 0)
+ $display("[mgmt_master] ERROR - Invalid jump label %0d!, must be between 0<=MAX_LABEL", label);
+ begin
+ `f_set_rom jump_not_equal_zero(label);
+ `f_inc_rom;
+ end
+ end
+endtask
+
+
+task pre_process;
+ begin
+ // Initialize ROM with HALT instructions
+ for(rom_i=0;rom_i<MAX_DEPTH;rom_i=rom_i+1) begin
+ prog_rom[rom_i] = halt(0);
+ end
+ // Initialize ROM labels (0 is an invalid address)
+ for(rom_i=0;rom_i<MAX_LABEL;rom_i=rom_i+1) begin
+ rom_labels[rom_i] = -1;
+ end
+
+ rom_i = 0;
+ f_noop(); // First instruction is a NOOP
+ end
+endtask
+
+// The post process task resolves code labels and jump instructions
+task post_process;
+ integer label;
+ begin
+ for(rom_i=0;rom_i<MAX_DEPTH;rom_i=rom_i+1) begin
+ label = prog_rom[rom_i][REG_VAL_OFST+:REG_VAL_SIZE];
+ if(prog_rom[rom_i][CMD_OFST+:CMD_SIZE] == CMD_JNEZ) begin
+ if(rom_labels[label] == -1) begin
+ $display("[post_process] ERROR - Invalid jump label %0d at address %0d. Label not initialized!", label, rom_i);
+ end else begin
+ `f_set_rom jump_not_equal_zero(rom_labels[label]);
+ end
+ end
+ end
+ end
+endtask
+
+`undef f_set_rom
+`undef f_inc_rom
+
+endpackage
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_master.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_master.sv
new file mode 100644
index 0000000000000000000000000000000000000000..31b76c2bdd1e10c97a463de3df514307ee414960
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_master.sv
@@ -0,0 +1,123 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+`timescale 1ps/1ps
+
+// Revision 2.0
+module pcie_mgmt_master #(
+ parameter CLOCKS_PER_SECOND = 125000000, // Used for time calculations
+ parameter PIO_OUT_SIZE = 8, // Width of PIO output port
+ parameter PIO_IN_SIZE = 8, // Width of PIO input port
+ parameter [PIO_OUT_SIZE-1:0] PIO_OUT_INIT_VALUE = 0, // Initial value for pio_out registers
+ parameter MEM_DEPTH = 8,
+ parameter ROM_DEPTH = 512 // Depth of command ROM
+// parameter INIT_FILE_NAME = "" // If specified, ROM will be initialized from file using $readmemh
+ ) (
+ input clk,
+ input reset,
+
+ output reg av_write,
+ output reg av_read,
+ output reg [30:0] av_address,
+ output reg [31:0] av_writedata,
+ input [31:0] av_readdata,
+ input av_waitrequest,
+
+ output reg [PIO_OUT_SIZE-1:0] pio_out,
+ input [ PIO_IN_SIZE-1:0] pio_in
+);
+
+import pcie_mgmt_functions_h::*;
+import pcie_mgmt_commands_h::*;
+import pcie_mgmt_program::*;
+
+
+//localparam LOAD_FROM_FILE = (INIT_FILE_NAME == "") ? 0 : 1;
+//localparam FILETYPE="hex";
+localparam ADDR_WIDTH = clogb2(ROM_DEPTH);
+
+reg [ROM_WIDTH-1:0] rom [0:(ROM_DEPTH-1)]; // Command storage ROM
+wire [ADDR_WIDTH-1:0] rom_address;
+wire rom_read;
+reg [ ROM_WIDTH-1:0] rom_data;
+
+//*********************************************************************
+//************************ Command ROM ********************************
+// Output addressed ROM contents
+always @ (posedge clk)
+ if(rom_read)
+ rom_data <= rom[rom_address];
+
+//********************** End Command ROM ******************************
+//*********************************************************************
+
+
+pcie_mgmt_cpu #(
+ .PIO_OUT_SIZE (PIO_OUT_SIZE),
+ .PIO_IN_SIZE (PIO_IN_SIZE ),
+ .PIO_OUT_INIT_VALUE (PIO_OUT_INIT_VALUE),
+ .ROM_DEPTH (ROM_DEPTH ),
+ .MEM_DEPTH (MEM_DEPTH)
+ ) mgmt_cpu_inst (
+ .clk (clk ),
+ .reset (reset ),
+
+ .av_write (av_write ),
+ .av_read (av_read ),
+ .av_address (av_address ),
+ .av_writedata (av_writedata ),
+ .av_readdata (av_readdata ),
+ .av_waitrequest (av_waitrequest ),
+
+ .rom_address (rom_address ),
+ .rom_read (rom_read ),
+ .rom_data (rom_data ),
+
+ .pio_out (pio_out ), .pio_in (pio_in )
+);
+
+
+//generate if(LOAD_FROM_FILE == 0) begin : load_ram
+ integer i;
+ initial begin
+ clocks_per_second = CLOCKS_PER_SECOND;
+ pre_process(); // Pre process
+ pcie_mgmt_program();
+ post_process(); // Post process program
+ // Copy program from temporary prog_rom to rom
+ for(i=0;i<ROM_DEPTH;i=i+1) begin
+ rom[i] = prog_rom[i];
+ end
+ end
+//end
+//
+//else begin
+// if(FILETYPE == "hex") begin
+// initial begin
+// $readmemh(INIT_FILE_NAME, rom);
+// end
+// end else begin
+// initial begin
+// $readmemb(INIT_FILE_NAME, rom);
+// end
+// end
+//end
+//endgenerate
+
+// Undefine previously defined macros
+`ifdef MGMT_UNDEF
+ `undef MGMT_PROGRAM_TASK
+ `undef MGMT_UNDEF
+`endif
+
+endmodule
diff --git a/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_program.sv b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_program.sv
new file mode 100644
index 0000000000000000000000000000000000000000..7ab8d3c9b376bb9d0abc01b983c0219f2d605852
--- /dev/null
+++ b/quartus/qsys/arria10_hps/altera_xcvr_native_a10_221/synth/pcie_mgmt_program.sv
@@ -0,0 +1,880 @@
+// (C) 2001-2023 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions, and any output
+// files from any of the foregoing (including device programming or simulation
+// files), and any associated documentation or information are expressly subject
+// to the terms and conditions of the Intel Program License Subscription
+// Agreement, Intel FPGA IP License Agreement, or other applicable
+// license agreement, including, without limitation, that your use is for the
+// sole purpose of programming logic devices manufactured by Intel and sold by
+// Intel or its authorized distributors. Please refer to the applicable
+// agreement for further details.
+
+
+// Revision 2.0
+package pcie_mgmt_program;
+
+ import pcie_mgmt_functions_h::*;
+ import altera_xcvr_native_pcie_dfe_params_h::*;
+
+ task pcie_mgmt_program;
+ begin
+ // Read the calibration status
+ f_sleep (SLEEP_DELAY);
+ f_read_reg (ADDR_CALIBRATION);
+
+ //////////////////////////////////////////////////////////
+ // All for-loops are done via handshake from the CPU to the SM
+ // This way, the loops can be parameterized via channel, and
+ // the looping won't require adding a new reg to the memory
+ //
+ // ** IMPORTANT **
+ // Don't know what I'm going to put here yet, but there has
+ // to be something important, right?
+ //////////////////////////////////////////////////////////
+ f_label (PRGM_BEGIN);
+
+ // Clear all pio_out
+ f_write_pio_bit (PIO_OUT_ERROR,0);
+ f_write_pio_bit (PIO_OUT_RUNNING,0);
+ f_write_pio_bit (PIO_OUT_SW_GEN_1_2,0);
+ f_write_pio_bit (PIO_OUT_SW_GEN_3,0);
+ f_write_pio_bit (PIO_OUT_PHASE2_CTLE,0);
+ f_write_pio_bit (PIO_OUT_PHASE2_DFE,0);
+ f_write_pio_bit (PIO_OUT_RESTORE_MODEB,0);
+
+ // Set Tag for beginning of program
+ f_load_result (32'b0); // Since the address store works off of r0... set r0 first
+ f_store_mem_address (); // Store r0 into the mem address
+
+ // Begin!
+ // First check for the "Go!"
+ // We hit the Go! - Set a bit to indicate SM is running
+ f_wait_for_pio_bit (PIO_IN_GO, 1);
+
+
+ //////////////////////////////////////////////////////////
+ // Decode the incoming PIO to determine which steps to run
+ // then jump to the correct section of the code. If none
+ // of the bits are asserted, then assert the error bit
+ // and go to the beginning of the program
+ //////////////////////////////////////////////////////////
+ // Read PIO[1] - Are We rate switching to Gen3
+ f_read_pio_bit (PIO_IN_SW_GEN_3);
+
+ // Jump!
+ f_jump_not_equal_zero (PRGM_SW_GEN3);
+
+
+ //////////////////////////////////////////////////////////
+ // Read PIO[2] - Are we entering Phase 2 Equalization; check ctle
+ f_read_pio_bit (PIO_IN_PHASE2_CTLE);
+
+ // Jump!
+ f_jump_not_equal_zero (PRGM_PHASE2_CTLE);
+
+
+ //////////////////////////////////////////////////////////
+ // Read PIO[2] - Are we entering Phase 2 Equalization; run DFE
+ f_read_pio_bit (PIO_IN_PHASE2_DFE);
+
+ // Jump!
+ f_jump_not_equal_zero (PRGM_PHASE2_DFE);
+
+
+ //////////////////////////////////////////////////////////
+ // Read PIO[3] - Are we returning to Gen1/2
+ f_read_pio_bit (PIO_IN_SW_GEN_1_2);
+
+ // Jump!
+ f_jump_not_equal_zero (PRGM_SW_GEN1_2);
+
+ //////////////////////////////////////////////////////////
+ // Read PIO[3] - Are we returning to Gen1/2
+ f_read_pio_bit (PIO_IN_RESTORE_MODEB);
+
+ // Jump!
+ f_jump_not_equal_zero (PRGM_RESTORE_MODEB);
+
+
+ //////////////////////////////////////////////////////////
+ // None of the PIO were asserted... we have an error
+ f_write_pio_bit (PIO_OUT_ERROR,1);
+ f_sleep (SLEEP_DELAY);
+ f_write_pio_bit (PIO_OUT_ERROR,0);
+
+ // Return to the beginning
+ f_load_result (FORCE_JUMP);
+ f_jump_not_equal_zero (PRGM_BEGIN);
+
+
+ //////////////////////////////////////////////////////////
+ // Code for returning to Gen1/2. The CTLE values are hard
+ // coded. We want to first assert the signal to indicate
+ // we are switching back. We can use this to verify the
+ // jump and the code. At the end of the
+ //////////////////////////////////////////////////////////
+ // We made it this far... we must be returning to Gen1/2
+ // Code for entering Gen1/2
+ f_label (PRGM_SW_GEN1_2);
+
+ // Assert the signal to indicate we are running Gen1/2 switch
+ f_write_pio_bit (PIO_OUT_SW_GEN_1_2,1);
+ f_write_pio_bit (PIO_OUT_RUNNING,1);
+
+ //<-- Put Code Here -->//
+ f_read_reg (31'h167);
+ f_modify_reg (32'h3E, GEN1_GEN2_CTLE_VAL);
+ f_write_result_to_reg (31'h167);
+
+ // Clear all DFE Taps
+ // Read second address for a channel... DFE Tap 1
+ f_read_reg (32'h14F);
+ f_modify_reg (32'hFF, 32'h00);
+ f_write_result_to_reg (32'h14F);
+
+ // Read second address for a channel... DFE Tap 2
+ f_read_reg (32'h150);
+ f_modify_reg (32'hFF, 32'h00);
+ f_write_result_to_reg (32'h150);
+
+ // Read second address for a channel... DFE Tap 3
+ f_read_reg (32'h151);
+ f_modify_reg (32'hFF, 32'h00);
+ f_write_result_to_reg (32'h151);
+
+ // Read second address for a channel... DFE Tap 4
+ f_read_reg (32'h152);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h152);
+
+ // Read second address for a channel... DFE Tap 5
+ f_read_reg (32'h153);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h153);
+
+ // Read second address for a channel... DFE Tap 6
+ f_read_reg (32'h154);
+ f_modify_reg (32'h3F, 32'h00);
+ f_write_result_to_reg (32'h154);
+
+ // Read second address for a channel... DFE Tap 7
+ f_read_reg (32'h155);
+ f_modify_reg (32'h3F, 32'h00);
+ f_write_result_to_reg (32'h155);
+
+ // Read second address for a channel... DFE Tap 8
+ f_read_reg (32'h157);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h157);
+
+ // Read second address for a channel... DFE Tap 9
+ f_read_reg (32'h158);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h158);
+
+ // Read second address for a channel... DFE Tap 10
+ f_read_reg (32'h159);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h159);
+
+ // Read second address for a channel... DFE Tap 11
+ f_read_reg (32'h15A);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h15A);
+
+ //<-- End Code Here -->//
+
+ // Indicate channel is done
+ f_write_pio_bit (PIO_OUT_RUNNING,0);
+
+ // If PIO_IN_GO isn't low, then we havn't completed all channels. Repeat
+ f_sleep (SLEEP_DELAY);
+ f_read_pio_bit (PIO_IN_GO);
+ f_jump_not_equal_zero (PRGM_SW_GEN1_2);
+
+ // Return to Beginning
+ f_load_result (FORCE_JUMP);
+ f_jump_not_equal_zero (PRGM_BEGIN);
+
+
+ //////////////////////////////////////////////////////////
+ // Code for entering Gen3
+ // When entering Gen3, restore the DFE settings from the mem
+ //////////////////////////////////////////////////////////
+ // We made it this far... we must be returning to Gen1/2
+ f_label (PRGM_SW_GEN3);
+
+ // Assert the signal to indicate we are switching to Gen3
+ f_write_pio_bit (PIO_OUT_SW_GEN_3,1);
+ f_write_pio_bit (PIO_OUT_RUNNING,1);
+
+ //<-- Put Code Here -->//
+ // Reading from the first address for a channel... CTLE value
+ f_read_reg (32'h167);
+ f_convert_ctle ();
+ f_write_result_to_reg (32'h167);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 1
+ f_read_reg (32'h14F);
+ f_modify_reg (32'hFF, 32'h00);
+ //f_mod_mem_value (32'hFF);
+ f_write_result_to_reg (32'h14F);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 2
+ f_read_reg (32'h150);
+ f_mod_mem_value (32'hFF);
+ f_write_result_to_reg (32'h150);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 3
+ f_read_reg (32'h151);
+ f_mod_mem_value (32'hFF);
+ f_write_result_to_reg (32'h151);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 4
+ f_read_reg (32'h152);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h152);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 5
+ f_read_reg (32'h153);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h153);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 6
+ f_read_reg (32'h154);
+ f_mod_mem_value (32'h3F);
+ f_write_result_to_reg (32'h154);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 7
+ f_read_reg (32'h155);
+ f_mod_mem_value (32'h3F);
+ f_write_result_to_reg (32'h155);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 8
+ f_read_reg (32'h157);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h157);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 9
+ f_read_reg (32'h158);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h158);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 10
+ f_read_reg (32'h159);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h159);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 11
+ f_read_reg (32'h15A);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h15A);
+ f_inc_mem_address ();
+
+ //////////////////////////////////////////////////////////
+ // Read the PIO bit
+ // Use the compare result function as an inverter... when the input
+ // is 0 and we compare it with 0, it will stay 0, else it will
+ // 1. To load taps, create a multi-cycle pulse
+ f_read_pio_bit (PIO_IN_CONTINUOUS_DFE);
+ f_compare_result (32'b1);
+
+ // Jump to skip loading the DFE taps to adaptation
+ f_jump_not_equal_zero (PRGM_SKIP_DFE_LOAD);
+
+ // Load the DFE Taps into the adaptation block
+ // adp_dfe_fxtap_load = RADP_DFE_FXTAP_LOAD_1
+ f_read_reg (32'h15B);
+ f_modify_reg (32'h2,32'h2);
+ f_write_result_to_reg (32'h15B);
+
+ // create an extended pulse
+ f_sleep (SLEEP_DELAY);
+
+ // Clear the load signal for the DFE taps
+ // adp_dfe_fxtap_load = RADP_DFE_FXTAP_LOAD_0
+ f_read_reg (32'h15B);
+ f_modify_reg (32'h2,32'h0);
+ f_write_result_to_reg (32'h15B);
+
+ // Skips loading the DFE taps
+ f_label (PRGM_SKIP_DFE_LOAD);
+
+ //<-- End Code Here -->//
+
+ // Indicate channel is done
+ f_write_pio_bit (PIO_OUT_RUNNING,0);
+
+ // If PIO_IN_GO isn't low, then we havn't completed all channels. Repeat
+ f_sleep (SLEEP_DELAY);
+ f_read_pio_bit (PIO_IN_GO);
+ f_jump_not_equal_zero (PRGM_SW_GEN3);
+
+ // Return to Beginning
+ f_load_result (FORCE_JUMP);
+ f_jump_not_equal_zero (PRGM_BEGIN);
+
+
+ //////////////////////////////////////////////////////////
+ // Code for entering Phase 2
+ // When running phase 2, wait for the GO signal, which should
+ // be after a 12ms timeout. At which point, save the CTLE
+ // setting, and read out the value before enabling DFE manual
+ // mode. once in manual mode, jump and let the Master SM
+ // change the channels before starting again. In the meantime
+ // the Master SM will run a 10ms timeout. After the 10ms,
+ // save the DFE settings into the memory
+ //////////////////////////////////////////////////////////
+ // CTLE Time - read out the CTLE value
+ // TODO: Do I need to save the originals?
+ f_label (PRGM_PHASE2_CTLE);
+
+ // Assert the signal to indicate we are switching to Gen3
+ f_write_pio_bit (PIO_OUT_PHASE2_CTLE,1);
+ f_write_pio_bit (PIO_OUT_RUNNING,1);
+
+ //<-- Put Code Here -->//
+ //////////////////////////////////////////////////////////
+ // Set the testbus
+ // Set the test mux value to point to CTLE
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h1B);
+ f_write_result_to_reg (32'h14C);
+
+ // Wait 5 cycles, then read the value out and compare it to verify we
+ // wrote the correct testbus
+ f_sleep (TST_MUX_DELAY);
+
+ // Read out the value
+ f_read_reg (32'h177); // Backup... in case 171 is a different setting
+ f_st_reg_to_address ();
+
+ //////////////////////////////////////////////////////////
+ // Disable the Adaptation Mode B and configure to Adaptation Mode E
+ // pdb_fxtap4t7 = FXTAP4T7_ENABLE
+ f_read_reg (32'h123);
+ f_modify_reg (32'h8,32'h8);
+ f_write_result_to_reg (32'h123);
+
+ // adp_dfe_fxtap_en = RADP_DFE_FXTAP_ENABLE
+ // adp_dfe_fltap_en = RADP_DFE_FLTAP_ENABLE
+ f_read_reg (32'h148);
+ f_modify_reg (32'h3,32'h3);
+ f_write_result_to_reg (32'h148);
+
+ // adp_dfe_fxtap_bypass = RADP_DFE_FXTAP_BYPASS_0
+ // adp_dfe_fltap_bypass = RADP_DFE_FLTAP_BYPASS_0
+ // adp_dfe_fxtap_hold_en = RADP_DFE_FXTAP_NOT_HELD
+ f_read_reg (32'h15B);
+ f_modify_reg (32'h15,32'h0);
+ f_write_result_to_reg (32'h15B);
+
+ // adp_vga_bypass = RADP_VGA_BYPASS_1
+ f_read_reg (32'h160);
+ f_modify_reg (32'h1,32'h1);
+ f_write_result_to_reg (32'h160);
+
+ // adp_dfe_mode = RADP_DFE_MODE_0
+ f_read_reg (32'h14D);
+ f_modify_reg (32'h7,32'h0);
+ f_write_result_to_reg (32'h14D);
+
+ // adp_ctle_adapt_cycle_window = RADP_CTLE_ADAPT_CYCLE_WINDOW_0
+ f_read_reg (32'h163);
+ f_modify_reg (32'hE0,32'h0);
+ f_write_result_to_reg (32'h163);
+
+ // adp_1s_ctle_bypass = RADP_1S_CTLE_BYPASS_1
+ f_read_reg (32'h166);
+ f_modify_reg (32'h1,32'h1);
+ f_write_result_to_reg (32'h166);
+
+ // adp_4s_ctle_bypass = RADP_4S_CTLE_BYPASS_1
+ f_read_reg (32'h167);
+ f_modify_reg (32'h1,32'h1);
+ f_write_result_to_reg (32'h167);
+
+ //////////////////////////////////////////////////////////
+ // Write back the CTLE Manual setting
+ f_convert_ctle ();
+ f_write_result_to_reg (32'h167);
+
+ // Index to the start of the next channel's CTLE memory address
+ f_load_mem_address ();
+ f_add_to_reg (NUM_ADDR_PER_CHNL);
+ f_store_mem_address ();
+
+ //////////////////////////////////////////////////////////
+ // Start the DFE
+ // adp_adapt_control_sel = RADP_ADAPT_CONTROL_SEL_1
+ f_read_reg (32'h149);
+ f_modify_reg (32'h10,32'h10);
+ f_write_result_to_reg (32'h149);
+
+ // assert adp_start = radp_adapt_start_0
+ f_read_reg (32'h149);
+ f_modify_reg (32'h20,32'h0);
+ f_write_result_to_reg (32'h149);
+
+ // rstn by adp_adp_rstn = radp_adapt_rstn_0
+ f_read_reg (32'h149);
+ f_modify_reg (32'h40,32'h0);
+ f_write_result_to_reg (32'h149);
+
+ // rstn by adp_adp_rstn = radp_adapt_rstn_1
+ f_read_reg (32'h149);
+ f_modify_reg (32'h40,32'h40);
+ f_write_result_to_reg (32'h149);
+
+ // assert adp_start = radp_adapt_start_1
+ f_read_reg (32'h149);
+ f_modify_reg (32'h20,32'h20);
+ f_write_result_to_reg (32'h149);
+
+ //<-- End Code Here -->//
+
+ // Indicate channel is done
+ f_write_pio_bit (PIO_OUT_RUNNING,0);
+
+ // If PIO_IN_GO isn't low, then we havn't completed all channels. Repeat
+ f_sleep (SLEEP_DELAY);
+ f_read_pio_bit (PIO_IN_GO);
+ f_jump_not_equal_zero (PRGM_PHASE2_CTLE);
+
+ // Return to beginning
+ f_load_result (FORCE_JUMP);
+ f_jump_not_equal_zero (PRGM_BEGIN);
+
+
+ //////////////////////////////////////////////////////////
+ // DFE time - read out the DFE converged values
+ // We are still in Phase 2, however the 10ms are up,
+ // and we can now store the values for the DFE
+ //////////////////////////////////////////////////////////
+ f_label (PRGM_PHASE2_DFE);
+
+ // Assert the signal to indicate we are reading out DFE
+ f_write_pio_bit (PIO_OUT_PHASE2_DFE,1);
+ f_write_pio_bit (PIO_OUT_RUNNING,1);
+
+ //<-- Put Code Here -->//
+ // Set the starting address for DFE
+ f_load_mem_address ();
+ f_add_to_reg (NUM_ADDR_CTLE);
+ f_store_mem_address ();
+
+ // Check the PIO in for continuous dfe... we need to skip the TAP hold
+ f_read_pio_bit (PIO_IN_CONTINUOUS_DFE);
+ f_jump_not_equal_zero (PRGM_SKIP_DFE_HOLD);
+
+ // Assert the Hold for DFE -- Might need to be moved
+ // adp_dfe_fxtap_hold_en = RADP_DFE_FXTAP_HELD
+ f_read_reg (32'h15B);
+ f_modify_reg (32'h10,32'h10);
+ f_write_result_to_reg (32'h15B);
+
+ // Used to skip the DFE HOLD on the Taps
+ f_label (PRGM_SKIP_DFE_HOLD);
+
+ // Setup the test mux for DFE
+ f_read_reg (32'h171);
+ f_modify_reg (32'h1E,32'h16);
+ f_write_result_to_reg (32'h171);
+
+ // Read back TAP 1
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h1E);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ // Read back TAP 2
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h1F);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ // Read back TAP 3
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h20);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ // Read back TAP 4
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h21);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ // Read back TAP 5
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h22);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ // Read back TAP 6
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h23);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ // Read back TAP 7
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h24);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ // Read back TAP 8
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h25);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ // Read back TAP 9
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h26);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ // Read back TAP 10
+ f_read_reg (32'h14C);
+ f_modify_reg (32'h3F,32'h27);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ // Read back TAP 11
+ f_read_reg (32'h14C);;
+ f_modify_reg (32'h3F,32'h28);
+ f_write_result_to_reg (32'h14C);
+ f_sleep (TST_MUX_DELAY);
+ f_read_reg (32'h176);
+ f_st_reg_to_address ();
+ f_inc_mem_address ();
+
+ //////////////////////////////////////////////////////////
+ // Check the status of continuous DFE. If the status is set, skip manual DFE
+ // and jump to the end of writing back the tap values. At that point write the
+ // bits to enable Mode 4. If we do run manual DFE, force a jump at the end to
+ // skip the continuous DFE Mode 4 write
+ f_read_pio_bit (PIO_IN_CONTINUOUS_DFE);
+
+ // Skip manual DFE
+ f_jump_not_equal_zero (PRGM_SKIP_MANUAL_DFE);
+
+ //////////////////////////////////////////////////////////
+ // Disable DFE One time, and switch to manual manual
+ // adp_dfe_fxtap_en = RADP_DFE_FXTAP_DISABLE
+ // adp_dfe_fltap_en = RADP_DFE_FLTAP_DISABLE
+ // adp_vref_en = RADP_VREF_DISABLE
+ // adp_vga_en = RADP_VGA_DISABLE
+ // adp_ctle_en = RADP_CTLE_DISABLE
+ f_read_reg (32'h148);
+ f_modify_reg (32'h1F,32'h0);
+ f_write_result_to_reg (32'h148);
+
+ // adp_dfe_fxtap_bypass = RADP_DFE_FXTAP_BYPASS_1
+ // adp_dfe_fltap_bypass = RADP_DFE_FLTAP_BYPASS_1
+ f_read_reg (32'h15B);
+ f_modify_reg (32'h5,32'h5);
+ f_write_result_to_reg (32'h15B);
+
+ // adp_vref_bypass = RADP_VREF_BYPASS_1
+ f_read_reg (32'h15E);
+ f_modify_reg (32'h1,32'h1);
+ f_write_result_to_reg (32'h15E);
+
+ // adp_ctle_adapt_cycle_window = RADP_CTLE_ADAPT_CYCLE_WINDOW_7
+ f_read_reg (32'h163);
+ f_modify_reg (32'hE0,32'hE0);
+ f_write_result_to_reg (32'h163);
+
+ // Might have to disable DFE Hold
+ // adp_dfe_fxtap_hold_en = RADP_DFE_FXTAP_NOT_HELD
+
+ //////////////////////////////////////////////////////////
+ // Load the DFE Manual
+ // Potential enhancement: Call Gen3_SW to set all the DFE Taps
+ // For now, finish, and then make an immediate call to run Gen3 SW
+ // Restore the address for the start of the Memory
+ f_load_mem_address ();
+ f_sub_from_reg (NUM_ADDR_DFE);
+ f_store_mem_address ();
+
+ // Read second address for a channel... DFE Tap 1
+ f_read_reg (32'h14F);
+ f_modify_reg (32'hFF, 32'h00);
+ //f_mod_mem_value (32'hFF);
+ f_write_result_to_reg (32'h14F);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 2
+ f_read_reg (32'h150);
+ f_mod_mem_value (32'hFF);
+ f_write_result_to_reg (32'h150);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 3
+ f_read_reg (32'h151);
+ f_mod_mem_value (32'hFF);
+ f_write_result_to_reg (32'h151);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 4
+ f_read_reg (32'h152);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h152);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 5
+ f_read_reg (32'h153);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h153);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 6
+ f_read_reg (32'h154);
+ f_mod_mem_value (32'h3F);
+ f_write_result_to_reg (32'h154);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 7
+ f_read_reg (32'h155);
+ f_mod_mem_value (32'h3F);
+ f_write_result_to_reg (32'h155);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 8
+ f_read_reg (32'h157);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h157);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 9
+ f_read_reg (32'h158);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h158);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 10
+ f_read_reg (32'h159);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h159);
+ f_inc_mem_address ();
+
+ // Read second address for a channel... DFE Tap 11
+ f_read_reg (32'h15A);
+ f_mod_mem_value (32'h7F);
+ f_write_result_to_reg (32'h15A);
+ f_inc_mem_address ();
+
+ //////////////////////////////////////////////////////////
+ // Force a jump to skip continuous DFE
+ // This jump is only executed when we run manual DFE; in continuous we
+ // use a jump to skip the manual process (including this jump) If we
+ // use this jump, go ahead and skip manual
+ f_load_result (FORCE_JUMP);
+ f_jump_not_equal_zero (PRGM_SKIP_CONT_DFE);
+
+ // label for the end of manual mode
+ f_label (PRGM_SKIP_MANUAL_DFE);
+
+ // Switch adaptation from Mode 8 to Mode 4 to support loading
+ // adp_mode = RADP_MODE_4
+ f_read_reg (32'h149);
+ f_modify_reg (32'h0F,32'h04);
+ f_write_result_to_reg (32'h149);
+
+ // label for the end of continuous DFE
+ f_label (PRGM_SKIP_CONT_DFE);
+
+ //<-- End Code Here -->//
+
+ // Indicate channel is done
+ f_write_pio_bit (PIO_OUT_RUNNING,0);
+
+ // If PIO_IN_GO isn't low, then we havn't completed all channels. Repeat
+ f_sleep (SLEEP_DELAY);
+ f_read_pio_bit (PIO_IN_GO);
+ f_jump_not_equal_zero (PRGM_PHASE2_DFE);
+
+ // Return to beginning
+ f_load_result (FORCE_JUMP);
+ f_jump_not_equal_zero (PRGM_BEGIN);
+
+
+ //////////////////////////////////////////////////////////
+ // If we hit a global reset or enter detect
+ //////////////////////////////////////////////////////////
+ f_label (PRGM_RESTORE_MODEB);
+
+ // Assert the signal to indicate we need to restore the original
+ // Adapation Mode settings
+ // TODO: should these be hard coded or do we need to save them?
+ f_write_pio_bit (PIO_OUT_RESTORE_MODEB,1);
+ f_write_pio_bit (PIO_OUT_RUNNING,1);
+
+ //<-- Put Code Here -->//
+ //////////////////////////////////////////////////////////
+ // We are reseting... Restore Mode B
+ // adp_dfe_fxtap_en = RADP_DFE_FXTAP_DISABLE
+ // adp_dfe_fltap_en = RADP_DFE_FLTAP_DISABLE
+ // adp_vref_en = RADP_VREF_ENABLE
+ // adp_vga_en = RADP_VGA_ENABLE
+ // adp_ctle_en = RADP_CTLE_ENABLE
+ f_read_reg (32'h148);
+ f_modify_reg (32'h1F,32'h1C);
+ f_write_result_to_reg (32'h148);
+
+ // Switch adaptation from Mode 4 to Mode 8 to support running
+ // continuous CTLE. If we are not in continuous DFE, skip
+ f_read_pio_bit (PIO_IN_CONTINUOUS_DFE);
+ f_compare_result (32'b1);
+ f_jump_not_equal_zero (PRGM_SKIP_DFE_MODE_8);
+
+ // adp_mode = RADP_MODE_8
+ f_read_reg (32'h149);
+ f_modify_reg (32'h0F,32'h08);
+ f_write_result_to_reg (32'h149);
+
+ // SKIP Mode8
+ f_label (PRGM_SKIP_DFE_MODE_8);
+
+ // adp_vref_bypass = RADP_VREF_BYPASS_0
+ f_read_reg (32'h15E);
+ f_modify_reg (32'h1,32'h0);
+ f_write_result_to_reg (32'h15E);
+
+ // adp_vga_bypass = RADP_VGA_BYPASS_1
+ f_read_reg (32'h160);
+ f_modify_reg (32'h1,32'h1);
+ f_write_result_to_reg (32'h160);
+
+ // adp_1s_ctle_bypass = RADP_1S_CTLE_BYPASS_0
+ f_read_reg (32'h166);
+ f_modify_reg (32'h1,32'h0);
+ f_write_result_to_reg (32'h166);
+
+ // adp_4s_ctle_bypass = RADP_4S_CTLE_BYPASS_0
+ f_read_reg (32'h167);
+ f_modify_reg (32'h1,32'h0);
+ f_write_result_to_reg (32'h167);
+
+ // Restore Gen1/2 rates
+ f_read_reg (31'h167);
+ f_modify_reg (32'h3E, GEN1_GEN2_CTLE_VAL);
+ f_write_result_to_reg (31'h167);
+
+ // Clear all DFE Taps
+ // Read second address for a channel... DFE Tap 1
+ f_read_reg (32'h14F);
+ f_modify_reg (32'hFF, 32'h00);
+ f_write_result_to_reg (32'h14F);
+
+ // Read second address for a channel... DFE Tap 2
+ f_read_reg (32'h150);
+ f_modify_reg (32'hFF, 32'h00);
+ f_write_result_to_reg (32'h150);
+
+ // Read second address for a channel... DFE Tap 3
+ f_read_reg (32'h151);
+ f_modify_reg (32'hFF, 32'h00);
+ f_write_result_to_reg (32'h151);
+
+ // Read second address for a channel... DFE Tap 4
+ f_read_reg (32'h152);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h152);
+
+ // Read second address for a channel... DFE Tap 5
+ f_read_reg (32'h153);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h153);
+
+ // Read second address for a channel... DFE Tap 6
+ f_read_reg (32'h154);
+ f_modify_reg (32'h3F, 32'h00);
+ f_write_result_to_reg (32'h154);
+
+ // Read second address for a channel... DFE Tap 7
+ f_read_reg (32'h155);
+ f_modify_reg (32'h3F, 32'h00);
+ f_write_result_to_reg (32'h155);
+
+ // Read second address for a channel... DFE Tap 8
+ f_read_reg (32'h157);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h157);
+
+ // Read second address for a channel... DFE Tap 9
+ f_read_reg (32'h158);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h158);
+
+ // Read second address for a channel... DFE Tap 10
+ f_read_reg (32'h159);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h159);
+
+ // Read second address for a channel... DFE Tap 11
+ f_read_reg (32'h15A);
+ f_modify_reg (32'h7F, 32'h00);
+ f_write_result_to_reg (32'h15A);
+
+ //<-- End Code Here -->