From efc9dde20e667e11d5c684715012b2675246bde2 Mon Sep 17 00:00:00 2001
From: Julia Chomicka <s188873@student.pg.edu.pl>
Date: Wed, 3 Jul 2024 13:12:40 +0000
Subject: [PATCH] Update README.md

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 6810e5b..a41c42b 100644
--- a/README.md
+++ b/README.md
@@ -7,7 +7,7 @@ Choose the appropriate branch to clone project for selected board:
 * arria10 SoC
 
 ### Generate Verilog from rdl:
-    `peakrdl regblock registers.rdl -o outputs/ --cpuif axi4-lite-flat`
+    peakrdl regblock registers.rdl -o outputs/ --cpuif axi4-lite-flat
 
 ### Output files generation:
 1. Open quartus from folder quartus:
-- 
GitLab