diff --git a/README.md b/README.md
index 6810e5bc4ebfceb083dd80f148f8bc45bb827a3a..a41c42ba8d2e3c77701f05d90957b43c6ac02e61 100644
--- a/README.md
+++ b/README.md
@@ -7,7 +7,7 @@ Choose the appropriate branch to clone project for selected board:
 * arria10 SoC
 
 ### Generate Verilog from rdl:
-    `peakrdl regblock registers.rdl -o outputs/ --cpuif axi4-lite-flat`
+    peakrdl regblock registers.rdl -o outputs/ --cpuif axi4-lite-flat
 
 ### Output files generation:
 1. Open quartus from folder quartus: