diff --git a/quartus/soc_system.qsf b/quartus/soc_system.qsf
index 42afb046cdca8ff6fd373142e6f3b756aa8d7bf2..fd0a57c1c6dcc25dc0282255b1ee372ad215507f 100644
--- a/quartus/soc_system.qsf
+++ b/quartus/soc_system.qsf
@@ -89,7 +89,25 @@ set_location_assignment PIN_AG29 -to refclk
 set_instance_assignment -name IO_STANDARD LVDS -to refclk
 set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to refclk
 
-
+# ETHERNET ports
+
+# ETH 1
+set_location_assignment PIN_AR20 -to eneta_mdc
+set_location_assignment PIN_AV16 -to eneta_mdio
+set_location_assignment PIN_N1 -to eneta_resetn
+set_location_assignment PIN_N2 -to eneta_intn
+set_location_assignment PIN_AG33 -to eneta_rx_p
+#set_location_assignment PIN_AG32 -to eneta_rx_n
+set_location_assignment PIN_AK39 -to eneta_tx_p
+#set_location_assignment PIN_AK38 -to eneta_tx_n
+
+# ETH 2
+set_location_assignment PIN_AV17 -to enetb_mdc
+set_location_assignment PIN_AW20 -to enetb_mdio
+set_location_assignment PIN_R2 -to enetb_resetn
+set_location_assignment PIN_R3 -to enetb_intn
+set_location_assignment PIN_AH35 -to enetb_rx_p
+set_location_assignment PIN_AL37 -to enetb_tx_p
 
 # IO Standard
 
diff --git a/rtl/top/soc_system.sv b/rtl/top/soc_system.sv
index fe6b7e1c166158424f6787554220ba68ad63dbf7..7b0a2e4387e065d5afd791150877aaa3a58c754a 100644
--- a/rtl/top/soc_system.sv
+++ b/rtl/top/soc_system.sv
@@ -3,10 +3,28 @@ module soc_system # (
  )(
   // FPGA clock and reset
   input  wire          fpga_clk_100,
-  input  wire          fpga_reset_n,
+  input  wire          fpga_reset_n, // dev_clrn
 
   input                fpga_clk_50, 
-  input                refclk,
+  input                refclk, // clk_enet_fpga_p
+
+    // ETHERNET 1
+    output           eneta_mdc,      
+    inout            eneta_mdio,     
+    input            eneta_rx_p,     
+    output           eneta_tx_p,     
+    output           eneta_intn,     //FPGA_IO2 -> ENETA_INTn 
+    output           eneta_resetn,
+
+
+    // ETHERNET 2
+
+    output           enetb_mdc,      
+	inout            enetb_mdio,     
+	input            enetb_rx_p,     
+	output           enetb_tx_p,     
+	output           enetb_intn,    //FPGA_IO3 -> ENETB_INTn 
+	output           enetb_resetn,
     
     
   // HPS memory controller ports