From a8facf22745d7d663f0325b9fd3f6aa31f6c0a0e Mon Sep 17 00:00:00 2001
From: Oleg <oleg.struk@adtran.com>
Date: Wed, 20 Nov 2024 14:43:00 +0100
Subject: [PATCH] Update readme (related to peakrdl use) and gitignore

---
 .gitignore | 3 ++-
 README.md  | 8 ++++++--
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/.gitignore b/.gitignore
index 2ccf515..52e6a64 100644
--- a/.gitignore
+++ b/.gitignore
@@ -21,4 +21,5 @@ vsim.wlf
 **/incremental_db/*
 **/hps_isw_handoff/*
 **/qdb/*
-**/tmp_svunit/
\ No newline at end of file
+**/tmp_svunit/
+**/.qsys_edit/
\ No newline at end of file
diff --git a/README.md b/README.md
index 8150894..38c0631 100644
--- a/README.md
+++ b/README.md
@@ -18,15 +18,19 @@
 
     git submodule update --init --recursive
 
-### <ins>Generate Verilog from rdl:</ins>
+### <ins>Generate files from RDL (Register Description Language):</ins>
 #### 1. Go to rdl directory:
 
     cd rdl
 
-#### 2. Generate Verilog from rdl file:
+#### 2. Generate SystemVerilog from RDL file:
 
     peakrdl regblock registers.rdl -o outputs/ --cpuif axi4-lite-flat
 
+#### 3. Generate HTML from RDL file:
+
+    peakrdl html registers.rdl -o outputs/html
+
 ### <ins>Simulate design</ins>
 #### 1. Go to test directory:
 
-- 
GitLab