diff --git a/.gitignore b/.gitignore
index 2ccf51509dcf9ba8003979ccf6a2d2be6586d7ec..52e6a64b890f60c7230033791a9d4d80e7ff7111 100644
--- a/.gitignore
+++ b/.gitignore
@@ -21,4 +21,5 @@ vsim.wlf
 **/incremental_db/*
 **/hps_isw_handoff/*
 **/qdb/*
-**/tmp_svunit/
\ No newline at end of file
+**/tmp_svunit/
+**/.qsys_edit/
\ No newline at end of file
diff --git a/README.md b/README.md
index 8150894da3f96730ee86f626f27c8ef451af5f11..38c0631449e6b4bfa4b415529e21a93f44177668 100644
--- a/README.md
+++ b/README.md
@@ -18,15 +18,19 @@
 
     git submodule update --init --recursive
 
-### <ins>Generate Verilog from rdl:</ins>
+### <ins>Generate files from RDL (Register Description Language):</ins>
 #### 1. Go to rdl directory:
 
     cd rdl
 
-#### 2. Generate Verilog from rdl file:
+#### 2. Generate SystemVerilog from RDL file:
 
     peakrdl regblock registers.rdl -o outputs/ --cpuif axi4-lite-flat
 
+#### 3. Generate HTML from RDL file:
+
+    peakrdl html registers.rdl -o outputs/html
+
 ### <ins>Simulate design</ins>
 #### 1. Go to test directory: